/external/llvm/lib/CodeGen/ |
H A D | VirtRegMap.cpp | 56 MRI = &mf.getRegInfo(); 84 unsigned Hint = MRI->getSimpleHint(VirtReg); 93 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); 121 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 126 << MRI->getRegClass(Reg)->getName() << "\n"; 130 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 134 << "] " << MRI->getRegClass(Reg)->getName() << "\n"; 161 MachineRegisterInfo *MRI; member in class:__anon25833::VirtRegRewriter 210 MRI = &MF->getRegInfo(); 234 MRI [all...] |
/external/llvm/lib/MC/MCDisassembler/ |
H A D | Disassembler.cpp | 46 const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple); local 47 if (!MRI) 51 const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, Triple); 68 MCContext *Ctx = new MCContext(MAI, MRI, nullptr); 89 *MAI, *MII, *MRI, *STI); 95 TheTarget, MAI, MRI, 333 const MCRegisterInfo *MRI = DC->getRegisterInfo(); local 338 AsmPrinterVariant, *MAI, *MII, *MRI, *STI);
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H A D | Disassembler.h | 64 std::unique_ptr<const llvm::MCRegisterInfo> MRI; member in class:llvm::LLVMDisasmContext 99 MRI.reset(mRI); 117 const MCRegisterInfo *getRegisterInfo() const { return MRI.get(); }
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 65 MachineRegisterInfo *MRI; member in class:__anon25930::AArch64AdvSIMDScalar 101 const MachineRegisterInfo *MRI) { 105 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); 110 const MachineRegisterInfo *MRI) { 112 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && 114 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && 124 const MachineRegisterInfo *MRI, 141 MRI) && 142 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) 145 MRI) 100 isGPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI) argument 109 isFPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI) argument 123 getSrcFromCopy(const MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &SubReg) argument [all...] |
H A D | AArch64RegisterInfo.cpp | 295 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local 297 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.cpp | 220 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { argument 250 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); 299 const MCRegisterInfo &MRI, 302 return new ARMInstPrinter(MAI, MII, MRI, STI); 295 createARMMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 44 const Thumb1RegisterInfo &MRI, 47 MRI, MIFlags); 91 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); local 224 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI))); 242 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset)); 248 nullptr, MRI->getDwarfRegNum(FramePtr, true))); 41 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, DebugLoc dl, const Thumb1RegisterInfo &MRI, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) argument
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H A D | Thumb1RegisterInfo.cpp | 94 const ARMBaseRegisterInfo& MRI, 123 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes, 170 const ARMBaseRegisterInfo& MRI, 229 TII, MRI, MIFlags); 303 const Thumb1RegisterInfo& MRI, 315 emitThumbRegPlusImmediate(MBB, MBBI, dl, DestReg, DestReg, Imm, TII, MRI); 88 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument 165 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument 299 emitThumbConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, const Thumb1RegisterInfo& MRI, DebugLoc dl) argument
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/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.h | 81 const MCRegisterInfo &MRI) 82 : MCInstPrinter(MAI, MII, MRI) {} 80 MipsInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCTargetDesc.cpp | 78 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { argument 81 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); 104 const MCRegisterInfo &MRI, 106 return new MipsInstPrinter(MAI, MII, MRI); 100 createMipsMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/Mips/ |
H A D | MipsOptimizePICCall.cpp | 260 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); local 261 MachineInstr *DefMI = MRI.getVRegDef(Reg);
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.cpp | 69 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { argument 83 MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0); 192 const MCRegisterInfo &MRI, 195 return new PPCInstPrinter(MAI, MII, MRI, isDarwin); 188 createPPCMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | R600MCCodeEmitter.cpp | 36 const MCRegisterInfo &MRI; member in class:__anon26110::R600MCCodeEmitter 41 : MCII(mcii), MRI(mri) { } 84 const MCRegisterInfo &MRI, 86 return new R600MCCodeEmitter(MCII, MRI); 163 return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT; 167 return MRI.getEncodingValue(RegNo) & HW_REG_MASK; 176 return MRI.getEncodingValue(MO.getReg()); 83 createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/R600/ |
H A D | R600OptimizeVectorRegisters.cpp | 49 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { argument 50 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), 51 E = MRI.def_instr_end(); It != E; ++It) { 54 if (MRI.isReserved(Reg)) { 66 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { argument 71 if (isImplicitlyDef(MRI, MO.getReg())) 86 MachineRegisterInfo *MRI; member in class:__anon26117::R600VectorRegMerger 190 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 217 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), 218 E = MRI [all...] |
H A D | SIInsertWaits.cpp | 51 const MachineRegisterInfo *MRI; member in class:__anon26125::SIInsertWaits 352 MRI = &MF.getRegInfo();
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.cpp | 36 static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, argument 39 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); 45 static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, argument 48 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); 152 const MCRegisterInfo &MRI, 154 return new SparcInstPrinter(MAI, MII, MRI, STI); 148 createSparcMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 67 MachineRegisterInfo &MRI = MF.getRegInfo(); local 79 MRI.setPhysRegUsed(SystemZ::ArgGPRs[I]); 84 MRI.setPhysRegUsed(SystemZ::R11D); 89 MRI.setPhysRegUsed(SystemZ::R14D); 98 if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) { 99 MRI.setPhysRegUsed(SystemZ::R15D); 318 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); local 339 nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); 366 unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true); 392 unsigned DwarfReg = MRI [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCTargetDesc.cpp | 212 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { argument 215 unsigned SEH = MRI->getEncodingValue(Reg); 216 MRI->mapLLVMRegToSEHReg(Reg, SEH); 260 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { argument 289 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 295 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 376 const MCRegisterInfo &MRI, 379 return new X86ATTInstPrinter(MAI, MII, MRI); 381 return new X86IntelInstPrinter(MAI, MII, MRI); 372 createX86MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 427 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local 431 if (!MRI->canReserveReg(FramePtr)) 437 return MRI->canReserveReg(BasePtr);
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H A D | X86VZeroUpper.cpp | 108 static bool checkFnHasLiveInYmm(MachineRegisterInfo &MRI) { argument 109 for (MachineRegisterInfo::livein_iterator I = MRI.livein_begin(), 110 E = MRI.livein_end(); I != E; ++I) 254 MachineRegisterInfo &MRI = MF.getRegInfo(); local 264 if (!MRI.reg_nodbg_empty(*i)) { 285 if (checkFnHasLiveInYmm(MRI))
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/external/llvm/lib/Target/XCore/MCTargetDesc/ |
H A D | XCoreMCTargetDesc.cpp | 56 static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, argument 88 const MCRegisterInfo &MRI, 90 return new XCoreInstPrinter(MAI, MII, MRI); 84 createXCoreMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 317 MachineRegisterInfo &MRI = MF.getRegInfo(); local 319 if (!MRI.isLiveIn(Reg)) { 320 VirtualRegister = MRI.createVirtualRegister(RC); 321 MRI.addLiveIn(Reg, VirtualRegister); 323 VirtualRegister = MRI.getLiveInVirtReg(Reg);
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H A D | AMDGPUInstrInfo.cpp | 241 MachineRegisterInfo &MRI = MF.getRegInfo(); local 249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg()); 254 MRI.setRegClass(MO.getReg(), newRegClass);
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H A D | R600ISelLowering.cpp | 57 MachineRegisterInfo &MRI = MF->getRegInfo(); local 111 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister); 120 unsigned NewAddr = MRI.createVirtualRegister( 122 unsigned ShiftValue = MRI.createVirtualRegister( 157 unsigned t0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 158 unsigned t1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 179 unsigned t0 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass); 180 unsigned t1 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass); 260 MachineRegisterInfo &MRI = MF.getRegInfo(); local 263 if (!MRI [all...] |
H A D | SIISelLowering.cpp | 69 MachineRegisterInfo & MRI = BB->getParent()->getRegInfo(); local 127 LowerSI_INTERP(MI, *BB, I, MRI); 130 LowerSI_INTERP_CONST(MI, *BB, I, MRI); 133 LowerSI_KIL(MI, *BB, I, MRI); 136 LowerSI_V_CNDLT(MI, *BB, I, MRI); 150 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const 152 unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); 153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); 183 MachineRegisterInfo &MRI) const 189 unsigned M0 = MRI [all...] |