/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.h | 77 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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H A D | AMDGPUInstrInfo.h | 135 int64_t Imm) const = 0;
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H A D | R600InstrInfo.cpp | 79 unsigned DstReg, int64_t Imm) const 84 MachineInstrBuilder(MI).addImm(Imm);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 52 inline SDValue getI32Imm(unsigned Imm) { argument 53 return CurDAG->getTargetConstant(Imm, MVT::i32);
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 539 unsigned Imm = MI->getOperand(2).getImm(); local 543 if (Imm & 3 || Imm > 1020) 558 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four. 673 unsigned Imm = MI->getOperand(2).getImm(); local 675 if (Imm > Limit)
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H A D | ARMCodeEmitter.cpp | 335 unsigned getShiftOp(unsigned Imm) const ; 404 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 405 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 1864 unsigned Imm = MI.getOperand(1).getImm(); 1865 unsigned Op = (Imm >> 12) & 1; 1866 unsigned Cmode = (Imm >> 8) & 0xf; 1867 unsigned I = (Imm >> 7) & 1; 1868 unsigned Imm3 = (Imm >> 4) & 0x7; 1869 unsigned Imm4 = Imm & 0xf;
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H A D | ARMTargetTransformInfo.cpp | 77 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override; 151 unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const { argument 158 int32_t SImmVal = Imm.getSExtValue(); 159 uint32_t ZImmVal = Imm.getZExtValue();
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16ISelLowering.cpp | 747 (unsigned shortOp, unsigned longOp, int64_t Imm) { 748 if (isUInt<8>(Imm)) 750 else if (isInt<16>(Imm)) 781 int64_t Imm = MI->getOperand(2).getImm(); local 782 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm); 784 TII->get(SltOpc)).addReg(regX).addImm(Imm); 746 Mips16WhichOp8uOr16simm(unsigned shortOp, unsigned longOp, int64_t Imm) argument
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/external/llvm/lib/Target/R600/ |
H A D | SIInstrInfo.cpp | 486 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const { 487 int32_t Val = Imm.getSExtValue(); 500 return (APInt::floatToBits(0.0f) == Imm) || 501 (APInt::floatToBits(1.0f) == Imm) || 502 (APInt::floatToBits(-1.0f) == Imm) || 503 (APInt::floatToBits(0.5f) == Imm) || 504 (APInt::floatToBits(-0.5f) == Imm) || 505 (APInt::floatToBits(2.0f) == Imm) || 506 (APInt::floatToBits(-2.0f) == Imm) || 507 (APInt::floatToBits(4.0f) == Imm) || 1296 uint32_t Imm = OffsetWidthOp.getImm(); local [all...] |
H A D | AMDGPUISelLowering.h | 121 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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/external/valgrind/main/VEX/priv/ |
H A D | host_mips_defs.c | 1009 op->Mrh.Imm.syned = syned; 1010 op->Mrh.Imm.imm16 = imm16; 1032 if (op->Mrh.Imm.syned) 1033 vex_printf("%d", (Int) (Short) op->Mrh.Imm.imm16); 1035 vex_printf("%u", (UInt) (UShort) op->Mrh.Imm.imm16); 2870 vassert(srcR->Mrh.Imm.imm16 != 0x8000); 2871 if (srcR->Mrh.Imm.syned) 2873 p = mkFormI(p, 9, r_srcL, r_dst, srcR->Mrh.Imm.imm16); 2876 p = mkFormI(p, 9, r_srcL, r_dst, srcR->Mrh.Imm.imm16); 2885 vassert(srcR->Mrh.Imm [all...] |
H A D | host_amd64_defs.c | 278 op->Armi.Imm.imm32 = imm32; 297 vex_printf("$0x%x", op->Armi.Imm.imm32); 358 op->Ari.Imm.imm32 = imm32; 371 vex_printf("$0x%x", op->Ari.Imm.imm32); 2315 if (0 == (i->Ain.Alu64R.src->Armi.Imm.imm32 & ~0xFFFFF)) { 2328 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32); 2333 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32); 2374 if (fits8bits(i->Ain.Alu64R.src->Armi.Imm.imm32)) { 2378 *p++ = toUChar(0xFF & i->Ain.Alu64R.src->Armi.Imm.imm32); 2383 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm [all...] |
H A D | host_ppc_defs.c | 399 op->Prh.Imm.syned = syned; 400 op->Prh.Imm.imm16 = imm16; 418 if (op->Prh.Imm.syned) 419 vex_printf("%d", (Int)(Short)op->Prh.Imm.imm16); 421 vex_printf("%u", (UInt)(UShort)op->Prh.Imm.imm16); 464 op->Pri.Imm = imm64; 477 vex_printf("0x%llx", dst->Pri.Imm); 1703 ppLoadImm(i->Pin.CMov.dst, i->Pin.CMov.src->Pri.Imm, mode64); 3755 vassert(srcR->Prh.Imm.syned); 3756 vassert(srcR->Prh.Imm [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 254 int64_t Imm; member in class:__anon26165::X86AsmParser::IntelExprStateMachine 263 Scale(1), Imm(imm), Sym(nullptr), StopOnLBrac(stoponlbrac), 271 int64_t getImm() { return Imm + IC.execute(); } 501 IC.pushOperand(IC_IMM, -TmpInt); // Push -Imm. 511 IC.pushOperand(IC_IMM, ~TmpInt); // Push ~Imm. 1225 const MCExpr *Imm = MCConstantExpr::Create(SM.getImm(), getContext()); local 1227 Disp = MCBinaryExpr::CreateAdd(Disp, Imm, getContext()); 1229 Disp = Imm; // An immediate displacement only. 1430 // .Imm gets lexed as a real. 1525 const MCExpr *Imm local [all...] |
H A D | X86Operand.h | 61 struct ImmOp Imm; member in union:llvm::X86Operand::__anon26166 100 return Imm.Val; 438 Res->Imm.Val = Val;
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/external/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 175 struct ImmOp Imm; member in union:__anon26131::SparcOperand::__anon26132 210 return Imm.Val; 241 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break; 312 Op->Imm.Val = Val; 375 const MCExpr *Imm = Op->getImm(); local 379 Op->Mem.Off = Imm;
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 454 bool isLegalICmpImmediate(int64_t Imm) const override; 460 bool isLegalAddImmediate(int64_t Imm) const override; 470 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600InstrInfo.cpp | 79 unsigned DstReg, int64_t Imm) const 84 MachineInstrBuilder(MI).addImm(Imm);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 223 int64_t Imm = MO.getImm(); local 224 O << '#' << Imm; local
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H A D | AArch64ISelLowering.h | 254 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 317 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.cpp | 341 int64_t Imm = Inst.getOperand(0).getImm(); 343 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.h | 50 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
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/external/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 103 const MCExpr *Imm; member in union:__anon26144::SystemZOperand::__anon26145 148 Op->Imm = Expr; 196 return Kind == KindImm && inRange(Imm, MinValue, MaxValue); 200 return Imm;
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.h | 209 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 208 bool SelectMOV64Imm32(SDValue N, SDValue &Imm); 275 inline SDValue getI8Imm(unsigned Imm) { argument 276 return CurDAG->getTargetConstant(Imm, MVT::i8); 281 inline SDValue getI32Imm(unsigned Imm) { argument 282 return CurDAG->getTargetConstant(Imm, MVT::i32); 343 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1)) 344 if (Imm->getAPIntValue().isSignedIntN(8)) 1394 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) { argument 1400 Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64); 1418 Imm 2584 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8); local 2656 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16); local 2678 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32); local [all...] |