Searched refs:CondCodes (Results 1 - 25 of 39) sorted by relevance

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/external/llvm/lib/Target/MSP430/
H A DMSP430.h23 enum CondCodes { enum in namespace:MSP430CC
H A DMSP430InstrInfo.cpp133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
228 MSP430CC::CondCodes BranchCode =
229 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
251 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
/external/llvm/lib/Target/ARM/
H A DThumb2RegisterInfo.h33 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
H A DThumb2ITBlockPass.cpp45 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
107 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
155 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg);
172 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
195 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
212 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg);
H A DThumb2RegisterInfo.cpp40 ARMCC::CondCodes Pred, unsigned PredReg,
H A DThumb1RegisterInfo.h41 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
H A DThumb2InstrInfo.h69 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
H A DARMBaseInstrInfo.h77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
382 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
403 ARMCC::CondCodes Pred, unsigned PredReg,
409 ARMCC::CondCodes Pred, unsigned PredReg,
H A DARMLoadStoreOptimizer.cpp103 ARMCC::CondCodes Pred, unsigned PredReg);
106 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
119 ARMCC::CondCodes Pred,
126 ARMCC::CondCodes Pred, unsigned PredReg,
336 ARMCC::CondCodes Pred, unsigned PredReg) {
416 int Opcode, ARMCC::CondCodes Pred,
616 ARMCC::CondCodes Pred, unsigned PredReg,
710 ARMCC::CondCodes Pred, unsigned PredReg,
795 ARMCC::CondCodes Pred, unsigned PredReg) {
830 ARMCC::CondCodes Pre
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H A DARMBaseRegisterInfo.h172 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
H A DARMBaseRegisterInfo.cpp402 ARMCC::CondCodes Pred,
758 ARMCC::CondCodes Pred = (PIdx == -1)
759 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
H A DThumb2InstrInfo.cpp62 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
215 ARMCC::CondCodes Pred, unsigned PredReg,
624 ARMCC::CondCodes
/external/llvm/lib/Target/NVPTX/
H A DNVPTX.h34 enum CondCodes { enum in namespace:llvm::NVPTXCC
44 inline static const char *NVPTXCondCodeToString(NVPTXCC::CondCodes CC) {
/external/llvm/lib/Target/Sparc/
H A DSparc.h44 enum CondCodes { enum in namespace:llvm::SPCC
81 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
H A DSparcInstrInfo.cpp88 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
182 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
/external/chromium_org/third_party/mesa/src/src/mesa/program/
H A Dprog_execute.h66 GLuint CondCodes[4]; /**< COND_* value for x/y/z/w */ member in struct:gl_program_machine
H A Dprog_execute.c460 if (test_cc(machine->CondCodes[GET_SWZ(swizzle, 0)], condMask) ||
461 test_cc(machine->CondCodes[GET_SWZ(swizzle, 1)], condMask) ||
462 test_cc(machine->CondCodes[GET_SWZ(swizzle, 2)], condMask) ||
463 test_cc(machine->CondCodes[GET_SWZ(swizzle, 3)], condMask)) {
506 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 0)],
511 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 1)],
516 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 2)],
521 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 3)],
545 machine->CondCodes[0] = generate_cc(value[0]);
547 machine->CondCodes[
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/external/chromium_org/third_party/mesa/src/src/mesa/swrast/
H A Ds_fragprog.c198 machine->CondCodes[0] = COND_EQ;
199 machine->CondCodes[1] = COND_EQ;
200 machine->CondCodes[2] = COND_EQ;
201 machine->CondCodes[3] = COND_EQ;
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h27 // The CondCodes constants map directly to the 4-bit encoding of the
29 enum CondCodes { // Meaning (integer) Meaning (floating-point) enum in namespace:llvm::ARMCC
47 inline static CondCodes getOppositeCondition(CondCodes CC) {
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
/external/mesa3d/src/mesa/program/
H A Dprog_execute.h66 GLuint CondCodes[4]; /**< COND_* value for x/y/z/w */ member in struct:gl_program_machine
H A Dprog_execute.c460 if (test_cc(machine->CondCodes[GET_SWZ(swizzle, 0)], condMask) ||
461 test_cc(machine->CondCodes[GET_SWZ(swizzle, 1)], condMask) ||
462 test_cc(machine->CondCodes[GET_SWZ(swizzle, 2)], condMask) ||
463 test_cc(machine->CondCodes[GET_SWZ(swizzle, 3)], condMask)) {
506 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 0)],
511 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 1)],
516 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 2)],
521 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 3)],
545 machine->CondCodes[0] = generate_cc(value[0]);
547 machine->CondCodes[
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/external/mesa3d/src/mesa/swrast/
H A Ds_fragprog.c198 machine->CondCodes[0] = COND_EQ;
199 machine->CondCodes[1] = COND_EQ;
200 machine->CondCodes[2] = COND_EQ;
201 machine->CondCodes[3] = COND_EQ;
/external/chromium_org/third_party/mesa/src/src/mesa/tnl/
H A Dt_vb_program.c252 machine->CondCodes[0] = COND_EQ;
253 machine->CondCodes[1] = COND_EQ;
254 machine->CondCodes[2] = COND_EQ;
255 machine->CondCodes[3] = COND_EQ;
/external/mesa3d/src/mesa/tnl/
H A Dt_vb_program.c252 machine->CondCodes[0] = COND_EQ;
253 machine->CondCodes[1] = COND_EQ;
254 machine->CondCodes[2] = COND_EQ;
255 machine->CondCodes[3] = COND_EQ;
/external/llvm/lib/Target/Sparc/InstPrinter/
H A DSparcInstPrinter.cpp170 O << SPARCCondCodeToString((SPCC::CondCodes)CC);

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