Searched refs:Reg2 (Results 1 - 20 of 20) sorted by relevance

/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp415 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); variable
426 Reg2 = getXRegFromWReg(Reg2);
428 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
431 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
434 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
437 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
440 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
445 Reg2 = getDRegFromBReg(Reg2);
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.h67 void EmitInstrRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2);
69 void EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2,
72 void EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1, unsigned Reg2,
H A DMipsAsmPrinter.cpp732 unsigned Reg2) {
741 Reg1 = Reg2;
742 Reg2 = Temp;
746 I.addOperand(MCOperand::CreateReg(Reg2));
751 unsigned Reg2, unsigned Reg3) {
755 I.addOperand(MCOperand::CreateReg(Reg2));
761 unsigned Reg2, unsigned FPReg1,
765 Reg1 = Reg2;
766 Reg2 = temp;
769 EmitInstrRegReg(MovOpc, Reg2, FPReg
731 EmitInstrRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2) argument
750 EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2, unsigned Reg3) argument
760 EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1, unsigned Reg2, unsigned FPReg1, unsigned FPReg2, bool LE) argument
[all...]
H A DMips16InstrInfo.h117 unsigned Reg1, unsigned Reg2) const;
H A DMips16InstrInfo.cpp266 unsigned Reg1, unsigned Reg2) const {
270 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
280 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
284 MIB3.addReg(Reg2, RegState::Kill);
H A DMipsISelLowering.cpp2268 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); local
2269 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2728 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), local
2730 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h117 unsigned Reg2, bool isKill2) {
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
115 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
/external/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp631 unsigned Reg2 = CSI[idx + 1].getReg(); local
653 assert(AArch64::GPR64RegClass.contains(Reg2) &&
661 assert(AArch64::FPR64RegClass.contains(Reg2) &&
671 << TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx()
682 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2))
706 unsigned Reg2 = CSI[i + 1].getReg(); local
724 assert(AArch64::GPR64RegClass.contains(Reg2) &&
731 assert(AArch64::FPR64RegClass.contains(Reg2) &&
740 << TRI->getName(Reg2) << ")
[all...]
/external/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h101 // UnionGroups - Union Reg1's and Reg2's groups to form a new
104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
H A DTargetInstrInfo.cpp138 unsigned Reg2 = MI->getOperand(Idx2).getReg(); local
149 Reg0 = Reg2;
151 } else if (HasDef && Reg0 == Reg2 &&
169 MI->getOperand(Idx1).setReg(Reg2);
H A DAggressiveAntiDepBreaker.cpp80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) argument
87 unsigned Group2 = GetGroup(Reg2);
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h80 bool contains(unsigned Reg1, unsigned Reg2) const {
81 return contains(Reg1) && contains(Reg2);
/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp645 unsigned Reg2 = MI->getOperand(2).getReg(); local
648 || !isARMLowRegister(Reg2))
650 if (Reg0 != Reg2) {
678 unsigned Reg2 = MI->getOperand(2).getReg(); local
679 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
H A DA15SDOptimizer.cpp84 unsigned Reg1, unsigned Reg2);
464 unsigned Reg1, unsigned Reg2) {
472 .addReg(Reg2)
461 createRegSequence(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Reg1, unsigned Reg2) argument
H A DARMFastISel.cpp2782 unsigned Reg2 = 0; local
2784 Reg2 = getRegForValue(Src2Value);
2785 if (Reg2 == 0) return false;
2798 MIB.addReg(Reg2);
/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h81 bool contains(unsigned Reg1, unsigned Reg2) const {
82 return MC->contains(Reg1, Reg2);
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp252 unsigned Reg2 = MI->getOperand(2).getReg(); local
275 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
279 .addReg(Reg2, getKillRegState(Reg2IsKill))
286 MI->getOperand(0).setReg(Reg2);
290 MI->getOperand(1).setReg(Reg2);
/external/llvm/lib/MC/
H A DMCDwarf.cpp1092 unsigned Reg2 = Instr.getRegister2(); local
1096 Streamer.AddComment(Twine("Reg2 ") + Twine(Reg2));
1100 Streamer.EmitULEB128IntValue(Reg2);
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1139 CodeGenRegister *Reg2 = i1->second; local
1141 if (Reg1 == Reg2)
1143 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1150 if (Reg2 == Reg3)
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5530 unsigned Reg2 = Op2.getReg(); local
5532 unsigned Rt2 = MRI->getEncodingValue(Reg2);

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