Searched refs:SubIdx (Results 1 - 25 of 50) sorted by relevance

12

/external/llvm/lib/Target/ARM/
H A DThumb2RegisterInfo.cpp38 unsigned DestReg, unsigned SubIdx,
50 .addReg(DestReg, getDefRegState(true), SubIdx)
35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DThumb2RegisterInfo.h32 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
H A DThumb1RegisterInfo.h40 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
H A DARMBaseRegisterInfo.h171 DebugLoc dl, unsigned DestReg, unsigned SubIdx,
/external/llvm/lib/CodeGen/
H A DLiveDebugVariables.h43 /// renameRegister - Move any user variables in OldReg to NewReg:SubIdx.
46 /// @param SubIdx If NewReg is a virtual register, SubIdx may indicate a sub-
48 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
H A DExpandPostRAPseudos.cpp88 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
89 unsigned SubIdx = MI->getOperand(3).getImm(); local
91 assert(SubIdx != 0 && "Invalid index for insert_subreg");
92 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
114 MI->RemoveOperand(3); // SubIdx
H A DTargetRegisterInfo.cpp47 if (SubIdx) {
49 OS << ':' << TRI->getSubRegIndexName(SubIdx);
51 OS << ":sub(" << SubIdx << ')'; local
H A DMachineCopyPropagation.cpp121 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); local
122 if (!SubIdx)
124 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
H A DMachineInstr.cpp68 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, argument
71 if (SubIdx && getSubReg())
72 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
74 if (SubIdx)
75 setSubReg(SubIdx);
1042 if (unsigned SubIdx = MO.getSubReg()) {
1044 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
1046 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
1269 unsigned SubIdx,
1267 substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo) argument
[all...]
H A DRegisterCoalescer.cpp180 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
333 "Cannot have a physical SubIdx");
954 unsigned SubIdx) {
978 if (DstInt && !Reads && SubIdx)
988 if (SubIdx && MO.isDef())
994 MO.substVirtReg(DstReg, SubIdx, *TRI);
1298 unsigned SubIdx; member in class:__anon25795::JoinVals
1404 : LI(li), SubIdx(subIdx), NewVNInfo(newVNInfo), CP(cp), LIS(lis),
1443 TRI->composeSubRegIndices(SubIdx, MO->getSubReg()));
1489 V.ValidLanes = V.WriteLanes = TRI->getSubRegIndexLaneMask(SubIdx);
952 updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx) argument
1784 usesLanes(MachineInstr *MI, unsigned Reg, unsigned SubIdx, unsigned Lanes) argument
[all...]
H A DPeepholeOptimizer.cpp265 unsigned SrcReg, DstReg, SubIdx; local
266 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
280 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx);
287 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
288 // SrcReg:SubIdx should be replaced.
290 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
315 // Only accept uses of SrcReg:SubIdx.
316 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
394 .addReg(DstReg, 0, SubIdx);
395 // SubIdx applie
[all...]
/external/llvm/lib/Target/R600/
H A DSIRegisterInfo.h53 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
56 unsigned SubIdx) const;
H A DSIRegisterInfo.cpp109 const TargetRegisterClass *RC, unsigned SubIdx) const {
110 if (SubIdx == AMDGPU::NoSubRegister)
H A DSIInstrInfo.h32 unsigned SubIdx,
38 unsigned SubIdx,
H A DAMDGPUInstrInfo.h55 unsigned &DstReg, unsigned &SubIdx) const override;
/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h336 const char *getSubRegIndexName(unsigned SubIdx) const {
337 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
339 return SubRegIndexNames[SubIdx-1];
343 /// register that are covered by SubIdx.
361 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const {
362 // SubIdx == 0 is allowed, it has the lane mask ~0u.
363 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
364 return SubRegIndexLaneMasks[SubIdx];
456 /// Reg so its sub-register of index SubIdx i
897 unsigned SubIdx; member in class:llvm::TargetRegisterInfo::PrintReg
[all...]
H A DTargetInstrInfo.h114 /// SubIdx.
117 unsigned &SubIdx) const {
199 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
215 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
216 /// SubIdx.
219 unsigned DestReg, unsigned SubIdx,
/external/llvm/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.h316 // registers have a SubIdx sub-register.
318 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
319 return SubClassWithSubReg.lookup(SubIdx);
322 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx, argument
324 SubClassWithSubReg[SubIdx] = SubRC;
328 // containing only SubIdx super-registers of this class.
329 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
332 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, argument
334 SuperRegClasses[SubIdx].insert(SuperRC);
H A DCodeGenRegisters.cpp480 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); local
481 if (!SubIdx)
484 NewIdx->addComposite(SI->first, SubIdx);
506 // Topological signature computed from SubIdx, TopoId(SubReg).
897 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx, argument
901 FindI = SuperRegClasses.find(SubIdx);
1493 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
1494 SubIdx != EndIdx; ++SubIdx) {
1495 const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1798 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; local
1831 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; local
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp436 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
439 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
441 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
446 // VReg has been adjusted. It can be used with SubIdx operands now.
452 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
453 assert(RC && "No legal register class for VT supports that SubIdx");
485 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
494 SubIdx == DefSubIdx &&
506 // VReg may not support a SubIdx sub-register, and we may need to
509 VReg = ConstrainForSubReg(VReg, SubIdx,
[all...]
H A DInstrEmitter.h85 /// supports SubIdx sub-registers. Emit a copy if that isn't possible.
87 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.cpp38 unsigned &SubIdx) const {
H A DAMDGPUInstrInfo.h52 unsigned &DstReg, unsigned &SubIdx) const;
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp161 unsigned &SubIdx) const {
168 SubIdx = PPC::sub_32;
651 unsigned SubIdx; local
655 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
656 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
657 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
658 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
659 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
660 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
661 case PPC::PRED_UN: SubIdx
1382 unsigned SubIdx = UseMI->getOperand(3).getSubReg(); local
[all...]

Completed in 2633 milliseconds

12