/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ResourcePriorityQueue.cpp | 98 MVT VT = ScegN->getSimpleValueType(i); 136 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); 336 MVT VT = SU->getNode()->getSimpleValueType(i); 345 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); 488 MVT VT = ScegN->getSimpleValueType(i); 499 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
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H A D | InstrEmitter.cpp | 104 MVT VT = Node->getSimpleValueType(ResNo); 127 MVT VT = Node->getSimpleValueType(Op.getResNo()); 226 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { 228 TLI->getRegClassFor(Node->getSimpleValueType(i)); 289 TLI->getRegClassFor(Op.getSimpleValueType()); 487 TLI->getRegClassFor(Node->getSimpleValueType(0)); 510 Node->getOperand(0).getSimpleValueType(), 542 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
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H A D | TargetLowering.cpp | 1230 isCondCodeLegal(SwappedCC, N0.getSimpleValueType()))) 1476 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) 1742 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) { 1749 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 1752 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 1755 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 1758 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 1762 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 1765 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 1768 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) [all...] |
H A D | LegalizeDAG.cpp | 727 MVT VT = Value.getSimpleValueType(); 840 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(), 888 MVT VT = Node->getSimpleValueType(0); 1212 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType(); 1664 MVT OpVT = LHS.getSimpleValueType(); 2147 switch (Node->getSimpleValueType(0).SimpleTy) { 2165 switch (Node->getSimpleValueType(0).SimpleTy) { 2180 switch (Node->getSimpleValueType(0).SimpleTy) { 2227 switch (Node->getSimpleValueType(0).SimpleTy) { 2284 switch (Node->getSimpleValueType( [all...] |
H A D | LegalizeVectorOps.cpp | 211 MVT ValVT = ST->getValue().getSimpleValueType(); 359 MVT VT = Op.getSimpleValueType();
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H A D | ScheduleDAGRRList.cpp | 1973 MVT VT = N->getSimpleValueType(i); 2020 MVT VT = N->getSimpleValueType(i); 2131 MVT VT = PN->getSimpleValueType(0); 2143 MVT VT = PN->getSimpleValueType(0); 2150 MVT VT = PN->getSimpleValueType(i); 2167 MVT VT = N->getSimpleValueType(i);
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H A D | ScheduleDAGSDNodes.cpp | 571 ValueType = Node->getSimpleValueType(DefIdx);
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H A D | SelectionDAGBuilder.cpp | 256 assert(RegisterVT == Parts[0].getSimpleValueType() && 3632 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType(); 3681 getValue(I.getValOperand()).getSimpleValueType(), 6246 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo)); 6249 OpVT = TLI->getSimpleValueType(CS.getType()); 6543 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
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H A D | SelectionDAG.cpp | 3349 assert(VT.getSimpleVT() <= N1.getSimpleValueType() && 3360 if (VT.getSimpleVT() == N1.getSimpleValueType()) 3595 assert(N2.getSimpleValueType() <= N1.getSimpleValueType() && 3605 if (VT.getSimpleVT() == N2.getSimpleValueType())
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H A D | DAGCombiner.cpp | 2812 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) && 2814 getSetCCResultType(N0.getSimpleValueType()))))) 3392 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) && 3744 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) { 4619 MVT VT = N->getSimpleValueType(0); 9521 switch (CFP->getSimpleValueType(0).SimpleTy) {
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H A D | SelectionDAGISel.cpp | 2742 MVT CurNodeVT = N.getSimpleValueType();
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 4024 MVT VT = SVOp->getSimpleValueType(0); 4319 MVT VT = SVOp->getSimpleValueType(0); 4535 MVT VT = N->getSimpleValueType(0); 4553 MVT VT = N->getSimpleValueType(0); 4580 MVT VT = N->getSimpleValueType(0); 4610 MVT VT = N->getSimpleValueType(0); 4634 MVT VT = N->getSimpleValueType(0); 4658 MVT VT = SVOp->getSimpleValueType(0); 4688 MVT VecVT = N->getOperand(0).getSimpleValueType(); 4703 MVT VecVT = N->getSimpleValueType( [all...] |
H A D | X86ISelDAGToDAG.cpp | 503 MVT SrcVT = N->getOperand(0).getSimpleValueType(); 504 MVT DstVT = N->getSimpleValueType(0); 795 MVT VT = N.getSimpleValueType(); 843 MVT VT = N.getSimpleValueType(); 916 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt; 926 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() - 927 X.getOperand(0).getSimpleValueType().getSizeInBits(); 935 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ); 942 MVT VT = N.getSimpleValueType(); 1071 if (X.getSimpleValueType() [all...] |
H A D | X86FastISel.cpp | 1288 MVT SrcVT = TLI.getSimpleValueType(I->getOperand(0)->getType()); 2615 MVT VT = TLI.getSimpleValueType(Arg.getType());
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCTRLoops.cpp | 339 TLI->getSimpleValueType(CI->getArgOperand(0)->getType(), true);
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H A D | PPCISelLowering.cpp | 4197 switch (Arg.getSimpleValueType().SimpleTy) { 4221 if (Arg.getSimpleValueType().SimpleTy == MVT::f32 && 4277 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 || 4278 Arg.getSimpleValueType() == MVT::v2i64) ? 4300 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 || 4301 Arg.getSimpleValueType() == MVT::v2i64) ? 4569 switch (Arg.getSimpleValueType().SimpleTy) { 5085 switch (Op.getSimpleValueType().SimpleTy) {
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/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 162 MVT getSimpleValueType() const { function in class:llvm::SDValue 655 MVT getSimpleValueType(unsigned ResNo) const {
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 455 switch (N->getSimpleValueType(0).SimpleTy) { 491 switch (N->getSimpleValueType(0).SimpleTy) { 502 switch (N->getSimpleValueType(0).SimpleTy) {
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H A D | AArch64ISelLowering.cpp | 6779 MVT NarrowTy = N.getSimpleValueType(); 6950 MVT VT = N->getSimpleValueType(0); 7023 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
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/external/llvm/include/llvm/Target/ |
H A D | TargetLowering.h | 659 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const { function in class:llvm::TargetLoweringBase
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 453 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy; 1823 MVT::SimpleValueType SourceVT = N1.getNode()->getSimpleValueType(0).SimpleTy;
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 1821 MVT VT = Op.getSimpleValueType(); 1833 MVT VT = Op.getSimpleValueType();
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H A D | SIISelLowering.cpp | 1311 return getRegClassFor(Op.getSimpleValueType());
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H A D | R600ISelLowering.cpp | 1985 isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 9119 MVT FloatTy = Op.getSimpleValueType().getVectorElementType(); 9120 MVT IntTy = N->getSimpleValueType(0).getVectorElementType(); 9170 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType(); 9171 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
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