| 06b9bc66d58dd6b2adf16142ca05875c953fcc5f |
|
21-Jan-2017 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Support the force_glsl_version driconf option.
Gallium drivers have had this for a while. It makes sense to support
it consistently across drivers, so expose it in i965 as well.
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 2f7a7ae13196c58eddea75fc51637f8c2a8579b0)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e6ae19944d977dc91bc45adff679337182c20683 |
|
24-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rework gl_TessLevel*[] handling to use NIR compact arrays.
Treating everything as scalar arrays allows us to drop a bunch of
special case input/output munging all throughout the backend.
Instead, we just need to remap the TessLevel components to the
appropriate patch URB header locations in remap_patch_urb_offsets().
We also switch to treating the TES input versions of these as ordinary
shader inputs rather than system values, as remap_patch_urb_offsets()
just makes everything work out without special handling.
This regresses one Piglit test:
arb_tessellation_shader-large-uniforms/GL_TESS_CONTROL_SHADER-array-at-limit
The compiler starts promoting the constant arrays assigned to gl_TessLevel*
to uniform arrays. Since the shader also has a uniform array that uses
the maximum number of uniform components, this puts it over the uniform
component limit enforced by the linker. This is arguably a bug in the
constant array promotion code (it should avoid pushing us over limits),
but is unlikely to penalize any real application.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 90c51ccf82e04d06aa63aea49121165b7f2e8991 |
|
08-Nov-2016 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Always set MaxViewports and related limits
Since 9d6ca7c3, there should be no performance hit for having
MaxViewports > 1. Always set this context state. This eliminates the
need to update this conditional as we add support for OES_viewport_array
on older GPUs.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a1da57c19c27505b9eab4792355f2f1b5c774a0a |
|
04-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
st/mesa/glsl/i965: move ImageUnits and ImageAccess fields to gl_program
Having it here rather than in gl_linked_shader allows us to simplify
the code.
Also it is error prone to depend on the gl_linked_shader for programs
in current use because a failed linking attempt will free infomation
about the current program. In i965 we could be trying to recompile
a shader variant but may have lost some required fields.
We drop the memset on ImageUnits because gl_program is already
created using rzalloc().
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a98f2e53e1c669dee3114badcce261e564748af4 |
|
04-Jan-2017 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: add a kernel_features bitfield to intel screen
We can use this to track various features that may or may not be supported
by the hw / kernel. Currently, we usually do this by checking the generation
and supported command parser versions in various places thoughtout the driver
code. With this patch, we centralize all these checks in just once place at
screen creation time, then we just query the bitfield wherever we need to
check if a particular feature is supported.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 1f1b8def48f5e4015d15e6cde42b1b7705459f17 |
|
04-Jan-2017 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: get rid of brw->can_do_pipelined_register_writes
Instead, check the screen field directly.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 02a44484f01848775642661c4dd38dfd56f6c345 |
|
04-Jan-2017 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Move the pipelined test for SO register access to the screen
Moving the test to the screen places it alongside the other global HW
feature tests that want to be shared between contexts.
Also, we need to know if we support pipelined register writes at
screen creation time so that we can tell if we can expose OpenGL 4.0
in gen7.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 1a8f2629e6d76517bc5b16e9f69cfa7cb4a342bd |
|
03-Jan-2017 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: remove brw_context dependency from intel_batchbuffer_init()
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ba30e0ca20c1e25e076da7f0779f71da563cf2f9 |
|
03-Jan-2017 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: make intel_batchbuffer_free() take a batchbuffer as argument
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 96c9ec9c274d54c5acf0d705e59188fc70b83bec |
|
22-Apr-2015 |
Robert Bragg <robert@sixbynine.org> |
i965: Remove perf monitor/query backend
In its current state the unified i965 backend for
AMD_performance_monitor and INTEL_performance_query isn't able to report
meaningful Observation Architecture metrics since we haven't so far had
the necessary kernel support to fully configure the OA unit, nor the
corresponding support for normalizing the counters into a form that can
be usefully interpreted by application developers (as opposed to raw
values that may, for example, scale by the number of EUs there are).
So that we can focus on implementing just one of these extensions fully
and since we anticipate some significant backend changes as we look to
use a new kernel interface to configure the OA unit, this patch removes
the current backend. This will simplify our ability to update the
frontend infrastructure and backend interface before updating our
support for performance counters.
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e9133dd90ec498cfb6a23fa22504e06488352c51 |
|
03-Nov-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Increase max texture to 16k for gen7+
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98297
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 62b8dbf35e0971ec9a310cf4b3b119c9fa1e8a70 |
|
28-Nov-2016 |
Ilia Mirkin <imirkin@alum.mit.edu> |
i965/gen7: expose larger gather offsets
This matches the capabilities of the hardware.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9c7717c066b4a315ed6dccd8a48d9eaf81a5b33f |
|
15-Sep-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Provide slice details to color resolver
v2: Make intel_miptree_resolve_color() take start layer and
layer count.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 12010b92263dd63a6cef785c730ff877f7912cc8 |
|
10-Jun-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Add new interface for full color resolves
Upcoming patches will introduce fast clear in level/layer
granularity like the driver does already for depth/hiz. This patch
introduces equivalent full resolve option.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ba40c8b03cb5250af771c50ff785bd5ec293e3c1 |
|
27-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get num_images from shader_info rather than gl_linked_shader
This is a step towards freeing gl_linked_shader after linking.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7bcb94bc2fc45fde806ad3fd062bf2ce97342359 |
|
03-Nov-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/compute: Allow ARB_compute_shader in compat profile
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97447
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Evan Odabashian <eodabash@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c0f505c7ef179249673e764de51b969e07fc8194 |
|
21-Oct-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Add function to indicate when sampling with hiz is supported
Currently it indicates that this is never supported, but soon it will
be supported for gen8+^w gen9+
v2 by Ben:
- Explicitly disable aux_hiz for gen < 9 (with comment)
- squashed in next patch to avoid unused and useless functions
i965: Support sampling with hiz during rendering
For gen8, we can sample from depth while using the hiz buffer. This
allows us to sample depth without resolving from hiz to the depth
texture.
To do this we must resolve to hiz before drawing so we can use the hiz
buffer to sample while rendering. Hopefully the hiz buffer will
already be resolved in most cases because it was previously rendered,
meaning the hiz resolve is a no-op.
Note that this is still controlled by the
intel_miptree_sample_with_hiz function, and we will enable hiz
sampling for gen8 in a separate patch.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> (v2)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| fe764477b04866cf4598005e94b374dcbca379e0 |
|
25-Oct-2016 |
Tapani Pälli <tapani.palli@intel.com> |
i956: set RobustAccess true when is supported
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3423488d55b9c483fcdb3996eb89b424c1031d24 |
|
19-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
st/mesa/r200/i915/i965: eliminate gl_fragment_program
Here we move OriginUpperLeft and PixelCenterInteger into gl_program
all other fields have been replace by shader_info.
V2: Don't use anonymous union/structs to hold vertex/fragment fields
suggested by Ian.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 17e28a1571b6141368fefc84cc8b0a3b4e52f8ee |
|
19-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965/mesa/st/swrast: set fs shader_info directly and switch to using it
Note we access shader_info from the program struct rather than the
nir_shader pointer because shader cache won't create a nir_shader.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e1af20f18a86f52a9640faf2d4ff8a71b0a4fa9b |
|
13-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
nir/i965/anv/radv/gallium: make shader info a pointer
When restoring something from shader cache we won't have and don't
want to create a nir_shader this change detaches the two.
There are other advantages such as being able to reuse the
shader info populated by GLSL IR.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b526a9b708b48c3d1c394783cba99f11eb17d0b9 |
|
05-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get outputs read from nir info
This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.
This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9ea48fc877f1b0d78edb37cafb4067bab776a74a |
|
28-Sep-2016 |
Chad Versace <chadversary@chromium.org> |
i965/sync: Replace 'intel' prefix with 'brw'
This is yet another patch for the great renaming begun long ago.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| cd69d3f929692c60ebed8fafdf65863d68e03052 |
|
27-Sep-2016 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/gen8+: Enable GL_OES_viewport_array
This patch causes 2 regressions in khronos' gles cts tests
on various intel platforms.
Failing tests:
ES3-CTS.functional.state_query.integers.viewport_getinteger
ES3-CTS.functional.state_query.integers.viewport_getfloat
Here is an explanation of what's causing the failures:
CTS tests are not clamping the x, y location of the viewport's
bottom-left corner as recommended by ARB_viewport_array and
OES_viewport_array:
"The location of the viewport's bottom-left corner, given by (x,y), are
clamped to be within the implementation-dependent viewport bounds range.
The viewport bounds range [min, max] tuple may be determined by
calling GetFloatv with the symbolic constant VIEWPORT_BOUNDS_RANGE_OES"
Khronos CTS merge request to fix the test case:
https://gitlab.khronos.org/opengl/cts/merge_requests/399
V2: Initialize the relevant variables for GL_OES_viewport_array on gen8+
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9d6ca7c3d091e1ab71ce2f75bf4f13dc8844d801 |
|
26-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Only emit 1 viewport when possible.
In core profile, we support up to 16 viewports. However, in the
majority of cases, only 1 of them is actually used - we only need
the others if the last shader stage prior to the rasterizer writes
gl_ViewportIndex.
Processing all 16 viewports adds additional CPU overhead, which hurts
CPU-intensive workloads such as Glamor. This meant that switching to
core profile actually penalized Glamor to an extent, which is
unfortunate.
This patch tracks the number of relevant viewports, switching between
1 and ctx->Const.MaxViewports if gl_ViewportIndex is written. A new
BRW_NEW_VIEWPORT_COUNT flag tracks this. This could mean re-emitting
viewport state when switching, but hopefully this is offset by doing
1/16th of the work in the common case. The new flag is also lighter
weight than BRW_NEW_VUE_MAP_GEOM_OUT, which we were using in one case.
According to Eric Anholt, x11perf -copypixwin10 performance improves by
11.5094% +/- 3.10841% (n=10) on his Skylake.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 94d0e7dc0848a5f70a550f2294e459eab51ace8f |
|
22-Sep-2016 |
Lionel Landwerlin <lionel.g.landwerlin@intel.com> |
i965: get rid of duplicated values from gen_device_info
Now that we have gen_device_info mutable, we can update its values and drop
all copies we had in brw_context.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| bc24590f0c579a2528fd94eb8d40dd4ce12eba29 |
|
22-Sep-2016 |
Lionel Landwerlin <lionel.g.landwerlin@intel.com> |
intel/i965: make gen_device_info mutable
Make gen_device_info a mutable structure so we can update the fields that
can be refined by querying the kernel (like subslices and EU numbers).
This patch does not make any functional change, it just makes
gen_get_device_info() fill a structure rather than returning a const
pointer.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9694b23f66f4c41407289fb7d3ff25321042ef49 |
|
01-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename intelScreen to screen.
"intelScreen" is wordy and also doesn't fit our style guidelines.
"screen" is shorter, which is nice, because we use it fairly often.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 8fec9fbb9f78c1cbc539b28cd914fe366fa7e344 |
|
01-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename __DRIScreen pointers to "dri_screen".
I want to use "screen" as the variable name for a struct intel_screen
pointer. This means that we can't use it for __DRIscreen pointers.
Sometimes we called it "screen", sometimes "sPriv", sometimes
"driScrnPriv", and sometimes "psp" (Pointer to Screen Private?).
The last one is particularly confusing because we use "psp" to refer to
the Gen4 PIPELINED_STATE_POINTERS packet as well.
Let's be consistent. "dri_screen" is clear, and it's not used often
enough that I'm worried about the verbosity.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 24be6306609179efddfb7e5cc6ec5d6a335c9b88 |
|
12-Sep-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
Revert "i965: Drop the maximum 3D texture size to 512 on Sandy Bridge"
This reverts commit 6ba88bce64b343761aabe3a6c7ee285c6020a959. The commit
was erroneous because GL has a separate limit, GL_MAX_FRAMEBUFFER_LAYERS
which guards the number of layers you are allowed to render into.
The GL 4.5 spec says:
"The framebuffer attachment point attachment is said to be framebuffer
attachment complete if [...] all of the following conditions are true:
[...]
If image is a three-dimensional, one- or two-dimensional array, or
cube map array texture and the attachment is layered, the depth or
layer count of the texture is less than or equal to the value of the
implementation-dependent limit MAX_FRAMEBUFFER_LAYERS."
and goes on to say that "framebuffer complete" requires all attachments to
be "framebuffer attachment complete".
On Sandy Bridge, we set GL_MAX_FRAMEBUFFER_LAYERS to 512 so creating a 3D
texture bigger than 512 is fine; you just can't render into all of the
slices at once.
Fixes ES3-CTS.gtf.GL3Tests.npot_textures.npot_tex_image on Sandy Bridge
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e54b70b3d4e88c71b47a9123d496dd05e0e056cd |
|
08-Sep-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/rbc: Clarify rational given for shader image resolves
Original commit added documentation explaining lossless compression
case:
commit 56f29911ec9da25c78fbd3d4945d499e65ca4b5a
Author: Topi Pohjolainen <topi.pohjolainen@intel.com>
Date: Tue Feb 2 10:00:41 2016 +0200
i965: Add a flag telling color resolve pass to ignore CCS_E
It, however, easily gives the impression that the sole purpose
of the intel_miptree_resolve_color() is to address lossless
compression. Original intention is to document the lack of
INTEL_MIPTREE_IGNORE_CCS_E flag given for the resolve call.
This patch fixes this along with a typo found spotted further
down.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 22d9a4824baf0bf89bb8e39025ad01fecb213888 |
|
04-Sep-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Track non-compressible sampling of renderbuffers
v3:
- Actually set the flags when needed instead of falsely
overwriting them (Jason).
- Use more generic name for flag (dropped RENDERBUFFER)
- Consult also shader images
v4:
- Consult only lossless compressd shader images
v5:
- Check the existence of renderbuffer before considering
if it matches the given miptree
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 979d0aca6277975986f5f278cad0f37616c9d91f |
|
26-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
intel: Rename brw_get_device_name/info to gen_get_device_name/info
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 527f37199929932300acc1688d8160e1f3b1d753 |
|
23-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
intel: s/brw_device_info/gen_device_info/
Generated by:
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a0b1260fe0577e504c8ef31c07e13025324af8f8 |
|
28-Aug-2016 |
Ilia Mirkin <imirkin@alum.mit.edu> |
i965: enable OES_primitive_bounding_box with the no-op implementation
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a14d1b63ce74773bec34d0c2b24b7d6fc36d0330 |
|
16-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Add a blorp_context struct and init/finish funcs
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 8d78b096f8bbcad5e15000539ee475a8733140ca |
|
12-Jun-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/gen7: Copy stencil when sampling the stencil texture
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 30fee52036ac5e0180073ace4a8fd760556495be |
|
15-Jun-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/hsw: Don't advertise more than 64 threads for compute shaders
thread_width_max in the GPGPU walker command limits us to a maximum of
64 threads.
This fixes a crash on Haswell in the OpenGLES 3.1 conformance test
suite which tests the advertised limits of the max invocation counts.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f92a87a14068dd17a32b41b1586421cef6eaa37f |
|
24-Aug-2016 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Embrace "unlimited" GTT mmap support
From about kernel 4.9, GTT mmaps are virtually unlimited. A new
parameter, I915_PARAM_MMAP_GTT_VERSION, is added to advertise the
feature so query it and use it to avoid limiting tiled allocations to
only fit within the mappable aperture.
A couple of caveats:
- fence support is still limited by stride to 262144 and the stride
needs to be a multiple of tile_width (as before, and same limitation as
the current 3D pipeline in hardware)
- the max_gtt_map_object_size forcing untiled may be hiding a few bugs
in handling of large objects, though none were spotted in piglits.
See kernel commit 4cc6907501ed ("drm/i915: Add I915_PARAM_MMAP_GTT_VERSION
to advertise unlimited mmaps").
v2: Include some commentary on mmap virtual space vs CPU addressable
space.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 99fb167839c8c9888f8de78e3b96de23f92a1012 |
|
01-Jul-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Resolve color for non-coherent FB fetch at UpdateState time.
This is required because the sampler unit used to fetch from the
framebuffer is unable to interpret non-color-compressed fast-cleared
single-sample texture data. Roughly the same limitation applies for
surfaces bound to texture or image units, but unlike texture sampling,
non-coherent framebuffer fetch is by definition non-coherent with
previous rendering, so the brw_render_cache_set_check_flush() call can
be omitted except after resolve.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e2dd3ce976c5cfcd41d040fc37c6be5b8373c3e9 |
|
23-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Add an isl_device to the brw_context
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f78a6b1ce398a537d77c25b1a93f156109086975 |
|
24-Jun-2016 |
Rob Clark <robclark@freedesktop.org> |
glsl: add driconf to zero-init unintialized vars
Some games are sloppy.. perhaps because it is defined behavior for DX or
perhaps because nv blob driver defaults things to zero.
So add driconf param to force uninitialized variables to default to zero.
This issue was observed with rust, from steam store. But has surfaced
elsewhere in the past.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 1fb8c6df884c2a17cf980c4ea32db4c214903b55 |
|
30-Jun-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
glsl/mesa: split gl_shader in two
There are two distinctly different uses of this struct. The first
is to store GL shader objects. The second is to store information
about a shader stage thats been linked.
The two uses actually share few fields and there is clearly confusion
about their use. For example the linked shaders map one to one with
a program so can simply be destroyed along with the program. However
previously we were calling reference counting on the linked shaders.
We were also creating linked shaders with a name even though it
is always 0 and called the driver version of the _mesa_new_shader()
function unnecessarily for GL shader objects.
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 6ba88bce64b343761aabe3a6c7ee285c6020a959 |
|
09-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Drop the maximum 3D texture size to 512 on Sandy Bridge
The RenderTargetViewExtent field of RENDER_SURFACE_STATE is supposed to be
set to the depth of a 3-D texture when rendering. Unfortunatley, that
field is only 9 bits on Sandy Bridge and prior so we can't actually bind
a 3-D texturing for rendering if it has depth > 512. On Ivy Bridge, this
field was bumpped to 11 bits so we can go all the way up to 2048. On Iron
Lake and prior, we don't support layered rendering and we use OffsetX/Y
hacks to render to particular layers so 2048 is ok there too.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c319512e16f19bf1f558670981bbb4af510ba9f4 |
|
01-Jun-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use a uniform for gl_PatchVerticesIn in the TCS on Gen8+.
We still need to recompile the passthrough shader when this value
changes, as it also affects the output vertex count. But otherwise,
we can eliminate recompiles on Gen8+.
We probably want to do this for Gen7 as well, but that requires
rewriting the input release code to use a loop, which is a trade-off
I'd need to consider in more detail.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 1bc194cd64085d07f1aae319cb6fb3c99d69aaeb |
|
01-Jun-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use a uniform for gl_PatchVerticesIn in the TES.
Fixes three GL44-CTS.tessellation_shader subtests:
- max_patch_vertices
- single.max_patch_vertices
- tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn
These use gl_PatchVerticesIn in the TES, but don't link against a
TCS (which would allow the linker to lower it to a constant). We had
no handling for the system value in the backend, so it would just
assert fail.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e7ab358e8186dd8651cf920d4db1500c60ccd2fc |
|
13-Jun-2016 |
Tomasz Figa <tfiga@chromium.org> |
i965: Check return value of screen->image.loader->getBuffers (v2)
The images struct is an uninitialized local variable on the stack. If the
callback returns 0, the struct might not have been updated and so should
be considered uninitialized. Currently the code ignores the return value,
which (depending on stack contents) might end up in reading a non-zero
value from images.image_mask and dereferencing further fields.
Another solution would be to initialize image_mask with 0, but checking
the return value seems more sensible and it is what Gallium is doing.
v2: fix typos in commit message,
fix indentation,
remove unnecessary parentheses and pointer dereference to keep line
length reasonable.
Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| be32a2132785fbc119f17e62070e007ee7d17af7 |
|
11-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/compiler: Bring back the INTEL_PRECISE_TRIG environment variable
This was removed in d9546b0c5d and replced with the precise_trig driconf
option. However, we still need precise trig in the Vulkan driver so this
commit brings back the environment variable and compiler->precise_trig is
effectively the logical OR of the two.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96484
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 667e5cec760d1908af73a40de28c53848b5b70a0 |
|
13-Jun-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't leak scratch BOs for TCS/TES.
These need to be freed too.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d9546b0c5d1a5136a92276cdd7c14883f0c62737 |
|
11-May-2016 |
Gurchetan Singh <gurchetansingh@chromium.org> |
i965: Integrate precise trig into configuration infrastructure
With this change, to enable precise SIN and COS instructions
on Intel hardware, one can put
<option name="precise_trig" value="true"/>
in the proper drirc file.
V2: Make option name more generic
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Stephane Marchesin <stephane.marchesin@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b1f22c6317940dac543e44dd638ea9f4fbcd6ca7 |
|
01-Jun-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Enable cross-thread constants and compact local IDs for hsw+
The cross thread constant support appears on Haswell. It allows us to
upload a set of uniform data for all threads without duplicating it
per thread.
One complication is that cross-thread constants are loaded into
registers before per-thread constants. Previously, our local IDs were
loaded before the uniform data and treated as 'payload' data, even
though they were actually pushed into the registers like the other
uniform data.
Therefore, in this patch we simultaneously enable a newer layout where
each thread now uses a single uniform slot for a unique local ID for
the thread. This uniform is handled specially to make sure it is added
last into the uniform push constant registers. This minimizes our
usage of push constant registers, and maximizes our ability to use
cross-thread constants for registers.
To swap from the old to the new layout, we also need to flip some
lowering pass switches to let our driver handle the lowering instead.
We also no longer force thread_local_id_index to -1.
v4:
* Minimize size of patch that switches from the old local ID layout
to the new layout (Jason)
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7b9def35835232a10010f256b9c108219f97f752 |
|
21-May-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
glsl: Add glsl LowerCsDerivedVariables option
v2:
* Move lower flag to context constants. (Ken)
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 30e9e6bd071097fd602a15f488b7eead45460885 |
|
31-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/gen9: Configure rbc buffers as plain for non-rbc tex views
Fixes rendering in Shadow of Mordor with rbc. Application writes
RGBA_UNORM texture filling it with values the application wants to
later on treat as SRGB_ALPHA.
Intel driver enables lossless compression for the buffer by the time
of writing. However, the driver fails to make sure the buffer can be
sampled as something else later on and unfortunately there is
restriction in the hardware for using lossless compression for srgb
formats which looks to extend itself to the sampling engine also.
Requesting srgb to linear conversion on top of compressed buffer
results the color values to be pretty much garbage.
Fortunately none of tracked benchmarks showed a regression with
this.
v2 (Matt): Add missing space
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 357495b94dad4101a5491ed30782574162de58db |
|
26-Apr-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Update compute workgroup size limit calculation for SIMD32.
This should have the side effect of enabling the ARB_compute_shader
extension on Gen8+ hardware and all Gen7 platforms that didn't
previously expose it (VLV and IVB GT1) due to the number of hardware
threads per subslice being insufficient in SIMD16 mode.
v2: Bump workgroup size limit for GLES too (Jordan).
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 1c1873b93b9aa30c8e9275000f813bce69ed99e4 |
|
21-May-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
mesa: Implement glGet*(GL_PRIMITIVE_RESTART_FOR_PATCHES_SUPPORTED).
Technically, this was introduced with GL 4.4. However, I believe it
was intended to be retroactive. As far as I know, AMD has never
supported primitive restart with patches, while NVidia and Intel do.
This necessitated the need for a query which would allow applications
to figure out whether this was usable or not.
I decided to expose it everywhere ARB_tessellation_shader is exposed.
(It's also in both OES and EXT_tessellation_shader.)
Enable this for i965 and Gallium drivers which expose the capability.
v2: Fix a bug in the state_tracker code (caught by Ilia Mirkin).
Bugzilla: https://cvs.khronos.org/bugzilla/show_bug.cgi?id=10364
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 09e041d61d367ff3a9e8492521606090050255d4 |
|
12-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Use blorp for all clears
We used to use a meta path on gen8 but we haven't since c7cf17ae758. We
might as well delete the meta path since blorp works on all gens.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 96d43f2d087e23ab692d43fc48fe1be30e923ae0 |
|
05-May-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Reimplement ARB_transform_feedback2 on Haswell and later.
My old implementation accumulated <start, end> pairs in a buffer,
and eventually processed that data on the CPU. This meant flushing
the batchbuffer and waiting for it to completely execute before we
could map it, resulting in really long stalls. We could also run out
of space in the buffer, and have to do this early.
Instead, we can use Haswell's MI_MATH command to do the (end - start)
subtraction, as well as the multiplication by 2 or 3 to convert from
the number of primitives written to the number of vertices written.
We still need to CS stall to read the counters, but otherwise everything
is completely pipelined - there's no CPU<->GPU synchronization required.
It also uses only 80 bytes in the buffer, no matter what.
Improves performance in Manhattan on Skylake GT3e at 800x600 by
6.1086% +/- 0.954166% (n=9). At 1920x1080, improves performance
by 2.82103% +/- 0.148596% (n=84).
v2: Fix number of primitives -> number of vertices calculation for
GL_TRIANGLES (I was multiplying by 4 instead of 3.) Caught by
Jordan Justen.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f00c399bae7376bad2257d085fe754adfaa11cc8 |
|
19-Apr-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Implement ARB_query_buffer_object for HSW+
v2:
* Declare loop index variable at loop site (idr)
* Make arrays of MI_MATH instructions 'static const' (idr)
* Remove commented debug code (idr)
* Updated comment in set_query_availability (Ken)
* Replace switch with if/else in hsw_result_to_gpr0 (Ken)
* Only divide GL_FRAGMENT_SHADER_INVOCATIONS_ARB by 4 on
hsw and gen8 (Ken)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b0e3ba61b5f8bb285472d5acda5ff233b05aeef4 |
|
07-Apr-2016 |
Haixia Shi <hshi@chromium.org> |
dri/i965: extend GLES3 sRGB workaround to cover all formats
It is incorrect to assume BGRA byte order for the GLES3 sRGB workaround.
v2: use _mesa_get_srgb_format_linear to handle all formats
Signed-off-by: Haixia Shi <hshi@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d1ab544bb883d040576f0bd7f28ad3cda4c8ae05 |
|
08-Feb-2016 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965/chv: Display proper branding
"Braswell" is a Cherryview based *thing*. It unfortunately requires extra
information to determine its marketing name. Unlike all previous products, and
hopefully all future ones, there is no unique 1:1 mapping of PCI device ID to
brand string.
I put up a fight about adding any complexity to our GL renderer string code for
a very long time. However, a wise man made a comment to me that I couldn't argue
with: if a user installs Windows on their hardware, the brand string should be
the same as what we display in Linux. The Windows driver apparently does this
check, so we should too.
Note that I did manage to find a good use for this info anyway in the compute
shader thread counts.
v2: memcpy instead of strncpy, and some minor changes (Matt)
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3dc3dbc8d826255d60e2aca8822b77619ace206a |
|
09-Feb-2016 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965/chv: Check that compute threads are above threshold
The way we are organizing this code, the statically configured max_cs_threads
should always be the minimum value we actually support (ie. are aware of). As a
result, we can fall back to that if we get invalid numbers from the kernel (ie.
when the query succeeds, but the result is lower than expected).
I was originally planning to use an assert, but there is no reason to be so
mean.
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9dd20b715af864ab771e36373f213c6cb4ca4bc1 |
|
09-Feb-2016 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965/chv: Use kernel provided info for max_cs_threads
With the previous patches, the code can find out the actual number of available
compute threads. It is enabled only for Cherryview since that is the only
platform I know for a fact has shipped devices which can benefit from this. It
seems like other platforms /might/ benefit from this because of fused
configurations which /might/ have shipped. Fallback code is still there.
v2: Some minor adjustments from Matt
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9ec246796f95996868d61ffc9b52a2c1811bb66d |
|
03-Mar-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set MaxFramebufferWidth/Height to 16384, not viewport.
dEQP-GLES31.functional.fbo.no_attachments.maximums.{all,height,size,width}
started hitting assertion failures when emitting SURFACE_STATE, after
commit e8fd60e7891c7 where Samuel increased the maximum viewport size to
32768, from 16384.
MaxFramebufferWidth/Height were being set to the maximum viewport size,
but are actually limited by the SURFACE_STATE width/height field range,
which is 16384 on Gen7+ (where ARB_framebuffer_no_attachments is
exposed). So, reduce these to 16384 explicitly.
Fixes assert fails in the above mentioned dEQP tests. (Those tests
still fail, however.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 82be7735f32776e76300de3602a72fc236b7261e |
|
24-Nov-2015 |
Eduardo Lima Mitev <elima@igalia.com> |
i965/formatquery: Respond queries SAMPLES and NUM_SAMPLE_COUNTS
This effectively disables old QuerySamplesForFormat driver hook, since it is
never called by Mesa anymore.
v2: Call brw_query_samples_for_format() with a dummy buffer to calculate num
samples, to avoid modifying the original buffer.
Reviewed-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2dabff9068a86a070615df587e4e9327b1d1ca6e |
|
14-Nov-2015 |
Eduardo Lima Mitev <elima@igalia.com> |
i965: Move brw_query_samples_for_format() to brw_queryformat.c
Now that there is a dedicated source file for internal format queries, this
function belongs there.
Reviewed-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 28144c4476343a5e2f679ce96ec72cddc5762b04 |
|
27-Oct-2015 |
Eduardo Lima Mitev <elima@igalia.com> |
i965: Add boilerplate function for QueryInternalFormat driver hook
By default, we call back the driver's hook fallback function that has generic
implementations for the all the queries.
Reviewed-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e8fd60e7891c7a931cfa04259762df4adb304049 |
|
26-Feb-2016 |
Samuel Iglesias Gonsálvez <siglesias@igalia.com> |
i965: set ctx->Const.MaxViewport{Width,Height} to 32k
From ARB_viewport_array spec:
" * On GL3-capable hardware the VIEWPORT_BOUNDS_RANGE should be at least
[-16384, 16383].
* On GL4-capable hardware the VIEWPORT_BOUNDS_RANGE should be at least
[-32768, 32767]."
This range is set using ctx->Const.MaxViewportWidth value, so just bump
those constants to 32k for gen7+ which can support OpenGL 4.0.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 8514c75a26ec2a83784ea9063ed5e6587184832c |
|
13-Feb-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Set compute shader shared memory max to 64k
See Ivy Bridge PRM, Volume 2, Part 2, 1.8.4 INTERFACE_DESCRIPTOR_DATA:
DWORD 5, bits 20:16: "This field indicates how much shared local
memory the thread group requires. The amount is specified in 4k
blocks, but only powers of 2 are allowed: 0, 4k, 8k, 16k, 32k and 64k
per half-slice."
For Haswell, see Volume 2d, INTERFACE_DESCRIPTOR_DATA:
DWORD 5, bits 20:16: With text identical to the Ivy Bridge PRM.
For Broadwell, see Volume 2d, INTERFACE_DESCRIPTOR_DATA:
DWORD 6, bits 20:16: With text identical to the Ivy Bridge PRM.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2bd58790e2e2015cbf5033786cc16e4e4849ef21 |
|
02-Feb-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Add a few assertions on lossless compression
v2 (Ben): Use combination of msaa_layout and number of samples
instead of introducing explicit type for lossless
compression (intel_miptree_is_lossless_compressed()).
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 56f29911ec9da25c78fbd3d4945d499e65ca4b5a |
|
02-Feb-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Add a flag telling color resolve pass to ignore CCS_E
v2 (Ben): Use combination of msaa_layout and number of samples
instead of introducing explicit type for lossless
compression (intel_miptree_is_lossless_compressed()).
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 40fcb6b9f95050370af0fef11abd12e16b8cc7d0 |
|
13-Feb-2016 |
Samuel Pitoiset <samuel.pitoiset@gmail.com> |
i965: fix MAX_COMPUTE_SHARED_SIZE constant value
MAX_COMPUTE_SHARED_SIZE should be set to 32768. This fixes a regression
introduced in be27f77 (mesa: do not use a constant for
MAX_COMPUTE_SHARED_SIZE).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94139
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f709a0845792540544982740fa47be672825ee8a |
|
08-Dec-2015 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Add means for limiting color resolves
Until now there has been only one type of color buffer that needs
to resolved - namely single sampled fast clear. As even the
sampler engine in GPU doesn't understand the associated meta data,
the color values need to be always resolved prior to reading them.
From SKL onwards there is new scheme supported called the lossless
compression of single sampled color buffers. This is something that
is understood by the sampling engine and therefore resolving of
these types of buffers is not necessary before sampling.
This patch adds means to make the distinction when considering if
resolve is needed.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| eb9cf3cfc99db0cff0a5a584941e8be43ac9b961 |
|
04-Feb-2016 |
Neil Roberts <neil@linux.intel.com> |
main: Use a derived value for the default sample count
Previously the framebuffer default sample count was taken directly
from the value given by the application. On the i965 driver on HSW if
the value wasn't one that is supported by the hardware it would hit an
assert when it tried to program the state for it. This patch fixes it
by adding a derived sample count to the state for the default
framebuffer. The driver can then quantize this to one of the valid
values in its UpdateState handler when the _NEW_BUFFERS state changes.
_mesa_geometric_samples is changed to use the new derived value.
Fixes the piglit test arb_framebuffer_no_attachments-query
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93957
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b3340cd32acf5935891f19833de0cfc500a93e0b |
|
21-Jan-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Implement a drirc workaround for broken dual color blending.
OpenGL's dual color blending feature was specified so that an
implementation could support both multiple render targets (MRT) and
dual source blending. Fragment shader outputs specify both "location"
(the render target number) and "index" (either color 0 or 1).
I believe DirectX only has the notion of "location" - if using dual
color blending, location 0 or 1 will specify the operands. If not,
then location means the render target index. The two features can't
be used together.
As such, some applications mistakenly try to use <loc = 0, index = 0>
and <loc = 1, index = 0> in a shader used for dual color blending with
a single render target, rather than the correct <loc = 0, index = 0>
and <loc = 0, index = 1>.
In particular, Unigine Heaven 4.0 and Valley 1.0 suffer from this bug.
Unigine is aware of the problem, and quickly developed a fix, but has
not bothered to change the download link on their website to a working
copy in over a year. People were still using the broken version and
complaining. We tried working around this by disabling dual color
blending, but that apparently hurts performance, and people were once
again unhappy.
On i965, dual source blending is achieved by using different framebuffer
write messages than normal rendering. So, we have to compile different
code for the two cases. We're not being pedantic: we actually have to
know in order to function.
Normally, dual source blending is detectable in the shader: if a shader
has an output with index = 1, then it's meant for blending, not MRT.
With the broken inputs, they're indistinguishable, so we can only tell
by looking at the current GL state.
This patch implements a new drirc workaround:
export dual_color_blend_by_location=true
which makes the i965 driver detect when OpenGL state is configured for
dual source blending, and recompile the fragment shader to use the right
messages. In that case, we allow either location = 1 or index = 1 to
specify the second source for the blending equations.
It also re-enables GL_ARB_blend_func_extended for Unigine.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92233
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f4ab7340ca72f6b61fe6e3e0995360546d2d6287 |
|
30-Dec-2015 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965: Remove unused hw_must_use_separate_stencil
I spotted this while looking for what needs updating in future platforms.
I'm too lazy to go through the git logs, but it was probably missed by Jason
when all the brw refactoring happened.
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 381a89cf2a0c1e7babb0f134a3b5b662045092a2 |
|
26-Nov-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable ARB_tessellation_shader on Gen7-7.5.
We've resolved all the GPU hangs, and everything seems to be working.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3b5d442661c9ea7d0606fe6403fd6a45b799e50d |
|
16-Dec-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Enable compute shaders in more cases for OpenGLES 3.1
Previously we were checking the desktop OpenGL ARB_compute_shader
requirements, but for OpenGLES 3.1, the requirements are lower.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 8c5310da9d1cbf2272f72d3ed4264544456a4683 |
|
08-Dec-2015 |
Neil Roberts <neil@linux.intel.com> |
i965: Fix crash when calling glViewport with no surface bound
If EGL_KHR_surfaceless_context is used then glViewport can be called
with NULL for the draw and read surfaces. This was previously causing
a crash because the i965 driver tries to use this point to invalidate
the surfaces and it was derferencing the NULL pointer.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93257
Cc: Nanley Chery <nanley.g.chery@intel.com>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Tested-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 82d459a4230c8fcb96fc5e85d00d2c2f4502d1e0 |
|
24-Nov-2015 |
Neil Roberts <neil@linux.intel.com> |
i965/gen9: Resolve SRGB color buffers when GL_FRAMEBUFFER_SRGB enabled
SKL can't cope with the CCS buffer for SRGB buffers. Normally the
hardware won't see the SRGB formats because when GL_FRAMEBUFFER_SRGB
is disabled these get mapped to their linear equivalents. In order to
avoid relying on the CCS buffer when it is enabled this patch now
makes it flush the renderbuffers.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d04612b60d98ff785646affaffc3d7243deecb74 |
|
03-Sep-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Enable ARB_compute_shader extension on supported hardware
Enable ARB_compute_shader on gen7+, on hardware that supports the
OpenGL 4.3 requirements of a local group size of 1024.
With SIMD16 support, this is limited to Ivy Bridge and Haswell.
Broadwell will work with a local group size up to 896 on SIMD16
meaning programs that use this size or lower should run when setting
MESA_EXTENSION_OVERRIDE=GL_ARB_compute_shader.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 595c8180714da1d97be445b9a66affa1dfea39f6 |
|
04-Sep-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Resolve color and flush for all active shader images in intel_update_state().
Fixes arb_shader_image_load_store/execution/load-from-cleared-image.shader_test.
Couldn't reproduce any significant FPS regression in CPU-bound
benchmarks from the Finnish benchmarking system on neither VLV nor BSW
after 30 runs with 95% confidence level.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92849
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 80ea18d1a184606bd3cf6e90296e129f0c7f100e |
|
09-Sep-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Add backend structures for tess stages
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 5340f37902328974ceeceaf13a8bb4984053117b |
|
09-Sep-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Set core tessellation-related limits
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a9e6a56a02155f0da5e5bfa1a4d188f3d6195066 |
|
25-Jul-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Request lowering of gl_TessLevel* from float[] to vec4s.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d278e31459374feb18edd97d5adaacccc08f978a |
|
18-Nov-2015 |
Rob Clark <robclark@freedesktop.org> |
util: move brw_env_var_as_boolean() to util
Kind of a handy function. And I'll want it available outside of i965
for common nir-pass helpers.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Nicolai Hähnle <nhaehnle@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 292df1940126f267418e656b9ec33eb3f06667b8 |
|
13-Nov-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set MaxCombinedUniformBlocks properly.
Up until now, we've been letting core Mesa initialize it to 36 for us
(which is presumably BRW_MAX_UBO (12) * (VS+GS+FS stages -> 3)).
With compute and tessellation, we need to increase this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 5ee5dfddeafde2e2b89f86d2a59769a61ce5d6b2 |
|
12-Nov-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Clean up context constant initialization code.
This was getting pretty out of hand, and with compute partially in place
and tessellation on the way, it was only going to get worse.
This patch makes a "stage exists?" predicate and a "number of stages"
count and uses them to clean up a lot of calculations. We can just
loop over shader stages and set things for the ones that exist. For
combined counts, we can just multiply by the number of stages.
It also tries to organize a little bit.
We should probably use _mesa_has_geometry_shaders/tessellation/compute
here, but we can't because ctx->Version isn't initialized yet. Perhaps
that could be fixed in the future.
No change in "glxinfo -l" on Broadwell.
v2: Drop stray compute shader hunk. Mark stage_exists as const.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 44d6c0c805d2911cc5dfe853e5bc5a505f87775f |
|
12-Nov-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Convert scalar_* flags to a scalar_stage array.
I was going to add scalar_tcs and scalar_tes flags, and then thought
better of it and decided to convert this to an array. Simpler.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 6c5f371a27f901d5bc60cf5a2a11cf6629f96f78 |
|
07-Sep-2015 |
Neil Roberts <neil@linux.intel.com> |
i965/skl+: Enable support for 16x multisampling
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 6980372010ad5929c0b4b0a0370d281cbd6f8b2e |
|
09-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Move the entire compiler API into a single file
At this point, the compiler API has been substantially simplified. In the
spirit of Kristian's making a compiler library, this commit makes a single
header file that contains, more-or-less, the entire compiler API.
There's still a bit of cleanup to do particularly in the area of geometry
shaders. However, this gets us much closer to having a separate compiler.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ea8b77e892cdf6aa4cdd8a9ff312c422b3509ae7 |
|
17-Sep-2015 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa/i965: Refactor brw_is_front_buffer_{drawing,reading} to common code
There are multiple similar implementations of these functions, and a
later patch was going to add another.
v2: Move removing intel_framebuffer to a different patch.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 41c4d45e08b3bf948f24d007c9b7d0c47f3f89d8 |
|
30-Sep-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Define BRW_MAX_SSBO
Instead of using hard-coded values.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 440f9348c1fb877910cebca5413c4300b6738428 |
|
30-Sep-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Define BRW_MAX_UBO
Instead of using hard-coded values.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 70e91d61fde239e8ae58148cacd4ff891126e2aa |
|
07-Aug-2015 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Remove early release of DRI2 miptree
intel_update_winsys_renderbuffer_miptree() will release the existing
miptree when wrapping a new DRI2 buffer, so we can remove the early
release and so prevent a NULL mt dereference should importing the new
DRI2 name fail for any reason. (Reusing the old DRI2 name will result
in the rendering going astray, to a stale buffer, and not shown on the
screen, but it allows us to issue a warning and not crash much later in
innocent code.)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86281
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| bdbabc57e302b73e2db30f6d46918afb2b442c7b |
|
19-Mar-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Set MaxShaderStorageBuffers for compute shaders
v2:
- Set it after the driver's MaxShaderStorageBuffers value assignment.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 36f392c4ef5fd8793127132f9b4465249e92c9ce |
|
09-Jun-2015 |
Samuel Iglesias Gonsalvez <siglesias@igalia.com> |
i965: set ARB_shader_storage_buffer_object related constant values
v2:
- Add tessellation shader constants assignment
v3:
- Set MaxShaderStorageBufferBindings to 36.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 332ff009ffcbdad2402f089060623c0a86fa253c |
|
19-Mar-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Use 64-byte offset alignment for shader storage buffers
This should be a cacheline (64 bytes) so that we can safely have the
CPU and GPU writing the same SSBO on non-cachecoherent systems (our
Atom CPUs). With UBOs, the GPU never writes, so there's no
problem. For an SSBO, the GPU and the CPU can be updating disjoint
regions of the buffer simultaneously and that will break if the
regions overlap the same cacheline.
v2:
- Use cacheline size (64 bytes) instead of 16 bytes (Kristian).
- Update commit log and add a comment in the code explaining
why we use cacheline size (Ben).
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| bf58a2c362d5afdba512f40b3eb300154201c7f0 |
|
09-Sep-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Advertise 65536 for GL_MAX_UNIFORM_BLOCK_SIZE.
Our old value of 16384 is the minimum value. DirectX apparently
requires 65536 at a minimum; that's also what nVidia and the Intel
Windows driver advertise. AMD advertises MAX_INT.
Ilia Mirkin noticed that "Shadow Warrior" uses UBOs larger than 16k
on Nouveau, which advertises 65536 bytes for this limit. Traces
captured on Nouveau don't work on i965 because our lower limit causes
the GLSL linker to reject the captured shaders. While this isn't
important in and of itself, it does suggest that raising the limit
would be beneficial.
We can read linear buffers up to 2^27 bytes in size, so raising this
should be safe; we could probably even go larger. For now, matching
nVidia and Intel/Windows seems like a good plan.
We have to reinitialize MaxCombinedUniformComponents as core Mesa will
have set it based on a stale value for MaxUniformBlockSize.
According to Tapani, there's an unreleased game that asserts on this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 47e0d5b9b28b0753adda70cbfb3ad111ba6169a8 |
|
17-Aug-2015 |
Francisco Jerez <currojerez@riseup.net> |
mesa: Rename MaxCombinedImageUnitsAndFragmentOutputs to MaxCombinedShaderOutputResources.
The name of both the GLSL built-in variable and the glGetInteger param
with the same value changed in GLSL ES 3.1 and GL 4.5. Its semantics
also changed slightly, since the limit now also takes into account the
number of SSBs in use. Switch our internal data structures to the
up-to-date name.
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3569742ec458c0a881857d9deb782c1e11f195d8 |
|
23-Nov-2013 |
Francisco Jerez <currojerez@riseup.net> |
i965: Define implementation constants for ARB_shader_image_load_store.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
v2: Drop VS support pre-Gen8, drop GS support.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 190756482e62cb57e2bc8c798181e5f0171726fb |
|
15-Apr-2015 |
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> |
i965: Enable hardware-generated binding tables on render path.
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each binding table offset in
the binding table pool is unique per each shader stage that are
enabled within a batch.
Also insert the required brw_tracked_state objects to enable
hw-generated binding tables in normal render path.
v2: - Use MOCS in binding table pool alloc for GEN8
- Fix spurious offset when allocating binding table pool entry
and start from zero instead.
v3: - Include GEN8 fix for spurious offset above.
v4: - Fixup wrong packet length in enable/disable hw-binding table
for GEN8 (Ville).
- Don't invoke HW-binding table disable command when we dont
have resource streamer (Chris).
v5: - Reorder the state cache invalidate flush so it happens in-between
enabling hw-generated binding tables and the previous sw-binding
table GPU state (Chris).
v6: - Do the same fix in v5 for gen7_disable_hw_binding_tables().
- Adhere to coding guidelines and make comments more informative.
Cc: kenneth@whitecape.org
Cc: syrjala@sci.fi
Cc: chris@chris-wilson.co.uk
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 090529af1828817344e0850ef27eebd1f096eb5f |
|
02-Jul-2013 |
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> |
i965: Enable resource streamer for the batchbuffer
Check first if the hardware and kernel supports resource streamer. If this
is allowed, tell the kernel to enable the resource streamer enable bit on
MI_BATCHBUFFER_START by specifying I915_EXEC_RESOURCE_STREAMER
execbuffer flags.
v2: - Use new I915_PARAM_HAS_RESOURCE_STREAMER ioctl to check if kernel
supports RS (Ken).
- Add brw_device_info::has_resource_streamer and toggle it for
Haswell, Broadwell, Cherryview, Skylake, and Broxton (Ken).
v3: - Update I915_PARAM_HAS_RESOURCE_STREAMER to match updated kernel.
v4: - Always inspect the getparam.value (Chris Wilson).
v5: - Fold redundant devinfo->has_resource_streamer check in context create
into init screen.
Cc: kenneth@whitecape.org
Cc: chris@chris-wilson.co.uk
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f1d08c4f75794add30d1714a4cd9ce2bf335148d |
|
01-May-2015 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Move pipecontrol workaround bo to brw_pipe_control
With the exception of gen8, the sole user of the workaround bo are for
emitting pipe controls. Move it out of the purview of the batchbuffer
and into the pipecontrol.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d1663ccb4c664b0f544ed5d6f0761f3ae2435199 |
|
18-Jun-2015 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965/bxt: Add basic Broxton infrastructure
The thread counts and URB information are all speculative numbers that were
based on some CHV numbers at the time.
v2:
Originally this patch had PCI IDs. I've moved that to a new patch at the end of
the series.
Remove is_cherryview hack.
Add PCI ids. These match the ones defined in the kernel. The only one tested by
us is 0x0a84.
Capitalize the hex string (Mark)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: "Lecluse, Philippe" <Philippe.Lecluse@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 6e255a3299c9ec5208cb5519b5da2edb0ce2972b |
|
17-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Add compiler options to brw_compiler
This creates the options at screen cration time and then we just copy them
into the context at context creation time. We also move is_scalar to the
brw_compiler structure.
We also end up manually setting some values that the core would have set by
default for us. Fortunately, there are only two non-zero shader compiler
option defaults that we aren't overriding anyway so this isn't a big deal.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 1bc3b62d4aad22b94b8031c29c654a8f90ccc24d |
|
17-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Move INTEL_DEBUG variable parsing to screen creation time
v2: Do bufmgr set_debug and set_aub_dump at screen time as well.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 83199998310591b9162ab12e922ed79ee235b5c8 |
|
17-Jun-2015 |
Kevin Rogovin <kevin.rogovin@intel.com> |
i965: enable ARB_framebuffer_no_attachments for Gen7+
Enable GL_ARB_framebuffer_no_attachments in i965 for Gen7 and higher.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 16658f426dbd81fcbc317b21ae9a3f7c9b6448fb |
|
09-Jun-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
Revert "i965: Advertise a line width of 40.0 on Cherryview and Skylake."
This reverts commit f3b709c0ac073cd0ec90a3a0d91d1ee94668e043.
The "dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4.
interpolation.lines_wide" test appears to be broken on Cherryview when
we expose line widths greater than 12.0. I'm not sure why.
For now, just go back to the limits we used on older platforms.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90902
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f9a18acb56c69b24c1e47cd326dc98e14fadcf94 |
|
10-Jun-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: do not round line width when multisampling or antialiaing are enabled
In commit fe74fee8fa721a we rounded the line width to the nearest integer to
match the GLES3 spec requirements stated in section 13.4.2.1, but that seems
to break a dEQP test that renders wide lines in some multisampling scenarios.
Ian noted that the Open 4.4 spec has the following similar text:
"The actual width of non-antialiased lines is determined by rounding the
supplied width to the nearest integer, then clamping it to the
implementation-dependent maximum non-antialiased line width."
and suggested that when ES removed antialiased lines, they removed
"non-antialised" from that paragraph but probably should not have.
Going by that note, this patch restricts the quantization implemented in
fe74fee8fa721a only to regular aliased lines. This seems to keep the
tests fixed with that commit passing while fixing the broken test.
v2:
- Drop one of the clamps (Ken, Marius)
- Add a rule to prevent advertising line widths that when rounded go beyond
the limits allowed by the hardware (Ken)
- Update comments in the code accordingly (Ian)
- Put the code in a utility function (Ian)
Fixes:
dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines_wide
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90749
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 52e5ad7bf8c731280ca4506b7d38e8c7a8e734b9 |
|
02-Jun-2015 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Set max texture buffer size to hardware limit
Previously we were leaving this at the default of 64K, which meets the
spec but is too small for some real uses. The hardware can handle up to
128M.
User was complaining about this on freenode ##OpenGL today.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 114497afff4e49139b8c7d61f11a7872b81398bf |
|
20-May-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Make NIR non-optional for scalar shaders
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 42298b05d1ebd8b17b89411723ae13295643e496 |
|
08-May-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Use NIR by default for vertex shaders on GEN8+
GLSL IR vs. NIR shader-db results for SIMD8 vertex shaders on Broadwell:
total instructions in shared programs: 2742062 -> 2681339 (-2.21%)
instructions in affected programs: 1514770 -> 1454047 (-4.01%)
helped: 5813
HURT: 1120
The gained programs are ARB vertext programs that were previously going
through the vec4 backend. Now that we have prog_to_nir, ARB vertex
programs can go through the scalar backend so they show up as "gained" in
the shader-db results.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 426023050d1d3cd1b5fc0b3508dd7e1ee3b061e7 |
|
04-Nov-2014 |
Neil Roberts <neil@linux.intel.com> |
i965: Use predicate enable bit for conditional rendering w/o stalling
Previously whenever a primitive is drawn the driver would call
_mesa_check_conditional_render which blocks waiting for the result of
the query to determine whether to render. On Gen7+ there is a bit in
the 3DPRIMITIVE command which can be used to disable the primitive
based on the value of a state bit. This state bit can be set based on
whether two registers have different values using the MI_PREDICATE
command. We can load these two registers with the pixel count values
stored in the query begin and end to implement conditional rendering
without stalling.
Unfortunately these two source registers were not in the whitelist of
available registers in the kernel driver until v3.19. This patch uses
the command parser version from intel_screen to detect whether to
attempt to set the predicate data registers.
The predicate enable bit is currently only used for drawing 3D
primitives. For blits, clears, bitmaps, copypixels and drawpixels it
still causes a stall. For most of these it would probably just work to
call the new brw_check_conditional_render function instead of
_mesa_check_conditional_render because they already work in terms of
rendering primitives. However it's a bit trickier for blits because it
can use the BLT ring or the blorp codepath. I think these operations
are less useful for conditional rendering than rendering primitives so
it might be best to leave it for a later patch.
v2: Use the command parser version to detect whether we can write to
the predicate data registers instead of trying to execute a
register load command.
v3: Simple rebase
v4: Changes suggested by Kenneth Graunke: Split the
load_64bit_register function out to a separate patch so it can be
a shared public function. Avoid calling
_mesa_check_conditional_render if we've already determined that
there's no query object. Some styling fixes.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0374159b0ce3c4634364ca5ab257e305765d4879 |
|
06-May-2015 |
Chris Forbes <chrisf@ijw.co.nz> |
i965/gen6: setup limits for ARB_viewport_array
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d376c3549b2d9c764d92e2c1e46b20e9c04223a4 |
|
05-May-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix missing type in local variable declaration.
Trivial. Fixes the following compiler warning (from GCC 5.1.0):
brw_context.c:629:10: warning: type defaults to ‘int’ in declaration
of ‘simd_size’ [-Wimplicit-int]
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 013031b2291e87f2559a67c2c54b9004c71ef91b |
|
10-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Implement DispatchCompute() back-end
brw_emit_gpgpu_walker will be implemented in a subsequent patch.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| cb18f3f0213c010e657fd0b41e681e960a20b790 |
|
29-Apr-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Set invocation counts based on max_cs_threads
For ES, we set the max counts based on SIMD8, which is currently
accurate.
For desktop GL, we set the max counts based on SIMD16, which can fail
in some cases where a SIMD16 program is not currently supported.
Therefore, this value is not currently accurate, but will work fine in
many cases, and lets us run more test cases. Eventually we want to
always be able to generate a SIMD16 program.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 73cb2d3a73425c5efa4f98b71393e7dad4f387c7 |
|
14-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Add max_cs_threads
Add values for gen7 & gen8. These are the number threads in a
subslice.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c380973a9564be57acdae5ab6c6a9efcb72cf6c9 |
|
31-Aug-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/fs: Support compute programs in fs_visitor
v2:
* Clean out some unneeded code copied from run_fs (krh)
* Always use NIR
* Split shader time out into a separate commit
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 05e7f7f4388bde882b7ce74124000a4d435affff |
|
22-Apr-2015 |
Zoë Blade <zoe@bytenoise.co.uk> |
Fix a few typos
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 38dc2ddab4a25398ebd07e1ecf52daa7466b6963 |
|
17-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/device_info: Add a supports_simd16_3src flag
This also involves moving revision checking to screen creation time and
passing that into brw_get_device_info so that we can get the right
device_info for early versions of SKL. Since the only place we used
revision was to check for SIMD16 3-src instruction support, it's safe to
remove the revision field from brw_context.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 28d9e90428282a5e0a6aa31ad858a5cf514d1264 |
|
07-Apr-2015 |
Marius Predut <marius.predut@intel.com> |
i965: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
No functional changes.
Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ea0c35faf88962e049c0a67ce714e03933383be1 |
|
11-Apr-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Remove useless null check.
If it were null, we'd have just derefernced it two lines above.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 58add76791459e023f82eab973719c71779dae9d |
|
04-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
nir: split out lower_sub from lower_negate
Originally you had to have one or the other. But actually I don't want
either. (Or rather I want whatever is the minimum # of instructions.)
TODO: not sure where the best place to insert a check that driver hasn't
set *both* lower_negate and lower_sub?
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d47405eb707b9921f70454049677a9d504ee3fa6 |
|
11-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Use NIR by default for fragment shaders
GLSL IR vs. NIR shader-db results on i965:
total instructions in shared programs: 2889747 -> 2890782 (0.04%)
instructions in affected programs: 2425446 -> 2426481 (0.04%)
helped: 3698
HURT: 5341
GLSL IR vs. NIR shader-db results on g4x:
total instructions in shared programs: 2547252 -> 2550440 (0.13%)
instructions in affected programs: 1984482 -> 1987670 (0.16%)
helped: 2844
HURT: 4776
GLSL IR vs. NIR shader-db results on Iron Lake:
total instructions in shared programs: 4053381 -> 4063828 (0.26%)
instructions in affected programs: 3026601 -> 3037048 (0.35%)
helped: 4110
HURT: 8331
GAINED: 1287
LOST: 9
GLSL IR vs. NIR shader-db results on Sandy Bridge:
total instructions in shared programs: 5307041 -> 5236666 (-1.33%)
instructions in affected programs: 3442908 -> 3372533 (-2.04%)
helped: 11829
HURT: 5604
GAINED: 33
LOST: 18
GLSL IR vs. NIR shader-db results on Ivy Bridge:
total instructions in shared programs: 4926333 -> 4857017 (-1.41%)
instructions in affected programs: 3144042 -> 3074726 (-2.20%)
helped: 11559
HURT: 4774
GAINED: 46
LOST: 25
GLSL IR vs. NIR shader-db results on Bay Trail:
total instructions in shared programs: 4926333 -> 4857017 (-1.41%)
instructions in affected programs: 3144042 -> 3074726 (-2.20%)
helped: 11559
HURT: 4774
GAINED: 46
LOST: 25
GLSL IR vs. NIR shader-db results on Haswell:
total instructions in shared programs: 4392487 -> 4293476 (-2.25%)
instructions in affected programs: 2800180 -> 2701169 (-3.54%)
helped: 13073
HURT: 3383
GAINED: 46
LOST: 23
GLSL IR vs. NIR shader-db results on Broadwell (FS only):
total instructions in shared programs: 4378113 -> 4283025 (-2.17%)
instructions in affected programs: 2743209 -> 2648121 (-3.47%)
helped: 12470
HURT: 3609
GAINED: 64
LOST: 27
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c2a0600d5b0645533ba442b5ab879b23c2564a4d |
|
10-Apr-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't set NirOptions for stages that will use the vec4 backend.
We've started using NirOptions != NULL to mean "we're using NIR for this
stage." However, when INTEL_USE_NIR=1, we set it for a bunch of stages
that still use the vec4 backend, and thus definitely aren't using NIR.
For example, if INTEL_USE_NIR=1 we disable the GLSL IR cubemap
normalization pass, even for vertex shaders and geometry shaders. This
is wrong, but breaks a very uncommon case.
When I started deleting GLSL IR for stages where we claimed to be using
NIR, this bug quickly became apparent.
For now, only set it for fragment shaders, and vertex shaders if
brw->scalar_vs is set.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| bff421332661bfd0f82ab9eee9e4fec9d06ed1a1 |
|
03-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Check the INTEL_USE_NIR environment variable once at context creation
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 218e45e2f7b2d6c20bbba837f6e5cbe15610771e |
|
23-Mar-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Use the same nir options for all gens
If we tell NIR to split ffma's, then we don't need seperate options
anymore.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 37703040a142da6bc7c458479a70e35118e10e6b |
|
23-Mar-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/nir: Run the ffma peephole after the rest of the optimizations
The idea here is that fusing multiply-add combinations too early can reduce
our ability to perform CSE and value-numbering. Instead, we split ffma
opcodes up-front, hope CSE cleans up, and then fuse after-the-fact.
Unless an algebraic pass does something silly where it inserts something
between the multiply and the add, splitting and re-fusing should never
cause a problem. We run the late algebraic optimizations after this so
that things like compare-with-zero don't hurt our ability to fuse things.
shader-db results for fragment shaders on Haswell:
total instructions in shared programs: 4390538 -> 4379236 (-0.26%)
instructions in affected programs: 989359 -> 978057 (-1.14%)
helped: 5308
HURT: 97
GAINED: 78
LOST: 5
This does, unfortunately, cause some substantial hurt to a shader in Kerbal
Space Program. However, the damage is caused by changing a single
instruction from a ffma to an add. This, in turn, *decreases* register
pressure in one part of the program causing it to fail to register allocate
and spill. Given the overwhelmingly positive results in other shaders and
the fact that the NIR for the Kerbal shaders is actually better, this
should be considered a positive.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 80390f91a0e200ae29a678bda495b91f6452023a |
|
17-Mar-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/nir: Use NIR lowering for ffma for gen < 6
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 484f9f4fcd53fcaa768e63934a5f74346bfb46a9 |
|
23-Mar-2015 |
Dave Airlie <airlied@redhat.com> |
i965: define I915_PARAM_REVISION
we are broken against the libdrm 2.4.60 minimum specified,
so fix it for now.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c02c4b567ce001f6605c46e71e089692b837bf26 |
|
04-Mar-2015 |
Neil Roberts <neil@linux.intel.com> |
i965: Store the GPU revision number in brw_context
brwContextInit now queries the GPU revision number via a new parameter
for DRM_I915_GETPARAM. This new parameter requires a kernel patch and
a patch to libdrm. If the kernel doesn't support it then it will
continue but set the revision number to -1. The intention is to use
this to implement workarounds that are only needed on certain
steppings of the GPU.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| eeb504e0ae7796e7ba475f6e9d6c26daa6b06608 |
|
11-Mar-2015 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Defer the throttle until we submit new commands
Currently, we throttle before the user begins preparing commands for the
next frame when we acquire the draw/read buffers. However, construction
of the command buffer can itself take significant time relative to the
frame time. If we move the throttle from the buffer acquire to the
command submit phase we can allow the user to improve concurrency
between the CPU and GPU (i.e. reduce the amount of time we waste inside
the throttle).
v2: Whitespace + delay throttling until after the next submission for
greater parallelism
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Chad Versace <chad.versace@linux.intel.com>
Cc: Ian Romanick <idr@freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com> [v1]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 64788b2e8dc2ddedc2712ed02b7e9096638b7bae |
|
19-Sep-2014 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Throttle to the previous frame
In order to facilitate the concurrency offered by triple buffering and to
offset the latency induced by swapping via an external process, which
may incur extra rendering itself, only throttle to the previous frame
and not the last. The second issue that mostly affects swap benchmarks,
but also can incur jitter in the throttling, is that the throttle bo is
closer to the next SwapBuffers rather than immediately after the previous
SwapBuffers. Throttling to the previous frame doubles the maximum possible
latency at the benefit of improving throughput and reducing jitter.
v2: Rename "first_post_swapbuffer" batches array to a plain
throttle_batch[] as the pluralisation was contorting the name and not
making it clear as to whether it was the first batch or first_post_swap
batch. Not least of which was that not all throttle points are SwapBuffers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Chad Versace <chad.versace@linux.intel.com>
Cc: Ian Romanick <idr@freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 8b9bd19021c0efef33d66ae24f8871b826d66e8a |
|
26-Feb-2015 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Throttle rendering to an fbo
When rendering to an fbo, even though it may be acting as a winsys
frontbuffer or just generally, we never throttle. However, when rendering
to an fbo, there is no natural frame boundary. Conventionally we use
SwapBuffers and glFinish, but potential callers avoid often glFinish for
being too heavy handed (waiting on all outstanding rendering to complete).
The kernel provides a soft-throttling option for this case that waits for
rendering older than 20ms to be complete (that's a little too lax to be
used for swapbuffers, but is here a useful safety net). The remaining
choice is then either never to throttle, throttle after every draw call,
or at after intermediate user defined point such as glFlush and thus all the
implied flushes. This patch opts for the latter as that is the current
method used for flushing to front buffers.
v2: Defer the throttling from inside the flush to the next
intel_prepare_render() and switch non-fbo frontbuffer throttling over to
use the same lax method. The issuing being that
glFlush()/intel_prepare_read() is just as likely to be called inside a
tight loop and not at "frame" boundaries.
v3: Rename from need_front_throttle to need_flush_throttle to avoid any
ambiguity between front buffer rendering and fbo rendering. (Chad)
v4: Whitespace
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Chad Versace <chad.versace@linux.intel.com>
Cc: Ian Romanick <idr@freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b200cbb0a41aaebb007668f870a483f0b9ecd898 |
|
06-Mar-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
nir: Add native_integers to nir_shader_compiler_options.
glsl_to_nir, tgsi_to_nir, and prog_to_nir all want to know whether the
driver supports native integers. Presumably other passes may as well.
Adding this to nir_shader_compiler_options is an easy way to provide
that information, as it's accessible via nir_shader::options.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a55da73be46b4576015417b2dff71a719bc8b797 |
|
06-Mar-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
nir: Try to make sense of the nir_shader_compiler_options code.
The code in glsl_to_nir is entirely dead, as we translate from GLSL to
NIR at link time, when there isn't a _mesa_glsl_parse_state to pass,
so every caller passes NULL.
glsl_to_nir seems like the wrong place to try and create the shader
compiler options structure anyway - tgsi_to_nir, prog_to_nir, and other
translators all would have to duplicate that code. The driver should
set this up once with whatever settings it wants, and pass it in.
Eric also added a NirOptions field to ctx->Const.ShaderCompilerOptions[]
and left a comment saying: "The memory for the options is expected to be
kept in a single static copy by the driver." This suggests the plan was
to do exactly that. That pointer was not marked const, however, and the
dead code used a mix of static structures and ralloced ones.
This patch deletes the dead code in glsl_to_nir, instead making it take
the shader compiler options as a mandatory argument. It creates an
(empty) options struct in the i965 driver, and makes NirOptions point
to that. It marks the pointer const so that we can actually do so
without generating "discards const qualifier" compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7f10e1678e4ff72791a544cbb9da669f373dc78d |
|
01-Oct-2014 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: free scratch buffers when destroying the context
If scratch space is needed for a shader stage we try to reuse the last scratch
buffer bound to that stage. If we can't, we free the old scratch buffer and
allocate a new one. This means we always keep the last scratch buffer for a
particular shader stage around for the entire life span of the context.
These buffers are being reported by Valgrind as definitely lost after
destroying the OpenGL context. For example, for the geometry shader stage:
==18350== 248 bytes in 1 blocks are definitely lost in loss record 85 of 150
==18350== at 0x4C2CC70: calloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==18350== by 0xA1B35D6: drm_intel_gem_bo_alloc_internal (intel_bufmgr_gem.c:724)
==18350== by 0xA1B383F: drm_intel_gem_bo_alloc (intel_bufmgr_gem.c:794)
==18350== by 0xA1AEFA3: drm_intel_bo_alloc (intel_bufmgr.c:52)
==18350== by 0x9D08E31: brw_get_scratch_bo (brw_program.c:226)
==18350== by 0x9D2A0F2: do_gs_prog (brw_vec4_gs.c:280)
==18350== by 0x9D2A635: brw_gs_precompile (brw_vec4_gs.c:401)
==18350== by 0x9D14F68: brw_shader_precompile(gl_context*, gl_shader_program*) (brw_shader.cpp:76)
==18350== by 0x9D157B8: brw_link_shader (brw_shader.cpp:269)
==18350== by 0x9B0941E: _mesa_glsl_link_shader (ir_to_mesa.cpp:3038)
==18350== by 0x99AE4ED: link_program (shaderapi.c:917)
==18350== by 0x99AF365: _mesa_LinkProgram (shaderapi.c:1385)
So make sure that by the time we destroy the context we check if we have live
scratch buffers for the various stages and release them if that is the case.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| fe74fee8fa721a42448470e063870d24f9453dab |
|
10-Feb-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Fix non-AA wide line rendering with fractional line widths
"(...)Let w be the width rounded to the nearest integer (...). If the
line segment has endpoints given by (x0,y0) and (x1,y1) in window
coordinates, the segment with endpoints (x0,y0-(w-1)/2) and
(x1,y1-(w-1/2)) is rasterized, (...)"
The hardware it not rounding the line width, so we should do it.
Also, we should be careful not to go beyond the hardware limits
for the line width after it gets rounded. Gen6-7 define a maximum line
width slightly below 8.0, so we should advertise a maximum line
width lower than 7.5 to make sure that 7.0 is the maximum integer
line width that we can select. Since the line width granularity in these
platforms is 0.125, we choose 7.375. Other platforms advertise rounded
maximum line widths, so those are fine.
Fixes the following 3 dEQP tests:
dEQP-GLES3.functional.rasterization.primitives.lines_wide
dEQP-GLES3.functional.rasterization.fbo.texture_2d.primitives.lines_wide
dEQP-GLES3.functional.rasterization.fbo.rbo_singlesample.primitives.lines_wide
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| eda3dd00760039493fa2afc00193aa47b6ce8c58 |
|
09-Sep-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Add device limits for tess threads & URB entries
This should cover all platforms prior to Skylake.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| aa727c1dd9e92dfafcc1ed39a9c65478ae40ce39 |
|
26-Nov-2014 |
Eduardo Lima Mitev <elima@igalia.com> |
i965: Sets missing vertex shader constant values for HighInt format
The range's min and max, and the precision value are not set correctly for the
vertex shader constants.
Fixes 1 dEQP test: dEQP-GLES3.functional.state_query.shader.precision_vertex_highp_int
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| cec8eff28e765b3958a2c3ac41578dfd1c4c8d0c |
|
31-Dec-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
i965/skl: Report more accurate number of samples for format
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ee5fb8d1ba7f50ed94e1a34fa0f6e15a0588145e |
|
21-Oct-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
i965: Generate vs code using scalar backend for BDW+
With everything in place, we can now use the scalar backend compiler for
vertex shaders on BDW+. We make scalar vertex shaders the default on
BDW+ but add a new vec4vs debug option to force the vec4 backend.
No piglit regressions.
Performance impact is minimal, I see a ~1.5 improvement on the T-Rex
GLBenchmark case, but in general it's in the noise. Some of our
internal synthetic, vs bounded benchmarks show great improvement, 20%-40%
in some cases, but real-world cases are mostly unaffected.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2881b123d00562fee8b7d2b4f7825f89a73e0d9f |
|
02-Dec-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Use ~0 to represent true on all generations.
Jason realized that we could fix the result of the CMP instruction on
Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4
backend before use, rather than when the bool was created. The FS does
this and it saves some unnecessary resolves.
On Ironlake:
total instructions in shared programs: 4289762 -> 4287277 (-0.06%)
instructions in affected programs: 619430 -> 616945 (-0.40%)
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2a4f5728ad27bd1605b3604908caa9ad4983e256 |
|
01-Dec-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove "disable_derivative_optimization" driconf option.
This was added in September 2013 when we first implemented the fast
(but lower quality) derivatives. A quick Google search didn't turn
up anyone using or recommending the option, so I suspect no one does.
Applications that want to control the quality of their derivatives can
use the new GL_ARB_derivative_control extension, or use the glHint
mechanism. The driconf option seems superfluous.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f3b709c0ac073cd0ec90a3a0d91d1ee94668e043 |
|
04-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Advertise a line width of 40.0 on Cherryview and Skylake.
According to the documentation, line widths higher than 40.0 may have
quality problems. That's already 20 times larger than we've been
exposing, so it seems totally sufficient.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 6dab04d7e3af2e0be8a05ca2df8c5669a5f54937 |
|
04-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Advertise larger line widths.
We've artificially been limiting this to 5 for no particular reason.
On Gen4-5, the limit is [0, 7.5] with a granularity of 0.5 (U3.1).
On Gen6+, the limit is [0, 7.9921875]. Since it's a U3.7, the
granularity should be 0.125 (1/8).
This patch conservatively advertises one granularity smaller than the
hardware's maximum value, just in case there's a problem using the
largest possible value. On Gen4-5, this is 7.5 - 0.5 = 7.0. On Gen6+,
this is 8.0 - 0.125 = 7.875.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 08599f668c5d991ab19376a19cb2e14e5245db95 |
|
07-May-2014 |
Eric Anholt <eric@anholt.net> |
i965: Skip recalculating URB allocations if the entry size didn't change.
We only get here if the VS/GS compiled programs change, but we can even
skip it if the VS/GS size didn't change.
Affects cairo runtime on glamor by -1.26471% +/- 0.674335% (n=234)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7a4790148c524fbdc75fca9aaa4d4439dce911a2 |
|
23-Sep-2014 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Initialize the SampleMap{2,4,8}x variables
with values specific to Intel hardware.
V2: Define and use gen6_get_sample_map() function to initialize
the variables.
V3: Change the function name to gen6_set_sample_maps() and use
memcpy() to fill in the data.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 808b8e59c09ac5977ab020bd1771225a4e0a4cc4 |
|
25-Apr-2014 |
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> |
i965: Avoid null access in intelMakeCurrent()
separate two null checks connected with && to their own if branches.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 66ec61c49f0e57ebe237de3ee5610c7fda972e9c |
|
30-Jul-2014 |
Iago Toral Quiroga <itoral@igalia.com> |
i965/gen6/gs: Enable texture units and upload sampler state.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 927f5db46135b3eb63f401833b1e40a3be9ca4e0 |
|
21-Jun-2014 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Request lowering gl_VertexID
Fixes the (new) piglit tests gles-3.0-drawarrays-vertexid,
gl-3.0-multidrawarrays-vertexid, and gl-3.2-basevertex-vertexid.
Fixes gles3conform failure in:
ES3-CTS.gtf.GL3Tests.transform_feedback.transform_feedback_vertex_id
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80247
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2e51dc838be177a09f60958da7d1d904f1038d9c |
|
09-Aug-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Use ~0 to represent true on Gen >= 6.
total instructions in shared programs: 4292303 -> 4288650 (-0.09%)
instructions in affected programs: 299670 -> 296017 (-1.22%)
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 39a5b6998538f5a436b2b9f7e30e4f8937aaaea9 |
|
29-May-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Split gen6 depth hiz state out from brw
We will program the gen6 hiz depth state differently to enable layered
rendering on gen6.
v2:
* Remove unneeded gen6_emit_depthbuffer as suggested by Topi
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 1f8e0fbd38da5635d2ade5ab397d840900d47c64 |
|
28-May-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Split gen6 renderbuffer surface state from gen5 and older
We will program the gen6 renderbuffer surface state differently to
enable layered rendering on gen6.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2f28a0dc23165123cf1e8b5942acad37878edd8a |
|
08-Jul-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
i965: Implement fast color clears using meta operations
This patch uses the infrastructure put in place by previous patches
to implement fast color clears and replicated color clears in terms of
meta operations.
This works all the way back to gen7 where fast clear was introduced and
adds support for fast clear on gen8. It replaces the blorp path
completely and improves on a few cases. Layered clears are now done
using instanced rendering and multiple render-target clears use a
MRT shader with rep16 writes.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 388f02729bbf88ba104f4f8ee1fdf005a240969c |
|
09-Aug-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
i965: Move pre-draw resolve buffers to dd::UpdateState
No functional change except for glBegin/glEnd style rendering, where we now
do the resolves at glBegin time instead of FLUSH_VERTICES time. This is also
the reason for this change, so that when we later switch fast clear resolve to
use meta, we won't be doing meta operations in the middle of a begin/end
sequence.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ff7a2fc322a0ae0a36a976444b7506e9313ac630 |
|
08-Jul-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
i965: Add context flag to disable the viewport transform
This lets us disable the viewport transform, which will be useful for
emitting 3DPRIM_RECTLIST.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 221d9c3e9c043d96dcd0df9f996cb15daaeffe47 |
|
08-Aug-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
i965: Rename intelValidateState to intel_update_state
This matches the name of the dd hook. Also convert a couple of nearby
dd implementations to lowercase + underscore as is now the standard.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 002211f9eea258acc253528024ee104aa1fcd90d |
|
03-Aug-2014 |
Marek Olšák <marek.olsak@amd.com> |
mesa: move ShaderCompilerOptions into gl_constants
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 410fea8dd9cc0b1b500477a8b6f68c950f7c895a |
|
28-Jun-2014 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Add support for ARB_copy_image
This, together with the meta path, provides a complete implemetation of
ARB_copy_image.
v2: Add a fallback memcpy path for when the texture is too big for the
blitter
v3: Properly support copying between two places on the same texture in the
memcpy fallback
v4: Properly handle blit between the same two images in the fallback path
v5: Properly handle blit between the same two compressed images in the
fallback path
v6: Fix a typo in a comment
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 31f1cbc24ddc32c2a7b768f9c017f2c7161c7728 |
|
08-Aug-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Support the allow_glsl_extension_directive_midshader option.
This adds support for Marek's new driconf parameter, which avoids
totally white rendering in Unigine Valley (which attempts to enable
the GL_ARB_sample_shading extension in an illegal place).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75664
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 1e0da6233be6e5fb0143615d5e3d3642ddb7964f |
|
25-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
util: Move ralloc to a new src/util directory.
For a long time, we've wanted a place to put utility code which isn't
directly tied to Mesa or Gallium internals. This patch creates a new
src/util directory for exactly that purpose, and builds the contents as
libmesautil.la.
ralloc seemed like a good first candidate. These days, it's directly
used by mesa/main, i965, i915, and r300g, so keeping it in src/glsl
didn't make much sense.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
v2 (Jason Ekstrand): More realloc uses and some scons fixes
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 6afe21da6236f74acfb4daa6fbc4d6d1de700790 |
|
26-Jul-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete gen7_upload_sampler_state_table and vtable mechanism.
brw_upload_sampler_state_table now handles all generations, so we don't
need the vtable mechanism either.
There's still a lot of code duplication; the next patches will address
that.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ccda1b9ba92d6644a61e646908a8c6e55e310f2e |
|
20-May-2014 |
Eric Anholt <eric@anholt.net> |
i965: Drop the memcmp for finding duplicated CURBE uploads.
At this point, the extra copy of the data and memcmp are as expensive as
just re-uploading.
Note: now that we'll always upload, and brw_constant_buffer watches
BRW_NEW_BATCH anyway, we don't need to explicitly unref the old curbe_bo
at batch reset time.
No significant performance difference on glamor copywinwin10 (n=55),
despite that test having a 98% hit rate on the cache.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 5b3492fa3ff1738fffbc8d05cf39b6e10da3dc39 |
|
13-Jun-2014 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Enable vertex streams up to MAX_VERTEX_STREAMS.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| fa1a3b2e3c2bdb358423ef960edddce3e3014ce6 |
|
15-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Add is_cherryview flag to brw_context.
Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 10e03b4401b025f84b97f7e578a716a63c687196 |
|
08-Jun-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Use override structure rather than separate env var
In 25268b93, we added a new environment variable
(INTEL_COMPUTE_SHADER) to allow some constant values to be upgraded
for the ARB_compute_shader extension.
Now, we can look to see if the extension was enabled via the
MESA_EXTENSION_OVERRIDE environment variable.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b11d345ab02ad78b17439179d794c91aa229d83c |
|
04-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Ask the VBO module to actually use VBOs.
Note that this covers the Begin/End rendering path, but not user vertex
arrays (so we can't drop copy_array_to_vbo_array() code). Improves
performance of isosurf GLVERTEX|TRIANGLES by 16.7506% +/- 4.98934%
(n=20). No difference on openarena (n=10), which was why this was reverted
back in cbde2765804a4fc62bcf092230a01376aedbf2cd.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f9a2679db5886a65eac7e08a8f75674cf3dff8b7 |
|
28-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965/gen7+: Move sampler state packets to the stage sampler state table update.
Now that we have the stage state coming into our setup of sampler states,
it's easy to drop an identifier into it of which stage the stage_state is,
and then look up which packet to emit in a little table.
No performance difference on cairo on glamor (n=492).
v2: Don't forget to do the workaround flush on IVB.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 5566747296f6a0b9dcadd056b0a9743c0fbce147 |
|
30-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Rename intel_regions.h to something more appropriate now.
We had the EGLimage structure laying around in intel_regions.h, but now
it's the only thing left in the file.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e16c5c906316c58c0633e9bba02339ef981e5ef3 |
|
25-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Drop use of intel_region from miptrees.
Note: region->width/height used to reflect the total_width/height padding
of separate stencil, though mt->total_width didn't. region->width/height
was being used in EGL images, where the padded value would have been the
wrong one, so I converted them to use rb->Width/Height.
v2: Drop debug printf that slipped in (caught by Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e3a9ca4563790f54976a969bf70cd5f45cbc4e13 |
|
25-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Replace the region in DRIimage with just a BO pointer and stride.
Regions aren't refcounted safely for multithreaded applications, and
they're not terribly useful wrappers of a BO, so I'm trying to remove
them.
Even the stride I added here could probably be reduced to use of an
existing field in the __DRIimageRec, but I want this to be as mechanical
of a change as possible.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c0bf5a7eff6e556cf1ecfed213cf70d9f3bd676d |
|
25-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Stop making a pointless region for DRI2 to just throw it away.
I noticed that we were doing this while changing the DRI3 path to not use
regions, which involved changing the signature of
intel_update_winsys_renderbuffer_miptree() this way.
v2: Replace my comment with Chad's version.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> (v1)
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3a7a20752fb410075a26b4fa95de0a00e49742b1 |
|
25-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Drop the global GEM name from regions.
Once a buffer has been named, drm_intel_bo_flink() is just a getter.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ac30e1adb49ec6947f740b47d90f8403fe416314 |
|
29-Apr-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Actually emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS.
For platforms using hardware contexts (currently Gen6+), we failed to
emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS, instead emitting MI_NOOP
for both.
During one of the context initialization reordering patches, we
accidentally moved brw_init_state before we set brw->CMD_PIPELINE_SELECT
and brw->CMD_VF_STATISTICS. So, when brw_init_state uploaded initial
GPU state (brw_init_state -> brw_upload_initial_gpu_state ->
brw_upload_invariant_state), these would be 0 (MI_NOOP).
Storing the commands in the context is not worthwhile. We have many
generation checks in our state upload code, and for platforms with
hardware contexts, this only gets called once per GL context anyway.
The cost is negligable, and it's easy to botch context creation
ordering.
This may fix hangs on Gen6+ when using the media pipeline.
Cc: "10.0 10.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 320e0c5205c8b24cd5428d8b7a914c6e604cc85a |
|
09-Apr-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Correct EmitNoIndirect shader compiler option flags.
These were out of sync with the flags used to control
lower_variable_index_to_cond_assign in brw_shader.cpp.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b02bcea7157020b01d5f4fdcb5da69c10013a818 |
|
01-Nov-2013 |
Eric Anholt <eric@anholt.net> |
i965: Use intel_upload_space() for pull constant uploads.
This also happens to fix a leak of the current GS pull constant BO on
context destroy, by just not holding on to the pull const bos after the
surface state is generated.
No statistically significant performance difference on GLB2.7 on HSW at
1024x768 (n=40) or 320x240 (n=44), or on BYT at 320x240 (n=47).
v2: Rebase on intel_upload simplification.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 44e944c87cafd55c00c8837d8223be074436015c |
|
21-Mar-2014 |
Eric Anholt <eric@anholt.net> |
i965: Simplify the no-reopening-the-winsys-buffer tests.
The formatting was weird, and the tests were duplicated, and it is
guaranteed that mt->region exists.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7a0fd3ca1d436591117d451ecee209a4cdb65aef |
|
17-Mar-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Allocate register sets at screen creation, not context creation.
Register sets depend on the particular hardware generation, but don't
depend on anything in the actual OpenGL context. Computing them is
fairly expensive, and they take up a large amount of memory. Putting
them in the screen allows us to compute/allocate them once for all
contexts, saving both time and space.
Improves the performance of a context creation/destruction
microbenchmark by about 3x on my Haswell i7-4750HQ.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 551d459af421a2eb937e9e16301bb64da4624f89 |
|
07-Mar-2014 |
Neil Roberts <neil@linux.intel.com> |
Add the EGL_MESA_configless_context extension
This extension provides a way for an application to render to multiple
surfaces with different buffer formats without having to use multiple
contexts. An EGLContext can be created without an EGLConfig by passing
EGL_NO_CONFIG_MESA. In that case there are no restrictions on the surfaces
that can be used with the context apart from that they must be using the same
EGLDisplay.
_mesa_initialze_context can now take a NULL gl_config which will mark the
context as ‘configless’. It will memset the visual to zero in that case.
Previously the i965 and i915 drivers were explicitly creating a zeroed visual
whenever 0 is passed for the EGLConfig. Mesa needs to be aware that the
context is configless because it affects the initial value to use for
glDrawBuffer. The first time the context is bound it will set the initial
value for configless contexts depending on whether the framebuffer used is
double-buffered.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ec542d74578bbef6b55125dd6aba1dc7f5079e65 |
|
03-Mar-2014 |
Eric Anholt <eric@anholt.net> |
i965: Drop broken front_buffer_reading/drawing optimization.
The flag wasn't getting updated correctly when the ctx->DrawBuffer or
ctx->ReadBuffer changed. It usually ended up working out because most
apps only have one window system framebuffer, or if they have more than
one and they have any front read/drawing, they will have called
glReadBuffer()/glDrawBuffer() on it when they get started on the new
buffer.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c10896b593720457e99a731e9493ce8d6c497fab |
|
05-Mar-2014 |
Eric Anholt <eric@anholt.net> |
i965: Fix render-to-texture in non-FinishRenderTexture cases.
We've had several problems now with FinishRenderTexture not getting called
enough, and we're ready to just give up on it ever doing what we need. In
particular, an upcoming Steam title had rendering bugs that could be fixed
by always_flush_cache=true.
Instead of hoping Mesa core can figure out when we need to flush our
caches, just track what BOs we've rendered to in a set, and when we render
from a BO in that set, emit a flush and clear the set.
There's some overhead to keeping this set, but most of that is just
hashing the pointer -- it turns out our set never even gets very large,
because cache flushes are so common (even on cairo-gl).
No statistically significant performance difference in cairo-gl (n=100),
despite spending ~.5% CPU in these set operations.
v1: (Original patch by Eric Anholt.)
v2: (Changes by Ken Graunke.)
- Rebase forward from May 7th 2013 -> March 4th 2014.
- Drop the FinishRenderTexture hook entirely; after rebasing the
patch, the hook was just an empty function.
- Move the brw_render_cache_set_clear() call from
intel_batchbuffer_emit_flush() to brw_emit_pipe_control_flush().
In theory, this could catch more cases where we've flushed.
- Consider stencil as a possible texturing source.
v3: (changes by anholt):
- Move set_clear() back to emit_mi_flush() -- it means we can drop
more forced flushes from the code. In the previous location, it
wouldn't have been called when we wanted pre-gen6.
- Move the set clear from batch init to reset -- it should be empty at
the start of every batch, since the kernel handled any inter-batch
flush for us.
v4: Drop the debug code in set.c that I accidentally committed.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Dylan Baker <baker.dylan.c@gmail.com> [v2]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 83daa88035af978c5158cfe5a196df45ce1555c1 |
|
23-Dec-2013 |
Eric Anholt <eric@anholt.net> |
i965: Move the remaining driver debug over to stderr.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3663bbe773187dee341556ef29e58b1143ef2f5c |
|
20-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Create a hardware context before initializing state module.
brw_init_state() calls brw_upload_initial_gpu_state(). If hardware
contexts are enabled (brw->hw_ctx != NULL), this will upload some
initial invariant state for the GPU. Without hardware contexts, we
rely on this state being uploaded via atoms that subscribe to the
BRW_NEW_CONTEXT bit.
Commit 46d3c2bf4ddd227193b98861f1e632498fe547d8 accidentally moved
the call to brw_init_state() before creating a hardware context.
This meant brw_upload_initial_gpu_state would always early return.
Except on Gen6+, we stopped uploading the initial GPU state via
state atoms, so it never happened.
Fixes a regression since 46d3c2bf4ddd227193b98861f1e632498fe547d8.
Cc: "10.0 10.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 57405605a8c320f9d6ea389afd43ce6f013330a5 |
|
10-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Actually claim to support MSAA on Broadwell.
We need to advertise 8x, 4x, and 2x multisamples. Previously, we only
claimed to support 0/1 samples.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7023786417d8ecf9ea8236d17c739af087ac05be |
|
07-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable HiZ on Broadwell.
It appears to work fine.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c593ad6e467b07ec0c70923d79259dbfb68b1bed |
|
02-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Bump MaxTexMbytes from 1GB to 1.5GB.
Even with the other limits raised, TestProxyTexImage would still reject
textures > 1GB in size. This is an artificial limit; nothing prevents
us from having a larger texture. I stayed shy of 2GB to avoid the
larger-than-aperture situation.
For 3D textures, this raises the effective limit:
- RGBA8: 645 -> 738
- RGBA16: 512 -> 586
- RGBA32F: 406 -> 465
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74130
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 6c044231535b93c5d16404528946cad618d96bd9 |
|
02-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Bump GL_MAX_CUBE_MAP_TEXTURE_SIZE to 8192.
Gen4+ supports 8192x8192 cube maps. Ivybridge and later can actually
support 16384, but that would place GL_MAX_CUBE_MAP_TEXTURE_SIZE above
GL_MAX_TEXTURE_SIZE, which seems like a bad idea.
(Unfortunately, we can't bump GL_MAX_TEXTURE_SIZE to 16384 without
causing regressions due to awful W-tiled stencil buffer interactions.)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74130
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 06b047ebc75c6af02f806d051a5703748ee76b69 |
|
02-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Bump MAX_3D_TEXTURE_SIZE to 2048.
It's highly unlikely that there will be enough memory in the system to
allocate enough space for this, but we should still expose the hardware
limit. It's what the Intel Windows driver does, and it seems most other
vendors do likewise.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74130
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 4e0924c5de5f3964e4ca81f923d877dbb59fad0a |
|
13-Feb-2014 |
Eric Anholt <eric@anholt.net> |
i965: Move singlesample_mt to the renderbuffer.
Since only window system renderbuffers can have a singlesample_mt, this
lets us drop a bunch of sanity checking to make sure that we're just a
renderbuffer-like thing.
v2: Fix a badly-written comment (thanks Kenneth!), drop the now trivial
helper function for set_needs_downsample.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 019560c127778dc3b08bdc7c3acdc68dbbb80ea0 |
|
13-Feb-2014 |
Eric Anholt <eric@anholt.net> |
i965: Drop some duplicated code in DRI winsys BO updates.
The only DRI2 vs DRI3 delta was just how to decide about frontbuffer-ness
for doing the upsample.
v2: Fix missing singlesample_mt->region->name update in the merged code,
which would have broken the DRI2 don't-recreate-the-miptree
optimization.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0c14c5c62a1b4648381c05f024db730e4a0f90c5 |
|
02-Feb-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Enable ARB_texture_gather for one component on Gen6.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0f6279bab29614e3764a333242680ead78068d91 |
|
31-Dec-2013 |
Eric Anholt <eric@anholt.net> |
i965: Add some informative debug when the X Server botches DRI2 GetBuffers.
We've had various bug reports over the years where miptrees are missing,
and when I screwed it up while adding DRI2 to the modesetting driver, I
figured I should put the info necessary for debug here.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 25268b930dbd9bc89c0cce83746c5ca2f534c016 |
|
07-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965/cs: Allow ARB_compute_shader to be enabled via env var.
This will allow testing of compute shader functionality before it is
completed.
To enable ARB_compute_shader functionality in the i965 driver, set
INTEL_COMPUTE_SHADER=1.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9cd65e3289ecb1df7148d01d453f8804e75c087f |
|
14-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.
The amount of cut and paste from Gen7 is rather ugly, and should
probably be cleaned up in the future. Even the Gen7 code is in need of
some tidying though; many of the function parameters aren't used on
platforms that use level/layer rather than tile offsets. Tidying both
can be left to a future patch series. This at least gets things going.
v2: Rebase on Paul's rename of NumLayers -> MaxNumLayers.
v3: Shift QPitch by 2 when storing it in the packet. Bits 14:0 store
bits 16:2 of the actual value. Fixes tests.
v4: Add missing stencil buffer QPitch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| dcbf25969ed0b7154506347efd9e7aaa945a3a16 |
|
05-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rework SURFACE_STATE entries for Broadwell.
v2: Add missing SCS setting in gen8_emit_buffer_surface_state (caught by
Eric Anholt).
v3: Use stored QPitch rather than recomputing it.
v4: Shift QPitch by 2 when setting it in the packet; bits 14:0 store
bits 16:2 of the actual value (fixes myriads of cube and array
texturing tests). Also, only enable cube face bits for cubemaps
(matches Chris Forbes' commit on master). Port to use offset64.
v5: s/gl_format/mesa_format/g
v6: Fix DW5 of renderbuffer state, which neglected to subtract
irb->mt->first_level. Use vertical_alignment() rather than
hardcoding 4. Use ffs for multisample counts rather than a
large switch statement (all caught/suggested by Eric).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| eeed49f5f290793870c60b5b635b977a732a1eb4 |
|
27-Jan-2014 |
Mark Mueller <MarkKMueller@gmail.com> |
mesa: Change many Type P MESA_FORMATs to meet naming spec
Conversion of Type P formats as follows (w/related comment fixes):
s/MESA_FORMAT_RGB565\b/MESA_FORMAT_B5G6R5_UNORM/g
s/MESA_FORMAT_RGB565_REV\b/MESA_FORMAT_R5G6B5_UNORM/g
s/MESA_FORMAT_ARGB4444\b/MESA_FORMAT_B4G4R4A4_UNORM/g
s/MESA_FORMAT_ARGB4444_REV\b/MESA_FORMAT_A4R4G4B4_UNORM/g
s/MESA_FORMAT_RGBA5551\b/MESA_FORMAT_A1B5G5R5_UNORM/g
s/MESA_FORMAT_XBGR8888_SNORM\b/MESA_FORMAT_R8G8B8X8_SNORM/g
s/MESA_FORMAT_XBGR8888_SRGB\b/MESA_FORMAT_R8G8B8X8_SRGB/g
s/MESA_FORMAT_ARGB1555\b/MESA_FORMAT_B5G5R5A1_UNORM/g
s/MESA_FORMAT_ARGB1555_REV\b/MESA_FORMAT_A1R5G5B5_UNORM/g
s/MESA_FORMAT_AL44\b/MESA_FORMAT_L4A4_UNORM/g
s/MESA_FORMAT_RGB332\b/MESA_FORMAT_B2G3R3_UNORM/g
s/MESA_FORMAT_ARGB2101010\b/MESA_FORMAT_B10G10R10A2_UNORM/g
s/MESA_FORMAT_Z24_S8\b/MESA_FORMAT_S8_UINT_Z24_UNORM/g
s/MESA_FORMAT_S8_Z24\b/MESA_FORMAT_Z24_UNORM_S8_UINT/g
s/MESA_FORMAT_X8_Z24\b/MESA_FORMAT_Z24_UNORM_X8_UINT/g
s/MESA_FORMAT_Z24_X8\b/MESA_FORMAT_X8Z24_UNORM/g
s/MESA_FORMAT_RGB9_E5_FLOAT\b/MESA_FORMAT_R9G9B9E5_FLOAT/g
s/MESA_FORMAT_R11_G11_B10_FLOAT\b/MESA_FORMAT_R11G11B10_FLOAT/g
s/MESA_FORMAT_Z32_FLOAT_X24S8\b/MESA_FORMAT_Z32_FLOAT_S8X24_UINT/g
s/MESA_FORMAT_ABGR2101010_UINT\b/MESA_FORMAT_R10G10B10A2_UINT/g
s/MESA_FORMAT_XRGB4444_UNORM\b/MESA_FORMAT_B4G4R4X4_UNORM/g
s/MESA_FORMAT_XRGB1555_UNORM\b/MESA_FORMAT_B5G5R5X1_UNORM/g
s/MESA_FORMAT_XRGB2101010_UNORM\b/MESA_FORMAT_B10G10R10X2_UNORM/g
s/MESA_FORMAT_AL88\b/MESA_FORMAT_L8A8_UNORM/g
s/MESA_FORMAT_AL88_REV\b/MESA_FORMAT_A8L8_UNORM/g
s/MESA_FORMAT_AL1616\b/MESA_FORMAT_L16A16_UNORM/g
s/MESA_FORMAT_AL1616_REV\b/MESA_FORMAT_A16L16_UNORM/g
s/MESA_FORMAT_RG88\b/MESA_FORMAT_G8R8_UNORM/g
s/MESA_FORMAT_GR88\b/MESA_FORMAT_R8G8_UNORM/g
s/MESA_FORMAT_GR1616\b/MESA_FORMAT_R16G16_UNORM/g
s/MESA_FORMAT_RG1616\b/MESA_FORMAT_G16R16_UNORM/g
s/MESA_FORMAT_SRGBA8\b/MESA_FORMAT_A8B8G8R8_SRGB/g
s/MESA_FORMAT_SARGB8\b/MESA_FORMAT_B8G8R8A8_SRGB/g
s/MESA_FORMAT_SLA8\b/MESA_FORMAT_L8A8_SRGB/g
Conflicts:
src/mesa/drivers/dri/i965/brw_surface_formats.c
src/mesa/main/format_pack.c
src/mesa/main/format_unpack.c
src/mesa/main/formats.c
src/mesa/main/texformat.c
src/mesa/main/texstore.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ef145ba4ded6aafb28e3bda02fb348e6b8bff12a |
|
20-Jan-2014 |
Mark Mueller <MarkKMueller@gmail.com> |
mesa: Rename 4 color component unsigned byte MESA_FORMATs
Change all 4 color component unsigned byte formats to meet spec for P
Type formats:
s/MESA_FORMAT_RGBA8888\b/MESA_FORMAT_A8B8G8R8_UNORM/g
s/MESA_FORMAT_RGBA8888_REV\b/MESA_FORMAT_R8G8B8A8_UNORM/g
s/MESA_FORMAT_ARGB8888\b/MESA_FORMAT_B8G8R8A8_UNORM/g
s/MESA_FORMAT_ARGB8888_REV\b/MESA_FORMAT_A8R8G8B8_UNORM/g
s/MESA_FORMAT_RGBX8888\b/MESA_FORMAT_X8B8G8R8_UNORM/g
s/MESA_FORMAT_RGBX8888_REV\b/MESA_FORMAT_R8G8B8X8_UNORM/g
s/MESA_FORMAT_XRGB8888\b/MESA_FORMAT_B8G8R8X8_UNORM/g
s/MESA_FORMAT_XRGB8888_REV\b/MESA_FORMAT_X8R8G8B8_UNORM/g
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d8c7740ddabeb456243e40dc3cf0e86c7fca09d0 |
|
15-Jan-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Support 32 texture image units on Haswell+.
The Intel closed source OpenGL driver recently began supporting 32
texture image units on Haswell. This makes the open source driver
support 32 as well.
Earlier generations don't have the message header field required to
support more than 16 sampler states, so we continue to advertise 16
there.
On Haswell, this causes us to advertise:
- GL_MAX_TEXTURE_IMAGE_UNITS = 32
- GL_MAX_VERTEX_TEXTURE_IMAGE_UNITS = 32
- GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS = 96
instead of the old values of 16, 16, and 48.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 11baad35088dfd4bdabc1710df650dbfb413e7a3 |
|
21-Jan-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Fix initial MakeCurrent for single-buffer drawables
Commit 05da4a7a5e7d5bd988cb31f94ed8e1f053d9ee39 attempts to eliminate the
call to intel_update_renderbuffer() in the case where we already have a
drawbuffer for the drawable. Unfortunately this only checks the
back left renderbuffer, which breaks in case of single buffer drawables.
This means that the initial viewport will not be set in that case. Instead,
we now check whether the initial viewport has not been set, in which case
we call out to intel_update_renderbuffer().
https://bugs.freedesktop.org/show_bug.cgi?id=73862
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 13100ac142e935c422018d5152b27ce3564def08 |
|
03-Jan-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Enable AOS optimizations for the geometry shader.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ebf91993c18bdf90c4699b42e58cb84d0b160f25 |
|
03-Jan-2014 |
Matt Turner <mattst88@gmail.com> |
mesa: rename PreferDP4 to OptimizeForAOS.
This flag was really just a proxy for determining whether the backend
was vector (AOS) or scalar (SOA). It will be used to apply a future
optimization only for vector backends.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7837f425e7242bfc12f3d6d57d343609071ea6aa |
|
13-Nov-2013 |
Courtney Goeltzenleuchter <courtney@LunarG.com> |
i965: Enable ARB_viewport_array
v2 (idr): Only enable the extension on GEN7+ w/core profile because it
requires geometry shaders.
v3 (idr): Add some casting to fix setting of ViewportBounds.Min.
Negating an unsigned value, then casting to float doesn't do what you
might think it does.
Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 05da4a7a5e7d5bd988cb31f94ed8e1f053d9ee39 |
|
18-Jan-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
i965: Only update renderbuffers on initial intelMakeCurrent
We call intel_prepare_render() in intelMakeCurrent() to make sure we have
renderbuffers before calling _mesa_make_current(). The only reason we
do this is so that we can have valid defaults for width and height.
If we already have buffers for the drawable we're making current, we
don't need this step.
In itself, this is a small optimization, but it also avoids a round trip
that could block on the display server in a unexpected place.
https://bugs.freedesktop.org/show_bug.cgi?id=72540
https://bugs.freedesktop.org/show_bug.cgi?id=72612
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 877128505431adaf817dc8069172ebe4a1cdf5d8 |
|
17-Jan-2014 |
José Fonseca <jfonseca@vmware.com> |
s/Tungsten Graphics/VMware/
Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the
old copyright name is creating unnecessary confusion, hence this change.
This was the sed script I used:
$ cat tg2vmw.sed
# Run as:
#
# git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed
#
# Rename copyrights
s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g
/Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./
s/TUNGSTEN GRAPHICS/VMWARE/g
# Rename emails
s/alanh@tungstengraphics.com/alanh@vmware.com/
s/jens@tungstengraphics.com/jowen@vmware.com/g
s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/
s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g
s/keithw\?@tungstengraphics.com/keithw@vmware.com/g
s/michel@tungstengraphics.com/daenzer@vmware.com/g
s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/
s/zack@tungstengraphics.com/zackr@vmware.com/
# Remove dead links
s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g
# C string src/gallium/state_trackers/vega/api_misc.c
s/"Tungsten Graphics, Inc"/"VMware, Inc"/
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 065bd6ffc23c9cfef9b10418fb06233a912d6471 |
|
05-Nov-2013 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Eliminate parameters to dd_function_table::Viewport
No driver uses them. They will just be annoying in future patches.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 84732a982c3eeaca2e2809532c8422dc5f7045c1 |
|
08-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
mesa: replace ctx->Const.{Vertex,Fragment,Geomtery}Program with an array.
These are replaced with
ctx->Const.Program[MESA_SHADER_{VERTEX,FRAGMENT,GEOMETRY}]. In
patches to follow, this will allow us to replace a lot of ad-hoc logic
with a variable index into the array.
With the exception of the changes to mtypes.h, this patch was
generated entirely by the command:
find src -type f '(' -iname '*.c' -o -iname '*.cpp' -o -iname '*.py' \
-o -iname '*.y' ')' -print0 | xargs -0 sed -i \
-e 's/Const\.VertexProgram/Const.Program[MESA_SHADER_VERTEX]/g' \
-e 's/Const\.GeometryProgram/Const.Program[MESA_SHADER_GEOMETRY]/g' \
-e 's/Const\.FragmentProgram/Const.Program[MESA_SHADER_FRAGMENT]/g'
Suggested-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 665b8d7b6d8eae03c9dc0ef1a744fe59d9cc6cb6 |
|
07-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
mesa: Clean up nomenclature for pipeline stages.
Previously, we had an enum called gl_shader_type which represented
pipeline stages in the order they occur in the pipeline
(i.e. MESA_SHADER_VERTEX=0, MESA_SHADER_GEOMETRY=1, etc), and several
inconsistently named functions for converting between it and other
representations:
- _mesa_shader_type_to_string: gl_shader_type -> string
- _mesa_shader_type_to_index: GLenum (GL_*_SHADER) -> gl_shader_type
- _mesa_program_target_to_index: GLenum (GL_*_PROGRAM) -> gl_shader_type
- _mesa_shader_enum_to_string: GLenum (GL_*_{SHADER,PROGRAM}) -> string
This patch tries to clean things up so that we use more consistent
terminology: the enum is now called gl_shader_stage (to emphasize that
it is in the order of pipeline stages), and the conversion functions are:
- _mesa_shader_stage_to_string: gl_shader_stage -> string
- _mesa_shader_enum_to_shader_stage: GLenum (GL_*_SHADER) -> gl_shader_stage
- _mesa_program_enum_to_shader_stage: GLenum (GL_*_PROGRAM) -> gl_shader_stage
- _mesa_progshader_enum_to_string: GLenum (GL_*_{SHADER,PROGRAM}) -> string
In addition, MESA_SHADER_TYPES has been renamed to MESA_SHADER_STAGES,
for consistency with the new name for the enum.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
v2: Also rename the "target" field of _mesa_glsl_parse_state and the
"target" parameter of _mesa_shader_stage_to_string to "stage".
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c426fb08cfd973b255d6e97d99350efc38b740ed |
|
22-Nov-2013 |
Keith Packard <keithp@keithp.com> |
i965: Correct check for re-bound buffer in intel_update_image_buffer
The buffer-object is the persistent thing passed through the loader, so when
updating an image buffer, check to see if it is already bound to the provided
bo. The region, on the other hand, is allocated separately for the miptree,
and so will never be the same as that passed back from the loader.
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 38366c0c6e715314367b15680702e382d5c46a4a |
|
08-Dec-2013 |
Kristian Høgsberg <krh@bitplanet.net> |
dri_util: Don't assume __DRIcontext->driverPrivate is a gl_context
The driverPrivate pointer is opaque to the driver and we can't assume
it's a struct gl_context in dri_util.c. Instead provide a helper function
to set the struct gl_context flags from the incoming DRI context flags.
v2 (idr): Modify the other classic drivers to also use
driContextSetFlags. I ran all the piglit GLX_ARB_create_context tests
with i965 and classic swrast without regressions.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> [v1]
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu> [v1 on Gallium nouveau]
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a7bdd4cba8ddcab8dff59ecaaa7efbd436c6c307 |
|
26-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Drop trailing whitespace from the rest of the driver.
Performed via:
$ for file in *; do sed -i 's/ *//g'; done
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 53a65e547c0bf769fff48b4ccb41d1477daa70de |
|
27-Nov-2013 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Properly reject __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS when __DRI2_ROBUSTNESS is not enabled
Only allow __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS in brwCreateContext if
intelInitScreen2 also enabled __DRI2_ROBUSTNESS (thereby enabling
GLX_ARB_create_context).
This fixes a regression in the piglit test
"glx/GLX_ARB_create_context/invalid flag"
v2: Remove commented debug code. Noticed by Jordan.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reported-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9b1c68638d8096304d3c4e0cceb97bb4dc61acc5 |
|
20-Nov-2013 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Only enable __DRI2_ROBUSTNESS if kernel support is available
Rather than always advertising the extension but failing to create a
context with reset notifiction, just don't advertise it. I don't know
why it didn't occur to me to do it this way in the first place.
NOTE: Kristian requested that I provide a follow-up for master that
dynamically generates the list of DRI extensions instead of selected
between two hardcoded lists.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Suggested-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0ae84399069b77e9464462c53405baf6f854a6fd |
|
18-Nov-2013 |
Ian Romanick <ian.d.romanick@intel.com> |
Revert "i965: Make the driver compile until a proper libdrm can be released."
libdrm 2.4.48 has been released.
This reverts commit bd4596efac2b783b789392a222da909efcd0fd3b.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 315b06ff62357d2196d9f1d4926c517d098e5647 |
|
07-Nov-2013 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Let driconf clamp_max_samples affect context version
Commit 2f89662 added the driconf option 'clamp_max_samples'. In that
commit, the option did not alter the context version. The neglect to
alter the context version is a fatal issue for some apps.
For example, consider running Chromium with clamp_max_samples=0.
Pre-patch, Mesa creates a GL 3.0 context but clamps GL_MAX_SAMPLES to
0. This violates the GL 3.0 spec, which requires GL_MAX_SAMPLES >= 4.
The spec violation causes WebGL context creation to fail in many
scenarios because Chromium correctly assumes that a GL 3.0 context
supports at least 4 samples.
Since the driconf option was introduced largely for Chromium, the issue
really needs fixing.
This patch fixes calculation of the context version to respect the
post-clamped value of GL_MAX_SAMPLES. This in turn fixes WebGL on
Chromium when clamp_max_samples=0.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 95ebabbc5fceec6a9c37dbb4d8f3282a86fe02ce |
|
07-Nov-2013 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Share code between intel_quantize_num_samples and clamp_max_samples
clamp_max_samples() and intel_quantize_num_samples() each maintained
their own list of which MSAA modes the hardware supports. This patch
removes the duplication by making intel_quantize_num_samples() use the
same list as clamp_max_samples(), the list maintained in
brw_supported_msaa_modes().
By removing the duplication, we prevent the scenario where someone
updates one list but forgets to update the other.
Move function `brw_context.c:static brw_supported_msaa_modes()` to
`intel_screen.c:(non-static) intel_supported_msaa_modes()` and patch
intel_quantize_num_samples() to use the list returned by that function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 8d1a8d65b55bac28fe2c63847b1ef216b7f2c9aa |
|
15-Nov-2013 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Terminate brw_supported_msaa_modes() list with -1, not 0
This simplifies the loop logic in a subsqequent patch that refactors
intel_quantize_num_samples() to use brw_supported_msaa_modes().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 379a246fc190c1bc1664a4ecf24aabca13314c7f |
|
31-Oct-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add basic driver hooks and plumbing for AMD_performance_monitor.
These stub functions will be filled out in later patches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 01ae16a0e7d95f408016ff5b07bc647ad5608841 |
|
15-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disable HiZ on Broadwell for now.
HiZ is difficult to implement, and while it's essential for performance,
we don't need it right away for purposes of hardware enabling.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7dfb4b2d00ddb8e5ee24d4c58eb9415dc4ccc21c |
|
05-Nov-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gen7: Emit workaround flush when changing GS enable state.
v2: Don't go to extra work to avoid extraneous flushes. (Previous
experiments in the kernel have suggested that flushing the pipeline
when it is already empty is extremely cheap).
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| bd4596efac2b783b789392a222da909efcd0fd3b |
|
08-Nov-2013 |
Eric Anholt <eric@anholt.net> |
i965: Make the driver compile until a proper libdrm can be released.
No depending on unreleased code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 442442026eb241f05f2b7c03da304e0be047a7da |
|
05-Nov-2013 |
Keith Packard <keithp@keithp.com> |
dri: add __DRIimageLoaderExtension and __DRIimageDriverExtension
These provide an interface between the driver and the loader to allocate
color buffers through the DRIimage extension interface rather than through a
loader-specific extension (as is used by DRI2, for instance).
The driver uses the loader 'getBuffers' interface to allocate color buffers.
The loader uses the createNewScreen2, createNewDrawable, createNewContext,
getAPIMask and createContextAttribs APIS (mostly shared with DRI2).
This interface will work with the DRI3 loader, and should also work with GBM
and other loaders so that drivers need not be customized for each new loader
interface, as long as they provide this image interface.
v2: Fix build of i915 and i965 together (by anholt)
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 888533dcd6fe30fc0729ef4ae8fa495c69dcc629 |
|
04-Jun-2013 |
Keith Packard <keithp@keithp.com> |
dri/intel: Split out DRI2 buffer update code to separate function
Make an easy place to splice in a DRI3 version of this function
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 83ffe47be0e26dcbaf917807447d82d53bb2c13b |
|
11-Oct-2013 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Refactor the renderer string creation out of intelGetString
This will soon be used in intel_screen.c from a function that doesn't
have a gl_context.
v2: Delete local variables that are now unused. This matches v1 of the
changes to the i915 driver.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 18291251ec3e17967b9df89815c9d2dc92bf41dc |
|
11-Oct-2013 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Refactor the vendor string out of intelGetString
This will soon be used in intel_screen.c from a function that doesn't
have a gl_context.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e8dac9632d35b5902b6565e64b22846ba6198b5b |
|
11-Sep-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Propagate the GPU reset notifiction strategy down into the driver
If the application requests reset notifiction, connect up the reset
status query method and set gl_context::ResetStrategy.
v2: Update based on kernel interface / libdrm changes.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 15c3bac3d00694245168586fee2d257920895a2f |
|
11-Sep-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Handle __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS flag
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7b140d1bdaf07badebdc5ac222ab4ff4d182ebec |
|
10-Sep-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa/dri: Move context flag validation down into the drivers
Soon some drivers will support a different set of flags than other
drivers. If some flags have to be filtered in the driver, we might as
well filter all of them in the driver.
The changes in nouveau use tabs because nouveau seems to have it's own
indentation rules.
v2: Fix some rebase failures noticed by Ken (returning the wrong types,
etc.).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 17c94de33baf66ad5c264b7a046394c651bc6126 |
|
10-Sep-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa/dri: Add basic plumbing for GLX_ARB_robustness reset notification strategy
No drivers advertise the DRI2 extension yet, so no driver should ever
see a value other than false for notify_reset.
The changes in nouveau use tabs because nouveau seems to have it's own
indentation rules.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 597634556e4d24c5a3aec2da227034a733693571 |
|
20-Oct-2013 |
Francisco Jerez <currojerez@riseup.net> |
i965/gen7: Expose ARB_shader_atomic_counters.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 30f61c471de5a9637e5d830e2b5b9dc4145f94d2 |
|
23-Oct-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
Revert "i965: Add support for GL_AMD_performance_monitor on Ironlake."
This reverts most of commit 0f2da773070c06b6d20ad264d3abb19c4dfd9761.
(I chose to leave the additions to brw_defines.h.)
My previous Ironlake implementation was somewhat broken: counter data
was global, rather than per-context. This meant that performance
monitors captured data from your compositor, 2D driver, and other 3D
programs.
Originally, I believed that Sandybridge and later had an easy way to
avoid this problem (setting per-context flags in OACONTROL), while
Ironlake did not. So I'd intended to leave it as a known limitation of
performance monitoring support on Ironlake. However, this turned out
not to be true.
Unfortunately, our hardware only has one set of aggregating performance
counters shared between all 3D programs, and their values are not saved
or restored by hardware contexts. Also, at least on Sandybridge and
Ivybridge, the counters lose their values if the GPU goes to sleep.
To work around both of these problems, we have to snapshot the
performance counters at the beginning and end of each batch, similar to
how we handle query objects on platforms that don't support hardware
contexts.
For occlusion queries, this batch bookending approach is fairly simple:
only one occlusion query can be active at a time, and the result is a
single integer. Performance monitors are more complex: an arbitrary
number of monitors can be active at a time, each monitoring some subset
of our ~30 observability counters. Individual monitors can be started
and stopped at any point during the batch. Tracking where each monitor
started/ended relative to batch flushes ends up being a pain. And you
can run out of space in the buffer.
Properly supporting this required some serious rearchitecting of the
code. Rather than writing patches to try and morph a broken system into
a working one (which operates quite differently), I decided it would be
simplest to revert the old code and start fresh. Parts will look
familiar, but other parts are new.
I also decided it would be best to include Sandybridge and Ivybridge
support from the start, since the newer platforms have added complexity
that I wanted to make sure worked. They're also what most people care
about these days.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e3854fe194021e61eff70c614550bbfc79d2b22e |
|
30-Oct-2013 |
Courtney Goeltzenleuchter <courtney@lunarg.com> |
i965: Fix compiler warning.
fix: intel_screen.c:1320:4: warning: initialization from
incompatible pointer type [enabled by default]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3f319eef76a31776085accb38c06851bc04f64b8 |
|
05-Nov-2013 |
Eric Anholt <eric@anholt.net> |
i965: Fix context initialization after 2f896627175384fd5
You can't return stack-initialized values and expect anything good to
happen.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| abd962f1d5e0991073312305560516a3e64ef1cb |
|
01-Nov-2013 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Eliminate the saved_viewport wrapper
The i965 driver never installed a dd_function_table::Viewport function,
so this wrapper never actually did anything.
No piglit regressions on IVB on DRI2.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jljusten@gmail.com>
Cc: Courtney Goeltzenleuchter <courtney@lunarg.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2f896627175384fd5943f21804700a155ba4e8a0 |
|
03-Nov-2013 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Add driconf option clamp_max_samples
The new option clamps GL_MAX_SAMPLES to a hardware-supported MSAA mode.
If negative, then no clamping occurs.
v2: (for Paul)
- Add option to i965 only, not to all DRI drivers.
- Do not realy on int->uint cast to convert negative
values to large positive values. Explicitly check for
clamp_max_samples < 0.
v3: (for Ken)
- Don't allow clamp_max_samples to alter context version.
- Use clearer for-loop and correct comment.
- Rename variables.
v4: (for Ken)
- Merge identical if-branches.
Reviewed-and-tested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 46d3c2bf4ddd227193b98861f1e632498fe547d8 |
|
26-Oct-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initialize batchbuffer and state modules before extensions.
We only want to enable ARB_transform_feedback2 if we can write to
registers from batchbuffers. In order to test that, we need to be able
to submit batches. And for batches to work, we need to program the
initial pipeline state (like PIPELINE_SELECT), which is done from
brw_state_init().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 82a5ee6be4b4f5881d86f18d4b002d23c9e18ea5 |
|
07-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Implement glDrawTransformFeedback().
Implementing the GetTransformFeedbackVertexCount() driver hook allows
the VBO module to call us with the right number of vertices.
The hardware doesn't directly count the number of vertices written by
SOL, so we instead use the SO_NUM_PRIMS_WRITTEN(n) counters and multiply
by the number of vertices per primitive.
Unfortunately, counting the number of primitives generated is tricky:
a program might pause a transform feedback operation, start a second one
with a different object, then switch back and resume. Both transform
feedback operations share the SO_NUM_PRIMS_WRITTEN counters.
To work around this, we save the counter values at Begin, Pause, Resume,
and End. This "bookends" each section where transform feedback is
active for the current object. Adding up differences of pairs gives
us the number of primitives generated. (This is similar to what we
do for occlusion queries on platforms without hardware contexts.)
v2: Fix missing parenthesis in assertion (caught by Eric Anholt).
v3: Reuse prim_count_bo rather than freeing it and immediately
allocating a new one (suggested by Topi Pohjolainen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ded34f65ad6bd69a4af94945527de74761a866e6 |
|
27-May-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
mesa: Add a new GetTransformFeedbackVertexCount() driver hook.
DrawTransformFeedback() needs to obtain the number of vertices written
to a particular stream during the last Begin/EndTransformFeedback block.
The new driver hook returns exactly that information.
Gallium drivers already implement this by passing the transform feedback
object to the drawing function, counting the number of vertices written
on the GPU, and using draw indirect. This is efficient, but doesn't
always work:
If vertex data comes from user arrays, then the VBO module needs to
know how many vertices to upload, so we need to synchronously count.
Gallium drivers are currently broken in this case.
It also doesn't work if primitive restart is done in software. For
normal drawing, vbo_draw_arrays() performs software primitive restart,
splitting the draw call in two. vbo_draw_transform_feedback() currently
doesn't because it has no idea how many vertices need to be drawn.
The new driver hook gives it that information, allowing us to reuse
the existing vbo_draw_arrays() code to do everything right.
On Intel hardware (at least Ivybridge), using the draw indirect approach
is difficult since the hardware counts primitives, rather than vertices,
which requires doing some simple math. So we always use this hook.
Gallium drivers will likely want to use this hook in some cases, but
want to use the existing draw indirect approach where possible. Hence,
I've added a flag to allow drivers to opt-in to this call.
v2: Make it possible to implement this hook but only use this path
when necessary (suggested by Marek).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 684958d1e7415267e8276654390ea610eefaa95f |
|
27-May-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Implement Pause/ResumeTransformfeedback driver hooks on Gen7+.
The ARB_transform_feedback2 extension introduces the ability to pause
and resume transform feedback sessions. Although only one can be active
at a time, it's possible to switch between multiple transform feedback
objects while paused.
In order to facilitate this, we need to save/restore the SO_WRITE_OFFSET
registers so that after resuming, the GPU continues writing where it
left off.
This functionality also exists in ES 3.0, but somehow we completely
forgot to implement it.
v2: Reduce alignment from 4096 to 64 (it seemed excessive).
v3: Use I915_GEM_DOMAIN_INSTRUCTION instead of RENDER, for consistency
with other writes. It shouldn't matter on IVB+.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0d7033c3940aa6aef7ab72dc31ab154b2e614b1b |
|
24-May-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Create a new brw_transform_feedback_object subclass.
This adds the basic driver hooks to allocate/free the brw variant.
It doesn't contain any additional information yet, but it will soon.
v2: Use the new _mesa_init_transform_feedback_object helper function
(requested by Eric and Ian).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 1e3e72e3054de27b35322feb6c715e433b00be2a |
|
16-Oct-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Reduce gl_MaxGeometryInputComponents to 64.
Although in principle there is no hardware limitation that prevents
gl_MaxGeometryInputComponents from being set to 128 on Gen7, we have
the following limitations in the vec4 compiler back end:
- Registers assigned to geometry shader inputs can't be spilled or
later re-used for any other purpose.
- The last 16 registers are set aside for the "MRF hack", meaning they
can only be used to send messages, and not for general purpose
computation.
- Up to 32 registers may be reserved for push constants, even if there
is sufficient register pressure to make this impractical.
A shader using 128 geometry input components, and having an input type
of triangles_adjacency, would use up:
- 1 register for r0 (which holds URB handles and various pieces of
control information).
- 1 register for gl_PrimitiveID.
- 102 registers for geometry shader inputs (17 registers per input
vertex, assuming DUAL_INSTANCED dispatch mode and allowing for one
register of overhead for gl_Position and gl_PointSize, which are
present in the URB map even if they are not used).
- Up to 32 registers for push constants.
- 16 registers for the "MRF hack".
That's a total of 152 registers, which is well over the 128 registers
the hardware supports.
Fortunately, the GLSL 1.50 spec allows us to reduce
gl_MaxGeometryInputComponents to 64. Doing that frees up 48
registers, brining the total down to 104 registers, leaving 24
registers available to do computation.
Fixes piglit test
spec/glsl-1.50/execution/geometry/max-input-components.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| fe36154ff3b2c095cf21462dd7ed6b5ae374fccc |
|
23-Oct-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix gl_MaxCombinedTextureImageUnits.
We've always overriden
ctx->Const.{Vertex,Fragment}Program.MaxTextureImageUnits to reflect
the number of texture image units supported by the hardware (rather
than using the default values assigned by Mesa core) so it seems
sensible to do that for GeometryProgram.MaxTextureImageUnits too. We
set it to 0 if geometry shaders aren't supported.
Once that is done, we can just unconditionally add
GeometryProgram.MaxTextureImageUnits to MaxCombinedTextureImageUnits.
Fixes piglit test "spec/glsl-1.50/built-in
constants/gl_MaxCombinedTextureImageUnits".
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a5e2e7f9a4bc813ce85f4a10bcd6086f21aa8a32 |
|
05-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_ARB_texture_buffer_range.
Supporting this extension turns out to simplify our code a bit over not
supporting this extension, once the glBufferSubData() synchronization code
lands.
v2: Use 16 byte alignment like we do for uniform buffers, due to unaligned
access penalties.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| cc2f87891bc6bb77ad26383e974ebeaf67b839fe |
|
22-Oct-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Drop unused simple_list.h includes.
These don't appear to be necessary. Everything compiles just fine.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b3360d23ac1db61390b2ac8963756c6133ba6e23 |
|
16-Oct-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fold brwInitVtbl() into brwCreateContext().
With most of the virtual functions gone, brwInitVtbl() is now tiny.
Merging it into the caller allows us to delete the entire file.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f8fef8ee92576b847a4e963f2bee9bc5d1f280ba |
|
16-Oct-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Merge brw_destroy_context() into intelDestroyContext().
Now that i915 and i965 have been split, the separation between
intelDestroyContext and brw_destroy_context is kind of arbitrary.
This patch replaces the only brw->vtbl.destroy() call with the body
of brw_destroy_context (the only implementation of that virtual
function).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 5f76bc37abe39bad8ad99a51864f8beda0f6d3d7 |
|
16-Oct-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Unindent the body of intelDestroyContext.
Having almost the entire body of the function indented one level for a
check that should never happen seems silly. Just early return.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 50c9f04c5f5700ac27f8552694d2a2f2ab6fe89f |
|
28-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move need_workaround_flush = true to intel_batchbuffer_init.
intel_batchbuffer_init() sets up initial batchbuffer state; it seems
like a reasonable place to initialize this flag.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ddc8decdb211f905bad5c903a38cd3cbbf62418d |
|
28-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move DriverFlag initialization to brw_init_state().
Configuring which dirty flags we want sounds like a job for
brw_init_state().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ba0cc79ab936fb0a5c7a666b98f69c28b31a00b5 |
|
27-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Merge intelInitContext into brwCreateContext.
The split here was completely arbitrary.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 90d52d2c76f88f1b3999ebbc7f737800e4b9bd06 |
|
27-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move viewport driver hook setup to brw_init_driver_functions.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f118fc26e14b460e1dfb735892b1627948f592fc |
|
27-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make brwInitFunctions take brw_context rather than intel_screen.
It actually just wants generation checking, and brw->gen is the usual
way of doing that. In the future, we'll also want to check brw->hw_ctx,
which isn't available from the screen.
While we're changing the function signature, convert from camel case to
our usual naming conventions.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9848a422879e0b5fef5930bfcb105b01d94f3bab |
|
27-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Merge intelInitFunctions() and brwInitFunctions().
They do exactly the same thing.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0138fd46104850afe2e86483f3d3a436007b2c12 |
|
27-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Merge intel_context.c into brw_context.c.
There's no point in having two files for context functions. This patch
moves the code from intel_context.c into brw_context.c unmodified
(other than whitespace fixes).
Right now, this looks silly; future patches will merge functions and
tidy things up.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| fc5b865cec99c34586b2f5484c46af419b2a0395 |
|
26-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove has_aa_line_parameters.
This flag is only used in one place, and is only set on one platform.
Just check for original Gen4 in the relevant function.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 220c1e5610faf228e342153e544a3ce9040301a1 |
|
26-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move state setup from brwCreateContext to brw_init_state().
This seems like a better place for it, and helps clean up
brwCreateContext (which is full of a lot of random stuff).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d31b928b93694de0a1408f36acb675485fea5973 |
|
26-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove the brw_context::emit_state_always flag.
This was always set to false, and is only used for debugging.
To enable it, simply change the if (0) block and recompile.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 02b632d8e8f2b14c155740d28c276b5869305c60 |
|
26-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move hardware feature flags to brw_device_info.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ea890c031ddc69abb6670ad9b769ef1eecd11e28 |
|
26-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move device quirks to brw_device_info.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d76f6c7ae4d738193af2b3a06c4e6321e5e4daac |
|
26-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move hardware limits to brw_device_info.
Since each kind of device has its own brw_device_info structure, we can
simply store the URB and thread limits there. This eliminates all the
large if-ladders, and simplifies the context initialization code quite a
bit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| afe05e71931f53843999ea967946fae1b219a374 |
|
04-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Replace some intel_screen fields with brw_device_info references.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 90511faedddff834ab1f6d92f4d5d25a3c32bd82 |
|
27-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pull most driconf option handling into a centralized function.
Using a helper function clarifies the context initialization code.
I would've liked to completely centralize it, but moving the optionCache
code from intelInitExtensions into here would've required setting flags
in the context, which seems like a waste.
v2: Rebase for the introduction of disable_derivative_optimization.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0fb525b87ceae543d581a5755ca547b54c58aa76 |
|
26-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move a bunch of code from intelInitContext to brwCreateContext.
Now that intelInitContext isn't shared between i915 and i965, the split
is fairly arbitrary. This patch moves a bunch of the basic context
creation and generation checking code up to the top-level function
(and slightly earlier).
More will follow.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3f7b4e5d04cf9f0274ddcd37d573eb96f835278e |
|
26-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename brwCreateContext's error parameter to dri_ctx_error.
"error" is a very generic name. dri_ctx_error is the name used in
intelInitContext(), which is more specific.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 95bd8a332d1c3f868d8e4ff454fb308acd9beed9 |
|
27-Sep-2013 |
Eric Anholt <eric@anholt.net> |
dri: Move i965-specific context flag logic to dri common.
Nobody else yet can do a forward context anyway, but others should be able
to do debug contexts, and those would have just had no effect currently.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ee8983beccfd4690e4cdd9b1d818aa284656ce88 |
|
27-Sep-2013 |
Eric Anholt <eric@anholt.net> |
i965: Clean up error handling for context creation.
The intel_screen.c used to be a dispatch to one of 3 driver functions, but
was down to 1, so it was kind of a waste. In addition, it was trying to
free all of the data that might have been partially freed in the kernel
3.6 check (which comes after intelInitContext, and thus might have had
driverPrivate set and result in intelDestroyContext() doing work on the
freed data). By moving the driverPrivate setup earlier, we can use
intelDestroyContext() consistently and avoid such problems in the future.
v2: Adjust the prototype of brwCreateContext to use the proper enum
(fixing a compiler warning in some builds)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7df985ad47df831f842843f2db9f7658b11d3df2 |
|
24-Mar-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Enable ARB_texture_gather on Gen7
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 848c0e72f36d0e1e460193a2d30b2f631529156f |
|
12-Sep-2013 |
Chia-I Wu <olv@lunarg.com> |
i965: compute DDX in a subspan based only on top row
Consider only the top-left and top-right pixels to approximate DDX in a 2x2
subspan, unless the application requests a more accurate approximation via
GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the
new driconf option disable_derivative_optimization.
This results in a less accurate approximation. However, it improves the
performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0%
confidence) on Haswell. No noticeable image quality difference observed.
The improvement comes from faster sample_d. It seems, on Haswell, some
optimizations are introduced to allow faster sample_d when all pixels in a
subspan have the same derivative. I considered SAMPLE_STATE too, which allows
one to control the quality of sample_d on Haswell. But it gave much worse
image quality without giving better performance comparing to this change.
No piglit quick.tests regression on Haswell (tested with v1).
v2: better guess for precompile program key
Signed-off-by: Chia-I Wu <olv@lunarg.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0f2da773070c06b6d20ad264d3abb19c4dfd9761 |
|
11-Apr-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add support for GL_AMD_performance_monitor on Ironlake.
Ironlake's counters are always enabled; userspace can simply send a
MI_REPORT_PERF_COUNT packet to take a snapshot of them. This makes it
easy to implement.
The counters are documented in the source code for the intel-gpu-tools
intel_perf_counters utility.
v2: Adjust for core data structure changes. Add a table mapping buffer
object offsets to exposed counters (which changes each generation).
Finally, add report ID assertions to sanity check the BO layout
(thanks to Carl Worth).
v3: Update for core BeginPerfMonitor hook changes (requested by Brian).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e1f8c585906c2a6ed463c13813e2a78357ebb341 |
|
18-Sep-2013 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Set *Program.Max{Input,Output}Components
Now that MaxVaryings is > 16, VertexProgram.MaxOutputComponents,
GeometryProgram.MaxInputComponents, GeometryProgram.MaxOutputComponents,
and FragmentProgram.MaxInputComponents also need to be set.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 24765c58bd7b041f92ff51ec354f5d6b0ce35daa |
|
03-Sep-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6+: Support 128 varying components.
GL 3.2 requires us to support 128 varying components for geometry
shader outputs and fragment shader inputs, and 64 varying components
otherwise. But there's no hardware limitation that restricts us to 64
varying components, and core Mesa doesn't currently allow different
stages to have different maximum values, so just go ahead and enable
128 varying components for all stages. This gets us better test
coverage anyway.
Even though we are only working on GL 3.2 support for gen7 right now,
gen6 also supports 128 varying components, so go ahead and switch it
on there too.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 588ec545acc930470c605005292c8ef10adf4919 |
|
01-Sep-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gen7.5: Fix lower bound on number of VS URB entries.
Haswell GT2 and GT3 require the number of vertex shader URB entries to
be at least 64, not 32.
At the moment, we always meet this requirement automatically, because
in the absence of a geometry shader, we assign all available URB space
to the vertex shader. But when we turn on support for geometry
shaders, this lower limit will become important.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b5c4795f386976830370f56d1fa5a1c4099d88e2 |
|
26-Aug-2013 |
Timothy Arceri <t_arceri@yahoo.com.au> |
mesa: Implement GL_DEBUG_OUTPUT
Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d65e3c082a02bd2e838d34b2ee9b87d36f6a2d25 |
|
22-Aug-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Allocate register set once at context creation.
Now that we use a fixed set of register classes, we can set up the
register set and conflict graphs once, at context creation, rather than
on every VS compile. This is obviously less expensive, and also what
we already do in the FS backend.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 52bac6e4ffb898d2222a59c9ee3c8d0a46426e20 |
|
10-Jun-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Initialize all elements of ctx->ShaderCompilerOptions.
Otherwise any GS that requires lowering (e.g. one that uses
gl_ClipDistance as an input or output) will fail to work.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c6b6c936434b98b0262fd0856b00f13f43edc6ba |
|
18-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: STATIC_ASSERT that there aren't too many BRW_NEW_* flags.
We are getting close to the maximum number of BRW_NEW_* bits that can
be stored in brw->state.dirty.brw without overflowing 32 bits, and
geometry shaders are going to add more. Add a STATIC_ASSERT so that
we will be alerted when we need to switch to 64 bits.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 4f739646b03f3d6e70461749ca0c0f3cb7390d75 |
|
07-Jul-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: allow 8 user clip planes on CTG+
There's no need to use a clip flag for NEGW on these gens, so
no reason we can't just enable 8 planes.
V2: - Bump (and document!) MAX_VERTS in the clip code.
- Fix clip flag masks in the clip unit state and in the shader
prolog
- Move this to the end of the series for less breakage.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 59f22148b361a5e1c06d9f5b200666afa854473c |
|
02-Aug-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't allocate curbe buffers on Gen6+.
These are only used on Gen4-5. Why waste the 8kB of space?
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9375c16e7247298ecef2ad0187b7782b13aba642 |
|
02-Aug-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initialize the maximum number of GS threads on Haswell.
We'll need proper values for max_gs_threads when we eventually support
geometry shaders. Also, we initialize it for every other platform.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 8c9a54e7bcfc80295ad77097910d35958dfd3644 |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete intel_context entirely.
This makes brw_context inherit directly from gl_context; that was the
only thing left in intel_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::gen and gt fields to brw_context.
Most functions no longer use intel_context, so this patch additionally
removes the local "intel" variables to avoid compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 794de2f3873bcedc78300b3ba69656adc755894c |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::is_<platform> flags to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b15f1fc3c6b3b9dc4422940c412f80e581c9900d |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::perf_debug to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 329779a0b45b63be17627f026533c80b2c8f7991 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::batch to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 5d8186ac1a22afbaa6ed68e0fb67d1f150f798cb |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::hw_ctx to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| eeb75b41f1d7be609861d3e98b64b6fffd13bb4f |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::bufmgr to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| fbdd3891e1d08f388571c20db96516f39fe11898 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::optionCache to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ca437579b3974b91a5298707c459908a628c1098 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_context to functions rather than intel_context.
This makes brw_context available in every function that used
intel_context. This makes it possible to start migrating fields from
intel_context to brw_context.
Surprisingly, this actually removes some code, as functions that use
OUT_BATCH don't need to declare "intel"; they just use "brw."
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 99ebf9d07a23b8c920912dc8289d97e17c753ee2 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move ctx->Const setup from intelInitContext to the new helper.
This also requires moving _mesa_init_point() to after the ctx->Const
initialization.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 963d9f78a4931b7dd73d904b4c1e5f01010cd477 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split code to set ctx->Const values into a helper function.
brwCreateContext() has a lot of random things to do. Factoring out the
part that initializes ctx->Const values and shader compiler options
makes the main function a bit easier to read.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b29381567a83b47ef92e6e4e8e7c402550f467cb |
|
21-May-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split BeginTransformFeedback hook into Gen6 and Gen7+ variants.
Most of the work in BeginTransformFeedback is only necessary on Gen6.
We may as well just skip it on Gen7+.
v2: Add an intel->gen == 6 assert.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e32cd5ffbb7231f8d4bb44189492c89c9a4fbfa9 |
|
16-May-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rely on hardware contexts for query objects on Gen6+.
Hardware contexts greatly simplify the query object code. The pipeline
statistics counters get saved and restored with the context, which means
that we don't need to worry about other workloads polluting them.
This means that we can simply write a single pair of values (one at
BeginQuery and one at EndQuery) rather than a series of pairs. This
also means we don't need to worry about the BO getting full. We also
don't need to delay BO allocation and starting snapshot until the first
draw.
The generation split here is a little off: technically, Ironlake can also
support hardware contexts. However, the kernel currently doesn't, and
even if it were to do so someday, we'd need to wait a while before
bumping the kernel requirement to take advantage of it.
v2: Incorporate Paul's feedback.
- Clarify which functions are Gen4/5-only via assertions and comments.
- Change how driver hook initialization happens.
- Update comments.
- Squash a bug fix from a later commit here where it belongs.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 92d2f5acfadea672417b6785710c9e8b7f605e41 |
|
16-May-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Require hardware contexts (and thus Kernel 3.6) on Gen6+.
Hardware contexts are necessary to reasonably support OpenGL 3.2.
In particular, we currently maintain software counters for transform
feedback buffer offsets and counters, which relies on knowing the number
of primitives generated. Geometry shaders violate that assumption.
At the time of writing, Debian has moved to Kernel 3.8, which means most
people probably have a newer kernel by now. It's also worth noting that
this patch won't land until Mesa 10 which is currently targeted for
September. By that point, even more people will have a newer kernel.
Also, don't bother trying to allocate contexts on pre-Gen6, as it
currently will always fail, and if this changes in the future, we'll
need to reevaluate our hw_ctx/gen checks.
This patch leaves the code for flagging BRW_NEW_CONTEXT on new
batchbuffers if hw_ctx == NULL since that still occurs pre-Gen6.
Also remove the Gen7+ check for kernel 3.3, since it's now redundant.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 72a0b7a43531eb5e5cc4355941957864f86dd719 |
|
18-Apr-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Set the PreferDP4 shader compiler option.
Doing matrix multiplies with DP4s is fewer instructions than MUL/ADD,
especially since we don't support MAD in the vertex shader.
Not observed to improve performance in any fixed function applications,
but is useful for the next patch.
I've left this unset for the fragment shader because the scalar backend
can't use DP4 and does have MAD support.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 77d8fbcfd4b79fa022c021ed52bda157d72e1ca9 |
|
26-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
mesa: add & use a new driver flag for UBO updates instead of _NEW_BUFFER_OBJECT
v2: move the flagging from intel_bufferobj_data to intel_bufferobj_alloc_buffer
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 5e78433eec94fcaa87bdcb2526ec0910a69ed347 |
|
02-May-2013 |
Marek Olšák <maraeo@gmail.com> |
mesa: move max texture image unit constants to gl_program_constants
Const.MaxTextureImageUnits -> Const.FragmentProgram.MaxTextureImageUnits
Const.MaxVertexTextureImageUnits -> Const.VertexProgram.MaxTextureImageUnits
etc.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d0b82b1add5d1d1419d4390a3f7c584b6ee7d92c |
|
07-Mar-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add chipset limits for the Haswell GT3 variant.
NOTE: This is a candidate for stable branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| df410863d7c2377cfbabfef907fc318e10c5486e |
|
19-Apr-2013 |
Eric Anholt <eric@anholt.net> |
intel: Remove the last spans code!
The remaining bits happen to do nothing that
_swrast_span_render_start()/finish() don't do.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 99bd76d834e0c771274f327e1efe9b089ff273d4 |
|
15-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
mesa: convert _NEW_RASTERIZER_DISCARD to a driver flag
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b95cbe5e800e95d888d148e20e6a4e34c8857a9e |
|
15-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
mesa,i965: use NewDriverState to communicate TFB state changes with the driver
_NEW_TRANSFORM_FEEDBACK is not used by core Mesa, so it can be removed.
Instead, an new private flag is added to i965 to serve the same purpose.
If you're new to this:
* When creating a context. you can set private dirty flags
in gl_context::DriverFlags, eg.:
ctx->DriverFlags.NewStateX = BRW_NEW_STATE_X;
* When StateX is changed, core Mesa does:
ctx->NewDriverState |= ctx->DriverFlags.NewStateX;
* When you have to draw, read and clear ctx->NewDriverState.
* Pros: not touching NewState, the driver decides the mapping between
GL states and hw state groups, unlimited number of flags in core Mesa
(still limited number of flags in the driver though)
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f56fb9d24825a94f25ba566f035e9d6062488397 |
|
24-Mar-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: bump MAX_DEPTH_TEXTURE_SAMPLES to 4/8
Bump MAX_DEPTH_TEXTURE_SAMPLES to match what GetInternalformativ is
claiming. Since that limit is what is actually enforced now, this
doesn't actually change anything except the queried value.
There's still no piglits verifying that multisample depth textures work,
but this works in the Unigine demos.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 86b83806007c65baea916a2ccf71ecbcc256ebba |
|
16-Feb-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
mesa: allow internalformat_query with multisample texture targets
Now that we support ARB_texture_multisample, there are multiple targets
accepted for this query, and they may have target-dependent limits, so
pass the target to the driverfunc.
For example, the sampling hardware may not be able to do general
texelFetch() for some format/sample count combination, but the driver
may still be able to implement a reasonable resolve operation, so it can
be supported for renderbuffers.
V2: - Don't break Gallium compile.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2dd22130cd708bad4d6ae4acb706394b1dd6ecd9 |
|
14-Mar-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't print a fatal-looking message if intelCreateContext fails.
With the old context creation mechanism, an application asked the GL to
give it a context. Failing to produce a context was a fatal error.
Now, with GLX_ARB_create_context, the application can request a specific
version. If it's higher than the maximum version we support, context
creation will fail. But this is a normal error that applications
recover from.
In particular, the new glxinfo tries to create OpenGL 4.3, 4.2, 4.1,
4.0, 3.3, and 3.2 contexts before finally succeeding at creating a 3.1
context. This led to it printing the following message 6 times:
"brwCreateContext: failed to init intel context"
There's no need to alarm users (and developers) with such a message.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 14cec07177f438717cc6fb9252525e16d6b3d8dd |
|
22-Feb-2013 |
Eric Anholt <eric@anholt.net> |
i965: Make perf_debug() output to GL_ARB_debug_output in a debug context.
I tried to ensure that performance in the non-debug case doesn't change
(we still just check one condition up front), and I think the impact is
small enough in the debug context case to warrant including all of it.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 032896cbf9daa6937cf6816e54cf4b1414cae901 |
|
05-Dec-2012 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: expose sample positions
Moves the definition of the sample positions out of
gen6_emit_3dstate_multisample, and unpacks them in
gen6_get_sample_position.
V2: Be consistent about `sample position` rather than `location`.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| abb5429537b4e7f42bcdd744ed7aaaf35b719cf4 |
|
30-Nov-2012 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: expose new max sample counts
V2: For now, only expose a depth sample count of 1, since there are
possible unresolved interactions with HiZ.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f29ab4ece5b6a0321f5e4a6fafb7ecacf7214044 |
|
08-Feb-2013 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Set UniformBufferOffsetAlignment to sizeof(vec4)
This matches the behavior of the Windows driver, but a bspec reference
should would be nice.
NOTE: This is a candidate for the 9.0 and 9.1 branches.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9add4e803877f97ad7f6d479d81d537426f09b6f |
|
13-Aug-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add chipset limits for Haswell GT1/GT2.
The maximum number of URB entries come from the 3DSTATE_URB_VS and
3DSTATE_URB_GS state packet documentation; the thread count information
comes from the 3DSTATE_VS and 3DSTATE_PS state packet documentation.
NOTE: This is a candidate for the 9.0 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| be4b1664fbc98b0b1d66bb91850ecada52b36b91 |
|
18-Jan-2013 |
Eric Anholt <eric@anholt.net> |
mesa: Make the drivers call a non-code-generated dispatch table setup.
I want to drive the Save dispatch table setup from this same function.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3c00a52f7e02007f40fa53a06fad517bed0328ff |
|
01-Dec-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Enable GL_ARB_internalformat_query
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a11fe62058ad9d44170be9346111e3f6630a3327 |
|
22-Nov-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Move validation of context version into intelInitContext
Each driver (i830, i915, i965) used independent but similar code to
validate the requested context version. With the rececnt arrival of GLES3,
that logic has needed an update. Rather than apply identical updates to
each drivers validation code, let's just move the validation into the
shared routine intelInitContext.
This refactor required some incidental changes to functions
i830CreateContext and intelInitContext. For each function, this patch:
- Adds context version parameters to the signature.
- Adds a DRI_CTX_ERROR out param to the signature.
- Sets the DRI_CTX_ERROR at each early return.
Tested against gen6 with piglit egl-create-context-verify-gl-flavor.
Verified that this patch does not change the set of exposed EGL context
flavors.
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c0c9c9966f54b2e4a4eb2ffa2abe343c1b82b823 |
|
05-Dec-2012 |
Carl Worth <cworth@cworth.org> |
driconf: Add a new option: disable_glsl_line_continuations
This is to enable a quirk for Savage2 which includes a shader with a stray '\'
at the end of a comment line. Interpreting that backslash as a line
continuation will break the compilation of the shader, so we need a way to
disable this.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 4bea4cb9fd55cdb267003a6e6e16f7e903e00940 |
|
16-Nov-2012 |
Jordan Justen <jordan.l.justen@intel.com> |
drivers: compute version and then initialize exec table
This change forces the context version to be computed before
initilizing the exec dispatch tables.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 71f06344a0d72a6bd27750ceca571fc016b8de85 |
|
27-Nov-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add a debug flag for counting cycles spent in each compiled shader.
This can be used for two purposes: Using hand-coded shaders to determine
per-instruction timings, or figuring out which shader to optimize in a
whole application.
Note that this doesn't cover the instructions that set up the message to
the URB/FB write -- we'd need to convert the MRF usage in these
instructions to GRFs so that our offsets/times don't overwrite our
shader outputs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
v2: Check the timestamp reset flag in the VS, which is apparently
getting set fairly regularly in the range we watch, resulting in
negative numbers getting added to our 32-bit counter, and thus large
values added to our uint64_t.
v3: Rebase on reladdr changes, removing a new safety check that proved
impossible to satisfy. Add a comment to the AOP defs from Ken's
review, and put them in a slightly more sensible spot.
v4: Check timestamp reset in the FS as well.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| dbd6135bc1ba285128ab991c03c4df6fbd6fefe8 |
|
27-Nov-2012 |
Paul Berry <stereotype441@gmail.com> |
mesa: Rename API_OPENGL to API_OPENGL_COMPAT.
This should help avoid confusion now that we're using the gl_api enum
to distinguishing between core and compatibility API's. The
corresponding enum value for core API's is API_OPENGL_CORE.
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 243cf7a924eaef78ce0d5150747fae6c3c4e6974 |
|
09-Nov-2012 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Validate requested GLES context version in brwCreateContext
For GLES1 and GLES2, brwCreateContext neglected to validate the requested
context version received from the DRI layer. If DRI requested an OpenGL
ES2 context with version 3.9, we provided it one.
Before this fix, the switch statement that validated the requested GL
context flavor was an ugly #ifdef copy-paste mess. Instead of reproducing
the copy-past-mess for GLES1 and GLES2, I first refactored it. Now the
switch statement is readable.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| be4c0a243e3314b8d8d24107494e2537a6d198ad |
|
03-Oct-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Statically allocate the reg_sets at context initialization.
Now that we've replaced all the variable settings other than reg_width, it's
easy to hang on to this (the expensive part of setting up the allocator).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7742952f7eaf0af475aeff28a3ec084762d0ed23 |
|
15-Oct-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
mesa: Remove the EmitNVTempInitialization shader compiler option.
Nobody uses it anymore.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 014aaa97d3d7f78629e6e030953be0e9fb7f33dd |
|
21-Sep-2012 |
Eric Anholt <eric@anholt.net> |
i965: Reduce maximum GL_ARB_fragment_program instruction count to 1024.
I don't know of any programs that would need more than this. The larger
programs I've seen have neared 100 instructions. This prevent excessive
runtimes of automatic tests that attempt to test up to the exposed maximums
(like fp-long-alu).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e87c63f2889fcbeb5a8bbd91eda1333d7ed44bf2 |
|
29-Sep-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: brwInitVtbl needs to know the chipset generation
Fixes major regressions since de958de.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 87f26214d6bdeb439b30615ec53c293c5141cf11 |
|
31-Aug-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Don't free the intel_context structure when intelCreateContext fails.
intelDestroyContext will eventually be called, and it will clean things
up. The call to brwInitVtbl is moved earlier so that
intelDestroyContext can call the device-specific destructor. This also
makes the code look more like the i915 code.
NOTE: This is a candidate for the 9.0 branch.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54301
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| fe72a069d1fcce943f315907b4744b63158938b1 |
|
01-Sep-2012 |
Brian Paul <brianp@vmware.com> |
mesa: s/FREE/free/
v2: replace instances in dri/common/ dirs
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0e0d66446194ab0b2d114dc83e76ec9c9b1a01f1 |
|
07-Aug-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Allow creation of OpenGL 3.1 contexts
v2: Fix API_OPENGL_CORE handling when TEXTURE_FLOAT_ENABLED is not
defined. Based on review feedback from Eric Anholt.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| bf8644e64daa4e1d59d1e399355b349406438d7a |
|
17-Aug-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Set context flags
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 67e9ae856355be532455c1cf1211d59b3a4c5992 |
|
27-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Disable the swrast context setup on GL 3.1 core.
I've reviewed the code, and the swrast callsites remaining are all in
drawpixels/copypixels/bitmap/accum, or _swrast_BlitFramebuffer that shouldn't
be hit. A piglit run with the context setup disabled on legacy GL and GLES2
showed regressions only in the copypixels and drawpixels tests.
If the context type is forced, this reduces the shader_runner maximum heap
size for glsl-algebraic-add-add-1.shader_test from 15,137,496b to 4,165,376b.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f0159018d7709b57d9916575512d75cb3f2fb395 |
|
18-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Add support for GL_ARB_timer_query.
Needs updated libdrm.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d60692601388b5448fb0ed4eb894103293b2f074 |
|
07-Aug-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Validate API and version in brwCreateContext
v2: Use base-10 for versions like gl_context::Version. Suggested by Ken.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| fbf86c7f0f1f12e52b927e3870535073879d0a4d |
|
27-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen7: Reduce GT1 WM thread count according to updated BSpec.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
https://bugs.freedesktop.org/show_bug.cgi?id=52382
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 588881430a3d328f2d99fbd5197d85dafc31209b |
|
27-Jul-2012 |
Zou Nan hai <nanhai.zou@intel.com> |
intel: increase wm thread number to 80 on gen6 GT2
It seems reset is not required for setting the max_wm_threads to 80
on gen6 GT2.
Increases performance in the Counter-Strike: Source video stress test
by 7.18% (n=5).
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Matt Turner <mattst88@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 497bf5dd2b36c7d0c8ae23d2bf039c91b97140fc |
|
18-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Switch on 8x MSAA for Gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 4afee38a2f2f9d0aedc02f1d7ba9b780914fce27 |
|
10-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Remove comment about falsely claiming to support MSAA.
Gen6+ hardware now supports MSAA properly.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b2a44cde6468fb6065169194fe3a67b2f4738b71 |
|
19-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen7: Increase the WM threads to hardware limits.
This thread count is only supposed to be enabled when "WIZ Hashing Disable in
GT_MODE register enabled." I've always been confused whether that means the
bit in the register should be 1 or 0. For my IVB GT2's register 0x7008 value
of 0x0, this appears to work fine.
Improves l4d2 performance at 640x480 by 0.88 +/- 0.11% (n=88). Improves
performance with rasterization at 1280x1024 by 1.45% +/- 0.36% (n=6).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 860d5bdf984730f69cd19b4f7145f3c84b57d33d |
|
12-Jun-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add hardware context support.
With fixes and updates from Ben Widawsky and comments from Paul Berry.
v2: Use drm_intel_gem_context_destroy to destroy hardware context;
remove useless initialization of hw_ctx, both suggested by Eric.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 8313f44409ceb733e9f8835926364164237b3111 |
|
21-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Fix centroid interpolation of unlit pixels.
From the Ivy Bridge PRM, Vol 2 Part 1 p280-281 (3DSTATE_WM:
Barycentric Interpolation Mode):
"Errata: When Centroid Barycentric mode is required, HW may
produce incorrect interpolation results when a 2X2 pixels have
unlit pixels."
To work around this problem, after doing centroid interpolation, we
replace the centroid-interpolated values for unlit pixels with
non-centroid-interpolated values (which are interpolated at pixel
centers). This produces correct rendering at the expense of a slight
increase in shader execution time.
I've conditioned the workaround with a runtime flag
(brw->needs_unlit_centroid_workaround) in the hopes that we won't need
it in future chip generations.
Fixes piglit tests "EXT_framebuffer_multisample/interpolation {2,4}
{centroid-deriv,centroid-deriv-disabled}". All MSAA interpolation
tests pass now.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 15ac66e331abdab12e882d80a6b4f647bc905298 |
|
18-Dec-2011 |
Marek Olšák <maraeo@gmail.com> |
mesa: rename MaxTransformFeedbackSeparateAttribs to MaxTransformFeedbackBuffers
This is a cleanup for ARB_transform_feedback3, where
GL_MAX_TRANSFORM_FEEDBACK_BUFFERS is introduced for interleaved attribs and
has the same meaning as GL_MAX_.._SEPARATE_ATTRIBS for separate attribs.
Also, the maximum number of TFB buffers is reduced from 32 to 4, which makes
this patch useful even without the extension.
I don't know of any hardware which can do more than 4.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f9389fbfb204995a650047949c48ab2b2703bfcf |
|
13-May-2012 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: add flag to enable cut_index
When brw->prim_restart.enable_cut_index is set, the cut index
will be enabled when uploading index_buffer commands.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| df7d1323de08274c816a8e5fab7e99b6f00f4fa3 |
|
13-May-2012 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: create code path to handle primitive restart in hardware
For newer hardware we disable the VBO module's software handling
of primitive restart. We now handle primitive restarts in
brw_handle_primitive_restart.
The initial version of brw_handle_primitive_restart simply calls
vbo_sw_primitive_restart, and therefore still uses the VBO
module software primitive restart support.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 29362875f2613ad87abe7725ce3c56c36d16cf9b |
|
25-Apr-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Add support for GL_ARB_blend_func_extended.
v2: Add support for gen6, and don't turn it on if blending is
disabled. (fixes GPU hang), and note it in docs/GL3.txt
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7b36c68ba6899c7f30fd56b7ef07a78b027771ac |
|
26-Jan-2012 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Rewrite the HiZ op
The HiZ op was implemented as a meta-op. This patch reimplements it by
emitting a special HiZ batch. This fixes several known bugs, and likely
a lot of undiscovered ones too.
==== Why the HiZ meta-op needed to die ====
The HiZ op was implemented as a meta-op, which caused lots of trouble. All
other meta-ops occur as a result of some GL call (for example, glClear and
glGenerateMipmap), but the HiZ meta-op was special. It was called in
places that Mesa (in particular, the vbo and swrast modules) did not
expect---and were not prepared for---state changes to occur (for example:
glDraw; glCallList; within glBegin/End blocks; and within
swrast_prepare_render as a result of intel_miptree_map).
In an attempt to work around these unexpected state changes, I added two
hooks in i965:
- A hook for glDraw, located in brw_predraw_resolve_buffers (which is
called in the glDraw path). This hook detected if a predraw resolve
meta-op had occurred, and would hackishly repropagate some GL state
if necessary. This ensured that the meta-op state changes would not
intefere with the vbo module's subsequent execution of glDraw.
- A hook for glBegin, implemented by brwPrepareExecBegin. This hook
resolved all buffers before entering
a glBegin/End block, thus preventing an infinitely recurring call to
vbo_exec_FlushVertices. The vbo module calls vbo_exec_FlushVertices to
flush its vertex queue in response to GL state changes.
Unfortunately, these hooks were not sufficient. The meta-op state changes
still interacted badly with glPopAttrib (as discovered in bug 44927) and
with swrast rendering (as discovered by debugging gen6's swrast fallback
for glBitmap). I expect there are more undiscovered bugs. Rather than play
whack-a-mole in a minefield, the sane approach is to replace the HiZ
meta-op with something safer.
==== How it was killed ====
This patch consists of several logical components:
1. Rewrite the HiZ op by replacing function gen6_resolve_slice with
gen6_hiz_exec and gen7_hiz_exec. The new functions do not call
a meta-op, but instead manually construct and emit a batch to "draw"
the HiZ op's rectangle primitive. The new functions alter no GL
state.
2. Add fields to brw_context::hiz for the new HiZ op.
3. Emit a workaround flush when toggling 3DSTATE_VS.VsFunctionEnable.
4. Kill all dead HiZ code:
- the function gen6_resolve_slice
- the dirty flag BRW_NEW_HIZ
- the dead fields in brw_context::hiz
- the state packet manipulation triggered by the now removed
brw_context::hiz::op
- the meta-op workaround in brw_predraw_resolve_buffers (discussed
above)
- the meta-op workaround brwPrepareExecBegin (discussed above)
Note: This is a candidate for the 8.0 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43327
Reported-by: xunx.fang@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44927
Reported-by: chao.a.chen@intel.com
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 642247883fb9e6dce9bad724f7f6503321e0ef6f |
|
25-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add a driconf option to force GLSL extension behavior to "warn".
This can be used to work around broken application behavior, like in
Unigine where it attempts to use texture arrays without declaring
either "#extension GL_EXT_texture_array : enable" or "#version 130".
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| dc435ae774b1deed3d00b7c7d33133c08b626737 |
|
24-Jan-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6/GT1: Increase max_vs_entries to 256.
Previously, max_vs_entries was set to 128 for GT1, and 256 for GT2,
based on the PRM (see Vol2, part1, p28). However, Bspec section 1.6.5
indicates that the maximum number of VS entries is 256 for GT1.
No piglit regressions on GT1.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| bdedd03b701781c8b71e162f7eb834e6a11105de |
|
17-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove the INTEL_OLD_VS option.
Now that we no longer generate Mesa IR from GLSL IR, it's impossible to
use the old vertex shader backend for GLSL programs. There's simply no
Mesa IR to codegen from.
Any attempt to do so would result in immediate GPU hangs, presumably due
to the driver uploading an empty program with no EOT message.
NOTE: This is a candidate for the 8.0 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| be4e46b21a60cfdc826bf89d1078df54966115b1 |
|
10-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965: Claim to support 4 multisamples on gen6+.
We're not quite ready to actually support it in the implementation,
but at least this allows GL 3.0 API-reliant applications to hopefully
run successfully, though they won't get multisampling.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3d4efc583ce46e6f0a13302679fe1349d521a4a3 |
|
09-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965: Increase the number of array texture levels to the hardware limit.
The EXT_texture_array required only 64, but GL 3.0 required 256.
Since we're already exposing values that can get us way beyond our
ability to map the single object directly, go ahead and expose all the
way to hardware limits.
Tested with new piglit EXT_texture_array/maxlayers on gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7f91c8bf2bf08afd297314c02a8869d8919f5f0e |
|
30-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen7: Flush the batch between transform feedbacks.
We need the kernel to reset our pointers to 0 in between. Note that
the initialization of function pointer had to move to after
InitContext since we didn't have intel->gen set up yet.
Fixes piglit EXT_transform_feedback/immediate-reuse
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 21504b462acda4977c5fdfffc192e73273b8fb26 |
|
14-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Implement bounds checking for transform feedback output.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 63cf7fad13fc9cfdd2ae7b031426f79107000300 |
|
10-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Flush pipeline on EndTransformFeedback.
A common use case for transform feedback is to perform one draw
operation that writes transform feedback output to a buffer, followed
by a second draw operation that consumes that buffer as vertex input.
Since vertex input is consumed at an earlier pipeline stage than
writing transform feedback output, we need to flush the pipeline to
ensure that the transform feedback output is completely written before
the data is consumed.
In an ideal world, we would do some dependency tracking, so that we
would only flush the pipeline if the next draw call was about to
consume data generated by a previous draw call in the same batch.
However, since we don't have that sort of dependency tracking
infrastructure right now, we just unconditionally flush the buffer
every time glEndTransformFeedback() is called. This will cause a
performance hit compared to the ideal case (since we will sometimes
flush the pipeline unnecessarily), but fortunately the performance hit
will be confined to circumstances where transform feedback is in use.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9308f298300beaa757194a0db8ed50924754c011 |
|
28-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Initial implementation of transform feedback.
This patch adds basic transform feedback capability for Gen6 hardware.
This consists of several related pieces of functionality:
(1) In gen6_sol.c, we set up binding table entries for use by
transform feedback. We use one binding table entry per transform
feedback varying (this allows us to avoid doing pointer arithmetic in
the shader, since we can set up the binding table entries with the
appropriate offsets and surface pitches to place each varying at the
correct address).
(2) In brw_context.c, we advertise the hardware capabilities, which
are as follows:
MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64
MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4
MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16
OpenGL 3.0 requires these values to be at least 64, 4, and 4,
respectively. The reason we advertise a larger value than required
for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already
set aside 64 binding table entries, so we might as well make them all
available in both separate attribs and interleaved modes.
(3) We set aside a single SVBI ("streamed vertex buffer index") for
use by transform feedback. The hardware supports four independent
SVBI's, but we only need one, since vertices are added to all
transform feedback buffers at the same rate. Note: at the moment this
index is reset to 0 only when the driver is initialized. It needs to
be reset to 0 whenever BeginTransformFeedback() is called, and
otherwise preserved.
(4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader
program to output transform feedback data as a side effect.
(5) In gen6_gs_state.c, we configure the geometry shader stage to
handle the SVBI pointer correctly.
Note: ordering of vertices is not yet correct for triangle strips
(alternate triangles are improperly oriented). This will be addressed
in a future patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 37d24a70daa41bbad9c7a85dd432f561a172e858 |
|
28-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Advertise our vertex shader texture units.
Previously, we advertised 0 VS texture units. Now that we have proper
support for using the sampling engine in the VS, we can advertise 16,
which is conveniently the number required for OpenGL 3.0.
v2: Enable on Gen4. I hacked up my tests to not use flat ivec varyings
and they pass.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 43e39b58c705714c01919e5b4b5566e82e803d58 |
|
07-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Allocate URB space for GS
When the GS is not in use, the entire URB space is available for the
VS. When the GS is in use, we split the URB space 50/50.
The 50/50 split is probably not optimal--we'll probably want tune this
for performance in a future patch. For example, in most situations,
it's probably worth allocating more than 50% of the space to the VS,
since VS space is used for vertex caching. But for now this is good
enough.
Based on previous work by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7a63a311e56fd492823b4b44e526df5a8dc0a021 |
|
15-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set the maximum number of GS URB entries on Sandybridge.
We never filled this in before because we didn't care.
I'm skeptical these are correct; my sources indicate that both the VS
and GS # of entries are 256 on both GT1 and GT2.
I'm also loathe to change it and break stuff.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c6abde211fa875f90e59e3709720cfe394669069 |
|
23-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't perform the precompile on fragment shaders by default.
It is useful to have this option for shader-db, and it was also good
at the time where we were rejecting shaders due to various internal
limits we hadn't supported yet. However, at this point the precompile
step takes extra time (since not all NOS is known at link time) and
spews misleading debug in the common case of debugging a real app.
This is left in place for VS, where we still have a couple of codegen
failure paths that result in link failure through precompile. Those
need to be fixed.
shader-db can still get at the debug info it wants using
"shader_precompile=true" driconf option. Long term, we can probably
build a good-enough app for shader-db to trigger real codegen.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ca10b2d4494798405a5fd654201291944645af5d |
|
15-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use the surface format table to determine render target supportedness.
This moves any chipset-dependent logic we want for render target
format choices to init time as well. There is still logic left at
state update for SRGB handling, where format choices change based on
GL state.
The brw_render_target_supported() function should now return correct
results, instead of relying on the limited results from
intel_span_supports_format() to avoid lying about FBO completeness.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b95986729ef3522a65b7357aea99c6358f9d53c8 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Prevent recursive calls to FLUSH_VERTICES [v2]
To do so, we must resolve all buffers on entering a glBegin/glEnd block.
For the detailed explanation, see the Doxygen comments in this patch.
v2:
- Fix typo: s/enusure/ensure/.
- In brwPrepareExecBegin(), do the same resolves as done by
brw_predraw_resolve_buffers().
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ba3b9fad60d156a4e3e6311b92c652b36d8969d2 |
|
11-Nov-2011 |
Brian Paul <brianp@vmware.com> |
i965: remove #include of api_noop.h
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f1694eabdd860c3026dc691474caee83fce7bb52 |
|
24-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add new brw_context::max_gs_threads constant.
These are correct to the best of my knowledge, gleaned from a variety of
internal sources. Sadly, the Sandybridge PRM has incorrect limits.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| db6dd6d88fdc4361193dd063e4f150f01a104faa |
|
24-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename (vs|wm)_max_threads to max_(vs|wm)_threads for consistency.
The inconsistency between vs_max_threads and max_vs_entries was rather
annoying. I could never seem to remember which one was reversed, which
made it harder to find quickly. "Max __ Threads" seems more natural.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 47f1d9deffee8aeb2d73d8e06f829d32125f944c |
|
24-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove "single threaded" INTEL_DEBUG mode.
According to the docs for 3DSTATE_PS (Gen7+) and 3DSTATE_WM (Gen6),
there is a platform dependent value for the minimum number of pixel
shader threads. It may also vary based on whether WIZ Hashing is on.
For example, Ivybridge requires at least 4 threads if WIZ hashing is
disabled, and 8 if it's enabled. Programming it to use less threads is
illegal. Sandybridge appears to have similar restrictions.
So on newer platforms, INTEL_DEBUG=sing will probably just hang the GPU.
Rather than try to patch it up for newer platforms and extend it to
support geometry shaders, just remove it as it isn't that useful anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 01f9fdc4acd28cc4630a3c71f2d007373f4d979c |
|
20-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set MaxIfDepth to UINT_MAX on Gen6+ and 16 on prior generations.
Commit 488fe51cf823ccd137c667f1e92dd86f8323b723 converted the EmitNoIfs
flag to MaxIfDepth, an unsigned integer saying "flatten if-statements
nested beyond this depth."
Unfortunately, i965 left this initialized to 0, which made ir_to_mesa
attempt to flatten all if-statements. We didn't notice right away
because we usually throw away ir_to_mesa's code in favor of the native
VS and FS backends...but this still creates a lot of unnecessary work.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b393fa91676aba0883d8f5260bd2910777aceb11 |
|
31-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Initialize intel_context::vtbl after calling intelInitContext()
intel_context::gen field is set by intelInitContext(). So, by calling
intelInitContext() before initializing the vtable, we can can construct
different vtables for different gens.
Specifically, this allows us to set the HiZ operations to be no-ops for
contexts for which HiZ is not enabled.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 669f1822d2a60865514faf37f9fde21e4567b3d2 |
|
06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_EXT_texture_array and GL_MESA_texture_array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 490e6470a09c3a6049e5e859d72b0b679ef5d070 |
|
24-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Introduce a new intel_context::gt field to go along with gen.
It seems that GT1/GT2 sorts of variations are here to stay, and more
special cases will likely be required in the future. Checking by PCI ID
via the IS_xxx_GTx macros is cumbersome; introducing a new 'gt' field
analogous to intel->gen will make this easier.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b9ef2b85b41272da9ed95071307310f9749cbf2b |
|
16-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Enable lower_clip_distance.
i965 requires gl_ClipDistance to be formatted as an array of 2 vec4's
(as opposed to an array of 8 floats), so enable the lowering pass that
performs this conversion.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d7c6c8428c9908047c88f2672cd1edf6ba60f785 |
|
07-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Switch to the new VS backend by default.
Now instead of env INTEL_NEW_VS=1 to get it, you need INTEL_OLD_VS=1
to not get it. While it's not quite to the same codegen efficiency as
the old backend, it is not regressing piglit on G965 and G45, and
actually fixing bugs on gen6, and the remaining codegen quality
regressions all appear tractable.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 4e64cfbb4ec92877803e70257af8b97c484c00c0 |
|
05-Sep-2011 |
Bryan Cain <bryancain3@gmail.com> |
mesa: add a UniformBooleanTrue option
Drivers supporting native integers set UniformBooleanTrue to the integer value
that should be used for true when uploading uniform booleans. This is ~0 for
Gallium and 1 for i965.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 55b7fbb70ffc1f4def5c3ded63c3ef569e693731 |
|
19-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use native integer uniforms when the new VS backend is in use.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2f82c33deefba61b3e72edb4375850c0629af224 |
|
19-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Move the flag for whether to use the new backend to the context.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
|
26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 348bdaa529c3eb60fcf03ed4531193bbf2e12491 |
|
13-Jul-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename CMD_VF_STATISTICS_(965|GM45) to include "3DSTATE".
Including the full "3DSTATE_VF_STATISTICS" should make it easier to
cross-reference the code and documentation.
Also, move the 965/GM45 suffix to the beginning for consistency with
newer #defines.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 35d5d5df72a2747262e00e521e650c8974d6c64d |
|
06-May-2011 |
Eric Anholt <eric@anholt.net> |
intel: Make our context structure be a ralloc context.
This will let me hang cached compiler structs off of the context
without having to worry about cleaning them up at destroy time.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0ab7d6f437f2f7a1b2d84f30497f3c2013b52791 |
|
18-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Limit the workaround flush to once per primitive.
We're about to call this function in a bunch of state emits, so let's
not spam the hardware with flushes too hard.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ef59049c5242a1be7fa59a182d342191185dd62b |
|
06-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix flipped GT1 vs GT2 URB VS entry count limits.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f61d1deac7d19dcec38b7852a635d92680624a32 |
|
02-Jun-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Raise const.MaxTextureLevels to 14 (8192)
Mesa now limits, by default, the max number of texture levels to 15 so we
can now support the architectural maximum for gen4-6 of 14.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3e0bb02358d627e784a2b7041d6e2e23e3dfd2c5 |
|
18-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename IS_GT1 and IS_GT2 to IS_SNB_GT1 and IS_SNB_GT2.
This should help distinguish Sandybridge GT1/GT2 from Ivybridge GT1/GT2.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| fa4b23581b4ee8a07400364dccbd61b749c2d1d1 |
|
14-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't use the GS for breaking down quads on Ivybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 8832920c298f4e13ffd5e53feeba509be69edb16 |
|
27-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge URB space partitioning, including push constants.
Currently this always reserves 16kB for push constants, regardless of
how much space is needed, and partitions it evenly betwen the VS and FS.
This is probably not ideal, but is straightforward.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 477e2fe0318c79978dedd51a5a6039cf05fc59fb |
|
09-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set maximum number of threads for Ivybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d55471768e308853432de7d18f663034ddbc8599 |
|
15-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename max_vs_handles to max_vs_entries for consistency.
The documentation uses the term "vertex URB entries", the code talks
about "entry size", and so on. Also, handles are just "pointers" to
entries (actually small integers).
Also rename max_gs_handles to max_gs_entries.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d67c08319fda7d0f2df98d60b64c8cc2f3e06c44 |
|
22-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move the CC VP to state streaming.
This is in a way a revert of f5bb775fd1f333d8e579d07a5cac1ded2bd54a2f.
The tiny win that had will be overwhelmed by the win of using the gen6
dynamic state base address.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 42a805700039e81a9245f46f153e2cd9705cd0d7 |
|
13-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Allocate the whole URB to the VS and fix calculations for Gen6.
Since we never enable the GS on Sandybridge, there's no need to allocate
it any URB space.
Furthermore, the previous calculation was incorrect: it neglected to
multiply by nr_vs_entries, instead comparing whether twice the size of
a single VS URB entry was bigger than the entire URB space. It also
neglected to take into account that vs_size is in units of 128 byte
blocks, while urb_size is in bytes.
Despite the above problems, the calculations resulted in an acceptable
programming of the URB in most cases, at least on GT2.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 904b8ba1bb604b2eaaa22f7f074d236011fe213f |
|
29-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix the VS thread limits for GT1, and clarify the WM limits on both.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2fb0aebd4a248d2a0725099cd5646253c30c1dc3 |
|
20-Jan-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Fix typeos from 3d028024 and 790ff232
...and remove egg from face.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3d028024e581b05f71f0be915657c2c105885de6 |
|
20-Jan-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Set correct values for range/precision of fragment shader types
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| bea6539abff17f39c822ac9c1c94f8249c396b18 |
|
04-Jan-2011 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Use last vertex convention for quad provoking vertex on sandybridge
Until we know how hw converts quads to polygon in beginning of
3D pipeline, for now unconditionally use last vertex convention.
Fix glean/clipFlat case.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 251d15d888dfaea045447f9e56ea094cb726830b |
|
02-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Enable IF statements in the VS.
While the actual IF instructions were fixed by Zhenyu, we were still
flattening them to conditional moves.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9effc1adf1e7ba57fb3b10909762b76c1ae12f61 |
|
12-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: re-enable gen6 IF statements in the fragment shader.
IF statements were getting flattened while they were broken. With
Zhenyu's last fix for ENDIF's type, everything appears to have lined
up to actually work.
This regresses two tests:
glsl1-! (not) operator (1, fail)
glsl1-! (not) operator (1, pass)
but fixes tests that couldn't work before because the IFs couldn't be
flattened:
glsl-fs-discard-01
occlusion-query-discard
(and, naturally, this should be a performance improvement for apps
that actually use IF statements to avoid executing a bunch of code).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d3491e775fb07f891463b2185d74bbad62f3ed24 |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Rename GLvisual and __GLcontextModes to struct gl_config
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 4d202da7a4951eb534f77014238e7cdca9f781e9 |
|
07-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Disable emitting if () statements on gen6 until we really fix them.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b91dba49e0b08b18dbd6c477facdcc7b5472c8c7 |
|
22-Sep-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Fix GL_ARB_shading_language_120 commit
Fix commit e7087175f8a04f777403366fb34b58edd00f4d60. Move the reference to
GL_VERSION_2_1_functions to intel_extensions.c where it's available,
don't try to enable a non-existing extension and advertise 1.20 for all
intel chipsets, not just GEN4 and up.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| e7087175f8a04f777403366fb34b58edd00f4d60 |
|
22-Sep-2010 |
Brian Paul <brianp@vmware.com> |
mesa: don't advertise bogus GL_ARB_shading_language_120 extension
Instead of using the invalid GL_ARB_shading_language_120 extension to
determine the GLSL version, use a new ctx->Const.GLSLVersion field.
Updated the intel and r600 drivers, but untested.
See fd.o bug 29910
NOTE: This is a candidate for the 7.9 branch (but let's wait and see if
there's any regressions).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a6ecd1c3724a78b76ab9e81ea39632f1279021f8 |
|
16-Sep-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
glsl2: Add flags to enable variable index lowering
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 4de7a3b76add1940f7316253a619c3728025d9db |
|
13-Sep-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Request that returns be lowered in shader main
Fixes piglit tests glsl-vs-main-return and glsl-fs-main-return.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2b70dbfe091af5ae7c788e16275e1af2cb1c284c |
|
10-Sep-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
glsl2: Add EmitNoNoise flag, use it to remove noise opcodes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 6d3a2c97f4a78e85545286e0e126cd3a27bd1cbd |
|
05-Sep-2010 |
Luca Barbieri <luca@luca-barbieri.com> |
glsl: make compiler options per-target
This allows us to specify different options, especially useful for chips
without unified shaders.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 35c127362f7b0c186923934f34148de319093cbf |
|
20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Set the maximum number of threads on Sandybridge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| da1502494b63fcd65bc60f50e59241164481f8b3 |
|
20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Sandybridge doesn't have Compr4 mode, since it's not needed any more.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ca12aefdacd22fb42e3f1d3852db4c12de886554 |
|
24-Jun-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'shader-file-reorg'
1. Move all GL entrypoint functions and files into src/mesa/main/
This includes the ARB vp/vp, NV vp/fp, ATI fragshader and GLSL bits
that were in src/mesa/shader/
2. Move src/mesa/shader/slang/ to src/mesa/slang/ to reduce the tree depth
3. Rename src/mesa/shader/ to src/mesa/program/ since all the
remaining files are concerned with GPU programs.
4. Misc code refactoring. In particular, I got rid of most of the
GLSL-related ctx->Driver hook functions. None of the drivers used
them.
Conflicts:
src/mesa/drivers/dri/i965/brw_context.c
|
| b6cfca42e39d7413af22c26251cca513a0df2028 |
|
12-Jun-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary header.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f5bb775fd1f333d8e579d07a5cac1ded2bd54a2f |
|
10-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set the CC VP state immediately on state change.
The cache lookup of these two little floats was .12% of total CPU time
on firefox-talos-gfx because we did it any time commonly-changed state
changed. On the other hand, updating the CC VP bo immediately whenver
CC VP state changes is a .07% overhead due to putting a driver hoook
in glEnable().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0a48949a11006f9c3b2ee0c93a796a03413345fa |
|
05-Jun-2010 |
Brian Paul <brianp@vmware.com> |
i965: remove UseProgram driver callback
It just duplicated the default/core Mesa behaviour.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ec2b92f98c2e7f161521b447cc1d9a36bce3707c |
|
11-Jun-2010 |
Brian Paul <brianp@vmware.com> |
mesa: rename src/mesa/shader/ to src/mesa/program/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 050eed095a3f7eaeada1e292f92f2b549d74963f |
|
05-Jun-2010 |
Brian Paul <brianp@vmware.com> |
i965: remove UseProgram driver callback
It just duplicated the default/core Mesa behaviour.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 503eb57a003f51c25687e9cf0ad6f7939a757f1b |
|
08-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Avoid calloc/free in the CURBE upload process.
In exchange we end up with an extra memcpy, but that seems better than
calloc/free. Each buffer is 4k maximum, and on the i965-streaming
branch this allocation was showing up as the top entry in
brw_validate_state profiling for cairo-gl.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| df3590f570cb88eb9695b443208d7576b5867fd1 |
|
17-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove the half-baked code for multiple OQs at the same time.
GL doesn't actually let you begin an OQ while one is active, so the
extra work was pointless.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| db2993faa0211b60efd46016de5d07110cb9777a |
|
11-May-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop viewport hack when we can
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 4b69100bdcf26dbb5be4d600b7ca5f5cdf6e8f20 |
|
27-Apr-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
dri: Add DRI entrypoints to create a context for a given API
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 56ff30a9f97a1a7094432333906544d6138d6bf2 |
|
10-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the PLN instruction when possible in interpolation.
Saves an instruction in PINTERP, LINTERP, and PIXEL_W from
brw_wm_glsl.c For non-GLSL it isn't used yet because the deltas have
to be laid out differently.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 89cce536cbc55460bc534acc06ea9f4d9ae71016 |
|
25-Feb-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't include SNB in has_negative_rhw_bug.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 93fcfc8369cc3fa42f6ba577c26474464f21e6ad |
|
14-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix up the VF stats packet header.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 298be2b028263b2c343a707662c6fbfa18293cb2 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace the _mesa_*printf() wrappers with the plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a098fd71d7b7347bb8f1841bad0e7ce24e0e6de9 |
|
26-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix build after merge of mesa stable branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
|
| 634ec5c2abf05a9a8c27d9199ded5d1ad91e538a |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d61f07318c8678901b948fdaa8ccdf37aa3203e9 |
|
01-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Remove leftover __DRI{screen,drawable,context}Private references
As part of the DRI driver interface rewrite I merged __DRIscreenPrivate
and __DRIscreen, and likewise for __DRIdrawablePrivate and
__DRIcontextPrivate. I left typedefs in place though, to avoid renaming
all the *Private use internal to the driver. That was probably a
mistake, and it turns out a one-line find+sed combo can do the mass
rename. Better late than never.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| cb3810dd19760797e699c47929f655b829c4d339 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_965 checks with context structure usage.
Saves another 600 bytes or so of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 0b87f143c466f7e5bd730895ee29f1cd20a68f9b |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_G4X() across the driver with context structure usage.
Saves ~2KB of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 51e945ec9c0b803f5e998f87449fb02a7c39ae65 |
|
10-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Attempt to fix up after "Update vertex texture code."
The MaxCombinedTextureImageUnits is the total number of samplers that can
be bound between vertex, geometry, and fragment, not 0. This should report
the correct value on 965 now. Other DRI drivers may also need updating if
their MaxVertexTextureImageUnits != 0 (for example, if using the sw vertex
pipeline).
It's not clear to me if there's going to be a valid value for this
limit other than MaxTextureImageUnits + MaxVertexTextureImageUnits (+
MaxGeometryTextureImageUnits eventually). If not, then we should probably
just move this into the core at Get time.
Bug #25518 (wine regression). Fixes piglit vp-combined-image-units.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 853d4807fe220b17cf5af5a76b24f2466238013b |
|
01-Dec-2009 |
Michal Krol <michal@vmware.com> |
mesa: Update vertex texture code after gallium changes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 198ec96d364dabd82952a451eeda7937db383f0d |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: define, use BRW_MAX_DRAW_BUFFERS
i965 might support more than 4 color draw buffers. But if not, this protects
from breakage if the Mesa limit is raised.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 726a04a2cd1bf159a6c40584b4b2b9bc5948a82e |
|
24-Sep-2009 |
Eric Anholt <eric@anholt.net> |
i965: Emit zero initialization for NV VP temporaries as required.
This is similar to what r300 does inside the driver, but I've added it as
a generic option since it seems most hardware will want it.
Fixes piglit nv-init-zero-reg.vpfp and nv-init-zero-addr.vpfp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| cbde2765804a4fc62bcf092230a01376aedbf2cd |
|
02-Sep-2009 |
Eric Anholt <eric@anholt.net> |
Revert "i965: Use VBOs in the VBO module on 965, now that we have ARB_map_buffer_range."
This reverts commit 00413d87426f14df47d90ba3c995e1889e9f88ca. Even with
fixes, using ARB_map_buffer_range in the VBO module isn't showing up as a
significant win, and some cases apparently regressed.
Bug #23624.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 00413d87426f14df47d90ba3c995e1889e9f88ca |
|
29-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use VBOs in the VBO module on 965, now that we have ARB_map_buffer_range.
This looks like it's a small win on blender.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 09c73c74376ed6b12e343c89b4eac94285439860 |
|
27-Aug-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Increase assmebly shader program parameter limits
Increase the number of native program parameters to the same values
exposed by GLSL.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| eabe12df44a41e97fb5736959e8864ddbd01be14 |
|
24-Aug-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
ARB prog: Change handling of program parameter limits
Several changes are made to program parameter limits. Several of the
non-NATIVE limits are set higher. All of the NATIVE limits are set to
zero in the core Mesa code. Each driver must set the actual value in
its context creation routine. If the NATIVE value remains zero, this
indicates that hardware shaders may not be supported.
Each of the preceeding changes matches the bahavior of Apple's shader
assembler, so it seems safe.
Finally, we limit the value of MaxEnvParams to be no greater than
MaxNativeAttribs. At least one case has been found where an
application does the wrong thing if MaxNativeAttribs < MaxEnvParams.
See also bugzilla #23490.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 50853be894aa3edd1e9271f7d625f319209e340f |
|
22-Apr-2009 |
Roland Scheidegger <sroland@vmware.com> |
intel: fix max anisotropy supported
i915 actually supports up to 4 (according to header file - not tested),
i965 up to 16 (code already handled this but slightly broken), so don't use 2
for all chips, even though angular dependency is very high.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| a9e753c84cc5acc2a89686a5e4109f3b056d4fb4 |
|
16-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: tell GLSL compiler to emit code using condition codes
The default for EmitCondCodes got flipped when gallium-0.2 was merged.
This fixes GLSL if/else/endif regressions.
Drivers that use GLSL should always explicitly set the flag to be safe.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 052c1d66a1ab1f2665870dc77dab28d20416cdf1 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw->attribs now that we can just always look in the GLcontext.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 14321fcfde9e30d0b9f15aab3c9a057271ae6295 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Delete old metaops code now that there are no remaining consumers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 954dfba12986f578f2d8461818f9e9ac1f8f2b41 |
|
31-Jan-2009 |
Keith Packard <keithp@keithp.com> |
i965: bump texture limit to 4kx4k
Rendering and textures are limited to 8kx8k, but mesa limits things to
4kx4k, and magic guard band stuff may break on 8kx8k drawing. This is safe
though, and makes compiz work on bigger screens.
Signed-off-by: Keith Packard <keithp@keithp.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 49b53407c7c4f08b5e13591fd04080ca602fba40 |
|
13-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: allow larger AA points on fallback path
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 4a6ad999ea312f0af85de621c8b6a15a3d3b7ffd |
|
01-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: increase number of texture samplers to 16
This lets GLSL shaders use up to 16 samplers.
Fixed function is still limited to 8 textures.
Tested with progs/glsl/samplers.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2adef553f2549e30b4a1894e7f9077ac339ea61c |
|
14-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i915: Don't overwrite i915's Viewport function from generic code.
Instead, have i965 and i915 both call the generic function from their Viewport.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 |
|
24-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix check_aperture calls to cover everything needed for the prim at once.
Previously, since my check_aperture API change, we would check each piece of
state against the batchbuffer individually, but not all the state against the
batchbuffer at once. In addition to not being terribly useful in assuring
success, it probably also increased CPU load by calling check_aperture many
times per primitive.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| c157cfc6376f7469ab272b18868183e5ff9ac754 |
|
07-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Add ARB_occlusion_query support.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| b5d59222ccbec9db23b6847737765a4dc0d8c47b |
|
26-Sep-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
Remove TNL-to-VP tracking from i965
The i965 driver previously had it's own set of code to convert
fixed-function TNL state to a vertex program. Core Mesa has code to
do this, so there is no reason to duplicate that effort in the driver.
In fact, this duplication leads to bugs when other aspects of the Mesa
infrastructure change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 2511d57fa487e4b46a4919913103c2491da7a856 |
|
23-Sep-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Adapt to new TNL program tracking semantics
This fixes bugzilla #17718.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 1e645b365900cf1c71ca5594bd6b549a1f203040 |
|
26-Jul-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
Merge branch 'master' into drm-gem
Conflicts:
src/mesa/drivers/dri/common/dri_bufmgr.c
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 442c195c4afce2509130a718c44a69a5b009979e |
|
09-Jul-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
Remove redundant initalization of MaxTextureUnits
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 43346fb1fb43f91cb3e90d84b442dc08d6c9550d |
|
02-Jul-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
set ctx->Const.MaxVertexTextureImageUnits = 0
This disallows vertex shader texture sampling. See bugs 16157, 13838.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 744357e29c6a51b9e1770e0340eee5105f6b5585 |
|
24-Jun-2008 |
Eric Anholt <eric@anholt.net> |
intel: Same pixel function init for everyone now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| de1e9880f8b239768293f7f434a9117dfab20162 |
|
29-Feb-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: use _Current pointer instead of Current pointer.
fix double free issue(bug#14710). It also corrects glsl/bitmap demo behavior.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 60c0f09abb9421de359cd92e094a943d650fc7fa |
|
27-Feb-2008 |
Kristian Høgsberg <krh@redhat.com> |
intel: Always use intelInitExtensions() for initializing extensions.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 20b8bff49cba3e8246e29004c5ff38f231d589ff |
|
26-Feb-2008 |
Kristian Høgsberg <krh@redhat.com> |
i965: Setup framebuffer texture in meta_draw_region.
With DRI2 we there is no screen region until a drawable is bound to
the context. Set up the framebuffer texture in meta_draw_region instead
which should also handle the case where the draw region changes as a
result of resizing a redirected window or resizing the screen.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 7381ccab449c65d843580f76426f87ab6b1649ce |
|
25-Feb-2008 |
Kristian Høgsberg <krh@redhat.com> |
intel: Add missing include file to silence last couple of warnings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 5b6ca237ee63fb85cff3bb942f5136f96f2c81ec |
|
25-Feb-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: fix assertion failure caused by commit dd1d66fc4ab5d7064113a2017a431c3461598b91.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| dd1d66fc4ab5d7064113a2017a431c3461598b91 |
|
23-Feb-2008 |
Kristian Høgsberg <krh@redhat.com> |
intel: Merge intel_context.c from i915 and i965.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
|
14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| d8fcb504a4d88dc1c4d63fb572fdb7393b8a33aa |
|
28-Nov-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: update RefCount when using Vertex/Fragment program.
It makes quake4-demo works well on 965.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 93c98a466947570e0589b662df49095b2f4bc43c |
|
05-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace 965 texture format code with common code.
The only functional difference should be that 965 now gets the optimization
where textures default to 16bpp when the screen is 16bpp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 6ef27b88e6f767cd476676b33cb7c4ea6922234e |
|
26-Oct-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Merge branch '965-glsl'
Conflicts:
src/mesa/drivers/dri/i965/brw_sf.h
src/mesa/drivers/dri/i965/intel_context.c
|
| ac985708f4820173bdc4509d032bdabeb93a0590 |
|
08-Oct-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Only vertex program fix, bypass tnl vertex program
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 38c30a81844214b030c9c637f9cf97bd2bf19cde |
|
26-Sep-2007 |
Eric Anholt <eric@anholt.net> |
[965] Remove AUB file support.
This code existed to dump logs of hardware access to be replayed in simulation.
Since we have real hardware now, it's not really needed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 35a0634e358baac832d6e5a76630fcae57a948a7 |
|
27-Sep-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
fix issue when only fragment shader or vertex shader is used
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 719cf0b7958d0dedf8727c97eaddb6a1f31977e1 |
|
17-Jul-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Use ProgramStringNotify
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 35707dbe57873adb5a8088cd47c13bd216e143e4 |
|
12-Apr-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Initial 965 GLSL support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 064ae479a770bf434958d673baf6f7530f642697 |
|
23-Feb-2007 |
Brian <brian@yutani.localnet.net> |
Update DRI drivers for new glsl compiler.
Mostly:
- update #includes
- update STATE_* token code
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 6a3fdc3a1ea6c306d9543791bf172dd1052d7382 |
|
16-Jan-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Merge branch 'master' of git+ssh://keithw@git.freedesktop.org/git/mesa/mesa into vbo-0.2
Conflicts:
src/mesa/array_cache/sources
src/mesa/drivers/dri/i965/brw_context.c
src/mesa/drivers/dri/i965/brw_draw.c
src/mesa/drivers/dri/i965/brw_fallback.c
src/mesa/drivers/dri/i965/brw_vs_emit.c
src/mesa/drivers/dri/i965/brw_vs_tnl.c
src/mesa/drivers/dri/mach64/mach64_context.c
src/mesa/main/extensions.c
src/mesa/main/getstring.c
src/mesa/tnl/sources
src/mesa/tnl/t_save_api.c
src/mesa/tnl/t_save_playback.c
src/mesa/tnl/t_vtx_api.c
src/mesa/tnl/t_vtx_exec.c
src/mesa/vbo/vbo_attrib.h
src/mesa/vbo/vbo_exec_api.c
src/mesa/vbo/vbo_save_api.c
src/mesa/vbo/vbo_save_draw.c
|
| 3cd06cf8c5ef6a27e36c584e12ba79ed8dacbf28 |
|
29-Nov-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add accelerated CopyPixels for non-overlapping, 1:1 blits.
Submitted by Gary Wong <gtw@gnu.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| f2eb6434ab1cf72e938956c82d2f530368a6be4a |
|
31-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
cleanup code, compiles with vbo changes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| efef291dc71eb57f90785a26957f4b3e01733156 |
|
30-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
checkpoint - remove dead files, otherwise untested
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 02df36f394da4f699b4841c279a6b573fcb7c32b |
|
08-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Basic facility for playing back captured aubfiles. Requires a small
hack to the drm to disable command verification on the cmd_buffer
ioctl. Doesn't exactly replay as commands are normally delivered as
batchbuffers but are captured and replayed as commands on the ring.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 3e05902d304e71493d05edef4c31c6ed1a22bf17 |
|
07-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Consistent return values from the bm* functions.
Get aubfile generation working again.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_context.c
|