/external/llvm/lib/Target/R600/ |
H A D | SIInstrInfo.h | 74 const TargetRegisterInfo *TRI) const override; 80 const TargetRegisterInfo *TRI) const override;
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.cpp | 127 const TargetRegisterInfo *TRI) const { 136 const TargetRegisterInfo *TRI) const {
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H A D | AMDGPUInstrInfo.h | 82 const TargetRegisterInfo *TRI) const; 87 const TargetRegisterInfo *TRI) const;
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/external/llvm/include/llvm/CodeGen/ |
H A D | LiveStackAnalysis.h | 28 const TargetRegisterInfo *TRI; member in class:llvm::LiveStacks
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H A D | MachineRegisterInfo.h | 705 /// TRI::getReservedRegs() when possible. 709 "Use TRI::getReservedRegs()."); 764 const TargetRegisterInfo &TRI, 978 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); local 981 PSet = TRI->getRegClassPressureSets(RC); 982 Weight = TRI->getRegClassWeight(RC).RegWeight; 985 PSet = TRI->getRegUnitPressureSets(RegUnit); 986 Weight = TRI->getRegUnitWeight(RegUnit);
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H A D | RegisterScavenging.h | 32 const TargetRegisterInfo *TRI; member in class:llvm::RegScavenger
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H A D | ResourcePriorityQueue.h | 60 const TargetRegisterInfo *TRI; member in class:llvm::ResourcePriorityQueue
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/external/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 30 TRI(*TM.getRegisterInfo()), Locs(locs), Context(C), 36 UsedRegs.resize((TRI.getNumRegs()+31)/32); 60 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
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H A D | ExpandPostRAPseudos.cpp | 32 const TargetRegisterInfo *TRI; member in struct:__anon25746::ExpandPostRA 92 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 185 TRI = MF.getTarget().getRegisterInfo();
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H A D | LiveDebugVariables.cpp | 252 void computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, 263 void rewriteLocations(VirtRegMap &VRM, const TargetRegisterInfo &TRI); 267 LiveIntervals &LIS, const TargetInstrInfo &TRI); 290 const TargetRegisterInfo *TRI; member in class:__anon25756::LDVImpl 635 const TargetRegisterInfo &TRI, 673 unsigned Unit = *MCRegUnitIterator(Loc.getReg(), &TRI); 691 userValues[i]->computeIntervals(MF->getRegInfo(), *TRI, *LIS, *MDT, UVS); 701 TRI = mf.getTarget().getRegisterInfo(); 873 UserValue::rewriteLocations(VirtRegMap &VRM, const TargetRegisterInfo &TRI) { argument 888 Loc.substPhysReg(VRM.getPhys(VirtReg), TRI); 634 computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument [all...] |
H A D | MachineTraceMetrics.cpp | 41 : MachineFunctionPass(ID), MF(nullptr), TII(nullptr), TRI(nullptr), 56 TRI = MF->getTarget().getRegisterInfo(); 701 const TargetRegisterInfo *TRI) { 722 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) { 734 for (MCRegUnitIterator Units(Kills[i], TRI); Units.isValid(); ++Units) 740 for (MCRegUnitIterator Units(UseMI->getOperand(DefOp).getReg(), TRI); 802 RegUnits.setUniverse(MTM.TRI->getNumRegUnits()); 836 updatePhysDepsDownwards(&UseMI, Deps, RegUnits, MTM.TRI); 877 const TargetRegisterInfo *TRI) { 891 for (MCRegUnitIterator Units(Reg, TRI); Unit [all...] |
H A D | MachineVerifier.cpp | 69 const TargetRegisterInfo *TRI; member in struct:__anon25778::MachineVerifier 95 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 189 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg); 296 TRI = TM->getRegisterInfo(); 461 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 683 for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true); 693 for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true); 904 TII->getRegClass(MCID, MONum, TRI, *MF)) { 907 *OS << TRI->getName(Reg) << " is not a " 916 TRI [all...] |
H A D | PeepholeOptimizer.cpp | 452 static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, argument 464 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, 475 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; 477 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; 549 const TargetRegisterInfo &TRI = *TM->getRegisterInfo(); local 572 ShouldRewrite = shareSameRegisterFile(TRI, DefRC, DefSubReg, SrcRC, 902 // To check the overlapping we need a MRI and a TRI. 915 // Get the TRI and check if inserted sub register overlaps with the 917 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); local 918 if (!TRI || [all...] |
H A D | TargetInstrInfo.cpp | 43 const TargetRegisterInfo *TRI, 50 return TRI->getPointerRegClass(MF, RegClass); 57 return TRI->getRegClass(RegClass); 319 const TargetRegisterInfo &TRI) const { 321 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); 501 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local 504 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); 506 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI); 659 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local 660 if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI)) 42 getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const argument [all...] |
H A D | MachineLICM.cpp | 67 const TargetRegisterInfo *TRI; member in class:__anon25767::MachineLICM 330 TRI = TM->getRegisterInfo(); 345 unsigned NumRC = TRI->getNumRegClasses(); 349 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), 350 E = TRI->regclass_end(); I != E; ++I) 351 RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF); 452 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 472 for (MCRegAliasIterator AS(Reg, TRI, true); AS.isValid(); ++AS) { 500 unsigned NumRegs = TRI->getNumRegs(); 524 for (MCRegAliasIterator AI(Reg, TRI, tru [all...] |
H A D | AggressiveAntiDepBreaker.h | 50 /// (i.e. TRI->getNumRegs()). 121 const TargetRegisterInfo *TRI; member in class:llvm::AggressiveAntiDepBreaker
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H A D | BranchFolding.h | 91 const TargetRegisterInfo *TRI; member in class:llvm::BranchFolder
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64CollectLOH.cpp | 286 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local 353 for (MCRegAliasIterator AI(CurReg, TRI, true); AI.isValid(); ++AI) { 484 unsigned NbReg, const TargetRegisterInfo *TRI, 490 DEBUG(dbgs() << "*** Reg " << PrintReg(IdToReg[CurReg], TRI) << " ***\n"); 1006 const TargetRegisterInfo *TRI) { 1009 unsigned NbReg = TRI->getNumRegs(); 1031 for (MCRegAliasIterator AI(CurReg, TRI, true); AI.isValid(); ++AI) 1037 DEBUG(dbgs() << "Register: " << PrintReg(*AI, TRI) << '\n'); 1046 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local 1056 collectInvolvedReg(MF, RegToId, IdToReg, TRI); 483 printReachingDef(const InstrToInstrs *ColorOpToReachedUses, unsigned NbReg, const TargetRegisterInfo *TRI, const MapIdToReg &IdToReg) argument 1004 collectInvolvedReg(MachineFunction &MF, MapRegToId &RegToId, MapIdToReg &IdToReg, const TargetRegisterInfo *TRI) argument [all...] |
H A D | AArch64InstrInfo.h | 90 const TargetRegisterInfo *TRI) const override; 115 const TargetRegisterInfo *TRI) const override; 120 const TargetRegisterInfo *TRI) const override;
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.h | 115 const TargetRegisterInfo *TRI) const override; 121 const TargetRegisterInfo *TRI) const override; 128 const TargetRegisterInfo &TRI) const override; 138 const TargetRegisterInfo *TRI) const; 231 const TargetRegisterInfo *TRI) const override;
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H A D | ARMExpandPseudoInsts.cpp | 47 const TargetRegisterInfo *TRI; member in class:__anon25968::ARMExpandPseudo 357 const TargetRegisterInfo *TRI, unsigned &D0, 360 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 361 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 362 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 363 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 365 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 366 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 367 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 368 D3 = TRI 356 GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3) argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 334 const TargetRegisterInfo *TRI = &getRegisterInfo(); local 338 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]); 339 unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]); 345 MovMI->addRegisterDefined(DestReg, TRI); 347 MovMI->addRegisterKilled(SrcReg, TRI); 354 const TargetRegisterInfo *TRI) const { 392 const TargetRegisterInfo *TRI) const {
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGRRList.cpp | 279 const TargetRegisterInfo *TRI, 301 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 309 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); 332 LiveRegDefs.resize(TRI->getNumRegs() + 1, nullptr); 333 LiveRegGens.resize(TRI->getNumRegs() + 1, nullptr); 550 unsigned CallResource = TRI->getNumRegs(); 754 unsigned CallResource = TRI->getNumRegs(); 826 unsigned CallResource = TRI->getNumRegs(); 1211 const TargetRegisterInfo *TRI) { 1212 for (MCRegAliasIterator AliasI(Reg, TRI, tru 276 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument 1207 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 68 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local 95 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF); 125 const TargetRegisterInfo *TRI) const { 203 &SystemZ::FP64BitRegClass, TRI); 214 const TargetRegisterInfo *TRI) const { 229 &SystemZ::FP64BitRegClass, TRI);
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/external/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 206 const X86RegisterInfo *TRI = local 208 if (TRI->hasBasePointer(DAG.getMachineFunction()) && 209 TRI->getBaseRegister() == X86::ESI)
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