Searched refs:getOperand (Results 76 - 100 of 529) sorted by relevance

1234567891011>>

/external/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp90 unsigned Reg = MI->getOperand(1).getReg();
100 Reg = DefMI->getOperand(1).getReg();
106 Reg = DefMI->getOperand(2).getReg();
118 unsigned Reg = MI->getOperand(0).getReg();
129 Reg = UseMI->getOperand(0).getReg();
144 unsigned Reg = MI->getOperand(1).getReg();
157 if (DefMI->getOperand(i + 1).getMBB() == MBB) {
158 unsigned SrcReg = DefMI->getOperand(i).getReg();
166 Reg = DefMI->getOperand(1).getReg();
172 Reg = DefMI->getOperand(
[all...]
H A DARMISelDAGToDAG.cpp300 isInt32Immediate(N->getOperand(1).getNode(), Imm);
346 SDValue N0 = N->getOperand(0);
347 SDValue N1 = N->getOperand(1);
374 SDValue Srl = N1.getOperand(0);
396 Srl.getOperand(0),
480 BaseReg = N.getOperand(0);
482 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
504 BaseReg = N.getOperand(0);
506 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
509 ShReg = N.getOperand(
[all...]
H A DARMBaseInstrInfo.cpp159 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
160 const MachineOperand &Base = MI->getOperand(2);
161 const MachineOperand &Offset = MI->getOperand(NumOps-3);
165 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
166 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
217 get(MemOpc), MI->getOperand(0).getReg())
221 get(MemOpc)).addReg(MI->getOperand(1).getReg())
228 get(MemOpc), MI->getOperand(0).getReg())
232 get(MemOpc)).addReg(MI->getOperand(
[all...]
H A DARMExpandPseudoInsts.cpp82 const MachineOperand &MO = OldMI.getOperand(i);
393 bool DstIsDead = MI.getOperand(OpIdx).isDead();
394 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
406 MIB.addOperand(MI.getOperand(OpIdx++));
409 MIB.addOperand(MI.getOperand(OpIdx++));
410 MIB.addOperand(MI.getOperand(OpIdx++));
413 MIB.addOperand(MI.getOperand(OpIdx++));
423 MIB.addOperand(MI.getOperand(OpIdx++));
424 MIB.addOperand(MI.getOperand(OpIdx++));
429 MachineOperand MO = MI.getOperand(SrcOpId
[all...]
/external/llvm/lib/Target/Mips/
H A DMips16RegisterInfo.cpp114 if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
115 FrameReg = MI.getOperand(OpNo+2).getReg();
132 Offset += MI.getOperand(OpNo + 1).getImm();
149 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
150 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
H A DMipsSEISelDAGToDAG.cpp48 unsigned Mask = MI.getOperand(1).getImm();
91 (MI.getOperand(1).getReg() == Mips::ZERO) &&
92 (MI.getOperand(2).getImm() == 0)) {
93 DstReg = MI.getOperand(0).getReg();
96 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
97 (MI.getOperand(2).getImm() == 0)) {
98 DstReg = MI.getOperand(0).getReg();
241 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
242 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(
[all...]
/external/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp108 if (IVOperand != UseInst->getOperand(OperIdx) ||
109 !isa<ConstantInt>(UseInst->getOperand(1)))
115 || !isa<ConstantInt>(IVOperand->getOperand(1)))
118 IVSrc = IVOperand->getOperand(0);
122 ConstantInt *D = cast<ConstantInt>(UseInst->getOperand(1));
160 if (IVOperand != ICmp->getOperand(0)) {
162 assert(IVOperand == ICmp->getOperand(1) && "Can't find IVOperand");
168 const SCEV *S = SE->getSCEV(ICmp->getOperand(IVOperIdx));
169 const SCEV *X = SE->getSCEV(ICmp->getOperand(1 - IVOperIdx));
198 if (IVOperand != Rem->getOperand(
[all...]
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp45 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) {
50 return I->getOperand(0);
57 return I->getOperand(0);
65 DecomposeSimpleLinearExpr(I->getOperand(0), SubScale, Offset);
120 DecomposeSimpleLinearExpr(AI.getOperand(0), ArraySizeScale, ArrayOffset);
189 Value *LHS = EvaluateInDifferentType(I->getOperand(0), Ty, isSigned);
190 Value *RHS = EvaluateInDifferentType(I->getOperand(1), Ty, isSigned);
200 if (I->getOperand(0)->getType() == Ty)
201 return I->getOperand(0);
205 Res = CastInst::CreateIntegerCast(I->getOperand(
[all...]
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp54 assert(MI.getOperand(0).isReg());
55 return MI.getOperand(0).getReg() == Mips::ZERO;
61 return (MI.getNumOperands() > 0 && MI.getOperand(0).isReg()
62 && MI.getOperand(0).getReg() == Mips::SP);
84 assert(MI.getOperand(0).isReg());
85 if (MI.getOperand(0).getReg() == Mips::ZERO)
106 unsigned AddrReg = MI.getOperand(0).getReg();
122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
128 unsigned SPReg = MI.getOperand(0).getReg();
156 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrId
[all...]
/external/llvm/lib/Analysis/
H A DLoads.cpp114 if (AreEquivalentAddressValues(LI->getOperand(0), V)) return true;
116 if (AreEquivalentAddressValues(SI->getOperand(1), V)) return true;
171 if (AreEquivalentAddressValues(LI->getOperand(0), Ptr)) {
180 if (AreEquivalentAddressValues(SI->getOperand(1), Ptr)) {
182 return SI->getOperand(0);
189 (isa<AllocaInst>(SI->getOperand(1)) ||
190 isa<GlobalVariable>(SI->getOperand(1))))
H A DTypeBasedAliasAnalysis.cpp157 MDNode *P = dyn_cast_or_null<MDNode>(Node->getOperand(1));
170 ConstantInt *CI = dyn_cast<ConstantInt>(Node->getOperand(2));
191 return dyn_cast_or_null<MDNode>(Node->getOperand(0));
194 return dyn_cast_or_null<MDNode>(Node->getOperand(1));
197 return cast<ConstantInt>(Node->getOperand(2))->getZExtValue();
205 ConstantInt *CI = dyn_cast<ConstantInt>(Node->getOperand(3));
237 cast<ConstantInt>(Node->getOperand(2))->getZExtValue();
239 MDNode *P = dyn_cast_or_null<MDNode>(Node->getOperand(1));
249 uint64_t Cur = cast<ConstantInt>(Node->getOperand(Idx + 1))->
261 uint64_t Cur = cast<ConstantInt>(Node->getOperand(TheId
[all...]
/external/llvm/lib/CodeGen/
H A DCalcSpillWeights.cpp48 if (mi->getOperand(0).getReg() == reg) {
49 sub = mi->getOperand(0).getSubReg();
50 hreg = mi->getOperand(1).getReg();
51 hsub = mi->getOperand(1).getSubReg();
53 sub = mi->getOperand(1).getSubReg();
54 hreg = mi->getOperand(0).getReg();
55 hsub = mi->getOperand(0).getSubReg();
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp230 const MCOperand &MO = MI.getOperand(OpIdx);
251 const MCOperand &MO = MI.getOperand(OpIdx);
278 const MCOperand &MO = MI.getOperand(OpIdx);
279 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
304 const MCOperand &MO = MI.getOperand(OpIdx);
326 const MCOperand &MO = MI.getOperand(OpIdx);
346 unsigned SignExtend = MI.getOperand(OpIdx).getImm();
347 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm();
355 const MCOperand &MO = MI.getOperand(OpIdx);
374 const MCOperand &MO = MI.getOperand(OpId
[all...]
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
269 return MI.getOperand(Op).getReg() == ARM::CPSR;
277 const MCOperand &MO = MI.getOperand(Op);
311 unsigned SoImm = MI.getOperand(Op).getImm();
344 return 64 - MI.getOperand(Op).getImm();
541 const MCOperand &MO = MI.getOperand(OpIdx);
542 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
571 const MCOperand &MO = MI.getOperand(OpIdx);
608 const MCOperand MO = MI.getOperand(OpIdx);
621 const MCOperand MO = MI.getOperand(OpId
[all...]
/external/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.cpp30 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
35 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
138 const MCOperand &Op = MI->getOperand(OpNo);
163 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
175 unsigned Imm = MI->getOperand(OpNum).getImm();
198 const MCOperand &Op = MI->getOperand(OpNo);
219 int32_t Imm = MI->getOperand(OpNo).getImm();
235 switch (MI->getOperand(OpNo).getImm()) {
266 const MCOperand &Op = MI->getOperand(OpN
[all...]
/external/llvm/lib/Target/R600/
H A DSILowerControlFlow.cpp182 unsigned Reg = MI.getOperand(0).getReg();
183 unsigned Vcc = MI.getOperand(1).getReg();
192 Skip(MI, MI.getOperand(2));
200 unsigned Dst = MI.getOperand(0).getReg();
201 unsigned Src = MI.getOperand(1).getReg();
211 Skip(MI, MI.getOperand(2));
220 unsigned Dst = MI.getOperand(0).getReg();
221 unsigned Src = MI.getOperand(1).getReg();
234 unsigned Dst = MI.getOperand(0).getReg();
235 unsigned Vcc = MI.getOperand(
[all...]
H A DAMDGPUInstrInfo.cpp136 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
137 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
139 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
141 buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
144 buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
151 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
152 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
154 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
157 MI->getOperand(ValOpIdx).getReg());
159 buildIndirectWrite(MBB, MI, MI->getOperand(ValOpId
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDILPeepholeOptimizer.cpp243 Constant *CV = dyn_cast<Constant>(CI->getOperand(0));
326 StringRef calleeName = CI->getOperand(CI->getNumOperands()-1)->getName();
337 Constant *CV = dyn_cast<Constant>(CI->getOperand(0));
349 ConstantInt *CV = dyn_cast<ConstantInt>(CI->getOperand(0));
363 Function *F = dyn_cast<Function>(CI->getOperand(CI->getNumOperands()-1));
403 shift = dyn_cast<Constant>(base->getOperand(1));
405 mask = dyn_cast<Constant>(base->getOperand(1));
414 src = dyn_cast<Instruction>(base->getOperand(0));
428 shift = dyn_cast<Constant>(src->getOperand(1));
429 src = dyn_cast<Instruction>(src->getOperand(
[all...]
/external/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp242 assert(Inst.getOperand(0).isReg() &&
243 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
244 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
245 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
249 unsigned Reg = Inst.getOperand(0).getReg();
254 MCOperand Saved = Inst.getOperand(ImmOp);
264 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILPeepholeOptimizer.cpp243 Constant *CV = dyn_cast<Constant>(CI->getOperand(0));
326 StringRef calleeName = CI->getOperand(CI->getNumOperands()-1)->getName();
337 Constant *CV = dyn_cast<Constant>(CI->getOperand(0));
349 ConstantInt *CV = dyn_cast<ConstantInt>(CI->getOperand(0));
363 Function *F = dyn_cast<Function>(CI->getOperand(CI->getNumOperands()-1));
403 shift = dyn_cast<Constant>(base->getOperand(1));
405 mask = dyn_cast<Constant>(base->getOperand(1));
414 src = dyn_cast<Instruction>(base->getOperand(0));
428 shift = dyn_cast<Constant>(src->getOperand(1));
429 src = dyn_cast<Instruction>(src->getOperand(
[all...]
/external/llvm/unittests/Analysis/
H A DScalarEvolutionTest.cpp68 EXPECT_EQ(cast<SCEVConstant>(M0->getOperand(0))->getValue()->getZExtValue(),
70 EXPECT_EQ(cast<SCEVConstant>(M1->getOperand(0))->getValue()->getZExtValue(),
72 EXPECT_EQ(cast<SCEVConstant>(M2->getOperand(0))->getValue()->getZExtValue(),
76 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
77 EXPECT_EQ(cast<SCEVUnknown>(M1->getOperand(1))->getValue(), V1);
78 EXPECT_EQ(cast<SCEVUnknown>(M2->getOperand(1))->getValue(), V2);
85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
86 EXPECT_EQ(cast<SCEVUnknown>(M1->getOperand(1))->getValue(), V0);
87 EXPECT_EQ(cast<SCEVUnknown>(M2->getOperand(1))->getValue(), V0);
148 EXPECT_EQ(Product->getOperand(
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp280 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
316 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
327 SDValue Wrapper = N->getOperand(1);
328 SDValue GlobalVal = Wrapper.getOperand(0);
334 SDValue Src = N->getOperand(0);
448 SDValue Chain = N->getOperand(0);
449 SDValue N1 = N->getOperand(1);
630 SDValue Chain = N->getOperand(0);
631 SDValue Op1 = N->getOperand(1);
668 N->getOperand(
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCBranchSelector.cpp117 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm())
118 Dest = I->getOperand(2).getMBB();
120 !I->getOperand(1).isImm())
121 Dest = I->getOperand(1).getMBB();
124 !I->getOperand(0).isImm())
125 Dest = I->getOperand(0).getMBB();
167 PPC::Predicate Pred = (PPC::Predicate)I->getOperand(0).getImm();
168 unsigned CRReg = I->getOperand(1).getReg();
174 unsigned CRBit = I->getOperand(0).getReg();
177 unsigned CRBit = I->getOperand(
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp356 MachineOperand MO = MI->getOperand(0);
484 if (MI->getOperand(opNum).isReg() &&
485 MI->getOperand(opNum).isDef()) {
486 DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
490 if (MI->getOperand(opNum).isReg() &&
491 MI->getOperand(opNum).isUse()) {
492 if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
493 return MI->getOperand(opNum);
499 assert(MI->getOperand(1).isReg() &&
501 return (MI->getOperand(
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp68 if ((MI->getOperand(1).isFI()) && // is a stack slot
69 (MI->getOperand(2).isImm()) && // the imm is zero
70 (isZeroImm(MI->getOperand(2))))
72 FrameIndex = MI->getOperand(1).getIndex();
73 return MI->getOperand(0).getReg();
90 if ((MI->getOperand(1).isFI()) && // is a stack slot
91 (MI->getOperand(2).isImm()) && // the imm is zero
92 (isZeroImm(MI->getOperand(2))))
94 FrameIndex = MI->getOperand(1).getIndex();
95 return MI->getOperand(
[all...]

Completed in 534 milliseconds

1234567891011>>