/external/llvm/lib/CodeGen/ |
H A D | PHIElimination.cpp | 86 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB); 87 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB); 558 unsigned Reg = BBI->getOperand(i).getReg(); local 578 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges) 581 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#" 585 // If Reg is not live-in to MBB, it means it must be live-in to some 589 // If Reg *is* live-in to MBB, the interference is inevitable and a copy 593 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges; 621 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) { argument 625 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MB 630 isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) argument [all...] |
H A D | BranchFolding.cpp | 145 unsigned Reg = I->getOperand(0).getReg(); local 146 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 163 unsigned Reg = MO.getReg(); local 164 if (ImpDefRegs.count(Reg)) 1502 unsigned Reg = MO.getReg(); local 1503 if (!Reg) 1506 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 1516 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 1541 unsigned Reg = MO.getReg(); local 1542 if (!Reg) 1570 unsigned Reg = MO.getReg(); local 1655 unsigned Reg = MO.getReg(); local 1706 unsigned Reg = MO.getReg(); local 1718 unsigned Reg = MO.getReg(); local [all...] |
H A D | LiveRangeCalc.cpp | 40 void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) { argument 43 // Visit all def operands. If the same instruction has multiple defs of Reg, 45 for (MachineOperand &MO : MRI->def_operands(Reg)) { 63 void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) { argument 66 // Visit all operands that read Reg. This may include partial defs. 67 for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) { 74 // MI is reading Reg. We may have visited MI before if it happens to be 75 // reading Reg multiple times. That is OK, extend() is idempotent. 83 // PHI operands are paired: (Reg, PredMBB). 101 extend(LR, Idx, Reg); [all...] |
H A D | TailDuplication.cpp | 343 static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB, argument 345 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { 437 unsigned Reg = MO.getReg(); local 438 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 441 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 444 LocalVRMap.insert(std::make_pair(Reg, NewReg)); 445 if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg)) 446 AddSSAUpdateEntry(Reg, NewReg, PredBB); 448 DenseMap<unsigned, unsigned>::iterator VI = LocalVRMap.find(Reg); 484 unsigned Reg = MO0.getReg(); local [all...] |
H A D | EarlyIfConversion.cpp | 236 unsigned Reg = MO->getReg(); local 239 if (MO->isDef() && TargetRegisterInfo::isPhysicalRegister(Reg)) 240 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) 243 if (!MO->readsReg() || !TargetRegisterInfo::isVirtualRegister(Reg)) 245 MachineInstr *DefMI = MRI->getVRegDef(Reg); 291 unsigned Reg = MO->getReg(); local 292 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) 294 // I clobbers Reg, so it isn't live before I. 296 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) 298 // Unless I reads Reg [all...] |
H A D | RegAllocPBQP.cpp | 198 for (unsigned Reg = 1, e = tri->getNumRegs(); Reg != e; ++Reg) { 199 if (mri->def_empty(Reg)) 201 pregs.insert(Reg); 202 mri->setPhysRegUsed(Reg); 444 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local 445 if (mri->reg_nodbg_empty(Reg)) 447 LiveInterval *li = &lis->getInterval(Reg);
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/external/llvm/lib/MC/MCParser/ |
H A D | COFFAsmParser.cpp | 581 unsigned Reg; local 582 if (ParseSEHRegisterNumber(Reg)) 589 getStreamer().EmitWinCFIPushReg(Reg); 594 unsigned Reg; local 596 if (ParseSEHRegisterNumber(Reg)) 613 getStreamer().EmitWinCFISetFrame(Reg, Off); 635 unsigned Reg; local 637 if (ParseSEHRegisterNumber(Reg)) 655 getStreamer().EmitWinCFISaveReg(Reg, Off); 662 unsigned Reg; local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMMachineFunctionInfo.h | 210 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
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H A D | Thumb2SizeReduction.cpp | 262 unsigned Reg = MO.getReg(); local 263 if (Reg == 0 || Reg == ARM::CPSR) 265 Defs.insert(Reg); 271 unsigned Reg = MO.getReg(); local 272 if (Defs.count(Reg)) 344 unsigned Reg = MO.getReg(); local 345 if (Reg == 0 || Reg == ARM::CPSR) 347 if (isPCOk && Reg 768 unsigned Reg = MO.getReg(); local [all...] |
H A D | Thumb1RegisterInfo.h | 56 unsigned Reg) const override;
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H A D | ARMBaseRegisterInfo.cpp | 208 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { argument 209 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 255 unsigned Reg = Order[I]; local 256 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 259 unsigned Paired = getPairedGPR(Reg, !Odd, this); 262 Hints.push_back(Reg); 267 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, argument 270 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 274 // If 'Reg' i [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 86 unsigned &Reg, unsigned &Imm, 513 unsigned Reg = MO.getReg(); local 514 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 517 switch (Reg) { 538 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, argument 544 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 866 unsigned Reg, Imm12; local 871 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 887 Reg = ARM::PC; 899 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm1 950 unsigned Reg, Imm8; local 992 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local 1243 unsigned Reg, Imm8; local [all...] |
H A D | ARMTargetStreamer.cpp | 51 void ARMTargetStreamer::emitMovSP(unsigned Reg, int64_t Offset) {} argument
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H A D | ARMUnwindOpAsm.h | 58 void EmitSetSP(uint16_t Reg);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCopyToCombine.cpp | 204 static bool isEvenReg(unsigned Reg) { argument 205 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && 206 Hexagon::IntRegsRegClass.contains(Reg)); 207 return (Reg - Hexagon::R0) % 2 == 0; 374 unsigned Reg = Op.getReg(); local 375 MachineInstr *DefInst = LastDef[Reg]; 402 unsigned Reg = Op.getReg(); local 403 if (Hexagon::DoubleRegsRegClass.contains(Reg)) { 404 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 407 } else if (Hexagon::IntRegsRegClass.contains(Reg)) [all...] |
/external/llvm/lib/Target/Sparc/Disassembler/ |
H A D | SparcDisassembler.cpp | 122 unsigned Reg = IntRegDecoderTable[RegNo]; local 123 Inst.addOperand(MCOperand::CreateReg(Reg)); 133 unsigned Reg = IntRegDecoderTable[RegNo]; local 134 Inst.addOperand(MCOperand::CreateReg(Reg)); 145 unsigned Reg = FPRegDecoderTable[RegNo]; local 146 Inst.addOperand(MCOperand::CreateReg(Reg)); 157 unsigned Reg = DFPRegDecoderTable[RegNo]; local 158 Inst.addOperand(MCOperand::CreateReg(Reg)); 170 unsigned Reg = QFPRegDecoderTable[RegNo]; local 171 if (Reg [all...] |
/external/clang/lib/StaticAnalyzer/Core/ |
H A D | ProgramState.cpp | 699 if (const MemRegion *Reg = V.getAsRegion()) 700 return isTainted(Reg, Kind); 704 bool ProgramState::isTainted(const MemRegion *Reg, TaintTagType K) const { argument 705 if (!Reg) 710 if (const ElementRegion *ER = dyn_cast<ElementRegion>(Reg)) 713 if (const SymbolicRegion *SR = dyn_cast<SymbolicRegion>(Reg)) 716 if (const SubRegion *ER = dyn_cast<SubRegion>(Reg)) 761 DynamicTypeInfo ProgramState::getDynamicTypeInfo(const MemRegion *Reg) const { 762 Reg = Reg 781 setDynamicTypeInfo(const MemRegion *Reg, DynamicTypeInfo NewTy) const argument [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]); local 143 ExplicitAliases.push_back(Reg); 144 Reg->ExplicitAliases.push_back(this); 586 Record *Reg = Lists[i][n]; variable 588 Name += Reg->getName(); 589 Tuple.push_back(DefInit::get(Reg)); 591 unsigned(Reg->getValueAsInt("CostPerUse"))); 691 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]); local 692 Members.insert(Reg); 693 TopoSigs.set(Reg 703 CodeGenRegister *Reg = RegBank.getReg(Order.back()); local 1032 CodeGenRegister *&Reg = Def2Reg[Def]; local 1294 const CodeGenRegister *Reg = Registers[i]; local 1315 const CodeGenRegister *Reg = nullptr; local 1366 normalizeWeight(CodeGenRegister *Reg, std::vector<UberRegSet> &UberSets, std::vector<UberRegSet*> &RegSets, std::set<unsigned> &NormalRegs, CodeGenRegister::RegUnitList &NormalUnits, CodeGenRegBank &RegBank) argument 1924 const CodeGenRegister *Reg = getReg(R); local 1969 CodeGenRegister *Reg = getReg(Regs[i]); local [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineTraceMetrics.h | 121 unsigned Reg; member in struct:llvm::MachineTraceMetrics::LiveInReg 127 LiveInReg(unsigned Reg, unsigned Height = 0) : Reg(Reg), Height(Height) {} argument
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.cpp | 39 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); local 40 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); 48 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); local 49 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.h | 85 // Emit code before MBBI to load immediate value into physical register Reg. 89 unsigned Reg, uint64_t Value) const;
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/external/llvm/lib/Target/Mips/ |
H A D | MipsDelaySlotFiller.cpp | 89 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg, 92 /// Returns true if Reg or its alias is in RegSet. 93 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const; 366 unsigned Reg, bool IsDef) const { 368 NewDefs.set(Reg); 369 // check whether Reg has already been defined or used. 370 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg)); 373 NewUses.set(Reg); 374 // check whether Reg ha 365 checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg, bool IsDef) const argument [all...] |
H A D | MipsFastISel.cpp | 26 unsigned Reg; member in union:__anon26050::Address::__anon26052 33 Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; } 151 Addr.Base.Reg = getRegForValue(Obj); 152 return Addr.Base.Reg != 0; 190 EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset); 239 EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
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/external/llvm/lib/Target/R600/ |
H A D | SIInsertWaits.cpp | 142 unsigned Reg = Op.getReg(); local 143 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); 192 unsigned Reg = Op.getReg(); local 193 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); 198 Result.first = TRI->getEncodingValue(Reg);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 199 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); local 200 if (TargetRegisterInfo::isVirtualRegister(Reg)) 201 return Reg; 248 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); local 249 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 250 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 252 VRBase = Reg; 823 unsigned Reg = II.getImplicitDefs()[i - NumDefs]; 827 UsedRegs.push_back(Reg); 828 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMa [all...] |