/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 860 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); local 861 Inst.addOperand(MCOperand::CreateReg(Reg)); 871 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); local 872 Inst.addOperand(MCOperand::CreateReg(Reg)); 900 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); local 901 Inst.addOperand(MCOperand::CreateReg(Reg)); 912 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); local 913 Inst.addOperand(MCOperand::CreateReg(Reg)); 924 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo); local 925 Inst.addOperand(MCOperand::CreateReg(Reg)); 935 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); local 946 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); local 957 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); local 967 unsigned Reg = fieldFromInstruction(Insn, 16, 5); local 987 unsigned Reg = fieldFromInstruction(Insn, 6, 5); local 1035 unsigned Reg = fieldFromInstruction(Insn, 21, 5); local 1056 unsigned Reg = fieldFromInstruction(Insn, 21, 5); local 1074 unsigned Reg = fieldFromInstruction(Insn, 16, 5); local 1128 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); local 1140 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); local 1152 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); local 1164 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); local 1176 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); local 1188 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); local 1200 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); local 1212 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); local 1224 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); local 1236 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsDelaySlotFiller.cpp | 89 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg, 92 /// Returns true if Reg or its alias is in RegSet. 93 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const; 366 unsigned Reg, bool IsDef) const { 368 NewDefs.set(Reg); 369 // check whether Reg has already been defined or used. 370 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg)); 373 NewUses.set(Reg); 374 // check whether Reg ha 365 checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg, bool IsDef) const argument [all...] |
H A D | MipsSEISelDAGToDAG.cpp | 731 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL, local 733 return std::make_pair(true, Reg.getNode());
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H A D | MipsSEInstrInfo.cpp | 89 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. 117 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. 145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. 155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. 371 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr); local 372 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); 401 unsigned Reg = RegInfo.createVirtualRegister(RC); local 404 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)); 406 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) 411 BuildMI(MBB, II, DL, get(Inst->Opc), Reg) [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 305 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); local 308 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 312 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 316 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 345 .addReg(Reg, RegState::Kill) 370 .addReg(Reg, RegState::Kill) 404 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); local 409 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 415 unsigned Reg1 = Reg; 416 Reg 448 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); local 477 unsigned Reg = 0; local 521 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); local 564 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); local 608 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); local 633 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); local 649 hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600ControlFlowFinalizer.cpp | 289 unsigned Reg = MO.getReg(); local 290 if (AMDGPU::R600_Reg128RegClass.contains(Reg)) 291 DstMI = Reg; 293 DstMI = TRI->getMatchingSuperReg(Reg, 294 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)), 298 unsigned Reg = MO.getReg(); local 299 if (AMDGPU::R600_Reg128RegClass.contains(Reg)) 300 SrcMI = Reg; 302 SrcMI = TRI->getMatchingSuperReg(Reg, 303 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)), [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86Operand.h | 60 struct RegOp Reg; member in union:llvm::X86Operand::__anon26166 95 return Reg.RegNo; 427 Res->Reg.RegNo = RegNo;
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86AsmBackend.cpp | 530 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true); local 531 SavedRegs[SavedRegIdx++] = Reg; 610 int getCompactUnwindRegNum(unsigned Reg) const { 619 if (*CURegs == Reg) 633 unsigned Reg = SavedRegs[i]; local 634 if (Reg == 0) break; 636 int CURegNum = getCompactUnwindRegNum(Reg);
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/external/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 249 unsigned Reg = Inst.getOperand(0).getReg(); local 250 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 310 unsigned Reg = Inst.getOperand(RegOp).getReg(); local 311 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg ! 799 unsigned Reg = MI->getOperand(0).getReg(); local [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.cpp | 51 unsigned Reg; member in struct:__anon26209::StackSlotInfo 52 StackSlotInfo(int f, int o, int r) : FI(f), Offset(o), Reg(r){}; 201 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg) 286 MBB.addLiveIn(SpillList[i].Reg); 288 .addReg(SpillList[i].Reg, RegState::Kill) 293 unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true); 329 MRI->getDwarfRegNum(SpillList[0].Reg, true), 332 MRI->getDwarfRegNum(SpillList[1].Reg, true), 426 unsigned Reg = it->getReg(); local 427 assert(Reg ! 456 unsigned Reg = it->getReg(); local [all...] |
/external/llvm/utils/TableGen/ |
H A D | DAGISelMatcherGen.cpp | 29 const CodeGenRegister *Reg = T.getRegBank().getReg(R); local 34 if (!RC.contains(Reg)) 625 const CodeGenRegister *Reg = local 627 AddMatcher(new EmitRegisterMatcher(Reg, N->getType(0))); 844 Record *Reg = Pattern.getDstRegs()[i]; local 845 if (!Reg->isSubClassOf("Register") || Reg == HandledReg) continue; 846 ResultVTs.push_back(getRegisterValueType(Reg, CGT)); 968 Record *Reg = Pattern.getDstRegs()[i]; local 969 if (!Reg [all...] |
H A D | RegisterInfoEmitter.cpp | 324 Record *Reg = Regs[i]->TheDef; local 325 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 327 if (DwarfRegNums.count(Reg)) 328 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 329 getQualifiedName(Reg) + "specified multiple times"); 330 DwarfRegNums[Reg] = RegNums; 391 Record *Reg = Regs[i]->TheDef; local 392 const RecordVal *V = Reg->getValue("DwarfAlias"); 398 DwarfRegNums[Reg] = DwarfRegNums[Alias]; 447 Record *Reg local 732 const CodeGenRegister *Reg = Regs[i]; local 823 const CodeGenRegister *Reg = Regs[i]; local 864 Record *Reg = Order[i]; local 874 Record *Reg = Order[i]; local 915 Record *Reg = Regs[i]->TheDef; local 1217 const CodeGenRegister &Reg = *Regs[i]; local [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/program/ |
H A D | prog_optimize.c | 842 GLuint Reg; /** The temporary register index */ member in struct:interval 893 if (list->Intervals[k].Reg == inv->Reg) { 1078 inv.Reg = i; 1092 printf("Reg[%d] live [%d, %d]:", 1093 inv->Reg, inv->Start, inv->End); 1166 printf("Consider register %u\n", live->Reg); 1183 const GLint regNew = registerMap[inv->Reg]; 1187 printf(" expire interval for reg %u\n", inv->Reg); 1209 registerMap[live->Reg] [all...] |
/external/clang/lib/CodeGen/ |
H A D | CGValue.h | 344 static LValue MakeGlobalReg(llvm::Value *Reg, argument 349 R.V = Reg;
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | ProgramState.cpp | 699 if (const MemRegion *Reg = V.getAsRegion()) 700 return isTainted(Reg, Kind); 704 bool ProgramState::isTainted(const MemRegion *Reg, TaintTagType K) const { argument 705 if (!Reg) 710 if (const ElementRegion *ER = dyn_cast<ElementRegion>(Reg)) 713 if (const SymbolicRegion *SR = dyn_cast<SymbolicRegion>(Reg)) 716 if (const SubRegion *ER = dyn_cast<SubRegion>(Reg)) 761 DynamicTypeInfo ProgramState::getDynamicTypeInfo(const MemRegion *Reg) const { 762 Reg = Reg 781 setDynamicTypeInfo(const MemRegion *Reg, DynamicTypeInfo NewTy) const argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineBasicBlock.h | 320 void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); } argument 329 void removeLiveIn(unsigned Reg); 333 bool isLiveIn(unsigned Reg) const; 621 /// computeRegisterLiveness - Return whether (physical) register \c Reg 628 /// \c Reg must be a physical register. 630 unsigned Reg, MachineInstr *MI,
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H A D | MachineFrameInfo.h | 38 unsigned Reg; member in class:llvm::CalleeSavedInfo 43 : Reg(R), FrameIdx(FI) {} 46 unsigned getReg() const { return Reg; }
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H A D | MachineRegisterInfo.h | 36 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0; 91 return MO->Contents.Reg.Next; 195 /// Verify the sanity of the use list for Reg. 196 void verifyUseList(unsigned Reg) const; 228 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { 229 return iterator_range<reg_iterator>(reg_begin(Reg), reg_end()); 244 reg_instructions(unsigned Reg) const { 245 return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg), 260 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { 261 return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg), 599 setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) argument 652 setPhysRegUsed(unsigned Reg) argument 666 setPhysRegUnused(unsigned Reg) argument 739 addLiveIn(unsigned Reg, unsigned vreg = 0) argument [all...] |
H A D | ScheduleDAG.h | 80 /// Reg - For Data, Anti, and Output dependencies, the associated 83 unsigned Reg; member in union:llvm::SDep::__anon25497 101 SDep(SUnit *S, Kind kind, unsigned Reg) argument 105 llvm_unreachable("Reg given for non-register dependence!"); 108 assert(Reg != 0 && 109 "SDep::Anti and SDep::Output must use a non-zero Reg!"); 110 Contents.Reg = Reg; 114 Contents.Reg = Reg; 240 setReg(unsigned Reg) argument [all...] |
H A D | SelectionDAG.h | 474 SDValue getRegister(unsigned Reg, EVT VT); 486 SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N) { argument 488 getRegister(Reg, N.getValueType()), N); 494 SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N, argument 497 SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue }; 502 // Similar to last getCopyToReg() except parameter Reg is a SDValue 503 SDValue getCopyToReg(SDValue Chain, SDLoc dl, SDValue Reg, SDValue N, argument 506 SDValue Ops[] = { Chain, Reg, N, Glue }; 511 SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) { argument 513 SDValue Ops[] = { Chain, getRegister(Reg, V 520 getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT, SDValue Glue) argument [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 543 bool hasImplicitUseOfPhysReg(unsigned Reg) const { 546 if (*ImpUses == Reg) return true; 552 bool hasImplicitDefOfPhysReg(unsigned Reg, argument 556 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs))) 563 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, argument 567 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) 569 return hasImplicitDefOfPhysReg(Reg, &RI);
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H A D | MCRegisterInfo.h | 71 bool contains(unsigned Reg) const { 72 unsigned InByte = Reg % 8; 73 unsigned Byte = Reg / 8; 329 unsigned getSubReg(unsigned Reg, unsigned Idx) const; 332 /// Reg so its sub-register of index SubIdx is Reg. 333 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 439 /// MCSubRegIterator enumerates all sub-registers of Reg. 440 /// If IncludeSelf is set, Reg itself is included in the list. 443 MCSubRegIterator(unsigned Reg, cons 494 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) argument 557 unsigned Reg; member in class:llvm::MCRegAliasIterator 565 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, bool IncludeSelf) argument [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 607 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 811 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 813 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 818 unsigned Reg, MachineRegisterInfo *MRI) const { 884 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 897 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 606 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 817 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument
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/external/llvm/lib/CodeGen/ |
H A D | BranchFolding.cpp | 145 unsigned Reg = I->getOperand(0).getReg(); local 146 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 163 unsigned Reg = MO.getReg(); local 164 if (ImpDefRegs.count(Reg)) 1502 unsigned Reg = MO.getReg(); local 1503 if (!Reg) 1506 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 1516 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 1541 unsigned Reg = MO.getReg(); local 1542 if (!Reg) 1570 unsigned Reg = MO.getReg(); local 1655 unsigned Reg = MO.getReg(); local 1706 unsigned Reg = MO.getReg(); local 1718 unsigned Reg = MO.getReg(); local [all...] |
H A D | InlineSpiller.cpp | 123 SibValueInfo(unsigned Reg, VNInfo *VNI) argument 125 SpillReg(Reg), SpillVNI(VNI), SpillMBB(nullptr), DefMI(nullptr) {} 164 bool isRegToSpill(unsigned Reg) { argument 166 RegsToSpill.end(), Reg) != RegsToSpill.end(); 169 bool isSibling(unsigned Reg); 181 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg); 187 void spillAroundUses(unsigned Reg); 212 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register, 214 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) { argument 217 if (MI->getOperand(0).getReg() == Reg) 228 unsigned Reg = Edit->getReg(); local 272 unsigned Reg = Edit->getReg(); local 314 isSibling(unsigned Reg) argument 513 unsigned Reg; local 656 unsigned Reg = RegsToSpill[i]; local 766 unsigned Reg = LI->reg; local 940 unsigned Reg = RegsToSpill[i]; local 954 unsigned Reg = RegsToSpill[i]; local 980 unsigned Reg = RegsToSpill[i]; local 1002 coalesceStackAccess(MachineInstr *MI, unsigned Reg) argument 1117 unsigned Reg = MO->getReg(); local 1206 spillAroundUses(unsigned Reg) argument [all...] |