/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 945 unsigned Shift = local 948 if (Shift != 0) 952 *CommentStream << '=' << (Val << Shift) << '\n';
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 408 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; local 409 EmitByte((Val >> Shift) & 0xff, OS); 1118 Binary <<= 7; // Shift amount is bits [11:7] 1119 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 937 bool Shift = false; local 955 Shift = true; 960 Shift = true; 970 if (Shift)
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGISel.cpp | 1897 unsigned Shift = 7; local 1901 Val |= (NextBits&127) << Shift; 1902 Shift += 7;
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H A D | TargetLowering.cpp | 983 SDValue Shift = In.getOperand(1); local 986 Shift = 1003 Shift)); 1676 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), local 1679 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); 1704 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, local 1707 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); 2623 // Shift the value upfront if it is even, so the LSB is one. 2685 // Shift right algebraic if shift value is nonzero 2725 unsigned Shift local 2854 SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT)); local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 75 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift); 76 bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift); 77 bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift); 78 bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) { argument 79 return SelectShiftedRegister(N, false, Reg, Shift); 81 bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) { argument 82 return SelectShiftedRegister(N, true, Reg, Shift); 166 SDValue &Shift); 227 /// Val set to the 12-bit value and Shift set to the shifter operand. 229 SDValue &Shift) { 228 SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift) argument 257 SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift) argument 318 SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg, SDValue &Shift) argument 535 SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift) argument [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 828 unsigned Shift = Log2_32(IVBump); local 830 // Generate NormR = LSR DistR, Shift. 835 .addImm(Shift);
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H A D | HexagonISelDAGToDAG.cpp | 982 SDValue Shift = N->getOperand(0); local 998 if (Shift.getNode()->getValueType(0) == MVT::i64) { 1000 if (Shift.getOpcode() != ISD::SRL) { 1004 SDValue ShiftOp0 = Shift.getOperand(0); 1005 SDValue ShiftOp1 = Shift.getOperand(1); 1007 // Shift by const 32
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 1956 unsigned Shift = 0; local 1961 Shift = countTrailingZeros<uint64_t>(Imm); 1962 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift; 1968 Shift = 32; 1976 if (!Shift) 1985 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
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H A D | PPCISelDAGToDAG.cpp | 104 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a 378 unsigned Shift = 32; local 382 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) 387 if (isShiftMask) Mask = Mask << Shift; 389 Indeterminant = ~(0xFFFFFFFFu << Shift); 392 if (isShiftMask) Mask = Mask >> Shift; 394 Indeterminant = ~(0xFFFFFFFFu >> Shift); 396 Shift = 32 - Shift; 937 unsigned Shift = 0; local [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 1049 SDValue Shift = Op.getOperand(2); local 1055 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); 1056 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); 1066 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift); 1068 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift); 1073 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); 1074 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); 1085 SDValue Shift = Op.getOperand(2); local 1093 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); 1094 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); 1372 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, local [all...] |
H A D | AMDGPUISelLowering.cpp | 1072 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32); local 1073 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift); 1823 SDValue Shift = DAG.getConstant(BitsDiff, VT); local 1824 // Shift left by 'Shift' bits. 1825 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift); 1826 // Signed shift Right by 'Shift' bits. 1827 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
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/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCasts.cpp | 493 Value *Shift = Builder->CreateLShr(A, Cst->getZExtValue()); 494 Shift->takeName(Src); 495 return CastInst::CreateIntegerCast(Shift, CI.getType(), false); 620 // Shift the bit we're testing down to the lsb. 1582 /// Shift is the number of bits between the lsb of V and the lsb of 1587 static bool CollectInsertionElements(Value *V, unsigned Shift, argument 1590 assert(isMultipleOfTypeSize(Shift, VecEltTy) && 1591 "Shift should be a multiple of the element type size"); 1604 unsigned ElementIndex = getTypeSizeIndex(Shift, VecEltTy); 1625 Shift, Element [all...] |
H A D | InstCombineCompares.cpp | 1186 BinaryOperator *Shift = dyn_cast<BinaryOperator>(LHSI->getOperand(0)); local 1187 if (Shift && !Shift->isShift()) 1188 Shift = nullptr; 1191 ShAmt = Shift ? dyn_cast<ConstantInt>(Shift->getOperand(1)) : nullptr; 1198 unsigned ShiftOpcode = Shift->getOpcode(); 1255 LHSI->setOperand(0, Shift->getOperand(0)); 1256 Worklist.Add(Shift); // Shift i [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | ScalarReplAggregates.cpp | 2354 uint64_t Shift = Layout->getElementOffsetInBits(i); local 2357 Shift = AllocaSizeBits-Shift-DL->getTypeAllocSizeInBits(FieldTy); 2360 if (Shift) { 2361 Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); 2394 uint64_t Shift; local 2397 Shift = AllocaSizeBits-ElementOffset; 2399 Shift = 0; 2406 if (Shift) { 2407 Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); 2498 uint64_t Shift; local [all...] |
/external/qemu/distrib/sdl-1.2.15/src/main/symbian/EKA2/ |
H A D | SDL_main.cpp | 82 const TWsEvent& Shift(); 130 const TWsEvent& CEventQueue::Shift() function in class:CEventQueue 132 const TWsEvent& event = iVector.Shift();
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 2622 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi. member in struct:InstructionTable 2626 { // ARM Opc S Shift Imm 2634 { // Thumb Opc S Shift Imm 2644 { // ARM Opc S Shift Imm 2652 { // Thumb Opc S Shift Imm 2682 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; local 2683 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) && 2694 bool ImmIsSO = (Shift != ARM_AM::no_shift); 2709 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; [all...] |
H A D | ARMISelDAGToDAG.cpp | 94 bool isShifterOpProfitable(const SDValue &Shift, 455 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift, argument 460 if (Shift.hasOneUse())
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 783 SDValue Shift, SDValue X, 785 if (Shift.getOpcode() != ISD::SRL || 786 !isa<ConstantSDNode>(Shift.getOperand(1)) || 787 !Shift.hasOneUse()) 790 int ScaleLog = 8 - Shift.getConstantOperandVal(1); 826 SDValue Shift, SDValue X, 828 if (Shift.getOpcode() != ISD::SHL || 829 !isa<ConstantSDNode>(Shift.getOperand(1))) 835 if (!N.hasOneUse() || !Shift.hasOneUse()) 839 unsigned ShiftAmt = Shift 781 FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 824 FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 891 FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 1250 SDValue Shift = N.getOperand(0); local [all...] |
/external/valgrind/main/VEX/priv/ |
H A D | host_arm64_defs.h | 662 } Shift; member in union:__anon31763::__anon31764
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/external/clang/lib/AST/ |
H A D | Expr.cpp | 867 int Shift = 28; local 868 while ((Char >> Shift) == 0) 869 Shift -= 4; 870 for (/**/; Shift >= 0; Shift -= 4) 871 OS << Hex[(Char >> Shift) & 15];
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/external/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 1765 Value *CodeGenFunction::EmitNeonRShiftImm(Value *Vec, Value *Shift, argument 1770 int ShiftAmt = cast<ConstantInt>(Shift)->getSExtValue(); 1786 Shift = ConstantInt::get(VTy->getElementType(), ShiftAmt); 1790 Shift = EmitNeonShiftVector(Shift, Ty, false); 1792 return Builder.CreateLShr(Vec, Shift, name); 1794 return Builder.CreateAShr(Vec, Shift, name);
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 662 unsigned Shift = ShiftedImm.ShiftAmount; local 664 if (Shift != 0 && Shift != 12) 813 template<int RegWidth, int Shift> 825 if (Value == 0 && Shift != 0) 828 return (Value & ~(0xffffULL << Shift)) == 0; 831 template<int RegWidth, int Shift> 848 return (Value & ~(0xffffULL << Shift)) == 0; 1045 unsigned Shift = getShiftExtendAmount(); local 1047 (Shift 1055 unsigned Shift = getShiftExtendAmount(); local 1065 unsigned Shift = getShiftExtendAmount(); local 1730 unsigned Shift = getShiftedImmShift(); local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 3633 // Shift the loaded value. 3641 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, local 3645 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3647 Val = Shift;
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 1381 auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1)); local 1382 if (!Shift) 1385 uint64_t Amount = Shift->getZExtValue(); 1942 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64, 1944 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
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