Searched defs:MBB (Results 101 - 125 of 191) sorted by relevance

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/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp128 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, argument
135 MachineBasicBlock::iterator I = MBB.end();
136 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
137 while (I != MBB.begin()) {
160 while (std::next(I) != MBB.end())
166 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
169 I = MBB.end();
170 UnCondBrIter = MBB.end();
186 if (AllowModify && UnCondBrIter != MBB.end() &&
187 MBB
231 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
281 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
351 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
389 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp106 // block MBB. IsImplicit says whether this is an explicit operand to the
109 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, argument
111 const TargetRegisterInfo *RI = MBB.getParent()->getTarget().getRegisterInfo();
113 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
117 MBB.addLiveIn(GPR64);
122 spillCalleeSavedRegisters(MachineBasicBlock &MBB, argument
129 MachineFunction &MF = *MBB.getParent();
133 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
174 MachineInstrBuilder MIB = BuildMI(MBB, MBB
211 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
282 emitIncrement(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, unsigned Reg, int64_t NumBytes, const TargetInstrInfo *TII) argument
311 MachineBasicBlock &MBB = MF.front(); local
499 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const argument
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H A DSystemZLongBranch.cpp273 MachineBasicBlock *MBB = MF->getBlockNumbered(I); local
277 Block.Alignment = MBB->getAlignment();
280 MachineBasicBlock::iterator MI = MBB->begin();
281 MachineBasicBlock::iterator End = MBB->end();
349 MachineBasicBlock *MBB = MI->getParent(); local
351 BuildMI(*MBB, MI, DL, TII->get(AddOpcode))
355 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
368 MachineBasicBlock *MBB = MI->getParent(); local
370 BuildMI(*MBB, MI, DL, TII->get(CompareOpcode))
373 MachineInstr *BRCL = BuildMI(*MBB, M
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/external/llvm/lib/Target/X86/
H A DX86CodeEmitter.cpp87 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
142 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
143 MBB != E; ++MBB) {
144 MCE.StartMachineBasicBlock(MBB);
145 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
259 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { argument
263 X86::reloc_pcrel_word, MBB));
H A DX86VZeroUpper.cpp45 void processBasicBlock(MachineBasicBlock &MBB);
47 MachineBasicBlock &MBB);
48 void addDirtySuccessor(MachineBasicBlock &MBB);
158 MachineBasicBlock &MBB) {
160 BuildMI(MBB, I, dl, TII->get(X86::VZEROUPPER));
165 // Add MBB to the DirtySuccessors list if it hasn't already been added.
166 void VZeroUpperInserter::addDirtySuccessor(MachineBasicBlock &MBB) { argument
167 if (!BlockStates[MBB.getNumber()].AddedToDirtySuccessors) {
168 DirtySuccessors.push_back(&MBB);
169 BlockStates[MBB
157 insertVZeroUpper(MachineBasicBlock::iterator I, MachineBasicBlock &MBB) argument
175 processBasicBlock(MachineBasicBlock &MBB) argument
292 MachineBasicBlock &MBB = *DirtySuccessors.back(); local
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/external/llvm/lib/Target/XCore/
H A DXCoreAsmPrinter.cpp204 MachineBasicBlock *MBB = JTBBs[i]; local
207 O << *MBB->getSymbol();
H A DXCoreInstrInfo.cpp170 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
194 XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, argument
199 MachineBasicBlock::iterator I = MBB.end();
200 if (I == MBB.begin())
204 if (I == MBB.begin())
215 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
238 if (SecondLastInst && I != MBB.begin() &&
282 XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, argument
294 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
298 BuildMI(&MBB, D
341 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
368 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
392 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
440 loadImmediate( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const argument
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H A DXCoreRegisterInfo.cpp65 MachineBasicBlock &MBB = *MI.getParent(); local
70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
98 MachineBasicBlock &MBB = *MI.getParent(); local
102 TII.loadImmediate(MBB, II, ScratchOffset, Offset);
106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
132 MachineBasicBlock &MBB local
166 MachineBasicBlock &MBB = *MI.getParent(); local
320 MachineBasicBlock &MBB = *MI.getParent(); local
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/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.cpp86 MachineBasicBlock &MBB) const {
87 while (iter != MBB.end()) {
100 MachineBasicBlock::iterator skipFlowControl(MachineBasicBlock *MBB) { argument
101 MachineBasicBlock::iterator tmp = MBB->end();
102 if (!MBB->size()) {
103 return MBB->end();
109 if (tmp == MBB->begin()) {
118 return MBB->end();
122 AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, argument
132 AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, argument
204 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600InstrInfo.cpp49 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
58 BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
163 findFirstPredicateSetterFrom(MachineBasicBlock &MBB, argument
166 while (I != MBB.begin()) {
177 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, argument
186 MachineBasicBlock::iterator I = MBB.end();
187 if (I == MBB.begin())
191 if (I == MBB.begin())
204 if (I == MBB
261 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
367 isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, unsigned ExtraPredCycles, const BranchProbability &Probability) const argument
387 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, const BranchProbability &Probability) const argument
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/external/llvm/include/llvm/CodeGen/
H A DMachineModuleInfo.h73 explicit LandingPadInfo(MachineBasicBlock *MBB) argument
74 : LandingPadBlock(MBB), LandingPadLabel(nullptr), Personality(nullptr) {}
/external/llvm/lib/CodeGen/
H A DMachineCSE.cpp37 "Number of cross-MBB physreg referencing CS eliminated");
81 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
86 const MachineBasicBlock *MBB,
97 void EnterScope(MachineBasicBlock *MBB);
98 void ExitScope(MachineBasicBlock *MBB);
99 bool ProcessBlock(MachineBasicBlock *MBB);
116 MachineBasicBlock *MBB) {
210 const MachineBasicBlock *MBB,
225 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
249 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB
115 PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB) argument
209 hasLivePhysRegDefUses(const MachineInstr *MI, const MachineBasicBlock *MBB, SmallSet<unsigned,8> &PhysRefs, SmallVectorImpl<unsigned> &PhysDefs, bool &PhysUseDef) const argument
268 const MachineBasicBlock *MBB = MI->getParent(); local
428 EnterScope(MachineBasicBlock *MBB) argument
434 ExitScope(MachineBasicBlock *MBB) argument
442 ProcessBlock(MachineBasicBlock *MBB) argument
652 MachineBasicBlock *MBB = Node->getBlock(); local
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H A DMachineSink.cpp81 bool ProcessBlock(MachineBasicBlock &MBB);
90 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
93 MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB,
96 MachineBasicBlock *MBB,
100 MachineBasicBlock *MBB);
115 MachineBasicBlock *MBB) {
148 MachineBasicBlock *MBB,
159 // BreakPHIEdge is true if all the uses are in the successor MBB being sunken
179 if (!(UseBlock == MBB && UseInst->isPHI() &&
203 if (!DT->dominates(MBB, UseBloc
114 PerformTrivialForwardCoalescing(MachineInstr *MI, MachineBasicBlock *MBB) argument
147 AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB, MachineBasicBlock *DefMBB, bool &BreakPHIEdge, bool &LocalUse) const argument
242 ProcessBlock(MachineBasicBlock &MBB) argument
440 isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, MachineBasicBlock *MBB, MachineBasicBlock *SuccToSinkTo) argument
476 FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB, bool &BreakPHIEdge) argument
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H A DPHIElimination.cpp68 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
69 void LowerPHINode(MachineBasicBlock &MBB,
81 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
86 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB);
87 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB);
183 MachineBasicBlock &MBB) {
184 if (MBB.empty() || !MBB.front().isPHI())
190 std::prev(MBB.SkipPHIsAndLabels(MBB
182 EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) argument
221 LowerPHINode(MachineBasicBlock &MBB, MachineBasicBlock::iterator LastPHIIt) argument
545 SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB, MachineLoopInfo *MLI) argument
621 isLiveIn(unsigned Reg, MachineBasicBlock *MBB) argument
630 isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) argument
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H A DPrologEpilogInserter.cpp81 bool PEI::isReturnBlock(MachineBasicBlock* MBB) { argument
82 return (MBB && !MBB->empty() && MBB->back().isReturn());
97 for (MachineFunction::iterator MBB = Fn.begin(), E = Fn.end();
98 MBB != E; ++MBB)
99 if (isReturnBlock(MBB))
100 ReturnBlocks.push_back(MBB);
363 MachineBasicBlock *MBB local
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp182 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB); local
183 MBBMap[BB] = MBB;
184 MF->push_back(MBB);
190 MBB->setHasAddressTaken();
213 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
445 MachineBasicBlock *MBB) {
451 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
468 MMI->addCatchTypeInfo(MBB, TyInfo);
474 MMI->addCleanup(MBB);
480 MMI->addFilterTypeInfo(MBB, TyInf
444 AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI, MachineBasicBlock *MBB) argument
498 AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI, MachineBasicBlock *MBB) argument
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/external/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp131 bool runOnBasicBlock(MachineBasicBlock &MBB);
132 bool colorChainSet(std::vector<Chain*> GV, MachineBasicBlock &MBB,
134 bool colorChain(Chain *G, Color C, MachineBasicBlock &MBB);
135 int scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB);
304 for (auto &MBB : F) {
305 Changed |= runOnBasicBlock(MBB);
311 bool AArch64A57FPLoadBalancing::runOnBasicBlock(MachineBasicBlock &MBB) { argument
313 DEBUG(dbgs() << "Running on MBB: " << MBB << " - scanning instructions...\n");
323 for (auto &MI : MBB)
419 colorChainSet(std::vector<Chain*> GV, MachineBasicBlock &MBB, int &Parity) argument
502 colorChain(Chain *G, Color C, MachineBasicBlock &MBB) argument
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H A DAArch64ConditionalCompares.cpp182 /// Find the compare instruction in MBB that controls the conditional branch.
184 MachineInstr *findConvertibleCompare(MachineBasicBlock *MBB);
186 /// Return true if all non-terminator instructions in MBB can be safely
188 bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
199 /// If the sub-CFG headed by MBB can be cmp-converted, initialize the
201 bool canConvert(MachineBasicBlock *MBB);
220 // PHI operands come in (VReg, MBB) pairs.
222 MachineBasicBlock *MBB = I.getOperand(oi + 1).getMBB(); local
224 if (MBB == Head) {
228 if (MBB
298 findConvertibleCompare(MachineBasicBlock *MBB) argument
380 canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI) argument
436 canConvert(MachineBasicBlock *MBB) argument
878 tryConvert(MachineBasicBlock *MBB) argument
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H A DAArch64LoadStoreOptimizer.cpp61 // Return the matching instruction if one is found, else MBB->end().
99 bool optimizeBlock(MachineBasicBlock &MBB);
746 bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB) { argument
764 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
832 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
910 TII->getRegClass(MI->getDesc(), 0, TRI, *(MBB.getParent()))
938 for (auto &MBB : Fn)
939 Modified |= optimizeBlock(MBB);
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/external/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp64 unsigned createDupLane(MachineBasicBlock &MBB,
70 unsigned createExtractSubreg(MachineBasicBlock &MBB,
76 unsigned createVExt(MachineBasicBlock &MBB,
81 unsigned createRegSequence(MachineBasicBlock &MBB,
86 unsigned createInsertSubreg(MachineBasicBlock &MBB,
91 unsigned createImplicitDef(MachineBasicBlock &MBB,
425 A15SDOptimizer::createDupLane(MachineBasicBlock &MBB, argument
431 AddDefaultPred(BuildMI(MBB,
444 A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB, argument
450 BuildMI(MBB,
461 createRegSequence(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Reg1, unsigned Reg2) argument
480 createVExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Ssub0, unsigned Ssub1) argument
496 createInsertSubreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned DReg, unsigned Lane, unsigned ToInsert) argument
513 createImplicitDef(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL) argument
531 MachineBasicBlock &MBB = *MI->getParent(); local
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H A DMLxExpansionPass.cpp68 void ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
71 bool ExpandFPMLxInstructions(MachineBasicBlock &MBB);
94 MachineBasicBlock *MBB = MI->getParent();
97 if (DefMI->getParent() != MBB)
123 MachineBasicBlock *MBB = MI->getParent();
125 if (UseMI->getParent() != MBB)
134 if (UseMI->getParent() != MBB)
142 /// a single-MBB loop.
148 MachineBasicBlock *MBB = MI->getParent();
152 if (DefMI->getParent() != MBB)
272 ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned MulOpc, unsigned AddSubOpc, bool NegAcc, bool HasLane) argument
328 ExpandFPMLxInstructions(MachineBasicBlock &MBB) argument
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/external/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp381 MachineBasicBlock* MBB = MBBb; local
384 << MBB->getNumber() << "\n");
385 DEBUG(MBB->dump());
403 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
437 //if(LVs.isLiveOut(predReg, *MBB)) break;
445 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
446 SIE = MBB->succ_end(); SI != SIE; ++SI) {
595 MBB->splice(jmpPos, MI->getParent(), MI);
596 MBB
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/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp64 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
87 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
97 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, argument
102 if (I != MBB.end()) DL = I->getDebugLoc();
103 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
108 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
114 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, argument
118 if (I != MBB.end()) DL = I->getDebugLoc();
119 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
125 BuildMI(MBB,
130 MachineBasicBlock &MBB = *MI->getParent(); local
197 makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
227 restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
263 adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Reg1, unsigned Reg2) const argument
290 adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
297 adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
309 loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, DebugLoc DL, unsigned &NewImm) const argument
439 ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opc) const argument
453 BuildAddiuSpImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const argument
[all...]
H A DMipsSEFrameLowering.cpp58 bool expandInstr(MachineBasicBlock &MBB, Iter I);
59 void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
60 void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
61 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
62 void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
64 bool expandCopy(MachineBasicBlock &MBB, Iter I);
65 bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
87 bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) { argument
90 expandLoadCCond(MBB, I);
93 expandStoreCCond(MBB,
123 expandLoadCCond(MachineBasicBlock &MBB, Iter I) argument
143 expandStoreCCond(MachineBasicBlock &MBB, Iter I) argument
163 expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize) argument
192 expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc, unsigned MFLoOpc, unsigned RegSize) argument
220 expandCopy(MachineBasicBlock &MBB, Iter I) argument
230 expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc, unsigned MFLoOpc) argument
276 MachineBasicBlock &MBB = MF.front(); local
449 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
493 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
[all...]
/external/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.cpp90 MachineBasicBlock &MBB) const {
91 while (iter != MBB.end()) {
106 AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, argument
116 AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, argument
125 MachineBasicBlock *MBB = MI->getParent(); local
141 buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
144 buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
156 buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
159 buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(),
167 MBB
235 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const argument
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