Searched refs:Reg (Results 226 - 250 of 321) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp153 unsigned Reg = II->getOperand(i).getReg(); local
158 if (localBegin->modifiesRegister(Reg, TRI) ||
159 localBegin->readsRegister(Reg, TRI))
H A DHexagonISelLowering.cpp191 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
205 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
206 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
216 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
217 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
262 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
263 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
277 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
278 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocV
720 unsigned Reg = local
987 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); local
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.h32 /// CreateLiveInRegister - Helper function that adds Reg to the LiveIn list
34 /// Reg.
36 unsigned Reg, EVT VT) const;
H A DAMDGPUInstrInfo.cpp165 unsigned Reg, bool UnfoldLoad,
164 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
H A DAMDGPUInstrInfo.h102 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
/external/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h209 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
211 void eraseVirtReg(unsigned Reg);
H A DSelectionDAG.h474 SDValue getRegister(unsigned Reg, EVT VT);
486 SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N) { argument
488 getRegister(Reg, N.getValueType()), N);
494 SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N, argument
497 SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };
502 // Similar to last getCopyToReg() except parameter Reg is a SDValue
503 SDValue getCopyToReg(SDValue Chain, SDLoc dl, SDValue Reg, SDValue N, argument
506 SDValue Ops[] = { Chain, Reg, N, Glue };
511 SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) { argument
513 SDValue Ops[] = { Chain, getRegister(Reg, V
520 getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT, SDValue Glue) argument
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/external/llvm/lib/CodeGen/
H A DExecutionDepsFix.cpp172 int regIndex(unsigned Reg);
205 int ExeDepsFix::regIndex(unsigned Reg) { argument
206 assert(Reg < AliasMap.size() && "Invalid register");
207 return AliasMap[Reg];
H A DTargetInstrInfo.cpp608 unsigned Reg = MO.getReg(); local
609 if (Reg == 0)
613 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
618 if (!MRI.isConstantPhysReg(Reg, MF))
629 if (MO.isDef() && Reg != DefReg)
/external/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.h116 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
H A DSIInstrInfo.cpp395 unsigned Reg = MI->getOperand(1).getReg(); local
398 MI->getOperand(2).ChangeToRegister(Reg, false);
586 unsigned Reg = MI->getOperand(i).getReg(); local
587 if (TargetRegisterInfo::isVirtualRegister(Reg))
591 if (!RC->contains(Reg)) {
772 unsigned Reg = MRI.createVirtualRegister(VRC); local
774 Reg).addOperand(MO);
775 MO.ChangeToRegister(Reg, false);
1205 unsigned Reg = Inst->getOperand(0).getReg(); local
1209 MRI.getRegClass(Reg),
1527 unsigned Reg = NewDesc.ImplicitUses[i]; local
1534 unsigned Reg = NewDesc.ImplicitDefs[i]; local
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/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.h32 /// CreateLiveInRegister - Helper function that adds Reg to the LiveIn list
34 /// Reg.
36 unsigned Reg, EVT VT) const;
H A DAMDGPUInstrInfo.cpp165 unsigned Reg, bool UnfoldLoad,
164 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
H A DAMDGPUInstrInfo.h102 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
/external/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp107 unsigned Reg) const {
110 switch (Reg) {
H A DAArch64LoadStoreOptimizer.cpp349 unsigned Reg = MO.getReg(); local
351 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
354 assert(MO.isUse() && "Reg operand not a def and not a use?!?");
355 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
395 unsigned Reg = FirstMI->getOperand(0).getReg(); local
465 if (MayLoad && Reg == MI->getOperand(0).getReg()) {
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp60 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
71 if (unsigned Reg = State.AllocateReg(RegList, 6))
72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
92 unsigned Reg = 0; local
96 Reg = SP::I0 + Offset/8;
99 Reg = SP::D0 + Offset/8;
102 Reg = SP::F1 + Offset/4;
105 Reg = SP::Q0 + Offset/16;
108 if (Reg) {
141 unsigned Reg = SP::I0 + Offset/8; local
163 toCallerWindow(unsigned Reg) argument
221 unsigned Reg = SFI->getSRetReturnReg(); local
486 unsigned Reg = SFI->getSRetReturnReg(); local
887 unsigned Reg = toCallerWindow(RegsToPass[i].first); local
1271 unsigned Reg = toCallerWindow(VA.getLocReg()); local
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/external/llvm/tools/llvm-readobj/
H A DWin64EHDumper.cpp73 static StringRef getUnwindRegisterName(uint8_t Reg) { argument
74 switch (Reg) {
/external/llvm/utils/TableGen/
H A DAsmWriterEmitter.cpp529 const CodeGenRegister &Reg = *Registers[i]; local
535 AsmName = Reg.TheDef->getValueAsString("AsmName");
537 AsmName = Reg.getName();
541 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
551 Reg.TheDef->getValueAsListOfStrings("AltNames");
553 PrintFatalError(Reg.TheDef->getLoc(),
H A DDAGISelMatcherEmitter.cpp455 const CodeGenRegister *Reg = Matcher->getReg(); local
458 if (Reg && Reg->EnumValue > 255) {
460 OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
464 if (Reg) {
465 OS << getQualifiedName(Reg->TheDef) << ",\n";
/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp71 unsigned Reg; member in union:__anon26084::Address::__anon26086
80 Base.Reg = 0;
382 if (Addr.Base.Reg == 0)
383 Addr.Base.Reg = getRegForValue(Obj);
387 if (Addr.Base.Reg != 0)
388 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
390 return Addr.Base.Reg != 0;
410 Addr.Base.Reg = ResultReg;
507 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
531 .addReg(Addr.Base.Reg)
1554 unsigned Reg = getRegForValue(RV); local
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/external/valgrind/main/VEX/priv/
H A Dhost_x86_defs.c252 op->Xrmi.Reg.reg = reg;
268 ppHRegX86(op->Xrmi.Reg.reg);
286 addHRegUse(u, HRmRead, op->Xrmi.Reg.reg);
301 op->Xrmi.Reg.reg = lookupHRegRemap(m, op->Xrmi.Reg.reg);
323 op->Xri.Reg.reg = reg;
333 ppHRegX86(op->Xri.Reg.reg);
348 addHRegUse(u, HRmRead, op->Xri.Reg.reg);
360 op->Xri.Reg.reg = lookupHRegRemap(m, op->Xri.Reg
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/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp98 void setBaseReg(SDValue Reg) { argument
100 Base_Reg = Reg;
1106 SDValue Reg; local
1113 Reg = MulVal.getNode()->getOperand(0);
1118 Reg = N.getNode()->getOperand(0);
1120 Reg = N.getNode()->getOperand(0);
1123 AM.IndexReg = AM.Base_Reg = Reg;
2585 SDValue Reg = N0.getNode()->getOperand(0); local
2596 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2597 Reg
2621 SDValue Reg = N0.getNode()->getOperand(0); local
2657 SDValue Reg = N0.getNode()->getOperand(0); local
2679 SDValue Reg = N0.getNode()->getOperand(0); local
[all...]
/external/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp356 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, argument
360 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
361 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
362 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
363 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
365 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
366 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
367 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
368 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
371 D0 = TRI->getSubReg(Reg, AR
[all...]
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DProgramState.h337 bool isTainted(const MemRegion *Reg, TaintTagType Kind=TaintTagGeneric) const;
340 DynamicTypeInfo getDynamicTypeInfo(const MemRegion *Reg) const;
343 ProgramStateRef setDynamicTypeInfo(const MemRegion *Reg,
347 ProgramStateRef setDynamicTypeInfo(const MemRegion *Reg, argument
350 return setDynamicTypeInfo(Reg, DynamicTypeInfo(NewTy, CanBeSubClassed));

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