Searched refs:UseMI (Results 1 - 25 of 36) sorted by relevance

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/external/llvm/lib/Target/Mips/
H A DMips16RegisterInfo.h34 MachineBasicBlock::iterator &UseMI,
H A DMips16RegisterInfo.cpp64 MachineBasicBlock::iterator &UseMI,
70 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
61 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const argument
/external/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp168 MachineInstr *DefMI = nullptr, *UseMI = nullptr; local
180 if (UseMI && UseMI != MI)
185 UseMI = MI;
188 if (!DefMI || !UseMI)
195 LIS.getInstructionIndex(UseMI)))
199 // Assume there are stores between DefMI and UseMI.
205 << " into single use: " << *UseMI); local
208 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
211 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Op
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H A DTargetSchedule.cpp157 const MachineInstr *UseMI, unsigned UseOperIdx) const {
164 if (UseMI) {
166 UseMI, UseOperIdx);
196 if (!UseMI)
200 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
203 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
155 computeOperandLatency( const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const argument
H A DOptimizePHIs.cpp146 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
147 if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle))
H A DRegisterScavenging.cpp282 /// longest after StargMII. UseMI is set to the instruction where the search
290 MachineBasicBlock::iterator &UseMI) {
348 UseMI = RestorePointMI;
387 MachineBasicBlock::iterator UseMI; local
388 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
413 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
425 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
427 II = std::prev(UseMI);
433 Scavenged[SI].Restore = std::prev(UseMI);
287 findSurvivorReg(MachineBasicBlock::iterator StartMI, BitVector &Candidates, unsigned InstrLimit, MachineBasicBlock::iterator &UseMI) argument
H A DMachineTraceMetrics.cpp636 // Get the input data dependencies that must be ready before UseMI can issue.
637 // Return true if UseMI has any physreg operands.
638 static bool getDataDeps(const MachineInstr *UseMI,
642 for (ConstMIOperands MO(UseMI); MO.isValid(); ++MO) {
662 static void getPHIDeps(const MachineInstr *UseMI,
669 assert(UseMI->isPHI() && UseMI->getNumOperands() % 2 && "Bad PHI");
670 for (unsigned i = 1; i != UseMI->getNumOperands(); i += 2) {
671 if (UseMI->getOperand(i + 1).getMBB() == Pred) {
672 unsigned Reg = UseMI
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H A DRegisterCoalescer.cpp625 MachineInstr *UseMI = MO.getParent(); local
626 unsigned OpNo = &MO - &UseMI->getOperand(0);
627 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
632 if (UseMI->isRegTiedToDefOperand(OpNo))
671 MachineInstr *UseMI = UseMO.getParent(); local
673 if (UseMI->isDebugValue()) {
679 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
689 if (UseMI == CopyMI)
691 if (!UseMI->isCopy())
693 if (UseMI
703 DEBUG(dbgs() << "\\t\\tnoop: " << DefIdx << '\\t' << *UseMI); local
962 MachineInstr *UseMI = &*(I++); local
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H A DMachineSSAUpdater.cpp223 MachineInstr *UseMI = U.getParent(); local
225 if (UseMI->isPHI()) {
226 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U);
229 NewVR = GetValueInMiddleOfBlock(UseMI->getParent());
H A DPeepholeOptimizer.cpp306 MachineInstr *UseMI = UseMO.getParent(); local
307 if (UseMI == MI)
310 if (UseMI->isPHI()) {
336 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
339 MachineBasicBlock *UseMBB = UseMI->getParent();
342 if (!LocalMIs.count(UseMI))
380 MachineInstr *UseMI = UseMO->getParent(); local
381 MachineBasicBlock *UseMBB = UseMI->getParent();
392 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI
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H A DMachineLICM.cpp984 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
986 if (UseMI.isPHI()) {
989 if (CurLoop->contains(&UseMI))
994 if (isExitBlock(UseMI.getParent()))
999 if (UseMI.isCopy() && CurLoop->contains(&UseMI))
1000 Work.push_back(&UseMI);
1015 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
1016 if (UseMI.isCopyLike())
1018 if (!CurLoop->contains(UseMI
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H A DTailDuplication.cpp270 MachineInstr *UseMI = UseMO.getParent(); local
272 if (UseMI->isDebugValue()) {
277 UseMI->eraseFromParent();
280 if (UseMI->getParent() == DefBB && !UseMI->isPHI())
345 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
346 if (UseMI.isDebugValue())
348 if (UseMI.getParent() != BB)
H A DMachineRegisterInfo.cpp428 MachineInstr *UseMI = &*I; local
429 if (UseMI->isDebugValue())
430 UseMI->getOperand(0).setReg(0U);
H A DTwoAddressInstructionPass.cpp459 MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg);
460 if (UseMI.getParent() != MBB)
464 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
466 return &UseMI;
469 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
471 return &UseMI;
667 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
669 if (IsCopy && !Processed.insert(UseMI))
672 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
H A DTargetInstrInfo.cpp787 /// Both DefMI and UseMI must be valid. By default, call directly to the
792 const MachineInstr *UseMI, unsigned UseIdx) const {
794 unsigned UseClass = UseMI->getDesc().getSchedClass();
816 /// dependent def and use when the operand indices are already known. UseMI may
829 const MachineInstr *UseMI, unsigned UseIdx) const {
838 if (UseMI)
839 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
790 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
827 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
/external/llvm/lib/Target/ARM/
H A DThumb1RegisterInfo.h54 MachineBasicBlock::iterator &UseMI,
H A DMLxExpansionPass.cpp124 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); local
125 if (UseMI->getParent() != MBB)
128 while (UseMI->isCopy() || UseMI->isInsertSubreg()) {
129 Reg = UseMI->getOperand(0).getReg();
133 UseMI = &*MRI->use_instr_nodbg_begin(Reg);
134 if (UseMI->getParent() != MBB)
H A DARMBaseInstrInfo.h209 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
217 const MachineInstr *UseMI,
279 const MachineInstr *UseMI,
H A DARMBaseInstrInfo.cpp2490 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, argument
2514 const MCInstrDesc &UseMCID = UseMI->getDesc();
2517 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2523 unsigned UseOpc = UseMI->getOpcode();
2538 Commute = UseMI->getOperand(2).getReg() != Reg;
2590 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2591 bool isKill = UseMI->getOperand(OpIdx).isKill();
2593 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2594 UseMI, UseMI
3497 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
3891 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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H A DThumb1RegisterInfo.cpp507 MachineBasicBlock::iterator &UseMI,
521 // The UseMI is where we would like to restore the register. If there's
523 // before that instead and adjust the UseMI.
525 for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
532 UseMI = II;
540 UseMI = II;
547 AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
/external/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h151 /// when the operand indices are already known. UseMI may be NULL for an
154 const MachineInstr *UseMI, unsigned UseOperIdx)
H A DRegisterScavenging.h195 /// longest after StartMI. UseMI is set to the instruction where the search
202 MachineBasicBlock::iterator &UseMI);
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp110 const MachineInstr *UseMI,
113 UseMI, UseIdx);
130 if (UseMI->isBranch() && IsRegCR) {
992 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, argument
1008 const MCInstrDesc &UseMCID = UseMI->getDesc();
1015 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
1016 if (UseMI->getOperand(UseIdx).isReg() &&
1017 UseMI->getOperand(UseIdx).getReg() == Reg)
1020 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
108 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
1375 MachineInstr *UseMI = &*I; local
1509 MachineInstr *UseMI = &*I; local
1775 MachineInstr *UseMI = UseMO.getParent(); local
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H A DPPCInstrInfo.h100 const MachineInstr *UseMI,
169 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h817 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, argument
851 const MachineInstr *UseMI,
858 const MachineInstr *UseMI, unsigned UseIdx)
893 const MachineInstr *UseMI, unsigned UseIdx) const {
890 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument

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