| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.h | 58 /// isStoreToStackSlot - If the specified machine instruction is a direct
63 unsigned isStoreToStackSlot(const MachineInstr *MI,
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| H A D | SparcInstrInfo.cpp | 61 /// isStoreToStackSlot - If the specified machine instruction is a direct
66 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:SparcInstrInfo
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.h | 45 /// isStoreToStackSlot - If the specified machine instruction is a direct
50 unsigned isStoreToStackSlot(const MachineInstr *MI,
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| H A D | XCoreInstrInfo.cpp | 79 /// isStoreToStackSlot - If the specified machine instruction is a direct
85 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:XCoreInstrInfo
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.h | 39 /// isStoreToStackSlot - If the specified machine instruction is a direct
44 unsigned isStoreToStackSlot(const MachineInstr *MI,
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| H A D | Mips16InstrInfo.h | 38 /// isStoreToStackSlot - If the specified machine instruction is a direct
43 unsigned isStoreToStackSlot(const MachineInstr *MI,
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| H A D | Mips16InstrInfo.cpp | 53 /// isStoreToStackSlot - If the specified machine instruction is a direct
59 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const function in class:Mips16InstrInfo
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| H A D | MipsSEInstrInfo.cpp | 60 /// isStoreToStackSlot - If the specified machine instruction is a direct
66 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const function in class:MipsSEInstrInfo
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 56 unsigned isStoreToStackSlot(const MachineInstr *MI,
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| H A D | AArch64InstrInfo.cpp | 1066 unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:AArch64InstrInfo
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 53 /// isStoreToStackSlot - If the specified machine instruction is a direct
58 unsigned isStoreToStackSlot(const MachineInstr *MI,
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| H A D | HexagonInstrInfo.cpp | 97 /// isStoreToStackSlot - If the specified machine instruction is a direct
102 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:HexagonInstrInfo
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 114 unsigned isStoreToStackSlot(const MachineInstr *MI,
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| H A D | PPCInstrInfo.cpp | 199 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:PPCInstrInfo
779 // update isStoreToStackSlot.
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| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.h | 139 unsigned isStoreToStackSlot(const MachineInstr *MI,
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| H A D | SystemZInstrInfo.cpp | 211 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:SystemZInstrInfo
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| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 195 unsigned isStoreToStackSlot(const MachineInstr *MI,
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| H A D | X86InstrInfo.cpp | 1609 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:X86InstrInfo
1622 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
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| /external/llvm/lib/CodeGen/ |
| H A D | InlineSpiller.cpp | 258 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
803 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
1007 InstrReg = TII.isStoreToStackSlot(MI, FI);
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| H A D | StackSlotColoring.cpp | 395 if (!(StoreReg = TII->isStoreToStackSlot(NextMI, SecondSS))) continue;
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| /external/llvm/include/llvm/Target/ |
| H A D | TargetInstrInfo.h | 150 /// isStoreToStackSlot - If the specified machine instruction is a direct
155 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, function in class:llvm::TargetInstrInfo
171 /// reference. If not, return false. Unlike isStoreToStackSlot,
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 100 unsigned isStoreToStackSlot(const MachineInstr *MI,
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| H A D | ARMBaseInstrInfo.cpp | 932 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:ARMBaseInstrInfo
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