Searched refs:DestReg (Results 51 - 75 of 84) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp437 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
449 unsigned DestReg = MI.getOperand(0).getReg(); local
450 assert(MI.definesRegister(DestReg) &&
458 if (DestReg != PPC::CR0) {
462 unsigned ShiftBits = getEncodingValue(DestReg)*4;
469 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
553 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
565 unsigned DestReg = MI.getOperand(0).getReg(); local
566 assert(MI.definesRegister(DestReg) &&
572 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
634 unsigned DestReg = MI.getOperand(0).getReg(); local
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H A DPPCFastISel.cpp144 bool isZExt, unsigned DestReg);
153 unsigned DestReg, bool IsZExt);
734 bool IsZExt, unsigned DestReg) {
818 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
821 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
859 unsigned DestReg = createResultReg(&PPC::F4RCRegClass); local
860 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg)
863 UpdateValueMap(I, DestReg);
970 unsigned DestReg = createResultReg(RC); local
979 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
733 PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2, bool IsZExt, unsigned DestReg) argument
1063 unsigned DestReg = createResultReg(&PPC::F8RCRegClass); local
1624 PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1822 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); local
1867 unsigned DestReg = createResultReg(RC); local
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/external/llvm/lib/CodeGen/
H A DPHIElimination.cpp231 unsigned DestReg = MPhi->getOperand(0).getReg(); local
248 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
260 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
264 TII->get(TargetOpcode::COPY), DestReg)
302 LV->addVirtualRegisterDead(DestReg, PHICopy);
303 LV->removeVirtualRegisterDead(DestReg, MPhi);
326 LiveInterval &DestLI = LIS->getInterval(DestReg);
341 // instruction from DestReg's live interval.
H A DLiveRangeEdit.cpp150 unsigned DestReg,
155 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
148 rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &tri, bool Late) argument
H A DTargetInstrInfo.cpp316 unsigned DestReg,
321 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
314 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600InstrInfo.h45 unsigned DestReg, unsigned SrcReg,
H A DAMDGPUInstrInfo.cpp134 unsigned DestReg, int FrameIndex,
132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600InstrInfo.h45 unsigned DestReg, unsigned SrcReg,
H A DAMDGPUInstrInfo.cpp134 unsigned DestReg, int FrameIndex,
132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/R600/
H A DSIInstrInfo.cpp38 unsigned DestReg, unsigned SrcReg,
44 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
73 if (AMDGPU::M0 == DestReg) {
93 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
95 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
99 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
101 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
105 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
110 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
115 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
36 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
239 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A DR600InstrInfo.cpp51 unsigned DestReg, unsigned SrcReg,
54 if ((AMDGPU::R600_Reg128RegClass.contains(DestReg) ||
55 AMDGPU::R600_Reg128VerticalRegClass.contains(DestReg)) &&
59 } else if((AMDGPU::R600_Reg64RegClass.contains(DestReg) ||
60 AMDGPU::R600_Reg64VerticalRegClass.contains(DestReg)) &&
70 RI.getSubReg(DestReg, SubRegIndex),
72 .addReg(DestReg,
77 DestReg, SrcReg);
49 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
H A DAMDGPUInstrInfo.cpp118 unsigned DestReg, int FrameIndex,
116 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DR600InstrInfo.h66 unsigned DestReg, unsigned SrcReg,
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); local
117 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
118 VRBase = DestReg;
120 } else if (DestReg != SrcReg)
473 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
474 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
475 VRBase = DestReg;
892 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
893 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
897 DestReg)
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H A DFunctionLoweringInfo.cpp322 unsigned DestReg = ValueMap[PN]; local
323 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
325 LiveOutRegInfo.grow(DestReg);
326 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp484 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); local
486 TII.get(Opc), DestReg).addImm(Imm));
487 return DestReg;
500 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); local
505 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
508 return DestReg;
549 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); local
561 TII.get(ARM::t2LDRpci), DestReg)
565 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg,
584 unsigned DestReg = createResultReg(RC); local
1498 unsigned DestReg = createResultReg(RC); local
2499 unsigned DestReg; local
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H A DARMBaseRegisterInfo.h171 DebugLoc dl, unsigned DestReg, unsigned SubIdx,
H A DARMBaseRegisterInfo.cpp401 unsigned DestReg, unsigned SubIdx, int Val,
412 .addReg(DestReg, getDefRegState(true), SubIdx)
398 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h215 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
219 unsigned DestReg, unsigned SubIdx,
516 unsigned DestReg, unsigned SrcReg,
541 unsigned DestReg, int FrameIndex,
514 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
539 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h187 /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
193 unsigned DestReg,
/external/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp646 unsigned DestReg = MemMI->getOperand(0).getReg(); local
653 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
701 unsigned DestReg = MemMI->getOperand(0).getReg(); local
712 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
H A DAArch64ConditionalCompares.cpp595 unsigned DestReg = local
599 .addReg(DestReg, RegState::Define | RegState::Dead)
H A DAArch64FastISel.cpp1599 unsigned DestReg = VA.getLocReg(); local
1601 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1632 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
/external/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp774 unsigned RdhwrOpc, DestReg; local
778 DestReg = Mips::V1;
781 DestReg = Mips::V1_64;
788 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
790 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1809 unsigned DestReg, unsigned SubIdx,
1825 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
3026 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, argument
3029 // SrcReg(VR128) -> DestReg(GR64)
3030 // SrcReg(VR64) -> DestReg(GR64)
3031 // SrcReg(GR64) -> DestReg(VR128)
3032 // SrcReg(GR64) -> DestReg(VR64)
3036 if (X86::GR64RegClass.contains(DestReg)) {
3046 if (X86::VR128XRegClass.contains(DestReg))
3050 if (X86::VR64RegClass.contains(DestReg))
1807 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
3073 copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) argument
3101 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
3274 getLoadRegOpcode(unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) argument
3320 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
3335 loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
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