Searched refs:DestReg (Results 1 - 25 of 84) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
H A DHexagonSplitConst32AndConst64.cpp89 int DestReg = MI->getOperand(0).getReg(); local
93 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
95 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
102 int DestReg = MI->getOperand(0).getReg(); local
106 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
108 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
115 int DestReg = MI->getOperand(0).getReg(); local
119 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
121 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
128 int DestReg local
139 int DestReg = MI->getOperand(0).getReg(); local
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H A DHexagonSplitTFRCondSets.cpp98 int DestReg = MI->getOperand(0).getReg(); local
114 if (DestReg != SrcReg1) {
116 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
118 if (DestReg != SrcReg2) {
120 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
128 int DestReg = MI->getOperand(0).getReg(); local
133 if (DestReg != SrcReg1) {
135 TII->get(Hexagon::TFR_cPt), DestReg).
140 TII->get(Hexagon::TFRI_cNotPt), DestReg).
145 TII->get(Hexagon::TFRI_cNotPt_f), DestReg)
156 int DestReg = MI->getOperand(0).getReg(); local
184 int DestReg = MI->getOperand(0).getReg(); local
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/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp42 unsigned DestReg, unsigned SrcReg,
44 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
80 unsigned DestReg, int FI,
84 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
85 isARMLowRegister(DestReg))) && "Unknown regclass!");
88 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
89 isARMLowRegister(DestReg))) {
100 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
40 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
79 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DThumb1InstrInfo.h43 unsigned DestReg, unsigned SrcReg,
53 unsigned DestReg, int FrameIndex,
H A DThumb2RegisterInfo.cpp38 unsigned DestReg, unsigned SubIdx,
50 .addReg(DestReg, getDefRegState(true), SubIdx)
35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DThumb2RegisterInfo.h32 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
H A DThumb2InstrInfo.cpp115 unsigned DestReg, unsigned SrcReg,
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
119 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
170 unsigned DestReg, int FI,
186 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
204 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
113 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
169 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
212 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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H A DThumb1RegisterInfo.cpp65 unsigned DestReg, unsigned SubIdx,
77 .addReg(DestReg, getDefRegState(true), SubIdx)
91 unsigned DestReg, unsigned BaseReg,
97 bool isHigh = !isARMLowRegister(DestReg) ||
108 unsigned LdReg = DestReg;
109 if (DestReg == ARM::SP) {
129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
132 if (DestReg == ARM::SP || isSub)
168 unsigned DestReg, unsigned BaseReg,
184 if (DestReg
62 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
88 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
165 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument
299 emitThumbConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, const Thumb1RegisterInfo& MRI, DebugLoc dl) argument
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H A DThumb2InstrInfo.h44 unsigned DestReg, unsigned SrcReg,
55 unsigned DestReg, int FrameIndex,
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
37 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
H A DSIInstrInfo.h35 unsigned DestReg, unsigned SrcReg,
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
37 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
H A DSIInstrInfo.h35 unsigned DestReg, unsigned SrcReg,
/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp37 unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
39 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
46 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
49 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
52 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
55 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
58 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
61 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
69 unsigned &DestReg) const {
84 DestReg
35 copyPhysReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
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H A DNVPTXInstrInfo.h48 * unsigned DestReg, int FrameIndex,
54 unsigned DestReg, unsigned SrcReg, bool KillSrc) const override;
56 unsigned &DestReg) const;
/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.h57 unsigned DestReg, unsigned SrcReg,
68 unsigned DestReg, int FrameIdx,
/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.h80 unsigned DestReg, unsigned SrcReg,
91 unsigned DestReg, int FrameIndex,
H A DSparcInstrInfo.cpp283 unsigned DestReg, unsigned SrcReg,
295 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
296 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
298 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
299 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
301 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
303 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
311 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
314 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
338 unsigned Dst = TRI->getSubReg(DestReg, subRegId
281 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
389 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.h67 unsigned DestReg, unsigned SrcReg,
78 unsigned DestReg, int FrameIndex,
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1267 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg,
1271 return ((DestReg - SrcReg) & 0x1f) < NumRegs;
1276 unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode,
1281 uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
1294 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
1302 unsigned DestReg, unsigned SrcReg,
1304 if (AArch64::GPR32spRegClass.contains(DestReg) &&
1308 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
1312 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
1326 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
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/external/llvm/lib/Target/R600/
H A DR600MachineScheduler.cpp273 unsigned DestReg = MI->getOperand(0).getReg(); local
274 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
275 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
277 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
279 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
281 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
283 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
362 unsigned DestReg = MI->getOperand(DstIndex).getReg(); local
369 MO.getReg() == DestReg)
372 // Constrains the regclass of DestReg t
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/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp84 unsigned DestReg, unsigned SrcReg,
89 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
110 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
118 if (Mips::CCRRegClass.contains(DestReg))
120 else if (Mips::FGR32RegClass.contains(DestReg))
122 else if (Mips::HI32RegClass.contains(DestReg))
123 Opc = Mips::MTHI, DestReg = 0;
124 else if (Mips::LO32RegClass.contains(DestReg))
125 Opc = Mips::MTLO, DestReg = 0;
126 else if (Mips::HI32DSPRegClass.contains(DestReg))
82 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
226 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
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H A DMipsInstrInfo.h100 unsigned DestReg, int FrameIndex,
103 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
115 unsigned DestReg, int FrameIndex,
H A DMipsSEInstrInfo.h49 unsigned DestReg, unsigned SrcReg,
61 unsigned DestReg, int FrameIndex,
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h240 unsigned DestReg) {
242 .addReg(DestReg, RegState::Define);
253 unsigned DestReg) {
257 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
264 unsigned DestReg) {
268 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
275 unsigned DestReg) {
278 return BuildMI(BB, MII, DL, MCID, DestReg);
282 return BuildMI(BB, MII, DL, MCID, DestReg);
339 unsigned DestReg) {
237 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
249 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
260 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
271 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
336 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
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