| f4ba40fc419a9d484da9be1df051ad03327ce4f4 |
19-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove pool blocking and assembler enablement from the API
The MacroAssemblerInsterface and AssemblerBase classes define methods
that should not be used directly. Instead, scope utilities should be
used.
This patch hides the following methods from the user:
~~~
void MacroAssemblerInterface::SetAllowMacroInstructions(bool allow);
void AssemblerBase::SetAllowAssembler();
void MacroAssemblerInterface::BlockPools();
void MacroAssemblerInterface::ReleasePools();
void MacroAssemblerInterface::EnsureEmitPoolsFor(size_t size);
~~~
Change-Id: I26b55c560cd94a2158757ca969c6bf95f7ba743b
acro-assembler-aarch32.h
|
| f5d9808e6dd26daf325219d67a304173a1909f30 |
20-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove support for loading from a label using the MacroAssembler
This patch removes the following API from the macro-assembler:
~~~
void Ldr(Condition cond, Register rt, Label* label);
void Ldrb(Condition cond, Register rt, Label* label);
void Ldrd(Condition cond, Register rt, Register rt2, Label* label);
void Ldrh(Condition cond, Register rt, Label* label);
void Ldrsb(Condition cond, Register rt, Label* label);
void Ldrsh(Condition cond, Register rt, Label* label);
void Vldr(Condition cond, DataType dt, DRegister rd, Label* label);
void Vldr(Condition cond, DataType dt, SRegister rd, Label* label);
~~~
In short, we cannot guarantee that the label will be in range, and when
using the macro-assembler, the user should have this guarantee. The only
way to generate these instruction is through the creation of literals.
Change-Id: I15be8d5d8a7a0b21987cb6ff767530446a615bbc
acro-assembler-aarch32.h
|
| fb37b5d8438252728469290fa35a779817faea00 |
18-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Add tests for pool blocking in nested ExactAssemblyScope
On top of adding tests, this patch adds a new top-level
MacroAssembler::ArePoolsBlocked() API method. This is useful for testing
that the pools are actually blocked or not, and that nesting does not
accidentally unblock them.
Change-Id: If3845c6686ef45ddf1d28b8876ffd349731cdd9d
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 0cec43d2696e745b8c031930dec336db5c58ac52 |
19-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Disallow implicitly creating a DataType from uint32_t
This triggered a bug were we accidentally let DataType be created from
any uint32_t, and incidently, any other enums. As a side effect, a
condition such as "hi" would implicitely cast to a "S8" DataType for
example.
Change-Id: I72a1b427f550c251d366164d599d9a38be792fc8
nstructions-aarch32.h
|
| 5c01c410ae559d0a77d68a023957c5bc9de143e0 |
18-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove Adr(Register, Label*) support from the MacroAssembler
The Adr macro-instruction taking a label should, in theory, be able to
handle a label bound anywhere in the 32-bit address space. However this
is not implemented therefore we shouldn't have it exposed in the
MacroAssembler as it can be misleading. One would naturally expect it to
generate the appropriate sequence for any label.
Let's enable this again later once it is entirely implemented.
Change-Id: I186b5f0ba1be4febb26ca548df2e1c056863e975
acro-assembler-aarch32.h
|
| 32929a7f73c3a103a2abe21f49258fba149a5157 |
18-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove Switch implementation from VIXL
The Switch implementation is not well tested, and uses Adr with a label
which we are going to temporarily disallow until we support patching
multiple instructions. The reason this is tricky is that pools can be
generated in between each macro-instruction and this can break Adr,
which breaks Switch.
Let's add it again later when the feature is ready.
Change-Id: I30d6adf89e4ddcebada6aa70ff7b6a5dc9239ad4
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 04d8afb2fe9efa2f9d95136191c9e5d5cdc99a68 |
19-Jan-2017 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix target=(t32|a32).
The benchmarks no longer assume that both ISAs are available. They started
failing after d503ed2, when I changed test.py to run target=t32 in a debug
build. The tests were already broken before, but we only ever tested these
configurations in release mode so the assertions didn't fire.
kDefaultISA now correctly selects T32 as the default if only T32 is available:
constants-aarch32.h needs to include globals-vixl.h so that
VIXL_INCLUDE_TARGET_T32_ONLY can be defined.
Change-Id: Idfaa5800cab8e1119f09f22e9a380f3d818e7c4c
onstants-aarch32.h
|
| 4339c4bbb18b2d975202d6da09a08eefdaabc27c |
12-Jan-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Remove some unnecessary curly brackets.
Change-Id: I8ba6a9be29381b5ed4dffba0b57e28782cee35ad
isasm-aarch32.cc
|
| d56f609907e454dd41bb8b2d98e078e69c4feafa |
11-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
ExactAssemblyScope: Force the pools not to be emitted
There was a bug where the AArch32 MacroAssembler would still generate
pools inside ExactAssemblyScope. In order to avoid this, this patch
renames the `kCheckPools` policy to `kBlockPools`. Saying "check"
implies we only assert that pools are not generated, which is not the case.
Change-Id: Ica717f56f99c7363add5361076174e8e827dd81c
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 59c315165e16fb505f10c1224a83c3803f9fdfd6 |
10-Jan-2017 |
Jacob Bramley <jacob.bramley@arm.com> |
Temporarily disable a check in VeneerPoolManager::Release().
ART assumes that pools will not be generated after macro instructions or
ExactAssemblyScopes. The EnsureEmitFor(0) check in VeneerPoolManager::Release()
breaks this assumption. We'll have to come up with a real solution, but this
quick fix should suffice for now.
Change-Id: I50937b9f575e69171419497d0cd376b514824529
abel-aarch32.cc
|
| 9a9331faeba996d6c85e6e2a6355ccfc22c6cab6 |
09-Dec-2016 |
Rodolph Perfetta <rodolph.perfetta@arm.com> |
Allow conditional inclusion of A32, T32 and A64.
The 'target_arch' option has been replace by 'target' which can be any
combination of aarch32, aarch64, a32, t32, a64.
Change-Id: Id5cd052276747cd718551f562b74f79443b91869
ssembler-aarch32.cc
ssembler-aarch32.h
onstants-aarch32.h
nstructions-aarch32.h
abel-aarch32.h
acro-assembler-aarch32.h
|
| a4cbc576a003da934ab58b293d9023d9b6f3077b |
05-Jan-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix veneer emission.
Change-Id: I2ef8b153f1ab87fa9972f80b1b4660ceefabceb4
abel-aarch32.cc
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| b2838fee50499a1c7963167b0d8144552f194e15 |
16-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Optimize Ldrd and Strd.
Change-Id: I2594b76c0c96fe86146fe453dcbb1acb45823128
acro-assembler-aarch32.cc
|
| 80b4a1f554a92b2c4d4504265d0bac545c74c69b |
14-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Optimize add/sub with a big constant.
Change-Id: I4d5e684fc9cb6a2fe754acfc3b75eb7b530273e2
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 2272afbda5f15c4bfb25c3c9bf95d960c9df39d6 |
04-Jan-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix for veneer pool when using near branches and cbz.
Change-Id: Ifc9cf13b07d6b5504f3fe4d4d45597cc05e069aa
abel-aarch32.cc
abel-aarch32.h
acro-assembler-aarch32.cc
|
| e99f34dd95e54fb15605a022309175ed8020bf2c |
21-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Check for unpredictable CLZ.
Change-Id: I2f8799efc32bd2aae3c3d9c604d389511eab8987
ssembler-aarch32.cc
|
| 0cc43be9ba1881f608a25467b1387927af3b4caa |
22-Dec-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Revert "[aarch32] Dot not abort when one uses unpredictable or strongly discouraged instructions"
This reverts commit d836966fcbe0ec3136486ec36de6bd2572d451eb.
Change-Id: I3e8b0ea9bc43594ab3ad569e54f78e00593dfea8
ssembler-aarch32.h
acro-assembler-aarch32.h
|
| d836966fcbe0ec3136486ec36de6bd2572d451eb |
19-Dec-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
[aarch32] Dot not abort when one uses unpredictable or strongly discouraged instructions
Calling VIXL_ABORT when a MacroAssembler object would call
AllowUnpredictable or AllowStronglyDiscouraged would prevent us from
handling those cases in delegates. It should be up to a delegate to
decide whether to give the user an error or generate an alternative code
sequence.
Additionally, the user is able (but that's not recommended of course) to
lift the UNPREDICTABLE or STRONGLY DISCOURAGED limitation using
scopes. Since the AllowUnpredictable() and AllowStronglyDiscouraged()
methods were virtual and overriden by the macro-assembler to
abort. There was no way to write the following code:
```c++
MacroAssembler masm(T32);
{
ExactAssemblyScope scope(&masm, ...);
AllowUnpredictableScope allow_unpredictable(&masm);
// Here be dragons!
}
```
This patch fixes this by turning AllowUnpredictable() and
AllowStronglyDiscouraged() into non-virtual methods.
Finally, the related scopes were inside the `aarch32::Assembler::`
namespace, which is inconsistent with other scopes. Move it to
`aarch32`.
Change-Id: I42e5b772e850a8c23521385cf399aaae77b5eab6
ssembler-aarch32.h
acro-assembler-aarch32.h
|
| 942e3b7b1d381454c8f17c31c8a3ccbe568512f7 |
30-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add unpredictable conditions for mov.
Change-Id: I193cc0ec2ba3882805496f6d2efb6a73161f98a6
ssembler-aarch32.cc
|
| a576eb92e2a877984e6e5c1e409e23c49c8b96a1 |
13-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add more identities.
Change-Id: I52ff78a7b101de88146ead71b555a17541f9b863
acro-assembler-aarch32.h
|
| 34ecc5b8b9af49df5727cfc357db1fddc674cb44 |
20-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Move some NO_RETURN attributes.
These appear to fail for some versions of Clang unless they are at the start of
the prototype.
Change-Id: I8c5a3ef614cbdd8ed1361017c41c00e5d1cfca93
perands-aarch32.h
|
| 028fb0566f6af6d839d34ccfec754ba394510302 |
15-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Improve and clean up abort messages.
In particular, with negative_testing=on, print the same helpful messages as in
normal builds.
Change-Id: I9426aba8149e22b13e489133c5c4531f513b0850
acro-assembler-aarch32.cc
perands-aarch32.h
|
| e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66 |
14-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Assert perfect nesting for UseScratchRegisterScope.
Since UseScratchRegisterScope now has a MacroAssembler pointer anyway, this
patch also removes available_ and availablefp_, and uses the MacroAssembler
directly.
Some negative tests would be useful but I'll add them separately.
Change-Id: Ia093c67a980044f8e1514cff81998fd9dbfaa44e
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 1091d74cee7404c902fccdc6dba81609bbbdf443 |
16-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Generate ADD and not ADDS for Add(DontCare, r1, r1, r2).
Change-Id: Iabb680bcd7b4027602ca48c34691d61d75b1e0af
acro-assembler-aarch32.h
|
| 5ddbc800588cde7e4d02f9fb7ca2f9e8c12522ef |
16-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Optimize IsModifiedImmediate and Orn/Orns delegate.
Change-Id: I05ac177e9ef28a99dc00b43a2de6d7fdfae87ef3
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| be9c4d02c96eaa6cdc9a9a5ae3cc65f57d54585c |
15-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Support conditional load literal for T32.
Change-Id: I2865cd2ef2e075c47d1d18838c97c04c9294177c
acro-assembler-aarch32.h
|
| cf91ee6bcaabf00356516bbc2d478acbeb8bed9a |
13-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Make rewinding of load literal instructions less conservative.
Change-Id: I2f1b7dce445ceff1edb1f93608b693737be1bc51
abel-aarch32.h
acro-assembler-aarch32.h
|
| 50e45c514c11300c91b370c251235a9a77bdaf5f |
13-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
After rewinding a load, only add the label to the literal pool if it's not bound.
Change-Id: I5f0296582630cc8f81a72a304986b1c15acab02c
acro-assembler-aarch32.h
|
| 4f002a865b625dc388e9175bfdda285812e17f2b |
14-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Increase max recursion limit for delegates.
The new case that needs a larger recursion limit is related to literal loads
with negative offsets (due to already bound labels). In some cases, the Ldrd
delegate (1) calls MemOperandComputationHelper which calls Add (2). The Add has
a negative immediate that cannot be encoded so calls Sub (3). This recurses in
the new code that handles add/sub with negative offsets (4), and after we
recurse we add a Mov and end up in that Delegate (5). This increases the limit
to 6 which works fine in this case.
Change-Id: I994dd46a201fb24afb377bd13c4e5dcd3cb29002
acro-assembler-aarch32.h
|
| efe0c1f222c9b2da15755b221ee0fa232939ce80 |
24-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Allow Operand::From to convert signed integrals
The static Operand::From factory method would not accept signed values
that can be encoded in 32 bits. To avoid implicit casting in
Operand::From, we've added uint32_t/int32_t/uint64_t versions of UintN
and IntN. Along with new tests.
Change-Id: I93b61102b7af8df369621f8929d9d7c74b363f38
perands-aarch32.h
|
| 4a30c5d68ebbc271d6d876d828ffa96db53d8d7c |
08-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add MacroAssembler B with hint.
Change-Id: Ic56a63c5af35c6d46b1a03a4b58165e991afc4d7
onstants-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| e31fda5ecc961cdb78a0a5311d692ae4b15e5933 |
13-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Correct number of bytes we check we can emit in ITScope.
This value was out of sync with MacroEmissionCheckScope, and we are
always using an ITScope together with a MacroEmissionCheckScope, so
we could potentially trigger an assertion that was not necessary.
Change-Id: I1e942d6b919070a3a41d4b38edde74feebb7cc19
acro-assembler-aarch32.h
|
| 9ae5da2ba518573576cc92e93e7a01dd34c8d1f7 |
05-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Specify instructions which use a delegate.
Change-Id: I47b2ed73eab09d5ed6541073d571300e2fcdeef0
ssembler-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| dd8e491930b4eb5928f0dec2441c69a471724ce5 |
12-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Generate 16-bit ADDS/SUBS for DontCare SUB/ADD with suitable immediates.
Change-Id: Ia2c11ad7ac8b14c8d04881ed6b872ae2af7dd3d6
acro-assembler-aarch32.h
|
| 4443cf950cac7b0cf8e82196e60c26f4b2799a97 |
08-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Tests for 16-bit T32 instruction generation for DontCare flags update.
This also fixes a few cases where we were failing to generate a 16-bit
instruction. The issues fixed were resulting in sub-optimal instructions being
generated, but they were not correctness issues.
Change-Id: I3042165eeac90674b89a15db7b7c065925bdd30c
acro-assembler-aarch32.h
|
| 89d2f7702f0dc1751574bd5f9d35b5182fc65fac |
08-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix very-long-range literal loads.
The code was basically functional but the CodeBufferCheckScope sizes had to be
increased. The generated code could be improved, but its a corner case anyway so
it's not a priority for now. Here's an example:
0x004223f2 f2af31ec adr r1, 0x00422008
0x004223f6 f44f5c00 mov ip, #8192
0x004223fa f2c00c42 movt ip, #66
0x004223fe eba1010c sub r1, ip
0x00422402 6809 ldr r1, [r1]
This sequence occurs for offset ranges over about 1MB. For ranges below 1MB, the
worst case is still adr+sub+ldr.
Change-Id: I6345127aed12abb59c819f63167170d57160da0b
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 52e987eb677af65859f169b20816fa5d293c6cf0 |
08-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix long-range literal loads.
This is the second attempt. We no longer generate unpredictable instructions. As
before, this has only been tested for T32.
Change-Id: If5519fe603281b081e93a25bb7980c3e965f037b
acro-assembler-aarch32.cc
|
| 356323a3dbec6b302b7882ed8cf46e9457217d01 |
25-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Check that we don't generate deprecated IT instructions.
Change-Id: If276f5f4f25408178b8a522ea1eb0c06707d0cfd
acro-assembler-aarch32.h
|
| 4cb13e841305b38acbd8195b1c511d59c91ec8d9 |
08-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Correct usage of scratch registers in tests.
Exclude all registers from the UseScratchRegister list for start and end code
in tests, then include ip where necessary. Similarly, exclude all registers
from the scratch register list in the Printf implementation, which handles
available registers in its own way.
Change-Id: I96100411a45f104f85bbc4020959fc9d98e240af
acro-assembler-aarch32.cc
|
| 1ddc52b438c2f07872e6e715c6b86e8d3b772795 |
08-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix MacroAssembler::GenerateInstruction.
Change-Id: Ibc942d3a8c3864f58a4f6d812864051b2d76bb59
acro-assembler-aarch32.h
|
| bd087d8fe70f7db770f37569073b8b9f77a9c372 |
29-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix concurrent veneer and literal emission.
Change-Id: I83be782d9e2862cb94ab618440c375a66c1da201
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 15985a2fcc72ce0ec5e19c410b444ceec899c11f |
28-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix veneer pool generation when several cbz/cbnz are generated one after the other and when several veneers have the same checkpoint.
Change-Id: Ic2d7f348854666f07c191aadc43f299b422867c5
onstants-aarch32.h
abel-aarch32.cc
abel-aarch32.h
acro-assembler-aarch32.cc
|
| 9c112d81bf7bc65d6bea5a1d889ef3db7609771d |
08-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix literal loads from unaligned instructions.
Change-Id: I07a1f7819328ef7ce1fb36ccdc0b940312e36afb
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 5c76fb48ece5cc54c3000abead7e6147ac843834 |
30-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Support arithmetic instructions that read PC.
This is required to implement support for out-of-range PC-relative MemOperands,
which are themselves required to implement long-range references to user-managed
literals.
Change-Id: I1c3ef9712f8fd6624d16eeb38e12f5746f2fa889
acro-assembler-aarch32.cc
|
| f8c2284645ce651f99ba410a512279102851076e |
29-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix Ldr for distant, bound literals.
Change-Id: I0ed3b1df4e93cbbc4bd5ce109130d1ce1ac35ef0
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 4c5d65bf4d3a5fcc6ccb5cd19fed81e2b735789b |
06-Dec-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Include AllowMacroInstructions methods in release mode
The SetAllowMacroInstructions and AllowMacroInstructions methods were
only included if VIXL_DEBUG was defined. While this is understandable,
these methods are virtual and part of the MacroAssemblerInterface, which
means the vtable of macro-assemblers has a different layout depending on
VIXL_DEBUG. This can produce strange errors when headers are used
incorrectly by the user, for instance if linking with a library compiled
with VIXL_DEBUG defined by mistake.
Additionally, this patch explicitely marks overriden methods of the
MacroAssemblerInterface as virtual, as well as adding missing "internal"
namespaces for AssemblerBase.
Change-Id: I2f4595bd5990c944381b177809853e33354e9244
acro-assembler-aarch32.h
|
| fd7f94dd378ec93adcc201d8eb9d71836948de09 |
01-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix macro-assembler temporaries' usage.
Change-Id: I5c14dfca88dc8fe8e973fb61379bde927bbe6d09
acro-assembler-aarch32.cc
|
| b323da089731b39a34ad0a77d20f0a96c1c1a1bc |
02-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Ensure that all used labels are bound.
Change-Id: I95c1a9c2d91c91303ac10898ca556e6e798403e5
ssembler-aarch32.cc
abel-aarch32.h
|
| 9ee25b5df54608e45947a7f99f2c23ce61802474 |
02-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Add Exclude(const Operand&).
This is useful for the common pattern of including destinations only if they
don't alias the input:
temps.Include(rd);
temps.Exclude(rn);
temps.Exclude(operand);
Change-Id: Ibc3af5447b8fb22d92f3b7dc55daf3b608c8e8d6
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 000f93f0af01f9a3f250ad8fb8cd7a42e7b31c99 |
01-Dec-2016 |
Baptiste Afsa <baptiste.afsa@arm.com> |
aarch32: Add a few assertions in code dealing with literals.
Change-Id: Idce680b4f7b98fa1fadfdbc079783e05aa01c3f0
ssembler-aarch32.h
nstructions-aarch32.h
acro-assembler-aarch32.h
|
| 1661f51a172e7c3dcce6caca55b6fe6d10ebd416 |
31-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Use the shared code generation scope `ExactAssemblyScope`.
This patch finishes the transition to shared code generation scopes
for the AArch32 backend.
Change-Id: Iccbdb5de48b41803408410a01307afabe30a7fee
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 8d191abf32edf41421f68f35585e4fce8da4d50c |
29-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Use the shared scopes `CodeBufferCheckScope` and `EmissionCheckScope`.
This patch continues toward the goal of unifying code-generation scopes for all
backends.
The new scopes differ from the existing AArch32 mechanisms, so a few tests for
literal and veneer pools needed to be updated.
The patch also adds AArch32 tests for the new scopes.
Change-Id: Ia6a93e6e860b47e703b6c9034fefa405810c18a0
ssembler-aarch32.h
abel-aarch32.cc
abel-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| d17e348e16bf0d6eca4f9ea0e935c7544098d045 |
23-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add unpredictable conditions for ADC_i, ADC_r, ADC_rr, ADD_ADR, ADD_i, ADD_r, ADD_rr, ADD_SP_i, ADD_SP_r, ADR and MOV_i.
Change-Id: I2d0255c352881d855b375db65794ee7f282b1cfe
ssembler-aarch32.cc
ssembler-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| e7a1690b45036db4c2730ab1c2699ca764a40a68 |
23-Nov-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Add tests for generating IT blocks with the MacroAssembler.
This also disallows generating an IT block for ROR (immediate), as
there is no 16-bit T32 encoding for this instruction.
Change-Id: Id4e9f3abc753b034219eeec6aad7a973cd5be69a
acro-assembler-aarch32.h
|
| adbb4a746d2d90dd2920a8e0b7cd2397e93d17b9 |
22-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Remove inheritance of Register for RegisterOrAPSR_nzcv.
Change-Id: Ie4baa104e243dc96bdf9f7d859597487ca62413b
nstructions-aarch32.h
acro-assembler-aarch32.h
|
| 7d0ad8b7de47bd31742317523a5d764cdd58a466 |
25-Nov-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Test switch without explicitly bound default label.
Change-Id: I98bb1913e114655abefb0678b92e456f80141112
acro-assembler-aarch32.cc
|
| 960c80d57d7ec81ad517b9f5117434ca930f05c6 |
25-Nov-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Reland: Test macro assembler support for NEON immediates
Test macro assembler support for NEON immediates with a range of data types.
Also, improve the code for moving F64 values into Q registers, and remove
some unreachable cases.
Relanding after fixing MacOS build problem.
Change-Id: I6d2a22c9d7d3a35f8470b11892bb796c493f043b
acro-assembler-aarch32.cc
|
| 6cec473ec0180a2922cb6fc02878b5d80a5f9828 |
25-Nov-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Revert "Test macro assembler support for NEON immediates"
This reverts commit aced8fe6982769fd99f04c8db886fc1f5e0bdd42.
Reverted due to failing MacOS tests.
Change-Id: I991555449128e8adf527a135f4fbebd1a926044b
acro-assembler-aarch32.cc
|
| b21b7623a9fb6d4c627aec1e3a0b51f278ef0a72 |
24-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Correctly exclude V registers in UseScratchRegisterScope
There was a nasty bug in UseScratchRegister::Exclude(VRegisterList). We were
taking the *core* register list as a source instead of the vfp register
list.
Add some tests for the Exclude/Include operations.
Change-Id: I8f58a8efa9d66927caf4d355e684b4a3b61b4da6
acro-assembler-aarch32.cc
|
| aced8fe6982769fd99f04c8db886fc1f5e0bdd42 |
22-Nov-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Test macro assembler support for NEON immediates
Test macro assembler support for NEON immediates with a range of data types.
Also, improve the code for moving F64 values into Q registers, and remove
some unreachable cases.
Change-Id: I7bca5d46c454e33de5860d11f2cd405c9872e6a5
acro-assembler-aarch32.cc
|
| 989663e3cb7be8ac458d71f8e8d99afd29b13a39 |
24-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Rename operand-aarch32.{h,cc} to operands-aarch32.{h,cc}
We were inconsistent in naming this file between the AArch64 and AArch32
targets, let's go with what AArch64 calls is and pluralize operand.
Change-Id: Id2581255e4aa398f2c6fa81e5abce1f4b9b8a364
ssembler-aarch32.cc
isasm-aarch32.cc
isasm-aarch32.h
acro-assembler-aarch32.h
perand-aarch32.cc
perand-aarch32.h
perands-aarch32.cc
perands-aarch32.h
|
| 740da998f1b2677636dfd76a6028e283d6175bf0 |
22-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Correctly require space before the branch in `PerformEnsureEmitFor()`.
Change-Id: Ib3828be4e3cf762ebb13c8fc654067fdccff9eac
acro-assembler-aarch32.cc
|
| 0eb25b040732354c6273c93df709f8d585a140de |
22-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Fix and test the precision of margins before pool emission.
This precision is paramount when writing tests for corner cases
of veneer or literal pools emission.
Also check that the buffer only grows when required.
Change-Id: I8992f1c389578a7a8301ea621ea6db7a7f9c9c11
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| fad927c4321a9dd7e235b91aadd88f5542561370 |
18-Nov-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
More MacroAssembler tests for loads and stores.
Add a few more tests for load immediate and tests for PlainRegister
MemOperands used in loads/stores. This patch also restricts the
cases of PlainRegister MemOperands we support in the MacroAssembler
to avoid unpredictable behaviour.
Change-Id: I1b416de439e858d6d16fde174088fac0a90040e5
acro-assembler-aarch32.cc
|
| d370ac5a89d8a5ce4f07326f5b04347465be2422 |
21-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Add tests for Orns and add assertions/comments in its delegate
Test coverage showed we didn't have tests for transformations of `orns`
into `orrs`. Also, let's add few assertions and comments in its
delegate, I found the handling of the immediate operand a little hard to
understand.
Change-Id: I31b2214d2202342c8b387a84d33fd051819305a6
acro-assembler-aarch32.cc
|
| 283bbdf1908649c90069ff80dfca45de4f675de4 |
21-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Cleanup return statements in delegates
Delegates and MacroAssembler instruction methods all return void,
however, we'd often write code as:
~~~
return MacroAssemblerMethod();
~~~
Break those cases into two lines:
~~~
MacroAssemblerMethod();
return;
~~~
Change-Id: I92b99a86d03a8fa672e2772932b60492983ad181
acro-assembler-aarch32.cc
|
| 7f2a44c6dce08e942080f14af19f83a202162104 |
17-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
MacroAssembler tests for Ldrd and Strd
On top of adding tests, adjust CodeBufferCheckScope for cases where we
may need up to 3 instructions to generate an immediate offset.
More importantly, there was a bug where a negative immediate would get
turned into a positive immediate.
Finally, the delegate would not allow re-using the destination registers
as scratch when trying to emit a Ldrd with a PreIndexed offset:
Before: Ldrd(r0, r1, MemOperand(r0, 0xabcd, PreIndex))
mov ip, #43981
add r0, ip
ldrd r0, r1, [r0]
After: Ldrd(r0, r1, MemOperand(r0, 0xabcd, PreIndex))
mov r1, #43981 // It's perfectly OK to re-use r1.
add r0, r1
ldrd r0, r1, [r0]
Change-Id: I51007d4cb45260d066db36222cb56bd4a93f8f74
acro-assembler-aarch32.cc
|
| b44f7a6ee7f9cd194cde9577f5a941f2864795a4 |
17-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove delegate support for load/store exclusive and pld
This patch removes delegates that were trying to handle the following
instructions:
- pld
- pldw
- pli
- lda
- ldab
- ldaex
- ldaexb
- ldaexh
- ldah
- ldrex
- ldrexb
- ldrexh
- stl
- stlb
- stlh
- ldaexd
- ldrexd
- stlex
- stlexb
- stlexh
- strex
- strexb
- strexh
- stlexd
- strexd
Instead, the user will get an error if they are used incorrectly. We no
longer try to make them work with addressing modes that are not already
supported by the instruction itself.
Instead of having the delegates use VIXL_ABORT_WITH_MSG directly, I've
changed the `UnimplementedDelegate` method to print the message
"Ill-formed '{}' instruction.". To do this, we now have a
`ToCString(InstructionType)` function to print instructions, defined in
a new file "aarch32/constants-aarch32.cc".
Change-Id: I4e1f955576b88aae3edaf4dad157f11d4755e6ca
ssembler-aarch32.h
onstants-aarch32.cc
onstants-aarch32.h
isasm-aarch32.cc
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| fd7a00db313b38f1b328c7fc6af1325d85bc31ad |
09-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Do not force alignment in `MacroAssembler::EnsureEmitFor()`.
The alignment requirements are relegated to users. The automatic alignment
otherwise interferes when trying to control precisely the size of code we want
to emit.
Change-Id: I9a7eb509344c390ce9b91d3c687f6e56d38ab889
acro-assembler-aarch32.h
|
| 39b5e60b78f447c4af8c18f12281ed7ab9c33c82 |
18-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix assembler for instructions with an operand like [<Rn>, imm].
Change-Id: Iff2f0f8a6bd67886cb8b658b606514a9845796f7
ssembler-aarch32.cc
|
| 40b7e470e71b158158ef6ce8a1a3f701857ce0e2 |
09-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix PerformEnsureEmit for literals.
Change-Id: Iab0cb33eb59a69a90a00754263c7210b16ad2044
abel-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 9fcf6d6dd240d7f40f187965c981749eb4eaa94b |
17-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix assembler for instructions with an operand like "[PC, #imm]".
Change-Id: If6a945b9ef2ae08639efe1e85fef9e7d28340c25
ssembler-aarch32.cc
|
| a01fbf25f9e2c9c53e82774126c4717ee37c1d91 |
18-Nov-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Add MacroAssembler tests for Msr.
Only handle immediates in the MacroAssembler: either for T32 which
does not have an immediate version of the instruction, or for A32
when the immediate cannot be encoded.
Change-Id: I8f83dce6a3548ebdebb19b8d677cc9ce59b3e56b
acro-assembler-aarch32.cc
|
| c0ee83fd133e93d3967d8347ad2bf2a218524348 |
18-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Use IsOffset, IsPreIndex and IsPostIndex.
Change-Id: Ib7fd5e55689954c12ce90cf2bb605528a3ea057c
ssembler-aarch32.cc
|
| 66170ac6e8c11239700e6031dc690cc2594c0675 |
15-Nov-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
MacroAssembler tests for the InstructionCondSizeROp Delegate.
Testing that register shifter register operands for T32 are expanded correctly,
and that wide immediates are handled properly.
Change-Id: I8aef918a290e68fda9af2364a0fb618d1bde8536
acro-assembler-aarch32.cc
|
| 2aa0afc4afb9409c97261e1dab9abc456a7551ed |
16-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
MacroAssembler tests for the CondSizeRROp delegate
This patch adds tests covering most of the delegates'
paths. Specifically, this delegate takes care of translating Add, Adc,
Sub and Sbc. As well as allowing register shifted register operands in
T32.
On top of adding tests for these instructions, this patch identified a
case where we should reserve space for 3 instruction, in case the
immediate is not encodable. Additionally, the delegate did not handle
the setflags version of those instructions.
Change-Id: Ice8459314ab38004afa61729eba4d18f3f788593
acro-assembler-aarch32.cc
|
| cf4d2842eb8d63c621d7003e240ec094a357cad0 |
15-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
AArch32: Check that the user doesn't pass in scratch registers.
The user must not use registers that the MacroAssembler can allocate as scratch
registers. This patch attempts to enforce this restriction by checking that the
user never passes an available scratch register to the MacroAssembler.
Change-Id: I7897b788df6dc0fabc452df0fe28d986fd84097c
acro-assembler-aarch32.h
perand-aarch32.h
|
| df9f46669cb7ea55844ab6e5ac0b12c26399b233 |
16-Nov-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Test masm support for vldr and vstr
Test vldr and vstr output from macro assembler. This also fixes a few bugs:
- vldr/vstr with negative offset/preindex/postindex
- vldr/vstr with zero preindex/postindex
- vldr/vstr with PC base register
- CodeBufferCheckScope sizes
Vldr/vstr with PC base register is fixed by disallowing it in the macro
assembler, including for cases where only single instructions need to be
generated. We assume the literal pool or assembler will be used, instead.
Change-Id: If2d81da4fa9776fb9ed93804a56b25a2106dc954
acro-assembler-aarch32.cc
|
| 29f71f91fc1282d12fd2d5eb87eec8cf0147f043 |
16-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Implement indexing for internal register list types.
Primarily, this adds accessors like DRegisterList::GetDRegister(n) to allow
simple iteration through the list.
Also, refactor NeonRegisterList so that it has a first+length arrangement like
the others.
Change-Id: Id36e5aa7a39b6e8cdd85f533589266e2f847e4b1
nstructions-aarch32.h
|
| 5b698cc633932dee5dd94f44a42f0fdec567fe2b |
15-Nov-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Add MacroAssembler tests for cbz/cbnz.
This patch adds MacroAssembler tests for cbz and cbnz. It also removes
MacroAssembler support for these instructions for A32, as we were substituting
them with a sequence that corrupted the flags, which the user might not expect.
Change-Id: I7abf0c283a6c5722edee5b7bf2d4249d176f08f6
acro-assembler-aarch32.cc
|
| e6c6319611916b73b227075c7a7c2f76bec50745 |
16-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Replace VRegisterList::Include with explicit variants.
Previously, it wasn't clear whether `list.Include(d0)` should have been true
when the list included s0 but not s1. Now, the user must call a specific variant
of Include to make this clear.
This patch also fixes the implementation of UseScratchRegisterScope accordingly,
and updates the test to check this behaviour. Further testing would be
beneficial here, but this patch is blocking other work.
Change-Id: I25499b8d3a292df217e3338e13d1817a7d125b45
nstructions-aarch32.h
acro-assembler-aarch32.cc
|
| a5372b10e91d4ecaddedc9c4aec2d61bf952a2ca |
12-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Optimize load/store with a big offset.
Change-Id: I08d3d94b1cb460d7a4535dd4547abe5c75832e9c
acro-assembler-aarch32.cc
|
| c12d772a9c07b86010ec7e929716a95bda2aab25 |
09-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix macro-assembler Movs with pc and wide immediate for T32.
Change-Id: I1e1efa8b202ac07875c783cd50d8ae90b833748e
acro-assembler-aarch32.cc
|
| 7827144797ee5ebfa0b574f45ad8ff235f919304 |
08-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Allow a label which is in the veneer pool to be bound with 'bind'.
Change-Id: I1e0d03498ec86ed23d94ef1db2d2adc5b73ef984
ssembler-aarch32.cc
ssembler-aarch32.h
abel-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| bf9f0ca0d76df354d17c181ef2121016859f299c |
15-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Add MacroAssembler tests for Rsc and Orn
This patch adds manual tests for the InstructionCondRROp delegate, and
fixes two cases where CodeBufferCheckScope triggers an assertion because
we have generated more instructions that we thought.
Also, this patch limits this delegate to only Orn, Orns, Rsc and
Rscs. Let's give an error to users if they have mis used the other
instructions.
Change-Id: I36ad39679839b81aa2fe8362064239aea3baa861
acro-assembler-aarch32.cc
|
| 4634a88b6db240a13adc66f26ff3437806f08aec |
14-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove Addw, Movw, Subw, Tbb and Tbh from the MacroAssembler
This patch removes instructions that should not be exposed to the user,
instead, the MacroAssembler can choose to generate them. For instance:
- Use Add/Mov/Sub instead of Addw/Movw/Subw. The latter instructions
just target a specific encoding, they are for the assembler only.
- Use Switch/Case/End to generate Tbb and Tbh instruction if they are
available.
This patch also removes references to these instructions in the
macro-assembler's delegates as well as simulator tests for them. Of
course, they are still covered by assembler tests.
Change-Id: I86d606f433aad8cdccba8dd9681ff6d94a9adac3
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 30aaad9e13111af88c55cbbba6dc31b06e1c8d5a |
14-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Restrict the "Condition, Register, Operand" delegate to only Teq
This patch changes the "InstructionCondROp" delegate to perform the
following transformations:
- Movt: Abort and tell the user the immediate needs to fit in 16 bits.
- Movw: Abort and tell the user to use Mov instead.
- Teq: Handle out-of-bounds immediates.
- Sxtb16/Uxtb16: Unimplemented.
Finally, this delegate used to handles short hands of Add and Sub, but
those are no longer supported.
Change-Id: I135b07be09a2aada9e9649fa082bbb6a3182b8ec
acro-assembler-aarch32.cc
|
| 4e329d4f71bb1a2f4dafca04a512e7c2862343f7 |
15-Nov-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Remove masm support for vld3/vst3
This covered only vld3 and vst3 for single or all lanes (not multiple lanes)
and was untested. It seems more prudent to remove this than complete the
support for other vld/vst instructions, with tests.
Change-Id: I707a0f2329ea530d16b64aa9062774e4de1c755d
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 21d8d8d551fc50cb15fc137f00a154ea65eb2b81 |
14-Nov-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Improve error reporting in macro asm ContextScope
Wrap ContextScope creation in a macro, and pass in the file and line number.
These locations are printed out when a recursion limit is reached.
Change-Id: Ia1339af9af146cf3682d9dc7bf2b131bea4524bf
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 2ec1f7562e90ebd295989c1323d59161a23dadfc |
11-Nov-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Fix comparison instructions with PC in masm
Remove Tst with PC destination for Thumb encodings, support Cmp with PC for ARM
encodings, and create a signed immediate getter to remove some undefined
behaviour.
Change-Id: Iae995de81ca83be3fe990a368345626fee81ee68
acro-assembler-aarch32.cc
perand-aarch32.h
|
| f8833fa525b25cb1d72beb4f2d033d5ad9a3eb80 |
09-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Allow Cbz/Cbnz to branch immediately after the instruction.
Change-Id: I7ad6bbc84d69bc7ac3b61999fd77823b6ea552a2
onstants-aarch32.h
abel-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 76887c1820d5a7c957135c94e7cd57e39084ba8d |
10-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add comment to MacroAssembler::ContextScope.
Change-Id: I8c7da6fef2456d61a4d3d3abbbd02103d2365249
acro-assembler-aarch32.h
|
| 60241a544be0ebf48347789bf0ec268414364627 |
10-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Specify NOLINT disabled directives.
Remain:
src/aarch32/operand-aarch32.h:207: Operand(float) VIXL_NO_RETURN_IN_DEBUG_MODE { // NOLINT
src/aarch32/operand-aarch32.h:210: Operand(double) VIXL_NO_RETURN_IN_DEBUG_MODE { // NOLINT
which can't be specified due to a linter bug.
Change-Id: I5cf55e18772564363a9d895ef83481381ae96635
ssembler-aarch32.cc
isasm-aarch32.cc
isasm-aarch32.h
nstructions-aarch32.cc
nstructions-aarch32.h
perand-aarch32.cc
perand-aarch32.h
|
| fad350715bbb9f13ea85c84da4e6095dfee3cd15 |
08-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix Condition for sanitizer.
Change-Id: I6633a0ffd669ce4929a7859e9ed82fa48c8b3055
isasm-aarch32.cc
nstructions-aarch32.h
|
| 3c1635a4387a8d19b33d558b75c376e6587c317e |
08-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix ImmediateA32 for sanitizer.
Change-Id: Iecf6715b5e6397f256ba881a84a6b42dc0707e4e
nstructions-aarch32.cc
|
| aaac397e490f27ca3011e8ba2cb61f4f455c1a4d |
09-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
AArch32: Replace uses of EnsureEmitFor with scopes.
The intention is to catch cases where we generate more code than we have
reserved space for. It is likely that many of these scopes reserve insufficient
size, but they all pass the tests that exist. We still need to review each one,
write tests, and update the sizes as appropriate.
Note that EmissionCheckScope is the proper scope to use, but it isn't
implemented consistently for AArch32 yet. However, it will be easy to replace
these uses of CodeBufferCheckScope with EmissionCheckScope once it is available.
Change-Id: Ie852c3688b2ae5b1b531d531ad1c2357808fb1eb
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 4e6b4af20e5664c43ca1717b4fa7d6fb4cb3667c |
08-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Fix `MacroAssembler:VeneerPoolIsEmpty()`.
Change-Id: I8a11f954e70fffe795336831a35eb3ee671c8a09
acro-assembler-aarch32.h
|
| e42218c6ca969b7d4032da978fb05f06641df100 |
19-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Make bind and place more consistent.
Change-Id: I1743511e3c6f995f05cded38347a015c198b1fb9
ssembler-aarch32.cc
ssembler-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 1075d15db3f11224e70960ed653462064018a001 |
02-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Rename pc to code_address for the disassembler.
Change-Id: I5e35cf27f0434bc856fe9075dae5e0a9f6e24d84
isasm-aarch32.cc
isasm-aarch32.h
|
| 7f4a230cbb795755d24e1d4658e99a7ccf1eb24b |
13-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add instruction information to the DisassemblerStream.
Change-Id: I2da5371c86c000caef7cf82db8f5440184c8d0a3
ssembler-aarch32.h
onstants-aarch32.h
isasm-aarch32.cc
isasm-aarch32.h
|
| dcffac4d0a5a586d3c14971e33bd28fc848bc148 |
19-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix veneer/pool emission while in a Delegate.
Change-Id: I76ff3e224f5e85a58a53865c62536d97e73b6730
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 3fac43c1a101f98f116e752b80abc122d32b83ac |
31-Oct-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Mark methods as `override` when compiling with C++11
This patch introduces a VIXL_OVERRIDE macro. When building with gcc
-std=c++11, we now enable the `-Wsuggest-override` warning so that we do
not forget to add them in the future.
Change-Id: I0f402599019ba9de1a7a654e9499f00a07f00201
ssembler-aarch32.cc
acro-assembler-aarch32.h
|
| 96ff2a40fffe1d0d754a2187efe5ebabef6d8e44 |
27-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Revert "Revert "Ensure that buffer disassembly will never read outside the buffer.""
This reverts commit 5d4a535c785cf1e911fa74b97f73298aecbd02ae, with the
appropriate fixes.
Change-Id: I8a3bad3bab9cc68495d6c0cfe2a78521fc947715
isasm-aarch32.cc
isasm-aarch32.h
|
| 5d4a535c785cf1e911fa74b97f73298aecbd02ae |
27-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Revert "Ensure that buffer disassembly will never read outside the buffer."
This reverts commit 87c05f09dbb6cada9998bdaeacb5d87d7ad82917.
Change-Id: Ie26bd0cd2575323043e230c2558a131f56512308
isasm-aarch32.cc
isasm-aarch32.h
|
| 26d0fc8c6e5d5a91011bc3150ec49e8b913c5ed5 |
19-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Use non constant value arguments for DisassemblerStream.
Change-Id: I47c2164b5d7008fef8d5066e30e89641798b4e86
isasm-aarch32.h
|
| 87c05f09dbb6cada9998bdaeacb5d87d7ad82917 |
11-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Ensure that buffer disassembly will never read outside the buffer.
t32_disassembler_limit1
0x00000000 eb0b0a0c add r10, r11, ip
0x00000004 e800 ?
t32_disassembler_limit2
0x00000000 eb0b0a0c add r10, r11, ip
0x00000004 4408 add r0, r1
Change-Id: I730460e4b7628b9d51d99ea99fbca3e9423d7654
isasm-aarch32.cc
isasm-aarch32.h
|
| 024aa58e9d83147f57a2509cf115b9fc9d260477 |
26-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Remove the implicit `aarch32::MemOperand` constructor.
Change-Id: Ieca14f0e4b411d059442842c81364836c503625d
acro-assembler-aarch32.cc
perand-aarch32.h
|
| 25e3987b3b684df88edc8069d60b483b95587be5 |
20-Oct-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Support getting the address of a literal with ADR
This patch changes the printf implementation in the MacroAssembler to
use ADR instead of LDR to get the address of the format string. The
format string is placed directly in the code stream.
Additionally, Literal<const char*> was changed to simply
StringLiteral. It may be surprising to have a completely different
behaviour for this case.
Change-Id: I15c7acd457eb8ffed056a60cc438b9d7b54a94e1
nstructions-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 6a049f97861bd71c69d81f643e42308d28c5de31 |
21-Sep-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Unify the `Assembler` helpers related to the code buffer.
A few helpers in `Assembler` classes that were simply wrappers around
`CodeBuffer` methods have been deprecated, and should be replaced by calls to
the `CodeBuffer` methods.
Change-Id: I72608c8c1f1f2823c58c8f6de042e932abe12629
ssembler-aarch32.h
|
| 919e3fe28a5024c53ede42922092bbc32e89dcb8 |
14-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Create a base class for assemblers.
This base class defines an interface that assemblers must adhere to.
For now, we use it to hold the code buffer.
Change-Id: I487430bb98c7044e57b348cffa1e74a2a4c8026f
ssembler-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| e2aa8941a5b41fbd9f855906b8663009eac14669 |
13-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
add some identities and macro-assembler rules
Change-Id: I8f0b03e829a73024d73955d9abcee032e22fceb8
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| f5348cedd702124c90fc75e75d0195e2e485c620 |
22-Sep-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove implicit 64 to 32 bit narrowing
This patch fixes cases of implicit 64 to 32 bit narrowing. The issue is
that `CodeBuffer` represents code offsets with `ptrdiff_t`, which will
be 64 bit on a 64 bit system. However, we want to support generating 32
bit code from a 64 bit program, therefore the 32 bit part of VIXL works
with `int32_t` for code offsets. We had implicit conversions happening
due to this.
We solve this by explicitely casting to `int32_t` in the AArch32
assembler when calling `GetCursorOffset`. If you are working with the
`CodeBuffer` directly, you are dealing with a code buffer on the host
and so will work with offsets as `ptrdiff_t`. But, when working with the
AArch32 assembler itself you will get offsets as `int32_t`. The
assembler is in charge of checking that the offsets it gets from the
code buffer fit into `int32_t`.
Additionally, we had narrowing cases when generally wrapping host
pointers into an Operand. This can only work if the pointer fits into 32
bits. This patch introduces a Operand::From() factory method that can be
used for converting any integral or pointer type to an immediate
operand.
Change-Id: Icc15711b34c2477ed997eef238e25496d86ea9aa
ssembler-aarch32.h
abel-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
perand-aarch32.h
|
| 51d1cccb2cbb843c41a586fbedad00ded8f0d6a0 |
22-Sep-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
add load functions with manually placed literals
Change-Id: I60c554b2396c608ca371a427d718fe69892bfa26
nstructions-aarch32.h
acro-assembler-aarch32.h
|
| 31dd2ae90d5e82871667fbf3ee2697a155e7c3ac |
05-Jul-2016 |
Alex Gilday <Alexander.Gilday2@arm.com> |
Correctly allocate executable memory in CodeBuffer
CodeBuffer allocates memory that is executable via an ExecuteMemory
function.
Change-Id: Ib2dca824e9edd3144694cfac627becd35dd48e3c
ssembler-aarch32.h
|
| 394263d02953f5bd9cffd3c8657f48f375ddcf0e |
20-Sep-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Clarify the ownership of the `DisassemblerStream`.
Change-Id: I7f5f9ebb6b9fbb13699cfb9ae2f3e771d3d236bc
isasm-aarch32.h
|
| 628c5263f1ff96c793173770b85b93ebf8bf8d44 |
21-Sep-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Optimise a few logical and arithmetic identities.
The identities are used to avoid generating code or for strength reduction.
Change-Id: I8eecd23ced2b283884651a49e794c8f34bda1d29
acro-assembler-aarch32.h
|
| 74e3ecd9dc3ecf92604e37c4ec9b9ced5048dedf |
21-Sep-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
AArch32: Add a `GetPcOffset()` helper to the `Label` class.
Change-Id: I58b7a18eed1565ddf9a38d4570af0c24fc79c431
abel-aarch32.h
|
| 753bb5554d5832fbd470a460b0c5f839c0f51201 |
20-Sep-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Remove the empty `Instructions` base class for `Assembler`.
Change-Id: Ic6c00c0ad98988ede47d3cad8426291972c59c0c
ssembler-aarch32.h
isasm-aarch32.h
nstructions-aarch32.h
|
| f678618ae35a43dab65455f446c3de324994c204 |
21-Sep-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add generic VFP functions which use VRegister instead of SRegister or DRegister.
Change-Id: I686e05ec11346711939b58be3730067021f7df72
nstructions-aarch32.h
acro-assembler-aarch32.h
|
| d2d8c09008ae28805b862ae7c79183db1ad50e9b |
19-Sep-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
remove It instruction from the macro assembler
Change-Id: I8676d3be1e69da3fa27f84e932401467dee92635
acro-assembler-aarch32.h
|
| 1107e04f82d4809214ff6592b3727298dee1fe45 |
20-Sep-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Differentiate AArch64 and AArch32 macro names.
The AArch64 macro is not `#undef`ed, and could cause errors related
to macro redifinition.
Change-Id: Idb5da594558116ec77f7d87a2b0873e5e3ed6791
nstructions-aarch32.h
|
| bf01e787b9ca4ff28b8c4d4355fd575c4ac81dfa |
14-Sep-2016 |
Anton Kirilov <anton.kirilov@linaro.org> |
Add some missing header file inclusions.
Change-Id: I8f7497ea6921b655e9996ab7843793f12b27eeed
ssembler-aarch32.h
onstants-aarch32.h
isasm-aarch32.h
abel-aarch32.h
|
| 2715e0b0654dc266f0224a68e04c30aa04a82aef |
15-Sep-2016 |
Scott Wakeling <scott.wakeling@linaro.org> |
Add IsReferenced() to AArch32 Label.
Change-Id: I3dcf521f5d1cfa3c3c0be783fc40e023b982456f
abel-aarch32.h
|
| 82af61c481f2d54e5718320a32af9ad933e0bf7d |
13-Sep-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Wrap literals with Int64 for consistency
Change-Id: I51505f9b72e80e5cebbb0255d49d279dd74524c6
isasm-aarch32.cc
|
| 120cafb9da939e107413e7158897ad73b83d55bf |
30-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Correctly assemble VCLE and VCLT
VCLE and VCLT are aliases for VCGE and VCGT, however the source operands
have to be commuted. The assembler did not do this.
Change-Id: Icfa437ed417d9e234510fcab6034aa983d53e744
ssembler-aarch32.cc
|
| 8ee2cef99dc4fae4129430834d2778d97cb5e076 |
12-Sep-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Revert "Correctly assemble VCLE and VCLT"
This reverts commit 702351b9ba0640958e17eed2ee041278294899b1.
Change-Id: Ic625aeecd276ebd582afd60005f8b1b2eea65f55
ssembler-aarch32.cc
|
| 702351b9ba0640958e17eed2ee041278294899b1 |
30-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Correctly assemble VCLE and VCLT
VCLE and VCLT are aliases for VCGE and VCGT, however the source operands
have to be commuted. The assembler did not do this.
Change-Id: Ia660ddce3c7a8aeaaf636b393b1df2b710d37c63
ssembler-aarch32.cc
|
| 8885c17bce593f82cf90c086da242e52943c50ef |
24-Aug-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
forbid direct use of assembler from the macro-assembler
Change-Id: Ic00c9c72e9aed7efaab72a6fd6838bbd0bda6531
ssembler-aarch32.cc
ssembler-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 260c6b6a014af9932f308fa53b82fb2ada3acba8 |
06-Sep-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix SRegisterList and DRegisterList.
Change-Id: I69a4a43dc32141efcbb4eb2dacbd45659aeecc60
nstructions-aarch32.h
|
| 69acb5618ef7c69bbe165d24493d1af0a00bcc4a |
05-Sep-2016 |
Anton Kirilov <anton.kirilov@linaro.org> |
Fix a formatting issue.
Change-Id: I37bdec882826511556ff30614867c471b7a9eebe
isasm-aarch32.cc
|
| f7535f22629946eb706d02b8b926e5fe77e3b398 |
31-Aug-2016 |
Anton Kirilov <anton.kirilov@linaro.org> |
Add PrintDisassembler::Decode*At() methods.
Change-Id: I5663f1d1e390fdabf88743b615464efb2d4c562a
isasm-aarch32.cc
isasm-aarch32.h
|
| 7f24bc630745306bf9be3881b510e00bbbf19ae3 |
16-Aug-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
add comments to MemOperand
Change-Id: I035a6203a48ab4316a99244b0a120f925c04ad1c
Change-Id: Ic59f5cdab36d10386d9a58d94f3513f4301bf259
perand-aarch32.h
|
| ab2f6c5f500c5b2df2ae8c7dd5a6f25cbdf8004e |
30-Aug-2016 |
Anton Kirilov <anton.kirilov@linaro.org> |
Restrict the set of special core register names used by the AArch32 disassembler
Only the special core register names specified in the AArch32 AAPCS, i.e. pc,
lr, sp, and ip, will be used; the rest will be printed using the generic
"r<number>" convention.
Change-Id: Idbd08a06db438ba3f26c9eefa28349ab565b3a11
nstructions-aarch32.cc
|
| 9cdd215b6b7b830619dd15f111d158a49a7d2367 |
24-Aug-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
fix disassembler after removing of RegisterListWithPC and RegisterListWithoutPC
Change-Id: I0062141f99a7db39f5ebfa4bf997c73481bc48e9
isasm-aarch32.h
|
| 7209fd094f20db08fd43fa5bdeea42644f30fc13 |
15-Aug-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
remove unused classes RegisterListWithPC and RegisterListWithoutPC
Change-Id: I97a346cb34662691fe237f7bb97e4bc92a23833d
nstructions-aarch32.cc
nstructions-aarch32.h
|
| 21376f637832074ecd3e00f2bf9c708e5e0244b4 |
17-Aug-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
AArch32: Optimize `MacroAssemblerHandleOutOfBoundsImmediate()`.
Use mvn if possible.
Only use one mov if possible.
Change-Id: I4d3913200f7d3937c39d31d9fdf3b76280701df0
acro-assembler-aarch32.cc
|
| 934696dd32c579b5a8aa80bae5384be22f0d9b9c |
18-Aug-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Allow specifying whether an instruction should set flags with an `enum`
This patch allow the macro-assembler user to call instructions which can
set flags with an argument.
That is instead of calling "add(rd, ...)" or "adds(rd, ...)" you can call
"add(flags, rd, ...)" with flags which can take the values:
- SetFlags
- LeaveFlags
- DontCare
It will call the right function (add or adds) depending on flags and the context.
Change-Id: I46d07d3b2989522d16d6432a469dc4b796682cbd
acro-assembler-aarch32.h
|
| 71bca307f4e94afdbc753e02c101b042cd218b4a |
23-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Use a length argument when constructing S and D register lists
This patch changes the SRegisterList and DRegisterList constructors to
take a length argument instead of a second register to represent a list.
Change-Id: I87cfbe09d1d80d213fc8a37bdfabca884a7eefa2
isasm-aarch32.cc
nstructions-aarch32.h
acro-assembler-aarch32.cc
|
| 6c4e9957284d43666a32c71e860d29b7a599fa43 |
17-Aug-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
fix cbz/cbnz delegate
Change-Id: I2cc60d2e934d5e45b5752b57525d188ba7f53b32
acro-assembler-aarch32.cc
|
| c591f74ae6d6a8fefaacedcfa5c23100cb23c23d |
19-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Introduce a custom Disassembler stream
This patch introduces a DisassemblerStream type that the user may
override to customize how elements (Register, Condition, Label, ...etc)
are printed. Some of those such as Labels need to be aware of the
context in which they are being used.
Change-Id: I7f2447d30738bf20a65ffe65623dc7c44b012fc7
isasm-aarch32.cc
isasm-aarch32.h
abel-aarch32.h
|
| 1e85b7f2e8ad2bfb233de29405aade635ed207ce |
05-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Introduce architecture specific guards for the simulator
This patch makes the VIXL_INCLUDE_SIMULATOR and
VIXL_GENERATE_SIMULATOR_CODE header guards specific to either AArch64 or
AArch32. Even though the simulator only support AArch64. The build
system was updated accordingly, the "simulator" variable now takes
"aarch64" or "none" as possible values instead of "on" and "off".
This fixes issues we have when we want to build VIXL natively on
AArch64 without a simulator, but still include the AArch32
macro-assembler. The later would check for VIXL_GENERATE_SIMULATOR_CODE
and then generate calls to native code, which breaks.
Change-Id: I2850782558d4cc37f37c1644f0efbd70a3123057
ssembler-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| 3e1b899f48c1328ac748b1f5fa78f417f7ec6581 |
14-Jul-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
AArch32: allow literals' update
Numerical literals can now be updated even after being emitted.
Change-Id: Ief50bac9079bb8c89c800c911ce6eb93a43ffd0e
nstructions-aarch32.h
|
| 97a5640aedb2d193ff27b9e7324a2412ed502a59 |
13-Jul-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
add lane access for D and Q registers
Change-Id: I7ebe3a5672327ae4ca05e5d6c691378041c8a92c
nstructions-aarch32.h
|
| 78973f258039f6e96eba85f1b5ecdb14b3c51dbb |
10-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Correctly include C headers
This patch refactors VIXL to use `extern` block when including C header
that do not have a C++ counterpart.
Change-Id: I203d7d107755dbac3e5f4cf8d2f196f70dea1e07
ssembler-aarch32.cc
isasm-aarch32.cc
nstructions-aarch32.cc
nstructions-aarch32.h
abel-aarch32.h
perand-aarch32.cc
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| fd09817b8770a5e3a64a6fe4fefe85cc29805cd7 |
09-Aug-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Do not include data members conditionally on `VIXL_DEBUG` in headers.
Objects visible via headers should have the same data-layout in release and
debug modes.
Change-Id: I7ce5014ab8406968cdd8e9818a7f840cb443b6c1
acro-assembler-aarch32.h
|
| 979b1d25d9104f3c545a2c5740612b026053b670 |
29-Jul-2016 |
Artem Serov <artem.serov@linaro.org> |
Add GetStartAddress helper function.
Change-Id: I957db991bc84493a36eaf89a16b699c907c3479f
ssembler-aarch32.h
|
| 10dae1a549308bddc1931f29754d6a4459f70c9b |
27-Jul-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
AArch32: Improve the API for selecting the ISA.
Specifically, replace SetT32(false) with SetA32(), and SetT32(true) with
SetT32(). This also adds a parameterised SetInstructionSet(...) helper, and
allows the instruction set to be set in the constructors.
Change-Id: I82609823a4b2af908b38c0a4240ff239561f7507
ssembler-aarch32.cc
ssembler-aarch32.h
nstructions-aarch32.h
abel-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| ad91cee685f33b45841b95999ea0a0eb2c3f9708 |
26-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Minor fix to a comment for Claim(), Drop(), and Peek().
Change-Id: I7c80121610c99bf3114af7644450209cfdb215cb
acro-assembler-aarch32.h
|
| d37560600128faaaf187963885366c3a9a5bdef8 |
27-Jul-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Keep comments describing an instruction on one line
This patch unwraps comments showing instruction's expected disassembly
in comments. We have a NOLINT marker so clang-format will not wrap it
again.
Change-Id: I66de6b4543e8f068799a89e0cb613ded7bd9ed6f
isasm-aarch32.cc
|
| 294e6f426db143d5409895ff4c755b2b203fc07d |
22-Jul-2016 |
Scott Wakeling <scott.wakeling@linaro.org> |
AArch32: Add GetSizeOfCodeGenerated() const accessor to Assembler.
Change-Id: I84877dd2c6aa6d0c5755c9dab6235e618bec26b6
ssembler-aarch32.h
|
| 6c0406d67666027875453d95be4702a6188847dc |
20-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Add a default argument for the `aarch32::PrintDisassembler` constructor.
Change-Id: If59c0fb16e4ea4ae72a7aeaa670ea8b54b218aca
isasm-aarch32.h
|
| 703ff06a087f67fccde24a7ffbc8a2e74a406cb1 |
11-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Aarch64: Rename `allow_simulator_instructions_` to `generate_simulator_code_`.
Change-Id: I72956db90ab3380b5ad62b37d2ed203ec4045931
ssembler-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
|
| d3832965c62a8ad461b9ea9eb0994ca6b0a3da2c |
04-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Update naming to `aarch32` and `aarch64`.
Change-Id: I40a929b1095ee3e1b2ca5ef879c7006d8b59acc9
ssembler-aarch32.cc
ssembler-aarch32.h
onstants-aarch32.h
isasm-aarch32.cc
isasm-aarch32.h
nstructions-aarch32.cc
nstructions-aarch32.h
abel-aarch32.h
acro-assembler-aarch32.cc
acro-assembler-aarch32.h
perand-aarch32.cc
perand-aarch32.h
|