History log of /drivers/clk/tegra/
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
b9e742c3164344fece3615aca42ec51b41753908 17-Sep-2014 Tomeu Vizoso <tomeu.vizoso@collabora.com> clk: tegra: Make clock initialization more robust

Don't abort clock initialization if we cannot match an entry in
tegra_clk_init_table to a valid entry in the clk array.

Also log a corresponding error message.

This was discovered when testing a patch that removed the EMC clock from
tegra124_clks but left a mention in tegra_clk_init_table.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
lk.c
4c495c204f794125db11e74bd61228901b0acaa7 11-Jul-2014 Mikko Perttunen <mperttunen@nvidia.com> clk: tegra124: Add PLL_M_UD and PLL_C_UD clocks

These clocks are used as parents for some EMC timings.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
lk-tegra124.c
44c916d58b9ef1f2c4aec2def57fa8289c716a60 08-Aug-2014 Linus Torvalds <torvalds@linux-foundation.org> Merge tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Olof Johansson:
"This merge window brings a good size of cleanups on various platforms.
Among the bigger ones:

- Removal of Samsung s5pc100 and s5p64xx platforms. Both of these
have lacked active support for quite a while, and after asking
around nobody showed interest in keeping them around. If needed,
they could be resurrected in the future but it's more likely that
we would prefer reintroduction of them as DT and
multiplatform-enabled platforms instead.

- OMAP4 controller code register define diet. They defined a lot of
registers that were never actually used, etc.

- Move of some of the Tegra platform code (PMC, APBIO, fuse,
powergate) to drivers/soc so it can be shared with 64-bit code.
This also converts them over to traditional driver models where
possible.

- Removal of legacy gpio-samsung driver, since the last users have
been removed (moved to pinctrl)

Plus a bunch of smaller changes for various platforms that sort of
dissapear in the diffstat for the above. clps711x cleanups, shmobile
header file refactoring/moves for multiplatform friendliness, some
misc cleanups, etc"

* tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits)
drivers: CCI: Correct use of ! and &
video: clcd-versatile: Depend on ARM
video: fix up versatile CLCD helper move
MAINTAINERS: Add sdhci-st file to ARCH/STI architecture
ARM: EXYNOS: Fix build breakge with PM_SLEEP=n
MAINTAINERS: Remove Kirkwood
ARM: tegra: Convert PMC to a driver
soc/tegra: fuse: Set up in early initcall
ARM: tegra: Always lock the CPU reset vector
ARM: tegra: Setup CPU hotplug in a pure initcall
soc/tegra: Implement runtime check for Tegra SoCs
soc/tegra: fuse: fix dummy functions
soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
soc/tegra: Add efuse and apbmisc bindings
soc/tegra: Add efuse driver for Tegra
ARM: tegra: move fuse exports to soc/tegra/fuse.h
ARM: tegra: export apb dma readl/writel
ARM: tegra: Use a function to get the chip ID
ARM: tegra: Sort includes alphabetically
ARM: tegra: Move includes to include/soc/tegra
...
7232398abc6a7186e315425638c367d50c674718 11-Jul-2014 Thierry Reding <treding@nvidia.com> ARM: tegra: Convert PMC to a driver

This commit converts the PMC support code to a platform driver. Because
the boot process needs to call into this driver very early, also set up
a minimal environment via an early initcall.

Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-tegra30.c
306a7f9139318a28063282a15b9f9ebacf09c9b9 17-Jul-2014 Thierry Reding <treding@nvidia.com> ARM: tegra: Move includes to include/soc/tegra

In order to not clutter the include/linux directory with SoC specific
headers, move the Tegra-specific headers out into a separate directory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-periph-gate.c
lk-tegra30.c
lk.c
0e548d50b95b59ccf123984bc44f17da72b12cdd 08-Jul-2014 Mikko Perttunen <mperttunen@nvidia.com> clk: tegra: Use XUSB-compatible SATA PLL sequence

Use a sequence for enabling hardware control of the SATA PLL
that works both when using the SATA lane with SATA and when
using it with XUSB.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
lk-pll.c
9f0030c8ad0ce357e8fc8c71ec6b4958041afccf 26-Jun-2014 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: export clock names for debugging

When writing a module for testing or debugging purposes, there is no way to
get hold of clk handles. This patch solves this by exposing all valid clocks
as clkdev's for the virtual device tegra-clk-debug.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk.c
0a7eec7f59b8cfccb381c0c43a6a441befe8058c 04-Jun-2014 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra124: init table updates

Ensure some clocks critical for system operation are always. Also enable csite
for JTAG debugging and set the tsensor and soc_therm clock frequencies for the
upcoming soctherm driver.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra124.c
cb44cc2f48371e002eaead79e6fb77a4fc71e40f 18-Jun-2014 Mikko Perttunen <mperttunen@nvidia.com> clk: tegra: Add SATA clocks to Tegra124 initialization table

This adds two clocks, SATA and SATA_OOB, to the Tegra124 clock initialization
table. The clocks are needed for working SATA support.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
lk-tegra124.c
37ab366251167cd6e517a391143db13cc2d3d65c 18-Jun-2014 Mikko Perttunen <mperttunen@nvidia.com> clk: tegra: Enable hardware control of SATA PLL

This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
lk-pll.c
167d5366c4dade2f90321c7f2ef9219cbd6fedcc 04-Jun-2014 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: fix vi_sensor clocks on Tegra124

vi_sensor and vi_sensor2 have a wrong hw clkid on Tegra124. Fix this by
correcting the hw clkid for Tegra124 and creating the Tegra114 vi_sensor clock
from its own data. Tegra124 was also using the wrong internal clock id.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra-periph.c
lk-tegra114.c
lk-tegra124.c
4c8f8062515a3e809cc48c2d378f51bf0346d587 28-May-2014 Mike Turquette <mturquette@linaro.org> Merge branch 'clk-fixes' into clk-next
5178438041cc94680e606e5a9c6d1ad9c911199b 28-May-2014 Mike Turquette <mturquette@linaro.org> Merge tag 'clk-tegra-fixes-3.15' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes

PLLE fixes for 3.15
4a7f10d67b7a015036823856d6669b1f75362ba0 15-May-2014 Andrew Bresticker <abrestic@chromium.org> clk: tegra: Initialize xusb clocks

Initialize the XUSB-related clocks with appropriate parents and rates
for both Tegra114 and Tegra124.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
lk-tegra124.c
5c992afcf8e4f91fac05d39b86c7f7922a50145c 15-May-2014 Andrew Bresticker <abrestic@chromium.org> clk: tegra: Fix xusb_hs_src clock hierarchy

Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock. It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-id.h
lk-tegra-periph.c
lk-tegra114.c
lk-tegra124.c
9d61707b1f83324fc30918787cb6ef101997ecbd 15-May-2014 Jim Lin <jilin@nvidia.com> clk: tegra: Fix xusb_fs_src mux

The parent-to-index mapping for xusb_fs_src is incorrect.
Fix it by adding a mux table.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra-periph.c
2cfe16748bec853cb6b83d19546dfd226898b222 15-May-2014 Jim Lin <jilin@nvidia.com> clk: tegra: Enable hardware control of PLLE

Enable hardware control of PLLE spread-spectrum, IDDQ, and enable
controls when enabling PLLE. The hardware (e.g. XUSB) using PLLE
will use these controls for power-saving optimizations.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-pll.c
d2c834abe2b39a2d5a6c38ef44de87c97cbb34b4 16-May-2014 Tuomas Tynkkynen <ttynkkynen@nvidia.com> clk: tegra: Fix wrong value written to PLLE_AUX

The value written to PLLE_AUX was incorrect due to a wrong variable
being used. Without this fix SATA does not work.

Cc: stable@vger.kernel.org
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: improved changelog]
lk-pll.c
9ba71705706aa83bcd7f9b74ae2d167da934c951 01-Apr-2014 Stephen Warren <swarren@nvidia.com> clk: tegra: remove non-existent clocks

The Tegra124 clock driver currently provides 3 clocks that don't actually
exist; 2 for NAND and one for UART5/UARTE. Delete these.

Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
lk-tegra124.c
4ccc402ece35695dd2884ec0b652d52ae0230f13 04-Apr-2014 Thierry Reding <treding@nvidia.com> clk: tegra: Fix enabling of PLLE

When enabling the PLLE as its final step, clk_plle_enable() would
accidentally OR in the value previously written to the PLLE_SS_CTRL
register.

Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-pll.c
c61e4e75b95bda4c6fec134aa9f08b5629b532e6 04-Apr-2014 Thierry Reding <treding@nvidia.com> clk: tegra: Introduce divider mask and shift helpers

Add div{m,n,p}_shift() and div{m,n,p}_mask_shifted() helpers to make the
code that modifies the m-, n- and p-divider fields of PLLs shorter and
easier to read.

Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-pll.c
d0f02ce3b1685ef6ffe43692034599790f83e7ab 04-Apr-2014 Thierry Reding <treding@nvidia.com> clk: tegra: Fix PLLE programming

PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider fields
the corresponding masks were never shifted, thereby clearing only the
lowest bits of the register. This lead to a situation where the PLLE
programming would only work if the register hadn't been touched before.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
lk-pll.c
ad077ceb8a90c7ef1fc15758ed3811448181ee80 25-Feb-2014 Mike Turquette <mturquette@linaro.org> Merge branch 'clk-fixes' into clk-next
22e5de816b49f1c75c1f1480a99d1c06d46fbe21 15-Jan-2014 Sachin Kamat <sachin.kamat@linaro.org> clk: tegra: Staticize tegra_clk_periph_no_gate_ops

tegra_clk_periph_no_gate_ops is a local symbol.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-periph.c
c7fbd4158433c1c910c62850247728cb05a94e42 20-Feb-2014 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra124: remove gr2d and gr3d clocks

Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the
vic03 and gpu clocks respectively.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra124.c
a9952a76bc0c24b3c9d355c053e001b8a3b65dd3 19-Feb-2014 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Fix vic03 mux index

The vic03 mux uses a linear mapping.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra-periph.c
3de5bdfb4cb3bd99052a4ffaee358189779be042 27-Dec-2013 Andrew Bresticker <abrestic@chromium.org> clk: tegra: use max divider if divider overflows

When requesting a rate less than the minimum clock rate for a divider,
use the maximum divider value instead of bailing out with an error.
This matches the behavior of the generic clock divider.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
lk-divider.c
88b4bd7071ac06e321b4bf4bdb8c69db40182c5a 27-Dec-2013 Andrew Bresticker <abrestic@chromium.org> clk: tegra: cclk_lp has a pllx/2 divider

When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines
whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that
the clk_super driver is aware of this.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
lk-tegra-super-gen4.c
20e7c323abac390deb35248705807bd844590048 27-Dec-2013 Andrew Bresticker <abrestic@chromium.org> clk: tegra: fix sdmmc clks on Tegra1x4

The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with
6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114
and Tegra124 to use these clocks instead.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
lk-id.h
lk-tegra-periph.c
lk-tegra114.c
lk-tegra124.c
82ba1c3c9988a8055f4a4d7ca2168e9efe7e7874 27-Dec-2013 Mark Zhang <markz@nvidia.com> clk: tegra: fix host1x clock on Tegra124

The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents.
Change thte id to tegra_clk_host1x_8 so that the correct clock gets
registered.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
lk-tegra124.c
0e766c2d9fc8cd2ad0e0fe97ff4e264cb686fc32 27-Dec-2013 David Ung <davidu@nvidia.com> clk: tegra: PLLD2 fixes for hdmi

Set correct pll_d2_out0 divider and correct the p div values for pll_d2.

Signed-off-by: David Ung <davidu@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
lk-tegra124.c
67fc26bfd7a265883fd0804f24f6287d16769e3d 27-Dec-2013 Rhyland Klein <rklein@nvidia.com> clk: tegra: Fix PLLD mnp table

PLLD was using the same mnp table as PLLP. Fix it to use its own
table which is different from PLLP's.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
lk-tegra124.c
2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a 27-Dec-2013 Gabe Black <gabeblack@chromium.org> clk: tegra: Fix PLLP rate table

This table had settings for 216MHz, but PLLP is (and is supposed to be)
configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is
not set, the kernel will panic in clk_pll_recalc_rate().

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
lk-tegra124.c
2edf3e035302776e4756e446baf3b6c7b94c3698 02-Dec-2013 Thierry Reding <thierry.reding@gmail.com> clk: tegra: Correct clock number for UARTE

UARTE has clock number 66. Number 65 is the right one for UARTD.

Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-tegra-periph.c
cb6448ab0a9ac5f1d1c72a0f573dd9677d8e5418 19-Dec-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Add missing Tegra20 fuse clks

Add clocks required for accessing fuses on Tegra20.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
lk-tegra20.c
7e21774db5cc9cf8fe93a64a2f0c6cf47db8ab24 24-Jan-2014 Linus Torvalds <torvalds@linux-foundation.org> Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux

Pull clk framework changes from Mike Turquette:
"The first half of the clk framework pull request is made up almost
entirely of new platform/driver support. There are some conversions
of existing drivers to the common-clock Device Tree binding, and a few
non-critical fixes to the framework.

Due to an entirely unnecessary cyclical dependency with the arm-soc
tree this pull request is broken into two pieces. The second piece
will be sent out after arm-soc sends you the pull request that merged
in core support for the HiSilicon 3620 platform. That same pull
request from arm-soc depends on this pull request to merge in those
HiSilicon bits without causing build failures"

[ Just did the ARM SoC merges, so getting ready for the second clk tree
pull request - Linus ]

* tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits)
devicetree: bindings: Document qcom,mmcc
devicetree: bindings: Document qcom,gcc
clk: qcom: Add support for MSM8660's global clock controller (GCC)
clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)
clk: qcom: Add support for MSM8974's global clock controller (GCC)
clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)
clk: qcom: Add support for MSM8960's global clock controller (GCC)
clk: qcom: Add reset controller support
clk: qcom: Add support for branches/gate clocks
clk: qcom: Add support for root clock generators (RCGs)
clk: qcom: Add support for phase locked loops (PLLs)
clk: qcom: Add a regmap type clock struct
clk: Add set_rate_and_parent() op
reset: Silence warning in reset-controller.h
clk: sirf: re-arch to make the codes support both prima2 and atlas6
clk: composite: pass mux_hw into determine_rate
clk: shmobile: Fix MSTP clock array initialization
clk: shmobile: Fix MSTP clock index
ARM: dts: Add clock provider specific properties to max77686 node
clk: max77686: Register OF clock provider
...
4e100354e5b7c8982d1563dca134d375979a8ead 08-Oct-2013 Sachin Kamat <sachin.kamat@linaro.org> clk: tegra: Staticize tegra_clk_periph_nodiv_ops

tegra_clk_periph_nodiv_ops is used only in this file. Make it static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-periph.c
e47e12f973a95634c11fe98330fe3a1df6f844d4 08-Oct-2013 Sachin Kamat <sachin.kamat@linaro.org> clk: tegra: Staticize local variables in clk-pll.c

Local variables used only in this file are made static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-pll.c
a85f06badc3cff4069f2f5112cea63cd39d99920 07-Nov-2013 Stephen Warren <swarren@nvidia.com> clk: tegra: remove bogus PCIE_XCLK

The "pcie_xclk" clock is not actually a clock at all, but rather a reset
domain. Now that the custom Tegra module reset API has been removed, we
can remove the definition of any "clocks" that existed solely to support
it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra20.c
lk-tegra30.c
2ae77527bb1a510070d039aaa22d1ae9a5807b6f 07-Nov-2013 Stephen Warren <swarren@nvidia.com> clk: tegra: remove legacy reset APIs

Now that no code uses the custom Tegra module reset API, we can remove
its implementation.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-periph-gate.c
lk-periph.c
lk.h
6d5b988e7dc56bb97c39bdcbc006fadcd6ca371b 06-Nov-2013 Stephen Warren <swarren@nvidia.com> clk: tegra: implement a reset driver

The Tegra CAR module implements both a clock and reset controller. So
far, the driver exposes the clock feature via the common clock API and
the reset feature using a custom API. This patch adds an implementation
of the common reset framework API (include/linux/reset*.h). The legacy
reset implementation will be removed once all drivers have been
converted.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra114.c
lk-tegra124.c
lk-tegra20.c
lk-tegra30.c
lk.c
lk.h
62ce7cd62f534023224912dc9b909963f26a38da 29-Oct-2013 Wei Yongjun <yongjun_wei@trendmicro.com.cn> clk: tegra: fix __clk_lookup() return value checks

In case of error, the function __clk_lookup() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should
be replaced with NULL test.

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-pll.c
8ba4b3b9cc3d95714b31467614205fc26b91fb7c 27-Nov-2013 Thierry Reding <thierry.reding@gmail.com> clk: tegra: Do not print errors for clk_round_rate()

clk_round_rate() can be used by drivers to determine whether or not a
frequency is supported by the clock. The current Tegra clock driver
outputs an error message and a stacktrace when the requested rate isn't
supported. That's fine for clk_set_rate(), but it's confusing when all
the driver does is query whether or not a frequency is supported.

Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-pll.c
39409aa4244f22eae3fa8f8db4b0cf9466b73c44 18-Nov-2013 Thierry Reding <thierry.reding@gmail.com> clk: tegra: Initialize DSI low-power clocks

The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.

Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-tegra114.c
5ab5d4048e6ed8811245a4ea45264456c180545e 21-Nov-2013 Alexandre Courbot <acourbot@nvidia.com> clk: tegra: add FUSE clock device

This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
lk-tegra114.c
lk-tegra124.c
lk-tegra20.c
lk-tegra30.c
c04bf559264de4f986463c639fabef2028542924 29-Oct-2013 Thierry Reding <thierry.reding@gmail.com> clk: tegra: Properly setup PWM clock on Tegra30

The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.

Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-tegra30.c
43e36a9646ec7d0180d638c095cca36484cc6f82 29-Oct-2013 Thierry Reding <thierry.reding@gmail.com> clk: tegra: Initialize secondary gr3d clock on Tegra30

There are two GPUs on Tegra30 and each of them uses a separate clock, so
the secondary clock needs to be initialized in order for the gr3d module
to work properly.

Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-tegra30.c
77f71730341e9072766eabc5bbd001aa286e7a23 29-Oct-2013 Mikko Perttunen <mperttunen@nvidia.com> clk: tegra114: Initialize clocks needed for HDMI

Add disp1 and disp2 clocks to the clock initialization table. These
clocks are required for display and HDMI support.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-tegra114.c
61792e40ca008d60331bb55df5faaa8fe220ac24 26-Sep-2013 Joseph Lo <josephl@nvidia.com> clk: tegra124: add suspend/resume function for tegra_cpu_car_ops

Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
lk-tegra124.c
9e036d3ef0b9fcb34acce5a89d1f2157f4f7b4ab 25-Sep-2013 Joseph Lo <josephl@nvidia.com> clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_ops

Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid warning message.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
lk-tegra124.c
76da314df603a08ebc463853030752251b260ab8 09-Sep-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra124: Add support for Tegra124 clocks

Implement clock support for Tegra124.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
akefile
lk-tegra124.c
3b34d8214dce9bfeef9049de3fe1e8bfbbbb2709 14-Oct-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra124: Add new peripheral clocks

Tegra124 introduces a number of new peripheral clocks. This patch adds those
to the common peripheral clock code.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra-periph.c
6d11632db44169a7b12a98da4853a8e9c96c3c7c 14-Oct-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra124: Add common clk IDs to clk-id.h

Tegra124 introduces a number of a new clocks. Introduce the corresponding
the IDs for them.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-id.h
b29f9e926442c35bd42ebd283aaed0de2c4f1477 18-Nov-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: add TEGRA_PERIPH_NO_GATE

Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-periph.c
lk-tegra-periph.c
lk.h
bc44275b8ea2df7c77658b08955ec545a37560ab 18-Nov-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: add locking to periph clks

Tegra124 has periph clocks which share the hw register. Hence locking is
required.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-tegra-periph.c
lk.h
2b239077d1e2061c65763dcf57ab978ae5261559 11-Sep-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Add periph regs bank X

Tegra124 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk.c
798e910bee3f9ad69a8b16d7e705086852d9f2de 09-Sep-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Add support for PLLSS

Tegra124 introduces a new PLL type, PLLSS. Add support for it.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-pll.c
lk.h
540fc26a02a950a523a62a16d75b87f0e2103584 07-Oct-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: move tegra20 to common infra

Move tegra20 to common tegra clock infrastructure.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra20.c
1bf409159b90804d5e36e4034abc0641555a292f 07-Oct-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: move tegra30 to common infra

Move tegra30 to common tegra clock infrastructure.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra30.c
a7c8485a0ebbdce303c6709e208bb4fd08aff8ad 03-Sep-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: introduce common gen4 super clock

Introduce a common function which performs super clock initialization for
Tegra114 and beyond.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
akefile
lk-tegra-super-gen4.c
lk-tegra114.c
lk.h
de4f30fd8403cd67449fbb9dc06a3d898fb9f10c 15-Oct-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: move PMC, fixed clocks to common files

Introduce new files for fixed and PMC clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
akefile
lk-tegra-fixed.c
lk-tegra-pmc.c
lk-tegra114.c
lk.h
76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8 04-Sep-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: move periph clocks to common file

Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
akefile
lk-tegra-periph.c
lk-tegra114.c
lk-tegra20.c
lk-tegra30.c
lk.h
6609dbe40e199ca8b1e99513d0e4bbc32b0d53b7 17-Sep-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: move audio clk to common file

Move audio clocks and PLLA initialization to a common file so it can be used by
multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114
which specifies which common clocks are available on Tegra114 and what their
DT IDs are.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
akefile
lk-tegra-audio.c
lk-tegra114.c
lk.h
73d37e4c7c4b9db26c9e4e1479e00996caa8e3f2 09-Oct-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: add clkdev registration infra

Add a common infra for registering clkdev. This allows decoupling clk
registration from clkdev registration.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra114.c
lk.c
lk.h
b8700d506ac4050fd96ce9305df04df811365326 14-Oct-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: add common infra for DT clocks

Introduce a common infrastructure for sharing clock initialization between
SoCs.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk.c
lk.h
a59ba9565ee20d162e858de03b9eebc0b9dbd8b6 02-Sep-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: add header for common tegra clock IDs

Many clocks are common between several Tegra SoCs. Define an enum to list
them so we can move them to separate files which can be shared between
SoCs. Each SoC specific file will provide an array with the common clocks
which are present on the SoC and their DT binding ID.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-id.h
ebe142b2ad35d5656caae35d5deefdbebe847d3b 04-Oct-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: move fields to tegra_clk_pll_params

Move some fields related to the PLL HW description to the tegra_clk_pll_params.
This allows some PLL code to be moved to common files later.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-pll.c
lk-tegra114.c
lk-tegra20.c
lk-tegra30.c
lk.h
8e9cc80aa348938078c3c1a7ab55efb3c40990e3 25-Nov-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: use pll_ref as the pll_e parent

Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also
add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents
the system from crashing at bootup because of an unsupported pll_re_vco
rate.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-pll.c
lk-tegra114.c
04edb099a4a7e774a98b241dc016957922cbfb44 06-Sep-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: move some PLLC and PLLXC init to clk-pll.c

VCO min clipping, dynamic ramp setup and IDDQ init can be done in the
respective PLL clk_register functions if the parent is already registered.
This is done for other some PLLs already.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-pll.c
lk-tegra114.c
5bb9d26700c3db54d5a4346c3b6621b8889f3813 02-Sep-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Add TEGRA_PERIPH_NO_DIV flag

This flag indicates the peripheral clock does not have a divider. It will
simplify the initialization tables and avoids some very similar code.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-periph.c
lk.h
343a607cb79259429afbb9820bf524d33084e66c 02-Sep-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: common periph_clk_enb_refcnt and clks

This patch makes periph_clk_enb_refcnt a global array, dynamically allocated
at boottime. It simplifies the macros somewhat and allows clocks common to
several Tegra SoCs to be defined in a separate files. Also the clks array
becomes global and dynamically allocated which allows the DT registration to
be moved to a generic funcion.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-periph.c
lk-tegra114.c
lk-tegra20.c
lk-tegra30.c
lk.c
lk.h
d5ff89a82a6d272d210db68a9487877682c94a24 22-Aug-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: simplify periph clock data

This patch determines the register bank for clock enable/disable and reset
based on the clock ID instead of hardcoding it in the tables describing the
clocks. This results in less data to be maintained in the tables, making the
code easier to understand. The full benefit of the change will be realized once
also other clocktypes will be table based.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-periph-gate.c
lk-periph.c
lk-tegra114.c
lk-tegra20.c
lk-tegra30.c
lk.c
lk.h
00c674e42c278e7af7b39b6c72dbbaa5e7ebd96c 18-Nov-2013 Thierry Reding <thierry.reding@gmail.com> clk: tegra: Fix clock rate computation

The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.

This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.

Signed-off-by: Thierry Reding <treding@nvidia.com>
lk-pll.c
f67a8d21e63876a79f9f94b734049e789d594c7b 02-Oct-2013 Thierry Reding <thierry.reding@gmail.com> clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3d

These clocks were named gr2d and gr3d on Tegra20 and Tegra30, so use the
same names on Tegra114 for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
lk-tegra114.c
642fb0cf517173948684122403d73513c8c8b033 26-Sep-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: PLLE spread spectrum control

Add spread spectrum control for PLLE in Tegra114.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-pll.c
897e1dde1ec1571a28545594633624927fa0a76e 07-Aug-2013 Andrew Chew <achew@nvidia.com> clk: tegra: Set the clk parent of host1x to pll_p

The power-on default parent for this clock is pll_m, which turns out to
be wrong. Previously, bootloader reparented this clock. We'll do it in
the kernel as well, so that there's one less thing that we depend on
bootloader to initialize.

Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
lk-tegra114.c
252d0d2bb07119296e215de7dc9afa8d12746b80 26-Nov-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks

Perform upwards rounding when calculating dividers for periph clks on Tegra30
and Tegra114.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra114.c
lk-tegra30.c
fc20eeff6c03fcdbb2b5ac21472778b573850e77 07-Aug-2013 Mark Zhang <markz@nvidia.com> clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2

pll_m will be the parent of gr2d/gr3d if we don't do this.
And because pll_m runs at a high rate so gr2d/gr3d will be
unstable. So change the parent of them to pll_c2.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra114.c
d17cb95fa0b8676a38c0d07e2da26885d4ff8187 07-Aug-2013 Mark Zhang <markz@nvidia.com> clk: tegra: Fix vde/2d/3d clock src offset

In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
So change the clock init macro for these clocks from
"TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".

Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
remove this macro.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra114.c
2b54ffc2693b917743de6f34815b63638ad3853f 08-Aug-2013 Mark Zhang <markz@nvidia.com> clk: tegra: Correct sbc mux width & parent

Tegra114 sbc1-sbc6 have more possible parent clocks than Tegra30.
So correct the parents and mux width for them.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra114.c
c9e2d69a1801045f28668e6853d9dccadbfbe494 22-Aug-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: replace enum tegra114_clk by binding header

As the clock IDs are now specified in a header file, we can use those
definitions instead of maintaining an internal enum.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
lk-tegra114.c
bef4a0ab984662d4ccd68d431a7c4ef3daebcb43 10-Sep-2013 Linus Torvalds <torvalds@linux-foundation.org> Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux

Pull clock framework changes from Michael Turquette:
"The common clk framework changes for 3.12 are dominated by clock
driver patches, both new drivers and fixes to existing. A high
percentage of these are for Samsung platforms like Exynos. Core
framework fixes and some new features like automagical clock
re-parenting round out the patches"

* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
clk: only call get_parent if there is one
clk: samsung: exynos5250: Simplify registration of PLL rate tables
clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
clk: samsung: exynos4: Register PLL rate tables for Exynos4210
clk: samsung: exynos4: Reorder registration of mout_vpllsrc
clk: samsung: pll: Add support for rate configuration of PLL46xx
clk: samsung: pll: Use new registration method for PLL46xx
clk: samsung: pll: Add support for rate configuration of PLL45xx
clk: samsung: pll: Use new registration method for PLL45xx
clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
clk: samsung: exynos4: Remove checks for DT node
clk: samsung: exynos4: Remove unused static clkdev aliases
clk: samsung: Modify _get_rate() helper to use __clk_lookup()
clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
clocksource: samsung_pwm_timer: Get clock from device tree
ARM: dts: exynos4: Specify PWM clocks in PWM node
pwm: samsung: Update DT bindings documentation to cover clocks
clk: Move symbol export to proper location
clk: fix new_parent dereference before null check
clk: wm831x: Initialise wm831x pointer on init
...
89ac8567b97fea558238c4bb73637471f9197813 28-Aug-2013 Tuomas Tynkkynen <ttynkkynen@nvidia.com> clk: tegra30: Don't wait for PLL_U lock bit

The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra30.c
819c1de344c5b8350bffd35be9a0fa74541292d3 29-Jul-2013 James Hogan <james.hogan@imgtec.com> clk: add CLK_SET_RATE_NO_REPARENT flag

Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.

To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Andrew Chew <achew@nvidia.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-tegra@vger.kernel.org
Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com> [tegra]
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi]
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
lk-tegra20.c
lk-tegra30.c
0017f447cc01fa499f1d10dec09702d381f13fe0 12-Aug-2013 Joseph Lo <josephl@nvidia.com> clk: tegra114: add LP1 suspend/resume support

When the system suspends to LP1, the CPU clock source is switched to
CLK_M (12MHz Oscillator) during suspend/resume flow. The CPU clock
source is controlled by the CCLKG_BURST_POLICY register, and hence this
register must be restored during LP1 resume.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra114.c
4c3b2404b4ef4c70f6b8a424fa1e62c86709569f 08-Aug-2013 Sachin Kamat <sachin.kamat@linaro.org> clk: tegra30: Fix incorrect placement of __initdata

__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra30.c
a0be7a9e6a63d8b2bd8657f34775d3d369a45624 08-Aug-2013 Sachin Kamat <sachin.kamat@linaro.org> clk: tegra20: Fix incorrect placement of __initdata

__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra20.c
056dfcf67ebaa9eb3aff5f35ce98c073157f1d5b 08-Aug-2013 Sachin Kamat <sachin.kamat@linaro.org> clk: tegra114: Fix incorrect placement of __initdata

__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
ad7d114083afda5fbbb52488c42b4a17107c6872 03-Jul-2013 Joseph Lo <josephl@nvidia.com> clk: tegra: add suspend/resume function for tegra_cpu_car_ops

Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra114.c
92295f632cefbdf15d46e9ac5f0fc3cfade35259 03-Jul-2013 Linus Torvalds <torvalds@linux-foundation.org> Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux

Pull clock framework updates from Mike Turquette:
"The common clock framework changes for 3.11 include new clock drivers
across several different platforms and architectures, fixes to
existing drivers, a MAINTAINERS file fix and improvements to the basic
clock types that allow them to be of use to more platforms than before.

Only a few fixes to the core framework are included with most all of
the changes landing in the various clock drivers themselves."

* tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux: (55 commits)
clk: tegra: fix ifdef for tegra_periph_reset_assert inline
clk: tegra: provide tegra_periph_reset_assert alternative
clk: exynos4: Fix clock aliases for cpufreq related clocks
clk: samsung: Add MUX_FA macro to pass flag and alias
clk: add support for Rockchip gate clocks
clk: vexpress: Make the clock drivers directly available for arm64
clk: vexpress: Use full node name to identify individual clocks
clk: tegra: T114: add DFLL DVCO reset control
clk: tegra: T114: add DFLL source clocks
clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL
clk: gate: add CLK_GATE_HIWORD_MASK
clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
clk: mux: add CLK_MUX_HIWORD_MASK
clk: Always notify whole subtree when reparenting
MAINTAINERS: make drivers/clk entry match subdirs
clk: honor CLK_GET_RATE_NOCACHE in clk_set_rate
clk: use clk_get_rate() for debugfs
clk: tegra: Use override bits when needed
clk: tegra: override bits for Tegra30 PLLM
clk: tegra: override bits for Tegra114 PLLM
...
3883cbb6c1bda013a3ce2dbdab7dc97c52e4a232 02-Jul-2013 Linus Torvalds <torvalds@linux-foundation.org> Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC specific changes from Arnd Bergmann:
"These changes are all to SoC-specific code, a total of 33 branches on
17 platforms were pulled into this. Like last time, Renesas sh-mobile
is now the platform with the most changes, followed by OMAP and
EXYNOS.

Two new platforms, TI Keystone and Rockchips RK3xxx are added in this
branch, both containing almost no platform specific code at all, since
they are using generic subsystem interfaces for clocks, pinctrl,
interrupts etc. The device drivers are getting merged through the
respective subsystem maintainer trees.

One more SoC (u300) is now multiplatform capable and several others
(shmobile, exynos, msm, integrator, kirkwood, clps711x) are moving
towards that goal with this series but need more work.

Also noteworthy is the work on PCI here, which is traditionally part
of the SoC specific code. With the changes done by Thomas Petazzoni,
we can now more easily have PCI host controller drivers as loadable
modules and keep them separate from the platform code in
drivers/pci/host. This has already led to the discovery that three
platforms (exynos, spear and imx) are actually using an identical PCIe
host controller and will be able to share a driver once support for
spear and imx is added."

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (480 commits)
ARM: integrator: let pciv3 use mem/premem from device tree
ARM: integrator: set local side PCI addresses right
ARM: dts: Add pcie controller node for exynos5440-ssdk5440
ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
ARM: EXYNOS: Enable PCIe support for Exynos5440
pci: Add PCIe driver for Samsung Exynos
ARM: OMAP5: voltagedomain data: remove temporary OMAP4 voltage data
ARM: keystone: Move CPU bringup code to dedicated asm file
ARM: multiplatform: always pick one CPU type
ARM: imx: select syscon for IMX6SL
ARM: keystone: select ARM_ERRATA_798181 only for SMP
ARM: imx: Synertronixx scb9328 needs to select SOC_IMX1
ARM: OMAP2+: AM43x: resolve SMP related build error
dmaengine: edma: enable build for AM33XX
ARM: edma: Add EDMA crossbar event mux support
ARM: edma: Add DT and runtime PM support to the private EDMA API
dmaengine: edma: Add TI EDMA device tree binding
arm: add basic support for Rockchip RK3066a boards
arm: add debug uarts for rockchip rk29xx and rk3xxx series
arm: Add basic clocks for Rockchip rk3066a SoCs
...
1c472d8e8284917a7687694effcc7ebb6911b63d 07-Jun-2013 Paul Walmsley <pwalmsley@nvidia.com> clk: tegra: T114: add DFLL DVCO reset control

Add DFLL DVCO reset line control functions to the CAR IP block driver.

The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
reset. Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.

Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and
saving hours of debugging time.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Aleksandr Frid <afrid@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
lk.h
9e60121fd18c22851c19ec04e8e58172cb5a7d2c 07-Jun-2013 Paul Walmsley <pwalmsley@nvidia.com> clk: tegra: T114: add DFLL source clocks

Add the input clocks needed by the DFLL IP blocks. Initialize them to
51MHz (as required by the DFLL GFD) and to use the PLL_P clock source.

This patch is a collaboration with Peter De Schrijver
<pdeschrijver@nvidia.com>.

Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the
requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout
issues.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Andrew Chew <achew@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
25c9ded6ed31184379c9b153ff37621fc323b084 07-Jun-2013 Paul Walmsley <pwalmsley@nvidia.com> clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL

Add clock functions to initialize, enable, and disable the FCPU clock
shapers, based on the FCPU voltage rail state. These will be used by
the DFLL clocksource driver code.

This version of the patch contains a fix for a problem noticed by Andrew
Chew <achew@nvidia.com>, where some of the FINETRIM_R bitfields were
incorrectly defined.

Based on code originally written by Aleksandr Frid <afrid@nvidia.com>.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Andrew Chew <achew@nvidia.com>
Reviewed-by: Andrew Chew <achew@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Cc: Aleksandr Frid <afrid@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
lk.h
ff49fad1d9bf2c49f52817b04cde8e4412434637 11-Jun-2013 Jay Agarwal <jagarwal@nvidia.com> ARM: tegra30: clocks: Fix pciex clock registration

Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert)

Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra30.c
7bf15412250747277cc53301d550d4894f749b12 15-Jun-2013 Olof Johansson <olof@lixom.net> Merge tag 'tegra-for-3.11-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc

From Stephen Warren:
ARM: tegra: core SoC support enhancements

This branch contains fixes and enhancement for core Tegra Soc support:
* CPU hotplug support for Tegra114.
* Some preliminary work on Tegra114 CPU sleep modes.
* Minor fix for EMC table DT parsing.

* tag 'tegra-for-3.11-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: don't pass CPU ID to tegra_{set,clear}_cpu_in_lp2
ARM: tegra: cpuidle: using IS_ENABLED for multi SoCs management in init func
ARM: tegra: hook tegra_tear_down_cpu function in the PM suspend init function
ARM: tegra: cpuidle: move the init function behind the suspend init function
ARM: tegra: remove ifdef in the tegra_resume
ARM: tegra: add cpu_disable for hotplug
ARM: tegra114: add CPU hotplug support
clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_ops
ARM: tegra114: add power up sequence for warm boot CPU
ARM: tegra: make tegra_resume can work for Tegra114
ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9
ARM: tegra: add an assembly marco to check Tegra SoC ID
ARM: tegra: emc: correction of ram-code parsing from dt

Signed-off-by: Olof Johansson <olof@lixom.net>
408a24f8227f259eea97c6b4f66d1592e2f651b6 06-Jun-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Use override bits when needed

PLLM has override bits in the PMC. Use those when PLLM_OVERRIDE_ENABLE
is set.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-pll.c
c09e32bb67a9fba318ae4387eaabba21e0d07a87 06-Jun-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: override bits for Tegra30 PLLM

Define override bits for Tegra30 PLLM.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra30.c
d53442e94db0f214989287aa7cd3806cffd1d0b3 06-Jun-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: override bits for Tegra114 PLLM

Define override bits for Tegra114 PLLM.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed up trivial merge conflict]
lk-tegra114.c
7b781c72c97563ba868599f192beb6772c55081b 06-Jun-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Add fields for override bits

PLLM can have override bits in the PMC. Describe those in the PLL parameters.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk.h
29b09447b648ed23ce290994389b3c281a1b6c69 05-Jun-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: fix sclk_parents

Use the correct parents for sclk according to the TRM.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
35d287a9f78dd4d7b080dee2eea3afce73d1bde1 05-Jun-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: fix pllre initilization

The PLLRE flags weren't set correctly. Fixed in this patch.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-pll.c
fd428ad87b1f4a12820de07ecb3a155c51c802c7 05-Jun-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: PLL m,n,p init for Tegra114

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
aa6fefde62401a84154161a8026872874a70e4c1 05-Jun-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: allow PLL m,n,p init from SoC files

The m,n,p fields don't have the same bit offset and width across all PLLs.
This patch allows SoC specific files to indicate the offset and width.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-pll.c
lk.h
c388eee21ad20929f440d6fae94c995791c5818b 05-Jun-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: pllp_out2 divider is int only

The pllp_out2 should be integer only, the fractional bit should always be 0.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
053b525f6f0ef59ac905f0d2e38d39296f8e4fa6 05-Jun-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: pllc and pllxc should use pdiv_map

The pllc and pllxc code weren't always using the correct pdiv_map to
map between the post divider value and the hw p field. This could result
in illegal values being programmed in the hw.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-pll.c
88235988d7ff394f77c0a5a8a9803962d0026ef1 04-Jun-2013 Mikko Perttunen <mperttunen@nvidia.com> clk: tegra114: Fix msenc clock register

The msenc clock's register was set to the usb3 clock's register.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
061cec925f212f145516e826f39962624a738ded 27-May-2013 Prashant Gaikwad <pgaikwad@nvidia.com> clk: tegra: Use common of_clk_init function

Use common of_clk_init() function for clocks initialization.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
lk-tegra20.c
lk-tegra30.c
lk.c
lk.h
9139227d4caef6a8daae8a428f9a4bbb7394ea8b 26-May-2013 Alexandre Courbot <acourbot@nvidia.com> clk: tegra114: correctly output clk_32k

Tegra has a blink timer register that allows to modulate the
clk_32k clock before outputting it. Since clk_32k is presented to the
kernel as a fixed clock, make sure this register does not tamper with
the clock frequency and that clk_32k is outputted as-is, similarly to
what is done on t20 and t30.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
995968e40e74ddf678e8b8312865d7400708d893 27-May-2013 Prashant Gaikwad <pgaikwad@nvidia.com> clk: tegra: fix clk_out parents list

Number of parents for clk_out_2 and clk_out_3 was incorrectly set
to clk_out1_parents. Even though it did not break anything since the
size was same better to fix.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra114.c
lk-tegra30.c
31972fd95527a5942b777e89404501d5421a0df0 20-May-2013 Joseph Lo <josephl@nvidia.com> clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_ops

The conventional CPU hotplug sequence on the other Tegra chips, we will also
clock gate the CPU in tegra_cpu_kill() after the CPU was power gated. For
Tegra114, the flow controller will clock gate the CPU after the power down
sequence. But we still need to implement a empty function for disable_clock
to avoid kernel warning message.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra114.c
6ec3240047ee6a4b34f90d45e19ed179bc9b4a2e 06-May-2013 Lucas Stach <dev@lynxeye.de> clk: tegra: add ac97 controller clock

AC97 controller clock is hardwired to pll_a_out0.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
lk-tegra20.c
7e94984495dbce182260fa3dd15687439236b0a1 06-May-2013 Lucas Stach <dev@lynxeye.de> clk: tegra: remove USB from clk init table

The USB clocks are just clock gates, so no need to set a specific clock.
In fact trying to set a specific clock is just a NOP if the requested
clockrate is the same as those of the parent (clk_m) or will trigger a
WARN_ON() if rates don't match up.

As we are not setting a specific rate, nor activating the clocks at
init, there is no point in keeping the the usb entries in the clock init
table.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
lk-tegra20.c
6fa52ed33bea997374a88dbacbba5bf8c7ac4fef 04-May-2013 Linus Torvalds <torvalds@linux-foundation.org> Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver changes from Olof Johansson:
"This is a rather large set of patches for device drivers that for one
reason or another the subsystem maintainer preferred to get merged
through the arm-soc tree. There are both new drivers as well as
existing drivers that are getting converted from platform-specific
code into standalone drivers using the appropriate subsystem specific
interfaces.

In particular, we can now have pinctrl, clk, clksource and irqchip
drivers in one file per driver, without the need to call into platform
specific interface, or to get called from platform specific code, as
long as all information about the hardware is provided through a
device tree.

Most of the drivers we touch this time are for clocksource. Since now
most of them are part of drivers/clocksource, I expect that we won't
have to touch these again from arm-soc and can let the clocksource
maintainers take care of these in the future.

Another larger part of this series is specific to the exynos platform,
which is seeing some significant effort in upstreaming and
modernization of its device drivers this time around, which
unfortunately is also the cause for the churn and a lot of the merge
conflicts.

There is one new subsystem that gets merged as part of this series:
the reset controller interface, which is a very simple interface for
taking devices on the SoC out of reset or back into reset. Patches to
use this interface on i.MX follow later in this merge window, and we
are going to have other platforms (at least tegra and sirf) get
converted in 3.11. This will let us get rid of platform specific
callbacks in a number of platform independent device drivers."

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits)
irqchip: s3c24xx: add missing __init annotations
ARM: dts: Disable the RTC by default on exynos5
clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
ARM: exynos: restore mach/regs-clock.h for exynos5
clocksource: exynos_mct: fix build error on non-DT
pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
reset: NULL deref on allocation failure
reset: Add reset controller API
dt: describe base reset signal binding
ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
ARM: EXYNOS: Enable PMUs for exynos4
irqchip: exynos-combiner: Correct combined IRQs for exynos4
irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
ARM: EXYNOS: fix compilation error introduced due to common clock migration
clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
clk: exynos4: export clocks required for fimc-is
clk: samsung: Fix compilation error
clk: tegra: fix enum tegra114_clk to match binding
...
99c6bcf46d2233d33e441834e958ed0bc22b190a 02-May-2013 Linus Torvalds <torvalds@linux-foundation.org> Merge tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC multiplatform updates from Olof Johansson:
"More multiplatform enablement for ARM platforms. The ones converted
in this branch are:

- bcm2835
- cns3xxx
- sirf
- nomadik
- msx
- spear
- tegra
- ux500

We're getting close to having most of them converted!

One of the larger platforms remaining is Samsung Exynos, and there are
a bunch of supporting patches in this merge window for it. There was
a patch in this branch to a early version of multiplatform conversion,
but it ended up being reverted due to need of more bake time. The
revert commit is part of the branch since it would have required
rebasing multiple dependent branches and they were stable by then"

* tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms
clocksource: nomadik-mtu: fix up clocksource/timer
Revert "ARM: exynos: enable multiplatform support"
ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ"
ARM: exynos: enable multiplatform support
rtc: s3c: make header file local
mtd: onenand/samsung: make regs-onenand.h file local
thermal/exynos: remove unnecessary header inclusions
mmc: sdhci-s3c: remove platform dependencies
ARM: samsung: move mfc device definition to s5p-dev-mfc.c
ARM: exynos: move debug-macro.S to include/debug/
ARM: exynos: prepare for sparse IRQ
ARM: exynos: introduce EXYNOS_ATAGS symbol
ARM: tegra: build assembly files with -march=armv7-a
ARM: Push selects for TWD/SCU into machine entries
ARM: ux500: build hotplug.o for ARMv7-a
ARM: ux500: move to multiplatform
ARM: ux500: make remaining headers local
ARM: ux500: make irqs.h local to platform
ARM: ux500: get rid of <mach/[hardware|db8500-regs].h>
...
4d26aa305414dbb33b3c32fb205b68004cda8ffc 02-May-2013 Linus Torvalds <torvalds@linux-foundation.org> Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC non-critical fixes from Olof Johansson:
"Here is a collection of fixes (and some intermixed cleanups) that were
considered less important and thus not included in the later parts of
the 3.9-rc cycle.

It's a bit all over the map, contents wise. A series of ux500 fixes
and cleanups, a bunch of various fixes for OMAP and tegra, and some
for Freescale i.MX and even Qualcomm MSM.

Note that there's also a patch on this branch to globally turn off
-Wmaybe-uninitialized when building with -Os. It's been posted
several times by Arnd and no dissent was raised, but nobody seemed
interested to pick it up. So here it is, as the topmost patch."

* tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
Turn off -Wmaybe-uninitialized when building with -Os
ARM: orion5x: include linux/cpu.h
ARM: tegra: call cpu_do_idle from C code
ARM: u300: fix ages old copy/paste bug
ARM: OMAP2+: add dependencies on ARCH_MULTI_V6/V7
ARM: tegra: solve adr range issue with THUMB2_KERNEL enabled
ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabled
ARM: tegra: fix build error when THUMB2_KERNEL enabled
ARM: msm: Fix uncompess.h tx underrun check
ARM: vexpress: Remove A9 PMU compatible values for non-A9 platforms
ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: mach-imx: mach-imx6q: Fix sparse warnings
ARM: mach-imx: src: Include "common.h
ARM: mach-imx: gpc: Include "common.h"
ARM: mach-imx: avic: Staticize *avic_base
ARM: mach-imx: tzic: Staticize *tzic_base
ARM: mach-imx: clk: Include "clk.h"
ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops
...
362ed48dee509abe24cf84b7e137c7a29a8f4d2d 30-Apr-2013 Linus Torvalds <torvalds@linux-foundation.org> Merge tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux

Pull clock framework update from Michael Turquette:
"The common clock framework changes for 3.10 include many fixes for
existing platforms, as well as adoption of the framework by new
platforms and devices.

Some long-needed fixes to the core framework are here as well as new
features such as improved initialization of clocks from DT as well as
framework reentrancy for nested clock operations."

* tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux: (44 commits)
clk: add clk_ignore_unused option to keep boot clocks on
clk: ux500: fix mismatched types
clk: vexpress: Add separate SP810 driver
clk: si5351: make clk-si5351 depend on CONFIG_OF
clk: export __clk_get_flags for modular clock providers
clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate.
clk: sunxi: Unify oscillator clock
clk: composite: allow fixed rates & fixed dividers
clk: composite: rename 'div' references to 'rate'
clk: add si5351 i2c common clock driver
clk: add device tree fixed-factor-clock binding support
clk: Properly handle notifier return values
clk: ux500: abx500: Define clock tree for ab850x
clk: ux500: Add support for sysctrl clocks
clk: mvebu: Fix valid value range checking for cpu_freq_select
clk: Fixup locking issues for clk_set_parent
clk: Fixup errorhandling for clk_set_parent
clk: Restructure code for __clk_reparent
clk: sunxi: drop an unnecesary kmalloc
clk: sunxi: drop CLK_IGNORE_UNUSED
...
494cc7606180bbf0bd7c82afeaacc45d5035d7cc 09-Apr-2013 Arnd Bergmann <arnd@arndb.de> Merge tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/multiplatform

From Stephen Warren <swarren@wwwdotorg.org>:

ARM: tegra: multi-platform conversion

This branch converts Tegra to support multi-platform/single-zImage.

One header is made accessible to drivers. The earlyprintk implementation
is moved to the multi-platform location. Some Kconfig changes are made
to enable multi-platform. Some dead files are deleted.

The APIs exposed in the now-global tegra-powergate.h should be replaced
with standard reset and power domain APIs in the future.

This branch is based on (part of) the previous soc pull request.

* tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: convert to multi-platform
ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h>

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3afeb0a046af159f0ff97a20cf6ebc44d0d2bd64 09-Apr-2013 Arnd Bergmann <arnd@arndb.de> Merge branch 'tegra/soc' into next/multiplatform

This is a dependency for the tegra multiplatform series.

Conflicts:
drivers/clocksource/tegra20_timer.c

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
6abb0576791c95cc7af259ea0372661e39439bde 09-Apr-2013 Arnd Bergmann <arnd@arndb.de> Merge tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/fixes-non-critical

From Stephen Warren <swarren@wwwdotorg.org>:

ARM: tegra: minor fixes

This branch contains a variety of small build and run-time fixes that
weren't important enough for 3.9.

* Enable CPU errata WARs in secondary reset handler as a preparation
for multi-platform support, and a related fix.
* Don't touch DBLGAR in reset/resume handlers, so enable the code to
run on A15 cores.
* Minor build fixes.
* A fix to the Tegra clock driver.
* Some error-handling fixes.

This branch is based on the previous fixes-for-mmc pull request.

* tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: powergate: Don't error out if new state == old state
ARM: tegra: Export tegra_powergate_sequence_power_up()
memory: tegra30: Fix build error w/o PM
ARM: tegra: fix ignored return value of regulator_enable
ARM: tegra: fix the logical detection of power on sequence of warm boot CPUs
ARM: tegra: Fix unchecked return value
ARM: tegra: don't unlock MMIO access to DBGLAR
clk: tegra: No 7.1 super clk dividers on Tegra20
ARM: tegra: remove save/restore of CPU diag register
ARM: tegra: add CPU errata WARs to Tegra reset handler
ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc host

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
964ea47572b89589b61b553e44bbe9907d4f12a6 05-Apr-2013 Stephen Warren <swarren@nvidia.com> clk: tegra: fix enum tegra114_clk to match binding

A gap exists in the binding's clock ID definitions. Fix the clock driver
to be consistent. This allows pclk to be looked up through device tree
and prevents:

ERROR: could not get clock /pmc:pclk(0)

Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra114.c
c604283f52855a4568c18cfd4011bdcfeccf2c52 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Remove forced clk_enable of uartd

The UART driver enables the console uart clock, so we don't need to do that
anymore in this file.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra114.c
27aa99dc0ec188771bd22f2188e56a571368303e 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: devicetree match for nvidia,tegra114-car

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk.c
lk.h
2cb5efefd6f7d3e7df9a7430b910a80515821256 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Implement clocks for Tegra114

Implement clocks for Tegra114.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
akefile
lk-tegra114.c
fdcccbd804088eb96881c9f6532de04868f9dbc1 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Workaround for Tegra114 MSENC problem

Workaround a hardware bug in MSENC during clock enable.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-periph-gate.c
lk.h
a26a029893096204f08a3ff5e262f99e1a75e273 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Add flags to tegra_clk_periph()

We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-periph.c
lk-tegra20.c
lk-tegra30.c
lk.h
c1d1939c5163088e5f12011c6b3a6a9fab40215f 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Add new fields and PLL types for Tegra114

Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-pll.c
lk.h
3e72771e210348fbd7ff0ea1b9e14cd88380c05b 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: move from a lock bit idx to a lock mask

PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-pll.c
lk-tegra20.c
lk-tegra30.c
lk.h
0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Add PLL post divider table

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-pll.c
lk-tegra20.c
lk-tegra30.c
lk.h
7ba28813b41120dd67329fd04dc732ea7fef05a0 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE

Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-pll.c
lk.h
dd93587be8dc8acf23a0d8a23efc74a91d8f0dfe 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Add TEGRA_PLL_BYPASS flag

Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-pll.c
lk.h
dba4072a4a20b2986562cced98ce04a887614528 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Refactor PLL programming code

Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.

The following changes were done:

* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()
* Split _tegra_clk_register_pll()

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-pll.c
lk-tegra20.c
lk-tegra30.c
lk.h
6a676fa0af4e2bd11ab3950e277e81a959a9a198 03-Apr-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: provide dummy cpu car ops

tegra_boot_secondary() relies on some of the car ops. This means having an
uninitialized tegra_cpu_car_ops will lead to an early boot panic.
Providing a dummy struct avoids this and makes adding Tegra114 clock support
in a bisectable way a lot easier.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk.c
441f199a37cfd66c5dd8dd45490bd3ea6971117d 25-Mar-2013 Stephen Warren <swarren@nvidia.com> clk: tegra: defer application of init table

The Tegra clock driver is initialized during the ARM machine descriptor's
.init_irq() hook. It can't be initialized earlier, since dynamic memory
usage is required. It can't be initialized later, since the .init_timer()
hook needs the clocks initialized. However, at this time, udelay()
doesn't work.

The Tegra clock initialization table may enable some PLLs. Enabling a PLL
may require usage of udelay(). Hence, this can't happen right when the
clock driver is initialized.

To solve this, separate the clock driver initialization from the clock
table processing, so they can execute at separate times.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra20.c
lk-tegra30.c
lk.c
lk.h
82ce742140f32394cc5be75f1c98cdbbff284582 04-Apr-2013 Prashant Gaikwad <pgaikwad@nvidia.com> clk: tegra: Fix cdev1 and cdev2 IDs

Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra20.c
lk-tegra30.c
ce910686f814fe220f4e55ecca5cfdea7082b3de 02-Apr-2013 Thierry Reding <thierry.reding@avionic-design.de> clk: tegra: Make gr2d and gr3d clocks children of pll_c

By default these clocks are children of pll_m, but in downstream kernels
they are reparented to pll_c. While at it, decrease their frequencies to
300 MHz because the defaults aren't in the specified range.

gr2d can reportedly run at much higher frequencies, but 300 MHz works
and is a more conservative default.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra20.c
lk-tegra30.c
4dd59cdd35506b77ed4ebf4bb90347d7653ba585 28-Mar-2013 Thierry Reding <thierry.reding@avionic-design.de> clk: tegra: Export peripheral reset functions

The tegra_periph_reset_assert() and tegra_periph_reset_deassert()
functions can be used by drivers to reset peripherals. In order to allow
such drivers to be built as modules, export the functions.

Note that this restores the status quo as the functions were exported
before the move to the drivers/clk tree.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-periph.c
5a88b0d10f198ddd5f988f40d34b52f34c87a5c6 06-Mar-2013 Yen Lin <yelin@nvidia.com> clk: tegra: Fix periph_clk_to_bit macro

The parameter name should be "gate", not "periph". This worked, however,
because it happens that everywhere periph_clk_to_bit is called, "gate" was
in the local scope.

Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Andrew Chew <achew@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-periph-gate.c
43089433b00a086980fc6e9571535477fb749e84 05-Apr-2013 Stephen Warren <swarren@nvidia.com> Merge remote-tracking branch 'linaro_mturquette_linux/clk-for-3.10' into for-3.10/clk
8aa15d82df291b398d604b527a20310f10c1c706 05-Apr-2013 Stephen Warren <swarren@nvidia.com> Merge branch 'for-3.10/soc' into for-3.10/clk
0f1bc12e9eddaba2baf52d020d37670dbabe3702 14-Mar-2013 Thierry Reding <thierry.reding@avionic-design.de> clk: tegra: Allow PLLE training to succeed

Under some circumstances the PLLE needs to be retrained, in which case
access to the PMC registers is required. Fix this by passing a pointer
to the PMC registers instead of NULL when registering the PLLE clock.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk-tegra20.c
e4bcda28344cc4762c57ad7333f0472a39e83479 30-Mar-2013 Stephen Warren <swarren@nvidia.com> ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h>

This is required so that code such as Tegra's PCIe and clock drivers
can still access this header file once Tegra is converted to
multiplatform, and <mach/> no longer exists.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra30.c
ce4f3313b05c836c21a91ac89f87dccf84ce9561 22-Mar-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: add table lookup to mux

Add a table lookup feature to the mux clock. Also allow arbitrary masks
instead of the width. This will be used by some clocks on Tegra114. Also
adapt the tegra periph clk because it uses struct clk_mux directly.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
lk.h
bf161d2163f7b8bf4823829dbc1a14111760187e 08-Feb-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: No 7.1 super clk dividers on Tegra20

Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk.
Remove the clocks related to the divider.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra20.c
984b839337da1eb7b4a4fb50e24cf28c2b473862 01-Mar-2013 Prashant Gaikwad <pgaikwad@nvidia.com> clk: Tegra: Remove duplicate smp_twd clock

Remove duplicate smp_twd clocks as these clocks are accessed using
DT now.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
lk-tegra20.c
lk-tegra30.c
527fad1bc519df8eedd397482febb51526e5d987 12-Feb-2013 Laxman Dewangan <ldewangan@nvidia.com> clk: tegra: initialise parent of uart clocks

Initialise the parent of UARTs to PLLP and disabling clock by
default.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra20.c
lk-tegra30.c
0203d91247090e57063e1ef63a6019e87548dfbc 12-Feb-2013 Stephen Warren <swarren@nvidia.com> clk: tegra: fix driver to match DT binding

enum tegra*_clk is intended to match the IDs listed in the Tegra clock
bindings. There are a few mismatches, which this patch fixes:

1) pll_s and cop were left out of the Tegra20 enum.

2) spdif_in and spdif_out were swapped relative to the Tegra30 binding.

3) i2cslow was misnamed as i2c_slow, and a duplicate i2cslow clock added
to the Tegra30 enum.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
lk-tegra20.c
lk-tegra30.c
b4c154a339b7efe48f2801d7fb10199c57dddafd 07-Feb-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: local arrays should be static

cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within
clk-tegra30.c. Declare them static to avoid namespace polution.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra30.c
d076a206b2dfa8ef7a735289fe1221e77d1fa83f 07-Feb-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Add missing spinlock for hclk and pclk

The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra20.c
lk-tegra30.c
c64c65d494ade53fa41fb0b980381807743b5095 07-Feb-2013 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: Implement locking for super clock

Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
actually used by the code. Fixed with this patch.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-super.c
22ca335f6db9cf614696bbcb83eb0b80db7b4110 07-Feb-2013 Joseph Lo <josephl@nvidia.com> clk: tegra: fix wrong clock index between se to sata_cold

The index of se should be 127. And the previous clock index was 125. So
we need to set up the index for se to get the correct index between se
to sata_cold.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra30.c
4a2e32794e71db679b91df1d9c98921b2e32ec4e 15-Jan-2013 Joseph Lo <josephl@nvidia.com> clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_ops

Implementing suspend, resume and rail_off_ready API for tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra20.c
ef3ffe5a0458606c488def757bb7f6dd013c2db5 11-Jan-2013 Prashant Gaikwad <pgaikwad@nvidia.com> clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()s

With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra30.c
e5dd26302275562d8bedf885e7aa91bd73bfa041 11-Jan-2013 Prashant Gaikwad <pgaikwad@nvidia.com> clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s

With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-tegra20.c
61fd290d213e25d5a119b8ca25644001ed9f8f2d 11-Jan-2013 Prashant Gaikwad <pgaikwad@nvidia.com> ARM: tegra: migrate to new clock code

Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: use to_clk_periph_gate().]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
lk-periph.c
lk.c
b08e8c0ecc42afa3a2e1019851af741980dd5a6b 11-Jan-2013 Prashant Gaikwad <pgaikwad@nvidia.com> clk: tegra: add clock support for Tegra30

Add Tegra30 clock support based on common clock framework.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: ensure all OF lookups return valid cookies i.e. an explicit
error pointer or valid pointer not NULL, adapt to renames in earlier
patches, fixed some checkpatch issues.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
akefile
lk-tegra30.c
lk.h
37c26a906527b8a6a252614ca83d21ad318c4e84 11-Jan-2013 Prashant Gaikwad <pgaikwad@nvidia.com> clk: tegra: add clock support for Tegra20

Add Tegra20 clock support based on common clock framework.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: s/1GHz/100MHz/ in call to tegra_clk_plle() to fix PCIe,
implemented KBC clock, ensure all OF lookups return valid cookies i.e.
an explicit error pointer or valid pointer not NULL, adapt to renames
in earlier patches, fixed some checkpatch issues.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
akefile
lk-tegra20.c
lk.h
8f8f484bf355e546c62c47b8a8c8d19b28787798 11-Jan-2013 Prashant Gaikwad <pgaikwad@nvidia.com> clk: tegra: add Tegra specific clocks

Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
akefile
lk-audio-sync.c
lk-divider.c
lk-periph-gate.c
lk-periph.c
lk-pll-out.c
lk-pll.c
lk-super.c
lk.c
lk.h