Cross Reference: /external/mesa3d/src/gallium/drivers/radeon/

History log of /external/mesa3d/src/gallium/drivers/radeon/
Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
542f6feda9bf18267dbd337943a5e871400d425a	06-Sep-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove R600InstrInfo.td from TD_FILES Fixes build bug introduced by cebbdd4ac23725963207bf6f8fc7101150e6065f (cherry picked from commit 2baaa5c7eb21517f0197bfd91154e9b4886fbb1b) akefile.sources
71b5503164deee189df5ac4e2b8d2fcd09a8ec55	29-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Cleanup makefile Hopefully, this will fix all the parallel make problems people have been having. (cherry picked from commit cebbdd4ac23725963207bf6f8fc7101150e6065f) akefile akefile.sources
2809ae3d445bc10a79f119946439431ba73bb069	29-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Fix encoding of FP immediates on SI CTargetDesc/SIMCCodeEmitter.cpp
05113fd2662eeb0d17fd1074001b7405eeeca43c	29-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Create a register class for the M0 register The Common Subexpression Elimination pass will not operate on instructions with physical register defs, so we end up with several redundant copies to M0 when using interpolation. Adding a register class that only contains the M0 register allows use to use a virtual register to represent M0, and makes it possible for the Common Subexpression Elimination pass to remove the extra copies. IGenRegisterInfo.pl IISelLowering.cpp IISelLowering.h IInstrInfo.td IInstructions.td
733c28a0d95c1da87b14ef893f8a59b1f940322a	29-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Set the neverHasSideEffects bit on more instructions This flag makes these instructions candidates for the dead code elimination and common subexpression elimination. IInstructions.td
cf4ac69928eb17685958e6b3b01b97544560d90e	29-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Declare the interpolation intrinsics as ReadOnly This signals to the Dead Code Elimination pass that it is safe to remove these instructions when they are dead. IInstrInfo.td IIntrinsics.td
73a2c4b9db638cad83e412097ed3433649aab47b	28-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Mark M0 as a def when lowering interpolation instructions IISelLowering.cpp
70f9dbe298043f0e3914e6956ddcc0a098f7eca3	28-Aug-2012	Michel Dänzer <michel.daenzer@amd.com>	radeon/llvm: Handle TGSI KIL opcode for SI. Fixes piglit fp-kil and glBitmap() with radeonsi. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> IISelLowering.cpp IISelLowering.h IInstructions.td
16e42a5dd065c09f6d561537009639906b22ce45	28-Aug-2012	Michel Dänzer <michel.daenzer@amd.com>	radeon/llvm: Basic support for SI EXEC register. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> MDGPUAsmPrinter.cpp IGenRegisterInfo.pl IInstructions.td
f402acdbe244e5de9b2b616e0a908f5d1416ce89	22-Aug-2012	Michel Dänzer <michel.daenzer@amd.com>	radeonsi: Use FP16 shader export format when necessary / possible. Fixes piglit fbo-blending-formats. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> IInstructions.td IIntrinsics.td
167ecf5ba358f750aecb07439ef5110e72895f25	24-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Cleanup R600Instructions.td 600InstrInfo.cpp 600Instructions.td
1434a86f50e4ffc69316c7e948ebfe56a25d31da	23-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Set End of Program bit on RAT instructions This code was accidently dropped during the MCCodeEmitter conversion. CTargetDesc/R600MCCodeEmitter.cpp 600ISelLowering.cpp 600Instructions.td
1bd7b29a661a336dbc96c160197c739657991ef3	23-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use correct instruction for moving immediates This should fix an assertion failure that was happening in some compute shaders. 600ISelLowering.cpp
2ad8608cb3e6a8d2f375ad2295504167b082711f	23-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Fix some coding style issues MDGPUAsmPrinter.cpp MDGPUAsmPrinter.h MDGPUMCInstLower.cpp MDGPUMCInstLower.h MDGPUSubtarget.cpp CTargetDesc/AMDGPUMCAsmInfo.cpp CTargetDesc/AMDGPUMCTargetDesc.cpp CTargetDesc/R600MCCodeEmitter.cpp CTargetDesc/SIMCCodeEmitter.cpp 600ExpandSpecialInstrs.cpp 600ISelLowering.cpp 600InstrInfo.cpp 600InstrInfo.h 600KernelParameters.cpp
228a6641ccddaf24a993f827af1e97379785985a	23-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Pull changes from external version of the backend MDGPUISelLowering.h MDIL7XXDevice.cpp MDIL7XXDevice.h MDILDevice.h MDILEvergreenDevice.cpp MDILEvergreenDevice.h MDILIntrinsicInfo.cpp MDILIntrinsicInfo.h CTargetDesc/AMDGPUAsmBackend.cpp CTargetDesc/AMDGPUMCAsmInfo.cpp CTargetDesc/AMDGPUMCAsmInfo.h CTargetDesc/AMDGPUMCTargetDesc.cpp CTargetDesc/AMDGPUMCTargetDesc.h CTargetDesc/AMDILMCAsmInfo.cpp CTargetDesc/AMDILMCAsmInfo.h CTargetDesc/AMDILMCTargetDesc.cpp CTargetDesc/AMDILMCTargetDesc.h CTargetDesc/R600MCCodeEmitter.cpp CTargetDesc/SIMCCodeEmitter.cpp akefile.sources 600ISelLowering.cpp 600RegisterInfo.cpp IAssignInterpRegs.cpp IRegisterInfo.cpp argetInfo/AMDGPUTargetInfo.cpp argetInfo/AMDILTargetInfo.cpp
5a1edb8655aeab17bf0d90e202fb31a1adb53498	23-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Simplify the convert to ISA pass MDGPUConvertToISA.cpp MDGPUInstrInfo.cpp MDGPUInstrInfo.h
cb5227b403a9c78a734e5e67657da6c485881cbb	23-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Make sure to use the Text section in the AsmPrinter MDGPUAsmPrinter.cpp
90bd1d52bbf95947955a66ec67f5f6c7dc87119a	21-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use the MCCodeEmitter for R600 MDGPU.h MDGPUInstrInfo.h MDGPUMCInstLower.cpp MDGPUTargetMachine.cpp MDGPUTargetMachine.h CTargetDesc/AMDILMCTargetDesc.cpp CTargetDesc/AMDILMCTargetDesc.h CTargetDesc/R600MCCodeEmitter.cpp CTargetDesc/SIMCCodeEmitter.cpp akefile.sources 600CodeEmitter.cpp 600Defines.h 600ExpandSpecialInstrs.cpp 600ISelLowering.cpp 600InstrInfo.cpp 600InstrInfo.h
235318a578b3d7772a60590c7e76791ed6d1a78e	17-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use the MCCodeEmitter for SI MDGPUAsmPrinter.cpp MDGPUAsmPrinter.h MDGPUTargetMachine.cpp CTargetDesc/AMDGPUAsmBackend.cpp CTargetDesc/AMDGPUMCCodeEmitter.h CTargetDesc/AMDILMCAsmInfo.cpp CTargetDesc/AMDILMCTargetDesc.cpp CTargetDesc/AMDILMCTargetDesc.h CTargetDesc/SIMCCodeEmitter.cpp akefile akefile.sources ICodeEmitter.cpp IInstrInfo.cpp IInstrInfo.h adeon_llvm_emit.cpp
2de24024c1ca5366e76f449b115392a97808ef2d	17-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Set 64BitPtr feature bit for SI rocessors.td
3f9b6aa0f467b8d918ce277697db2f42abe1cf4c	17-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SI MDILInstrInfo.td 600Instructions.td IInstructions.td
e30b4644b613a130318cdf240ad237b0afbc525a	17-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add AsmPrinter MDGPUAsmPrinter.cpp MDGPUAsmPrinter.h MDGPUMCInstLower.cpp MDGPUMCInstLower.h nstPrinter/AMDGPUInstPrinter.cpp nstPrinter/AMDGPUInstPrinter.h CTargetDesc/AMDILMCTargetDesc.cpp akefile.sources
e61c54cb6b220dea243568919a001e5dc7c01303	16-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Mark JUMP as a pseudo instruction 600Instructions.td
ead72204f1864008430189421663a5d07a02293b	23-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove the last uses of MachineOperand flags 600InstrInfo.cpp 600InstrInfo.h
67a47a445b544ac638d10303dc697d70f25d12fb	22-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add flag operand to some instructions This new operand replaces the MachineOperand flags in LLVM, which will be deprecated soon. Eventually all instructions should have a flag operand, but for now this operand has only been added to instructions that need it. MDGPUInstrInfo.h 600CodeEmitter.cpp 600ExpandSpecialInstrs.cpp 600ISelLowering.cpp 600InstrInfo.cpp 600InstrInfo.h 600Instructions.td
3a7a56e7aa56bc6cb847c241ef6bd749713ae6e1	21-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Encapsulate setting of MachineOperand flags MachineOperand flags will be removed soon, so it is convienent to have only one function that modifies them. 600ExpandSpecialInstrs.cpp 600ISelLowering.cpp 600InstrInfo.cpp 600InstrInfo.h
1cb07bd3b8abd5e52e9dbd80bb1666058545387e	21-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: ExpandSpecialInstrs - Add support for cube instructions 600CodeEmitter.cpp 600ExpandSpecialInstrs.cpp 600InstrInfo.cpp 600Instructions.td
6c99f2101fbd3edb7d5899c44ca9d984a3c0f8b6	21-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: ExpandSpecialInstrs - Add support for vector instructions 600CodeEmitter.cpp 600ExpandSpecialInstrs.cpp
82a5d0c64142990236b40567561b6e99b7158216	20-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add R600ExpandSpecialInstrs pass This pass expends reduction instructions into a MachineInstrBundle that contains 4 instruction, one for each instruction slot. MDGPU.h MDGPUInstrInfo.h MDGPUTargetMachine.cpp akefile.sources 600CodeEmitter.cpp 600ExpandSpecialInstrs.cpp
05882985757e655f5298af483c881008d45e6249	20-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add helper function for getting sub reg indices 600InstrInfo.cpp 600RegisterInfo.cpp 600RegisterInfo.h
926a4a922f9a5ec397cb3d316dd915b00b39c54d	18-Aug-2012	Mathias Fröhlich <Mathias.Froehlich@gmx.net>	radeon-llvm: Start multithreaded before using llvm. This is required to make some of llvm's api calls thread save. In particular the PassRegistry, which is implicitly accessed while compiling shader programs. The PassRegistry uses a mutex that is only active if the llvm_is_multithreaded() returns true. Calling llvm_start_multithreading() makes this happen and by calling this function we try to make sure that we can savely compile shaders in paralell. Since there is also a call llvm_stop_multithreading() in the llvm api, we cannot guarantee that this does not get switched off while we are relying on this being set, but for the easier use cases this fixes a race with the radeon llvm compiler we have as of today. Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de> Signed-off-by: Tom Stellard <thomas.stellard@amd.com> adeon_llvm_emit.cpp
5f82d1924831da7467bfe8025ca18e98b9548ca4	16-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Lower implicit parameters before ISel 600ISelLowering.cpp 600ISelLowering.h 600Instructions.td
565a4e2a8625c79bde0eacf674a4f633151eeb0e	01-Aug-2012	Vincent Lejeune <vljn@ovi.com>	radeon/llvm: Enable if-cvt Signed-off-by: Tom Stellard <thomas.stellard@amd.com> MDGPUTargetMachine.cpp
a614979286f8d329af318c1e9fb067e17cab4315	01-Aug-2012	Vincent Lejeune <vljn@ovi.com>	radeon/llvm: Add callbacks needed by if-cvt Signed-off-by: Tom Stellard <thomas.stellard@amd.com> 600InstrInfo.cpp 600InstrInfo.h
0eca5fd919b0a31ea926b5f5072e5e56f7a55269	01-Aug-2012	Vincent Lejeune <vljn@ovi.com>	radeon/llvm: Lower branch/branch_cond into predicated jump Signed-off-by: Tom Stellard <thomas.stellard@amd.com> MDGPUInstrInfo.cpp MDGPUInstrInfo.h MDILCFGStructurizer.cpp MDILInstrInfo.td 600ISelLowering.cpp 600InstrInfo.cpp 600InstrInfo.h
6db2e9fdb0a35e27e6fc86a1485918b78717a425	01-Aug-2012	Vincent Lejeune <vljn@ovi.com>	radeon/llvm: Add a predicated JUMP instruction Signed-off-by: Tom Stellard <thomas.stellard@amd.com> 600Instructions.td
8263408a91b6b3beb5af5de6bdc7e5d13197a268	01-Aug-2012	Vincent Lejeune <vljn@ovi.com>	radeon/llvm: Support for predicate bit Tom Stellard: - A few changes to predicate register defs Signed-off-by: Tom Stellard <thomas.stellard@amd.com> MDGPUInstrInfo.h 600CodeEmitter.cpp 600GenRegisterInfo.pl 600ISelLowering.cpp 600InstrInfo.cpp 600InstrInfo.h 600Instructions.td 600RegisterInfo.cpp
4444b9d1ecddb09468d2878ffb1463a66ea0ffd3	12-Aug-2012	Christian König <deathsimple@vodafone.de>	radeon/llvm: add support to fetch temps as vectors Necessary for texture fetches with temp regs as source on SI. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> adeon_setup_tgsi_llvm.c
b6051bc7859829588b2361da96f8e828a7fe1326	26-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDGPUUtil.cpp MDGPUISelLowering.cpp MDGPUUtil.cpp MDGPUUtil.h akefile.sources 600ISelLowering.cpp IAssignInterpRegs.cpp ICodeEmitter.cpp IRegisterInfo.cpp
040c2e04568e2fe9ec07167f5300a3dcdfebb04e	26-Jul-2012	Apostolos Bartziokas <barz621@gmail.com>	radeon/llvm: Cleanup AMDGPUUtil.cpp MDGPUInstrInfo.h MDGPUUtil.cpp MDGPUUtil.h 600CodeEmitter.cpp 600InstrInfo.cpp 600InstrInfo.h
3aaa209293a281e103ef71e3578fad042972e092	26-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Lower loads from USE_SGPR adddress space during DAG lowering MDGPUISelLowering.cpp MDGPUISelLowering.h IISelLowering.cpp IISelLowering.h IInstructions.td
40c41fe890e53d99afb4e2c3fbf10043081edd9e	25-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add live-in registers during DAG lowering Psuedo instructions emulating live-in registers have been removed and their corresponding intrinsics are now being lowered during DAG lowering. MDGPUISelLowering.cpp MDGPUISelLowering.h MDGPUUtil.cpp 600ISelLowering.cpp 600Instructions.td IISelLowering.cpp IInstructions.td IIntrinsics.td
f3480f92349c90f55e2e80d9a4536ab048fb5652	26-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Lower store_output intrinsic during DAG lowering MDGPUIntrinsics.td 600ISelLowering.cpp 600Instructions.td
a76a0f74225802f4d3f11028ab54afe98b26302b	15-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Force VTX_READ instructions to use same reg for src and dst I was seeing some GPU hangs that seemed to be cause by ALU instructions writing to the same register used as the source for VTX_READ. Adding this constraint to the VTX_READ instructions avoids this situation. 600Instructions.td
b49771970bb8d06a179da69a7eb6b0af1b379d2d	01-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Inline immediate offset when lowering implicit parameters 600ISelLowering.cpp
2fae8227ad906a6d6290134368b62f5dd3a1858e	13-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use correct opcocde for BREAK_LOGICALNZ_i32 600CodeEmitter.cpp
f6ad8b45c2731075d91f43e92862847f2c26e95a	02-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add $(LLVM_LDFLAGS) to the loader linker flags akefile
4a89a207179d8cf25f259aba8e6c867de42bae54	02-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add support for more f32 CMP instructions on SI IInstructions.td
a35eea786823f0130b925cb25486d7d162f2d68c	02-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add support for fneg on SI IISelLowering.cpp IInstructions.td
4104bae063a3a06ddc00371a576ad0a55f520473	02-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add support for fp_to_sint on SI IInstructions.td
f7fcaa07df7b3aab124576dec346ae4fa7c6715b	02-Aug-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove CMOVLOG DAG node MDGPUISelLowering.cpp MDGPUISelLowering.h MDILISelLowering.cpp MDILInstrInfo.td 600ISelLowering.cpp 600Instructions.td
93b4f1f97ea961f09218c9cf7d928e499f267f58	02-Aug-2012	Michel Dänzer <michel.daenzer@amd.com>	radeonsi: Handle TGSI DIV opcode. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> IInstructions.td
a3c6607be19af895ed6857c0a82b9b0821893dc6	01-Aug-2012	Christian König <deathsimple@vodafone.de>	radeon/llvm: fix fp immediates on SI I don't know if this is a good idea, but it fixes the problem at hand. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> ICodeEmitter.cpp
6574fe3c4a9e36791cde88dfd73429ba4faf3215	31-Jul-2012	Christian König <deathsimple@vodafone.de>	radeon/llvm: fix calculation of max register number Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> ICodeEmitter.cpp
a488fdd3d97a6e9fa1ff8b8d22193551391170d3	31-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add pseudo-support for 64-bit immediate types on SI SI does not support 64-bit immediates natively, but llvm will generate i64 immediates when indexing loads and stores (since SI has 64-bit pointers). The i64 indices will always be small enough to fit into 32-bits (i.e. the high 32 bits will always be all zeros), so we can treat these index values as 32-bits. IInstrInfo.td IInstructions.td
be468742811364f55a81d7f49164a60291bdd5ff	31-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Fix incorrect return value in SelectADDRReg() We need to return true when we match the pattern. MDILISelDAGToDAG.cpp
056b77ca22a3e7a2e24a32941daf65313f604042	31-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Move SMRD IMM pattern before SMRD SGPR pattern In tablegen, if two patterns match, the one that comes first in the file is given preference. We want the SMRD IMM pattern to be given preference, because it encodes the pointer offset in its immediate field, which saves us an add instruction. IInstrInfo.td
cd0949eb2869ec37b135fdff2110090008bbcff6	30-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Cleanup AMDIL.h MDIL.h MDILCFGStructurizer.cpp MDILISelDAGToDAG.cpp MDILPeepholeOptimizer.cpp
2f921101c0826dc52a2c69f85c3da0f7f6e8212a	30-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Rename all AMDIL* classes to AMDGPU* MDGPUSubtarget.cpp MDGPUSubtarget.h MDGPUTargetMachine.cpp MDGPUTargetMachine.h MDIL.h MDIL7XXDevice.cpp MDIL7XXDevice.h MDILBase.td MDILCFGStructurizer.cpp MDILDevice.cpp MDILDevice.h MDILDeviceInfo.cpp MDILDeviceInfo.h MDILEvergreenDevice.cpp MDILEvergreenDevice.h MDILFrameLowering.cpp MDILFrameLowering.h MDILISelDAGToDAG.cpp MDILISelLowering.cpp MDILInstrInfo.td MDILIntrinsicInfo.cpp MDILIntrinsicInfo.h MDILNIDevice.cpp MDILNIDevice.h MDILPeepholeOptimizer.cpp MDILSIDevice.cpp MDILSIDevice.h 600Instructions.td 600KernelParameters.cpp IInstructions.td
b72ab79d73b29ec087d90cf2c698adbab4db5def	30-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtarget MDGPUSubtarget.cpp MDGPUSubtarget.h MDGPUTargetMachine.cpp MDIL7XXDevice.cpp MDIL7XXDevice.h MDILDevice.cpp MDILDevice.h MDILDeviceInfo.cpp MDILDeviceInfo.h MDILEvergreenDevice.cpp MDILEvergreenDevice.h MDILISelDAGToDAG.cpp MDILISelLowering.cpp MDILIntrinsicInfo.cpp MDILNIDevice.cpp MDILNIDevice.h MDILPeepholeOptimizer.cpp MDILSIDevice.cpp MDILSIDevice.h MDILSubtarget.cpp MDILSubtarget.h akefile.sources 600CodeEmitter.cpp 600InstrInfo.cpp ICodeEmitter.cpp
27ae41c83dafcec09e870b3cf08b060064dbb122	30-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLowering MDGPUISelLowering.cpp MDGPUISelLowering.h MDGPUInstrInfo.cpp MDILISelLowering.cpp MDILISelLowering.h MDILInstrInfo.td 600ISelLowering.cpp 600InstrInfo.cpp ICodeEmitter.cpp IISelLowering.cpp IInstrInfo.cpp
c96490e3b5ea0e369837dbb8067cf3d6b0d6b767	30-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove IL_cmp DAG node MDIL.h MDILISelLowering.cpp MDILISelLowering.h MDILInstrInfo.td
aece7970eb171ec6c28c412d22f42362b4f52bac	27-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Cleanup and reorganize AMDIL .td files MDGPU.td MDILBase.td MDILEnumeratedTypes.td MDILFormats.td MDILInstrInfo.td MDILInstructions.td MDILIntrinsics.td MDILMultiClass.td MDILNodes.td MDILOperands.td MDILPatterns.td MDILProfiles.td MDILTokenDesc.td
0ce6e506016222b264163ee718202371f19064db	27-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove lowering code for unsupported features e.g. function calls, load/store from stack MDGPUISelLowering.cpp MDGPUISelLowering.h MDGPUInstrInfo.cpp MDILBase.td MDILCallingConv.td MDILISelLowering.cpp MDILISelLowering.h MDILInstructions.td
caeaf43dad367a9a39d2f42d91731148f6dfdf32	27-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILVersion.td MDGPU.td MDILVersion.td
c3111eb639f3ff1f4e320325c325cc21efe58ca3	27-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILAlgorithms.tpp MDILAlgorithms.tpp MDILPeepholeOptimizer.cpp
ac669c32c6e80841e3ee63d65b58c0031b22e7b8	27-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Merge AMDILInstrInfo.cpp into AMDGPUInstrInfo.cpp MDGPUInstrInfo.cpp MDGPUInstrInfo.h MDGPUUtil.cpp MDIL.h MDILCFGStructurizer.cpp MDILISelDAGToDAG.cpp MDILInstrInfo.cpp MDILInstrInfo.h MDILPeepholeOptimizer.cpp akefile.sources 600CodeEmitter.cpp 600InstrInfo.h
3a0187b1b53eca3143286a5ae7917cd71117b902	27-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Merge AMDILRegisterInfo into AMDGPURegisterInfo MDGPURegisterInfo.cpp MDGPURegisterInfo.h MDIL.h MDILCFGStructurizer.cpp MDILISelDAGToDAG.cpp MDILISelLowering.cpp MDILInstrInfo.cpp MDILInstrInfo.h MDILRegisterInfo.cpp MDILRegisterInfo.h akefile.sources 600RegisterInfo.h
9c42fb6f26bb7db1bc793f5fcc922bbae6700d74	27-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Change the tablegen target from AMDIL to AMDGPU MDGPUCodeEmitter.h MDGPUSubtarget.cpp MDGPUSubtarget.h MDILBase.td MDILCodeEmitter.h MDILInstrInfo.cpp MDILInstrInfo.h MDILRegisterInfo.cpp MDILRegisterInfo.h MDILSubtarget.cpp MDILSubtarget.h CTargetDesc/AMDILMCTargetDesc.cpp akefile.sources 600CodeEmitter.cpp ICodeEmitter.cpp
c9ef27276f83b021221fb7e2c7397719e143709c	25-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add instruction defs for branches on SI MDILCFGStructurizer.cpp IInstrInfo.td IInstructions.td
ee0f0f03c6c174a160e5fb3882ec5c03cdfcd163	26-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Fix VOPC and V_CNDMASK encoding IISelLowering.cpp IInstrFormats.td IInstrInfo.td IInstructions.td
d4bdd09d4714ae51b9f5675f7f5c678d431061e8	25-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Assert if we try to copy SCC reg IInstrInfo.cpp
fd1f19a191c648e7c6fdaac3167e900e4fed4a6d	25-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add SI DAG optimizations for setcc, select_cc These are needed for correctly lowering branch instructions in some cases. IISelLowering.cpp IISelLowering.h
cd5d4c50738b15c4885105ef4dcc89a1ea9e02fb	25-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add support for encoding SI branch instructions ICodeEmitter.cpp
50ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48	25-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add special nodes for SALU operations on VCC The VCC register is tricky because the SALU views it as 64-bit, but the VALU views it as 1-bit. In order to deal with this we've added some special bitcast and binary operations to help convert from the 64-bit SALU view to the 1-bit VALU view and vice versa. MDGPUISelLowering.h IISelLowering.cpp IISelLowering.h IInstrFormats.td IInstrInfo.td IInstructions.td
c424975572af2edd46863e5bb9fe3c51c96b4f9b	25-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add i1 registers for SI. IISelLowering.cpp
bdda1cb914a291f42cb2221b42e922f22dccb777	25-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Fix CCReg definitions on SI IGenRegisterInfo.pl IInstrFormats.td
ad95bcb31fcf49015446f5158dfaf97fefac75cd	19-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add bitconvert patterns for SI IInstructions.td
4cab682184640242d1e6f034f2b6bd7c4378c162	19-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add custom lowering for SELECT_CC nodes on SI IISelLowering.cpp IISelLowering.h
ba76684292e568c164cb7cbe7537181af4b452b8	19-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Move conditional pattern leafs to common tablegen file MDGPUInstructions.td 600Instructions.td
d36455ba2c3febe5da6fc6f53e4acd98f771532a	25-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Implement getSetCCResultType for SI IISelLowering.cpp IISelLowering.h
e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218	18-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Custom lower BR_CC for SI IISelLowering.cpp IISelLowering.h
87272e9e2560a88352cf54d164507569ac43e502	18-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Move lowering of BR_CC node to R600ISelLowering SI will handle BR_CC different from R600, so we need to move it out of the shared instruction selector. MDILISelLowering.cpp MDILISelLowering.h 600ISelLowering.cpp 600ISelLowering.h
92823fb72abf1539bdb545fedc5525e9fc0b04cc	18-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Move lowering of SETCC node to R600ISelLowering SI will handle SETCC different from R600, so we need to move it out of the shared instruction selector. MDILISelLowering.cpp MDILISelLowering.h 600ISelLowering.cpp 600ISelLowering.h
46d12c99a24cebe01cd00575b39961231dec47c8	18-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use correct node type when lowering SETCC MDILISelLowering.cpp
47d1b0a80990dda4e14073f667f0c2b939dfb925	18-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Move LowerSELECT_CC into R600ISelLowering SI will handle SELECT_CC different from R600, so we need to move it out of the shared instruction selector. MDGPUISelLowering.cpp MDGPUISelLowering.h 600ISelLowering.cpp 600ISelLowering.h
bc4b4c605cc04138e5209782fa5939bfd71930bd	14-Jul-2012	Vincent Lejeune <vljn@ovi.com>	radeon/llvm: Fix a bug with IF LOGICALNZ with int operand Signed-off-by: Tom Stellard <thomas.stellard@amd.com> MDILISelLowering.cpp 600CodeEmitter.cpp
e3ff4d4c10e038b7be6dffe6c12b015ef36b5e7c	13-Jul-2012	Andreas Boll <andreas.boll.dev@gmail.com>	radeon/llvm: Fix CR/LF in AMDILSIDevice.h MDILSIDevice.h
cc3907856ed7ec24359eea11fc2231dab680e2c4	13-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Clean up AMDILIntrinsicInfo.cpp MDILIntrinsicInfo.cpp MDILIntrinsicInfo.h
f323c6260d54357d2408f1993a21e08f091b1e27	13-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Coding style fixes 600CodeEmitter.cpp 600KernelParameters.cpp
f92873be2c7fcb07154282bd0e418a4c88b6507e	12-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Don't use lp_build_swizzle_aos() for swizzles This function assumes that lp_build_context::type is a vector type, which is not true for r600 or radeonsi. This fixes an assertion failure using glamor 2D accel. adeon_setup_tgsi_llvm.c
49ae102ee346d4be6a61ebdaba6e5d5ad8469407	10-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use multiclasses for floating point loads The original strategy for handling floating point loads, which was to lower (f32 load) to (f32 bitcast (i32 load)) wasn't really working. The main problem was that the DAG legalizer couldn't handle replacing a node with two results (load) with a node with only one result (bitcast). MDGPUISelLowering.cpp MDGPUISelLowering.h 600CodeEmitter.cpp 600ISelLowering.cpp 600Instructions.td IInstrInfo.td IInstructions.td
bbdf3af8577ca61fc54c4a1615e80940c904636e	10-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Don't set the IMM bit in SMRD instruction definitions. The IMM bit is already being set in SICodeEmitter. IInstrInfo.td
76b44034b9b234d3db4012342f0fae677d4f10f6	08-Jul-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Rename namespace from AMDIL to AMDGPU MDGPUInstructions.td MDGPURegisterInfo.td MDGPUUtil.cpp MDGPUUtil.h MDILCFGStructurizer.cpp MDILFormats.td MDILISelDAGToDAG.cpp MDILISelLowering.cpp MDILInstrInfo.cpp MDILRegisterInfo.cpp MDILRegisterInfo.h MDILRegisterInfo.td MDILUtilityFunctions.h 600CodeEmitter.cpp 600GenRegisterInfo.pl 600ISelLowering.cpp 600InstrInfo.cpp 600Instructions.td 600RegisterInfo.cpp IAssignInterpRegs.cpp ICodeEmitter.cpp IGenRegisterInfo.pl IISelLowering.cpp IInstrInfo.cpp IRegisterInfo.cpp
a31b2f71076b9d3fe9bc5f2bae3228f1e7b99ee2	28-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Enable vec4 loads on R600 MDGPUISelLowering.cpp 600CodeEmitter.cpp 600Instructions.td
e17c586d08aee5bbaad6ac5efd2d30fe1d179406	28-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Enable floating point stores on R600 600Instructions.td
b66ef1f48c946fdb0762e0092fa13a6f53e53e90	27-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Handle floating point loads on R600 MDGPUISelLowering.cpp MDGPUISelLowering.h
c01199dfc0d30ad4c20cc4a2ebe3cdcbc74debb6	27-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Expand UDIV and UREM nodes MDGPUISelLowering.cpp
2c485cda2062ca2b9af89ea62618515d960c7904	29-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Emit raw ISA for vertex fetch instructions 600CodeEmitter.cpp 600Instructions.td
563a764110ac9a2e93e2a01e362d8dc756232634	20-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Turn on the BitExtract peephole optimization Thie BitExtract optimization folds a mask and shift operation together into a single instruction (BFE_UINT). MDILPeepholeOptimizer.cpp 600Instructions.td
c53c8d05551083437eb991e79002c0a272541a79	20-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Lower ROTL to BIT_ALIGN MDGPUISelLowering.h MDGPUInstrInfo.td MDILISelLowering.cpp 600ISelLowering.cpp 600ISelLowering.h 600Instructions.td
cd287301ec598d2811f3f85c03d23bae01be2359	20-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use the VLIW Scheduler for R600->NI It's not optimal, but it's better than the register pressure scheduler that was previously being used. The VLIW scheduler currently ignores all the complicated instruction groups restrictions and just tries to fill the instruction groups with as many instructions as possible. Though, it does know enough not to put two trans only instructions in the same group. We are able to ignore the instruction group restrictions in the LLVM backend, because the finalizer in r600_asm.c will fix any illegal instruction groups the backend generates. Enabling the VLIW scheduler improved the run time for a sha1 compute shader by about 50%. I'm not sure what the impact will be for graphics shaders. I tested Lightsmark with the VLIW scheduler enabled and the framerate was about the same, but it might help apps that use really big shaders. MDGPUInstructions.td MDGPUSubtarget.h MDGPUTargetMachine.cpp MDGPUTargetMachine.h MDILBase.td MDILFormats.td akefile akefile.sources 600ISelLowering.cpp 600InstrInfo.cpp 600InstrInfo.h 600Schedule.td
988ad7831c041154828f32cee96a4f01d2573f21	19-Jun-2012	Török Edwin <edwin+mesa@etorok.net>	radeon/llvm: Fix CR/LF in Processors.td Signed-off-by: Tom Stellard <thomas.stellard@amd.com> rocessors.td
7c005d5687eeca5b3115f69a681d21e61741c5dc	18-Jun-2012	Török Edwin <edwin+mesa@etorok.net>	radeon/llvm: Fix sin/cos codegen on R700 Based on https://bugs.freedesktop.org/show_bug.cgi?id=50317#c4 Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=50316 https://bugs.freedesktop.org/show_bug.cgi?id=50317 Signed-off-by: Tom Stellard <thomas.stellard@amd.com> 600Instructions.td
7fab4b648b0b35d65b5d33482f9703c248a46c17	19-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Update comment in AMDGPU.td MDGPU.td
984ad0788c54386801b185740b973c446e55d3b9	07-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove unused AMDIL TableGen definitons MDGPUISelLowering.h MDGPUUtil.cpp MDILCallingConv.td MDILFormats.td MDILISelDAGToDAG.cpp MDILISelLowering.cpp MDILISelLowering.h MDILInstrInfo.cpp MDILInstructions.td MDILMultiClass.td MDILNodes.td MDILOperands.td MDILRegisterInfo.td MDILUtilityFunctions.h MDILVersion.td 600RegisterInfo.cpp IGenRegisterInfo.pl IRegisterInfo.cpp
34ff22b75f8e3616109c3deacea2ec27f12f3398	15-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Eliminate getRegClassFromType() function We can use TargetLowering::getRegClassFor() instead. MDILISelLowering.cpp
440ab9ea02690008b4d8da11494fd1e9cd86e57e	15-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove deadcode from AMDILISelLowering.cpp MDILISelLowering.cpp MDILISelLowering.h 600ISelLowering.cpp IISelLowering.cpp
4c418cf1a37f824676bcc0454fcc4cf6916e0fdd	07-Jun-2012	Thomas Stellard <tom.stellard@amd.com>	radeonsi: Handle SUB_f32. Signed-off-by: Thomas Stellard <tom.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> MDILInstructions.td IInstructions.td
4c4ef9c29acf4f1f40aa3c5d268322efd26c1786	07-Jun-2012	Michel Dänzer <michel.daenzer@amd.com>	radeonsi: Only dump shaders with environment variable RADEON_DUMP_SHADERS=1. ICodeEmitter.cpp
743e505315b6be851618caed61981d7c1617bf45	15-May-2012	Eric Anholt <eric@anholt.net>	automake: Globally add stub automake targets to the old Makefiles. I tried to update all the old Makefiles that included the default config to be sure they had a default target if they didn't previously have one, since this new all target will always point at it. Almost everything had one. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> akefile
5f3f63b76d36b752d7d98c04ab044b5a961b5593	06-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Emulate RECIP_UINT instruction on Cayman 600CodeEmitter.cpp 600Instructions.td
0c9f5f22d5cf3cad01ee3685116011ff7ff67140	06-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove some duplicate code in the R600 CodeEmitter 600CodeEmitter.cpp
9c46cb23685d0b28d5b9124f6dd26f27d028ed30	06-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Fix MULLO* instructions on Cayman On Cayman, the MULLO* instructions must fill all slots in an instruction group. 600CodeEmitter.cpp 600InstrInfo.cpp 600InstrInfo.h 600Instructions.td
0c4b19ac63efa41242c515824301e6161aceeea5	05-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	r600g: Compute support for Cayman 600Instructions.td
d4942eb9fa1247053619be2b1e5a1b79f35c535d	06-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove obselete hooks for the ConvertToISA pass We can't remove this pass yet, because we need it to convert AMDIL registers in BRANCH* instructions, but we don't need it for instruction conversion any more. MDGPUInstrInfo.cpp MDGPUInstrInfo.h 600InstrInfo.cpp 600InstrInfo.h IInstrInfo.cpp IInstrInfo.h
edceed1b9a46c4a92a6113e8b1c5d2433568143d	06-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL MOVE* instructions MDILISelDAGToDAG.cpp MDILISelLowering.cpp MDILInstrInfo.cpp MDILInstrInfo.h MDILInstructions.td
f81e4663a766e71e907886640327abea4a0d78e2	02-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add isMov() to AMDILInstrInfo This enables the CFGStructurizer to work without the AMDIL::MOV* instructions. MDILCFGStructurizer.cpp MDILInstrInfo.h 600InstrInfo.cpp 600InstrInfo.h IInstrInfo.cpp IInstrInfo.h
1777c99bff40f160b09dd3c9708b0963c772610a	02-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove deadcode from the AMDILISelLowering class MDILISelLowering.cpp MDILISelLowering.h
8cc9b463deae8f6116963e1fea0c62930066b563	02-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Don't lower RETURN to S_ENDPGM on SI Instead create an S_ENDPGM instruction in the CodeEmitter and emit it after all the other instructions. ICodeEmitter.cpp IInstrInfo.cpp
de7366701d21842787d65320c12e6b4ecaea3807	02-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL VCREATE* instructions This obsoletes the AMDGPULowerInstruction pass. MDGPU.h MDGPUInstructions.td MDGPULowerInstructions.cpp MDGPUTargetMachine.cpp MDILInstructions.td akefile.sources 600Instructions.td IInstructions.td
8d53ddb375d2a82860b398bc463294373c5a62b0	02-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL LOADCONST* instructions This obsoletes the R600LowerInstruction and SIPropagateImmReads passes. MDGPU.h MDGPUTargetMachine.cpp MDILISelLowering.cpp MDILInstrInfo.td MDILInstrPatterns.td MDILInstructions.td MDILRegisterInfo.cpp akefile.sources 600Instructions.td 600LowerInstructions.cpp IInstrInfo.cpp IInstructions.td IPropagateImmReads.cpp
0ebf2318b3d5e60adfc43e477b19acdc3cd4cc07	01-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Fix VTX_READ patterns The VTX_READ instructions were using the ADDRParam ComplexPattern which allows a load instruction's offset to be a register, but VTX_READ instructions can only handle an immediate offset. Also, the load_param pattern fragment had an erroneous return true; statement that was causing it to match the wrong load instructions. MDILISelDAGToDAG.cpp 600CodeEmitter.cpp 600Instructions.td
c108831d4451f624167d2c433282c6ac63541a79	01-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Emit 2 bytes for vertex fetch offsets 600CodeEmitter.cpp
85a68814ee98d649e92223a42bab9db7392649ba	01-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Only use indirect (vertex fetch) parameters for kernels Kernel parameters can only be retrieved via vertex fetchs. Direct parameters (i.e parameters stored in the constant buffer) are not supported yet. 600KernelParameters.cpp
d6c2d3722d795381d3cdf11fe00f63780ad0725a	01-Jun-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Eliminate CFGStructurizer dependency on AMDIL instructions Add some hooks to the R600,SI InstrInfo and RegisterInfo classes, so that the CFGStructurizer pass can run without any relying on AMDIL instructions. MDILCFGStructurizer.cpp MDILInstrInfo.h MDILRegisterInfo.h 600InstrInfo.cpp 600InstrInfo.h 600RegisterInfo.cpp 600RegisterInfo.h IInstrInfo.cpp IInstrInfo.h IRegisterInfo.cpp IRegisterInfo.h
65917004d99ccb79f709e621f8f6cf66715ffdca	31-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Change prefix on tablegen files to AMDGPU MDGPU.td MDIL.h MDIL.td MDILISelDAGToDAG.cpp MDILISelLowering.cpp MDILInstrInfo.cpp MDILInstrInfo.h MDILIntrinsicInfo.cpp MDILIntrinsicInfo.h MDILRegisterInfo.cpp MDILRegisterInfo.h MDILSubtarget.cpp MDILSubtarget.h CTargetDesc/AMDILMCTargetDesc.cpp CTargetDesc/AMDILMCTargetDesc.h akefile akefile.sources 600CodeEmitter.cpp
afea59bf6546c99e98409945fa69860096952bc3	31-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove deadcode from the R600LowerInstructions pass 600LowerInstructions.cpp
883a0af53a2a4ef612e31b61a22fa4443121a2b8	31-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL GLOBALSTORE* instructions MDILInstructions.td 600ISelLowering.cpp 600Instructions.td 600LowerInstructions.cpp
f2781271c735fcdf94ed2dd831a7fa3a854deae5	31-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL GLOBALLOAD* instructions MDILInstrInfo.cpp MDILInstructions.td 600CodeEmitter.cpp 600ISelLowering.cpp 600Instructions.td 600LowerInstructions.cpp
83169900fb96f1a51d8292e66c203c64a82e204d	29-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Update and fix some comments 600ISelLowering.cpp IISelLowering.cpp
89ece086bcd2186ab53cb6a69d53005893cab0ea	29-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeonsi: Remove use.sgpr* intrinsics, use load instructions instead We now model loading uses sgpr values with LLVM IR load instructions that use the USER_SGPR address space. The definition of the sgpr parameter to the use_sgpr() helper function in radeonsi_shader.c has changed so that you can pass raw sgpr values rather than having to divide the sgpr value you want to use by the dword width of the type you want to load. MDIL.h IISelLowering.cpp IInstructions.td IIntrinsics.td
467f51613eb1f2cdaa8624bbbb3d5fae2abca4f2	16-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeonsi: Handle TGSI CONST registers We now emit LLVM load instructions for TGSI CONST register reads, which are lowered in the backend to S_LOAD_DWORD* instructions. MDILCodeEmitter.h MDILISelDAGToDAG.cpp MDILISelLowering.cpp 600ISelLowering.cpp ICodeEmitter.cpp IGenRegisterInfo.pl IISelLowering.cpp IInstrInfo.td IInstructions.td IIntrinsics.td IPropagateImmReads.cpp
32b83e0366560a77798545880f980adc04b4361f	28-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILIntrinsicInfo::GetDeclaration fuction body This function was causing compile errors in the tablegen'd code for some intrinsic definitions. I don't think we really need this function, so I'm removing the function body just as a temporary solution. I'll look into removing the entire AMDILIntrinsicInfo class later. MDILIntrinsicInfo.cpp
49fb99bd131a4ed89e6f55cf360f67618acafec4	28-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILTargetMachine MDGPUTargetMachine.cpp MDGPUTargetMachine.h MDIL.h MDILCFGStructurizer.cpp MDILISelDAGToDAG.cpp MDILISelLowering.cpp MDILInstrInfo.cpp MDILInstrInfo.h MDILIntrinsicInfo.cpp MDILIntrinsicInfo.h MDILRegisterInfo.cpp MDILRegisterInfo.h MDILTargetMachine.cpp MDILTargetMachine.h CTargetDesc/AMDILMCTargetDesc.cpp CTargetDesc/AMDILMCTargetDesc.h akefile.sources argetInfo/AMDILTargetInfo.cpp adeon_llvm_emit.cpp
704eac09166aa6dc4c1aa82f8d0938c4060e51f4	25-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use a custom inserter for MASK_WRITE MDGPUInstructions.td 600ISelLowering.cpp 600Instructions.td 600LowerInstructions.cpp
4863477e22e02af046915ca2a33dbecfd0ed34b4	25-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use tablegen pattern to lower bitconvert MDGPUInstructions.td MDILISelLowering.cpp 600Instructions.td 600LowerInstructions.cpp
667cdba2118cf82e0027bf44314c9d1334d00840	25-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use a custom inserter to lower FNEG MDGPUInstructions.td MDILInstructions.td 600ISelLowering.cpp 600Instructions.td 600LowerInstructions.cpp
d784bc77405012b442ae9d68f200e9d115030b3c	25-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use a custom inserter to lower CLAMP MDGPUInstructions.td MDILInstructions.td 600ISelLowering.cpp 600Instructions.td 600LowerInstructions.cpp IISelLowering.cpp IInstrInfo.cpp IInstrInfo.h IInstructions.td
17f852892346fdf3b1e9eec56b7a55c470279bc8	25-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use a custom inserter to lower FABS MDGPUISelLowering.cpp MDGPUInstructions.td MDILInstructions.td 600ISelLowering.cpp 600Instructions.td 600LowerInstructions.cpp IISelLowering.cpp IInstrInfo.cpp IInstrInfo.h IInstructions.td
1c5c4243c9c10666280a540fb2789c2d09e095b3	25-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructions Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> 600Instructions.td
5a1b59b4e67370ccfb8e484434914fc32ef53a8c	25-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: prepare to revert the round mode state to default Use TRUNC before FLT_TO_INT on evergreen/cayman. Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> 600Instructions.td
029776753b69dc6054cabd8c2cc07c981ab20616	25-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: fix opcode for RECIP_UINT_r600 Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50312 Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Tested-by: Kai Wasserbäch <kai@dev.carbon-project.org> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> 600Instructions.td
6806f81fb40ae3dc2da9bd8dbd602fb9c1a4dfc1	25-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm/loader: convert hardcoded gpu name to option Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> oader.cpp
33e7db9a1dafdcf5c7c745180831403e0485544d	24-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Lower UDIV using the Selection DAG MDGPUISelLowering.cpp MDGPUISelLowering.h MDGPUInstrInfo.td MDILISelLowering.cpp 600InstrInfo.cpp 600InstrInfo.h 600Instructions.td 600LowerInstructions.cpp
d088da917bb3495491b9a5da5ca1716ddd91ddd5	24-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove auto-generated AMDIL->ISA conversion code MDGPUGenInstrEnums.pl MDGPUInstrInfo.cpp MDGPUInstrInfo.h MDGPUInstructions.td MDGPUUtil.cpp MDILInstructions.td akefile akefile.sources 600InstrInfo.cpp 600InstrInfo.h 600Instructions.td IInstrFormats.td IInstrInfo.cpp IInstructions.td
662ccbfc21a650e0a52f6d293fa33f9e23e654c6	24-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL instructions MULHI, SMUL MDGPUGenInstrEnums.pl MDILInstructions.td 600Instructions.td
177b420283547e472632bc650f218ad4b0b541d5	24-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR) MDGPUGenInstrEnums.pl MDGPUUtil.cpp MDILConversions.td MDILISelLowering.cpp MDILInstrPatterns.td MDILInstructions.td 600InstrInfo.cpp 600Instructions.td
9d41a401dcdfda1e3bfdabdedac239ef1d6b93e4	24-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL FTOI and ITOF instructions MDGPUGenInstrEnums.pl MDGPUUtil.cpp MDILConversions.td MDILISelLowering.cpp MDILInstrPatterns.td MDILInstructions.td 600Instructions.td
a8ba697c1ec3e07e331cba85e67bf5c2b8d41e57	23-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL EXP* instructions MDGPUGenInstrEnums.pl MDGPUISelLowering.cpp MDGPUUtil.cpp MDILInstructions.td 600Instructions.td
dd9927eb36614eccbc48b316befe6a3e37644694	23-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL ADD instructions MDGPUGenInstrEnums.pl MDILISelLowering.cpp MDILInstructions.td MDILRegisterInfo.cpp 600InstrInfo.cpp 600Instructions.td
1404e6b9fcc6ff4f962cafa8d81226dff5fef54d	23-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT) MDGPUGenInstrEnums.pl MDILConversions.td MDILISelLowering.cpp MDILInstrPatterns.td MDILInstructions.td 600InstrInfo.cpp 600Instructions.td 600LowerInstructions.cpp
3059c075a73aa275cc43cf72ba87d64f6d748cd6	23-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILMachinePeephole pass MDIL.h MDILMachinePeephole.cpp MDILTargetMachine.cpp akefile.sources
e9d8901a80dfcc9825ddcc1f258b0431d7b42ac0	23-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL CMP instructions and associated lowering code MDILISelLowering.cpp MDILISelLowering.h MDILInstructions.td
ea00632fe0667766783fb66f9db5198554fee159	23-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL ROUND_NEAREST instruction MDGPUGenInstrEnums.pl MDGPUISelLowering.cpp MDILInstructions.td 600Instructions.td
0bfa3b3e9629d81a5e31c1b91fd25eab734804fa	23-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL ROUND_POSINF instruction MDGPUGenInstrEnums.pl MDGPUISelLowering.cpp MDILInstructions.td 600Instructions.td
d4984f346320e64b58e38e443e5b99d09b7067bc	23-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add custom SDNode for FRACT MDGPUGenInstrEnums.pl MDGPUISelLowering.cpp MDGPUISelLowering.h MDGPUInstrInfo.td MDILInstructions.td 600Instructions.td
5523502ff917803166051c8947f5dd3b23c6fcf8	23-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use -1 as true value for SET* integer instructions MDGPUISelLowering.cpp MDGPUISelLowering.h 600Instructions.td
86dfae1103faa9e0329e68e3ab7c1684a0c12892	23-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Handle SETGE_INT, SETGE_UINT, and SETGT_UINT opcodes Support for these was inadvertently dropped in commit cee23ab246f22210b3063cdc47bdb45b3d943526 600InstrInfo.cpp
cc7a6d269170cc3668caa4f5af29228920e8d7a7	24-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Avoid error with SI in EmitInstrWithCustomInserter() We need to return immediately after inserting instructions that require S_WAITCNT so that the parent class' custom inserter won't try to insert them again. IISelLowering.cpp
cee23ab246f22210b3063cdc47bdb45b3d943526	18-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Handle selectcc DAG node R600 can now select instructions from the selectcc DAG node, which is typically lowered to one of the SET* instructions. MDGPUISelLowering.cpp MDGPUISelLowering.h 600ISelLowering.cpp 600InstrInfo.cpp 600Instructions.td oader.cpp adeon_setup_tgsi_llvm.c
c20e7417992380871261699c2b0123819e7d51fc	18-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Fix segfault while lowering lrp intrinsic MDGPUISelLowering.cpp
7e3cd8df183448e2cc01a8f2645a001b0972f4ab	18-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add DAG nodes for MIN instructions Also, remove the AMDIL MIN* instruction defs. MDGPUGenInstrEnums.pl MDGPUISelLowering.cpp MDGPUISelLowering.h MDGPUInstrInfo.td MDILInstructions.td 600Instructions.td
c6c8a05c509b30600d2ccb4be635f05cd71c68a4	17-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Lower lrp intrinsic during ISel MDGPUISelLowering.cpp MDGPUISelLowering.h 600Instructions.td
ef8e66bc165ea2ef9987ab6406268ce195f74eb0	17-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL MAD instruction defs MDGPUGenInstrEnums.pl MDGPUISelLowering.cpp MDILInstructions.td 600Instructions.td IInstrInfo.cpp IInstructions.td
d07473fcf4126c740802e6458452e82cc5c799ba	17-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL MUL_IEEE* instructions MDGPUGenInstrEnums.pl MDILInstructions.td 600Instructions.td
1fe70c6ae12e85cdb5967ba6d72fca8a9e5c3ec3	17-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Expand fsub during ISel 600ISelLowering.cpp 600LowerInstructions.cpp
9916f2d2af18a26f32efb85aff5c11e1b998e19c	17-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL floating-point ADD instruction defs MDGPUGenInstrEnums.pl MDILInstructions.td 600Instructions.td 600LowerInstructions.cpp IInstructions.td
91484de22dd5143cef5f2fe7786f96abfbc795c8	17-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDIL CMOVLOG* instruction defs MDGPUGenInstrEnums.pl MDILInstructions.td 600Instructions.td 600LowerInstructions.cpp
9a020092aedc6310d5bfc72b2aa6fc4348fe5c32	17-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Move lowering of ABS_i32 to ISel MDGPUISelLowering.cpp MDGPUISelLowering.h MDILInstructions.td 600LowerInstructions.cpp
89b945591bb5d434518cea481209b1ea7a435861	17-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove sub patterns from AMDILInstrPatterns.td MDILInstrPatterns.td 600Instructions.td
431bb79a41bd5e7402954385daea1594c3e750ab	17-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add custom SDNodes for MAX We now lower the various intrinsics for max to SDNodes and then use tablegen patterns to lower the SDNodes to instructions. MDGPUGenInstrEnums.pl MDGPUISelLowering.cpp MDGPUISelLowering.h MDGPUInstrInfo.td MDIL.td MDILISelDAGToDAG.cpp MDILISelLowering.h MDILInstructions.td 600Instructions.td IInstructions.td
4a8d47c264eb7e01ebfda2fbcbe0bf42f0882d38	15-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add support for texture offsets, fix TEX_LD Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> MDGPUIntrinsics.td 600CodeEmitter.cpp 600Instructions.td adeon_setup_tgsi_llvm.c
fa5a963dd6c2622c416d53e49b08c4b3cbce7483	15-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_G Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> MDGPUIntrinsics.td MDGPUUtil.cpp 600ISelLowering.cpp 600Instructions.td adeon_setup_tgsi_llvm.c
b655f78b25454e00f4300fb5ccd35b3d0ab8a740	15-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: increase const regs count Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> 600GenRegisterInfo.pl
12a2374da380a9a28cacf968c33b93ba320b0407	15-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: use IntrNoMem property for intrinsics where possible Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> MDGPUIntrinsics.td MDILFormats.td 600IntrinsicsNoOpenCL.td 600IntrinsicsOpenCL.td adeon_llvm.h adeon_setup_tgsi_llvm.c
63a85952711415ab151a39d21c4a67da97f2734e	15-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: use correct intrinsic for CEIL Should be round_posinf instead of round_neginf. Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> 600Instructions.td adeon_setup_tgsi_llvm.c
0298238bdd65344b91731973902fb46530e74cca	15-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: improve ABS_i32 lowering We can save one instruction by lowering it to: SUB_INT tmp, 0, src MAX_INT dst, src, tmp Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> 600LowerInstructions.cpp
76e4898ba3c67082524786a0e0c67557a8abc58b	15-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: fix BUILD_VECTOR lowering for replicated value We expect that all elements will be assigned even if they are equal Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> MDILISelLowering.cpp
4b8db65dbfc4074f045ea0319edd8de2f59545bf	15-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add names for AMDGPU* passes Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> MDGPUConvertToISA.cpp MDGPULowerInstructions.cpp
76ba7e22056aa461c40d8a8c8bd82d81ccba111c	15-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add generated files to .gitignore Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> gitignore
1deb2be2b7887d7435e103fdb042857e745ff08d	14-May-2012	Michel Dänzer <michel.daenzer@amd.com>	radeonsi: Flesh out shader interpolation related code. Handle perspective interpolation and ceontroid vs. center. IInstructions.td IIntrinsics.td
ec201667bf201ba9549059697f687b830bdeb6b3	14-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Coding style fixes for R600CodeEmitter.cpp 600CodeEmitter.cpp
224e187f986223e5c95deb9502c9663d968014ac	14-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Lower bitcast instructions to copies 600LowerInstructions.cpp
bcfc97dbf40c256ed59c2424e0c55b845f0f2569	11-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: More comments and cleanups MDGPUConvertToISA.cpp MDGPUISelLowering.cpp MDGPUISelLowering.h MDGPUInstrInfo.cpp MDGPUInstrInfo.h MDGPULowerInstructions.cpp MDGPURegisterInfo.h MDGPUTargetMachine.cpp MDGPUTargetMachine.h MDGPUUtil.cpp MDGPUUtil.h 600CodeEmitter.cpp 600ISelLowering.h 600RegisterInfo.h IAssignInterpRegs.cpp ICodeEmitter.cpp IISelLowering.cpp IISelLowering.h IInstrInfo.h IPropagateImmReads.cpp IRegisterInfo.cpp IRegisterInfo.h
4d11a6a0c798301863d5b202703dcca37dc24e7c	11-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Fix Evergreen/Cayman tablegen predicates Some Evergreen/Cayman instructions were being enabled for SI. 600Instructions.td
03d9c24c0468ae992a704c6a2f72bc349557b671	10-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILMCCodeEmitter.cpp MDILMCCodeEmitter.cpp akefile.sources
628e5b208a1ca04c696f52c8d4d18b0ea5457a22	10-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove SILowerShaderInstructions.cpp MDGPU.h MDGPUTargetMachine.cpp akefile.sources ILowerShaderInstructions.cpp
f8e9c29020289387f0f429ac6d3c28e73e5847a3	10-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeonsi/llvm: Move lowering of RETURN to ConvertToISA pass IInstrInfo.cpp ILowerShaderInstructions.cpp
fa63f976522bd4faf19249e8c9ac4d3edda498d9	09-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add some comments MDGPU.h MDGPUGenInstrEnums.pl MDGPUInstructions.td MDGPUIntrinsics.td MDGPURegisterInfo.h MDGPURegisterInfo.td MDGPUTargetMachine.cpp MDGPUTargetMachine.h MDIL.td MDIL7XXDevice.cpp MDILCFGStructurizer.cpp MDILCodeEmitter.h MDILConversions.td MDILDevice.cpp MDILDeviceInfo.cpp MDILDeviceInfo.h MDILDevices.h MDILEnumeratedTypes.td MDILEvergreenDevice.cpp MDILInstructions.td MDILMultiClass.td MDILNIDevice.cpp MDILPeepholeOptimizer.cpp MDILSIDevice.cpp MDILSIDevice.h MDILSubtarget.cpp MDILTokenDesc.td MDILVersion.td 600CodeEmitter.cpp 600GenRegisterInfo.pl 600ISelLowering.cpp 600ISelLowering.h 600InstrFormats.td 600InstrInfo.cpp 600InstrInfo.h 600Instructions.td 600IntrinsicsNoOpenCL.td 600KernelParameters.cpp 600KernelParameters.h 600LowerInstructions.cpp 600MachineFunctionInfo.cpp 600MachineFunctionInfo.h 600OpenCLUtils.h 600RegisterInfo.cpp 600RegisterInfo.h 600Schedule.td IAssignInterpRegs.cpp ICodeEmitter.cpp IGenRegisterInfo.pl IISelLowering.cpp IISelLowering.h IInstrFormats.td IInstrInfo.cpp IInstrInfo.h IInstrInfo.td IInstructions.td IIntrinsics.td ILowerShaderInstructions.cpp IMachineFunctionInfo.cpp IMachineFunctionInfo.h IPropagateImmReads.cpp IRegisterInfo.cpp IRegisterInfo.h ISchedule.td
92faa21d29b49689ccfff852cfff257fccec514e	10-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Move util functions into AMDGPU namespace MDGPUUtil.cpp MDGPUUtil.h 600CodeEmitter.cpp
b0bb125736fd29dbad6cfa8d4de0c44eaf5e28ad	10-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_eg 600CodeEmitter.cpp 600Instructions.td
fa3747ff2ce929ceda499fde93927354685f20ef	10-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Delete all instructions that have been custom lowered 600ISelLowering.cpp
788fd04dacb9eb1e32010050c57cd2f49779311b	09-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDGPUConstants.pm MDGPUConstants.pm 600GenRegisterInfo.pl
c2e081030e5c6f96ea3eb9948e5c0d0d2ed79a3d	09-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_const MDGPUGenShaderPatterns.pl akefile akefile.sources 600ISelLowering.cpp 600Instructions.td
d0403cafd479964a80d95299d079845593e9891f	09-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicate IInstrInfo.td IInstructions.td
5aaaa6a426258dc714c7346bec062795998f9986	08-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILUtilityFunctions.cpp MDIL.h MDILCFGStructurizer.cpp MDILISelDAGToDAG.cpp MDILISelLowering.cpp MDILInstrInfo.cpp MDILInstrInfo.h MDILMachinePeephole.cpp MDILPeepholeOptimizer.cpp MDILRegisterInfo.cpp MDILUtilityFunctions.cpp MDILUtilityFunctions.h akefile.sources 600CodeEmitter.cpp
21ab46eae8b1156667dd35142829392701a8637d	08-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove some unused functions from AMDILInstrInfo MDILInstrInfo.cpp MDILInstrInfo.h
f903da7335433ae243cf7ff59662be1a03ee9a14	07-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add some comments and fix coding style MDGPU.h MDGPUConvertToISA.cpp MDGPUISelLowering.cpp MDGPUISelLowering.h MDGPUInstrInfo.h MDGPULowerInstructions.cpp MDGPURegisterInfo.cpp MDGPUTargetMachine.cpp
a8d82c44f79e27d2b78458f9ea560c73eef3d3b5	08-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove the EXPORT_REG instruction MDGPU.h MDGPUInstructions.td MDGPUIntrinsics.td MDGPUTargetMachine.cpp MDGPUUtil.cpp akefile.sources 600ISelLowering.cpp 600Instructions.td 600LowerShaderInstructions.cpp
8a4c25dd7e9002ab7a2821753bcae1ff6af2ca1c	08-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use a custom inserter to lower RESERVE_REG MDGPUInstructions.td MDGPUIntrinsics.td akefile.sources 600ISelLowering.cpp 600Instructions.td 600LowerShaderInstructions.cpp 600MachineFunctionInfo.cpp 600MachineFunctionInfo.h 600RegisterInfo.cpp
94e797d0faed18dfa80bcce7a6d03ef369b6a820	08-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use a custom inserter to lower STORE_OUTPUT MDGPUInstructions.td 600ISelLowering.cpp 600Instructions.td 600LowerShaderInstructions.cpp
4226433625f7f1cbfff0503397adf74c6076b7f4	08-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDGPULowerShaderInstructions class It is no longer used. MDGPU.h MDGPULowerShaderInstructions.cpp MDGPULowerShaderInstructions.h akefile.sources 600LowerShaderInstructions.cpp ILowerShaderInstructions.cpp
ad385c402e665b2aedc7b456575d19df32584e73	08-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use a custom inserter to lower LOAD_INPUT MDGPUInstructions.td 600ISelLowering.cpp 600Instructions.td 600LowerShaderInstructions.cpp
52a7f212d36bd9829494bd588ecb9a3ebe9fc28a	07-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove the ReorderPreloadInstructions pass MDGPU.h MDGPUInstrInfo.cpp MDGPUInstrInfo.h MDGPUInstructions.td MDGPUReorderPreloadInstructions.cpp MDGPUTargetMachine.cpp akefile.sources ICodeEmitter.cpp IInstructions.td
e042b3aeed917b179d24c1f7a099c4cce56d2e25	07-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove old comment from AMDIL.h MDIL.h
d6aa7cd7f82a3695243e1ecb1c73cdb796b12523	07-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add suport for cube textures Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> adeon_setup_tgsi_llvm.c
e98e209528b2c7acb721a84a7cfda925aeed4d57	07-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add support for CUBE ALU instruction Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> MDGPUIntrinsics.td MDGPUUtil.cpp MDGPUUtil.h 600CodeEmitter.cpp 600Instructions.td
996fa375ec275ab5053855dc95f9cc4f301d596c	07-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add support for some ALU instructions Add support for IABS, NOT, AND, XOR, OR, UADD, UDIV, IDIV, MOD, UMOD, INEG, I2F, U2F, F2U, F2I, USEQ, USGE, USLT, USNE, ISGE, ISLT, ROUND, MIN, MAX, IMIN, IMAX, UMIN, UMAX Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> MDGPUGenInstrEnums.pl MDGPUIntrinsics.td 600Instructions.td adeon_setup_tgsi_llvm.c
e9be193430a9c50975bc2ce4724e5cc517502467	07-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add missing cases for BREAK/CONTINUE Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> MDGPUUtil.cpp 600CodeEmitter.cpp
e740b60845b56f9bb08ae751d80b058a27c73d5a	06-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add support for AHSR/LSHR/LSHL instructions Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> 600InstrInfo.cpp 600InstrInfo.h 600Instructions.td adeon_setup_tgsi_llvm.c
95ed0e9b6b445c70e920d340818fc0f84d45233e	06-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add support for TXQ/TXF/DDX/DDY instructions Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> MDGPUIntrinsics.td MDGPUUtil.cpp 600Instructions.td adeon_setup_tgsi_llvm.c
d8a120485444968c930f0ab675473692b221cb75	07-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add support for VertexID, InstanceID Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> adeon_llvm.h adeon_setup_tgsi_llvm.c
e3e7ae732c903235a57760e10de542f128c1fe62	07-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: fix live-in handling for inputs Set the input registers as live-in for entry basic block. Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> MDGPUUtil.cpp 600LowerShaderInstructions.cpp
757f471ba99446a942107fd9dba6bfbfe1652c14	07-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: add support for v4i32 Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> MDGPULowerInstructions.cpp 600GenRegisterInfo.pl 600ISelLowering.cpp 600Instructions.td
06db74a753bb71adf5370d3f1133c43ae40aec72	07-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: fix ABS_i32 instruction lowering Swap source operands. Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> 600LowerInstructions.cpp
3a6a1cd75fc98895569a34d5d7dfdc9e90381691	07-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: use integer comparison for IF Replacing "float equal to 1.0f" with "int not equal to 0". This should help for further optimization of boolean computations. Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> adeon_setup_tgsi_llvm.c
2a88dfc521bff7255e27e2ef8efcd08f9db53747	07-May-2012	Vadim Girlin <vadimgirlin@gmail.com>	radeon/llvm: use bitcasts for integers We're using float as default type, so basically for every instruction that wants other types for dst/src operands we need to perform the bitcast to/from default float. Currently bitcast produces no-op MOV instruction, will be eliminated later. Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> adeon_llvm.h adeon_setup_tgsi_llvm.c
c425c3823fbd475dc83211fef47f7ea58421ed17	07-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove references to DebugFlag and isCurrentDebugType() These weren't being used at all and they were causing build failures when LLVM was built with NDEBUG defined and mesa was not. https://bugs.freedesktop.org/show_bug.cgi?id=49110 MDILCFGStructurizer.cpp MDILMCCodeEmitter.cpp MDILMachinePeephole.cpp MDILPeepholeOptimizer.cpp
9e522bd201e7cba526e19f7f0422d5cf781be6e8	27-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	r600g/llvm: Lower ULT A, B, C to SETGT_UINT A, C, B 600LowerInstructions.cpp
ddb4dac13341d5b33b9e129ecb0e2abec30a27b6	24-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	r600g/llvm: Don't duplicate R600 intrinsics installed by LLVM At this point, in order for OpenCL to work correctly with r600g, OpenCL specific intrinsics need to be defined in the LLVM tree. So, we need to check for these intrinsics in the LLVM include directory to make sure not to re-define them. akefile akefile.sources 600Intrinsics.td 600IntrinsicsNoOpenCL.td 600IntrinsicsOpenCL.td
c8fb30abf1131072c855f2539db6455fac65dcb0	02-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Fix MachineInstr dump MDILSubtarget.cpp adeon_llvm_emit.cpp
d742d812d82ef61de1f41a18c8251db9b001bdd1	01-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Fix build for updated LLVM 3.1 release branch MDGPUTargetMachine.cpp MDILTargetMachine.cpp
ff10dbf35f1c083d38bbdbec30cadf6703b609e5	01-May-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Add subtarget feature: DumpCode With this feature enabled, the LLVM backend will dump the MachineIntrs prior to emitting code. The mesa env variable R600_DUMP_SHADERS will enable this feature in the backend. MDGPUTargetMachine.h MDILBase.td MDILSubtarget.h 600CodeEmitter.cpp adeon_llvm_emit.cpp
7bf3fe851c9ac45f0c297d05b5272c3b312109d7	28-Apr-2012	Dragomir Ivanov <drago.ivanov@gmail.com>	r600g/llvm: Remove unnecessary dynamic casts When the result of dynamic_cast is not checked, it can be replaced with static_cast Signed-off-by: Tom Stellard <thomas.stellard@amd.com> MDILISelLowering.cpp
7ed04fa7d80b904fc7e543db9e99d45cb920f404	29-Apr-2012	Dragomir Ivanov <drago.ivanov@gmail.com>	r600g/llvm: Add pattern for llvm.AMDGPU.kill v2 Signed-off-by: Tom Stellard <thomas.stellard@amd.com> MDGPUIntrinsics.td 600Instructions.td
4da1fcacf1d78c5fcae9e81eaf2a9d7c8117af3e	30-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	r600g/llvm: Fix handling of MASK_WRITE instructions We can't delete MASK_WRITE instructions from the program, because this will cause instructions being masked by MASK_WRITE to be marked dead and then deleted in the dce pass. MDGPUUtil.cpp 600LowerInstructions.cpp
77d2780cbc00d525b25c6e625b1faeb37e3ad6d0	30-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Use a custom emit function for TGSI_OPCODE_KIL adeon_setup_tgsi_llvm.c
a2f7ecfa74cdc73f3e0a7ea739ce962f7a029799	26-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeonsi/llvm: Silence a warning IPropagateImmReads.cpp
21d3dd831e28452bd3229bf93367aa3fa719ad10	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove unused header files MDILCompilerWarnings.h MDILKernel.h
30f2a38cef4d4a75776fbd822ff4ad716302b888	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILMachineFunctionInfo.cpp MDGPUTargetMachine.cpp MDGPUUtil.cpp MDILCFGStructurizer.cpp MDILCompilerErrors.h MDILISelLowering.cpp MDILMachineFunctionInfo.cpp MDILMachineFunctionInfo.h MDILPeepholeOptimizer.cpp akefile.sources 600CodeEmitter.cpp 600LowerInstructions.cpp IMachineFunctionInfo.cpp IMachineFunctionInfo.h IPropagateImmReads.cpp
540ec964db1c0046935def3c85b2a5c7bd634782	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILModuleInfo.cpp MDILMachineFunctionInfo.cpp MDILModuleInfo.cpp MDILModuleInfo.h akefile.sources
9f4509343369e8adb43268329c845148ea32a114	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILELFWriterInfo.cpp MDILELFWriterInfo.cpp MDILELFWriterInfo.h MDILTargetMachine.cpp MDILTargetMachine.h akefile.sources
d96682169eee693000846cddab6928e141ac274e	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILLiteralManager.cpp MDIL.h MDILLiteralManager.cpp MDILTargetMachine.cpp akefile.sources
ba333a6518d3d7ed1c1fcd7bc6da457e54941dcd	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILInliner.cpp MDGPUTargetMachine.cpp MDIL.h MDILInliner.cpp MDILTargetMachine.cpp akefile.sources
160d4a789110f09950a43c9bf763fcf3d7e46a2e	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILBarrierDetect.cpp MDGPUTargetMachine.cpp MDIL.h MDILBarrierDetect.cpp MDILTargetMachine.cpp akefile.sources
0e7161cce8210164613dca3dd88f29754dc1ef94	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILPrintfConvert.cpp MDGPUTargetMachine.cpp MDIL.h MDILPrintfConvert.cpp MDILTargetMachine.cpp akefile.sources
04993c963008ded3a6ad5e5b4d69ba08d1948a93	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove GlobalManager and KernelManager MDGPUTargetMachine.cpp MDILGlobalManager.cpp MDILGlobalManager.h MDILISelLowering.cpp MDILKernelManager.cpp MDILKernelManager.h MDILLiteralManager.cpp MDILPeepholeOptimizer.cpp MDILPrintfConvert.cpp MDILSubtarget.cpp akefile.sources
8d3bf7ced5a3bb17910e9a763edc152fa5fbcd92	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AsmPrinter files MDILAsmBackend.cpp MDILAsmBackend.h MDILAsmPrinter7XX.cpp MDILAsmPrinterEG.cpp akefile.sources
ba9bd41880a7ce285537c3ead8a8c439c5a50555	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove IOExpansion files MDGPUTargetMachine.cpp MDIL.h MDIL789IOExpansion.cpp MDIL7XXDevice.cpp MDIL7XXDevice.h MDIL7XXIOExpansion.cpp MDILDevice.h MDILEGIOExpansion.cpp MDILEvergreenDevice.cpp MDILEvergreenDevice.h MDILIOExpansion.cpp MDILIOExpansion.h MDILImageExpansion.cpp MDILTargetMachine.cpp akefile.sources
4b11f4321b0971cf21e596b3af788434c38db0d9	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Remove AMDILPointerManager.cpp MDIL.h MDIL7XXDevice.cpp MDIL7XXDevice.h MDILDevice.h MDILEvergreenDevice.cpp MDILEvergreenDevice.h MDILPointerManager.cpp MDILPointerManager.h MDILTargetMachine.cpp akefile.sources
76940ba852a9b9a34a36afc4b1709d548e036f2a	25-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeonsi/llvm: Fix initialization of SIMachineFunctionInfo SIMachineFunctionInfo needs to be initialized before any of the AMDIL passes. MDGPUTargetMachine.cpp
d7f9b6ce13dcfc4f1d7c84c121d66606f8d05f7b	20-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Don't print an error message when there is no error A blank line with an empty error message was being printed even when the target lookup succeeded. adeon_llvm_emit.cpp
f5fc3ac284eb8312e8076a5a9d47a5c082ebb537	19-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon/llvm: Lower VCREATE_v4f32 for R600 and SI MDGPU.h MDGPULowerInstructions.cpp MDGPUTargetMachine.cpp akefile.sources 600CodeEmitter.cpp IConvertToISA.cpp
519789d7e6f32efa0e01a9fbc7374bc494d76769	19-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	r600g/llvm: Let ISel handle lowering to {INSERT,EXTRACT}_SUBREG MDGPUInstructions.td 600CodeEmitter.cpp 600ISelLowering.cpp 600Instructions.td 600LowerInstructions.cpp IInstructions.td
3c0f521cbfb551bf69cc14c606dcdd20c0529589	19-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	r600g/llvm: Only emit an instruction's explicit operands 600CodeEmitter.cpp
b3863eb9a5a7a844f04acde5f15151c898ff3bac	20-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	r600g/llvm: Handle copies between vector registers 600GenRegisterInfo.pl 600InstrInfo.cpp
d4da0a062779c24ee84b0dbabd65800e4ed9c641	19-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	r600g/llvm: Remove debugging hack from R600InstrInfo::copyPhysReg() 600InstrInfo.cpp
90a42df0d092dd43782fec83199750e194759d89	19-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	r600g/llvm: Tell the code emitter to ignore KILL and BUNDLE 600CodeEmitter.cpp
fa52aeb3964e38b8e7b9e34c427fa1b5a42f358f	28-Feb-2012	Tom Stellard <thomas.stellard@amd.com>	r600/llvm: Add LOAD_VTX instruction 600Instructions.td
509ddb0a0414cfc83102c463da542d95d83eabad	16-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon: Move radeon_llvm_emit.cpp declarations into their own header Reviewed-by: Alex Deucher <alexander.deucher@amd.com> oader.cpp adeon_llvm.h adeon_llvm_emit.cpp adeon_llvm_emit.h
6e238bf27c34fa9d79c9f371c102a5423db86de8	16-Apr-2012	Tom Stellard <thomas.stellard@amd.com>	radeon: Remove HAVE_LLVM ifdefs Only LLVM 3.1 is supported, so these are not necessary. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> adeon_llvm_emit.cpp
dbf48e88eb11270e080eced8468008ed2c3329cc	19-Apr-2012	Michel Dänzer <michel.daenzer@amd.com>	radeonsi: Fix VGPR_BIT() definition. Fixes encoding of VOP3 shader instructions. The shift was wrong for source registers 2 and 3, and the resulting value was only 32 bits, so the shift in SICodeEmitter::VOPPostEncode() didn't work as intended. ICodeEmitter.cpp
e1a173fb33b2090476130c944423ac3359ed8fd8	19-Apr-2012	Michel Dänzer <michel.daenzer@amd.com>	radeonsi: MIMG shader instructions require waiting for the results. IInstrInfo.td
a75c6163e605f35b14f26930dd9227e4f337ec9e	06-Jan-2012	Tom Stellard <thomas.stellard@amd.com>	radeonsi: initial WIP SI code This commit adds initial support for acceleration on SI chips. egltri is starting to work. The SI/R600 llvm backend is currently included in mesa but that may change in the future. The plan is to write a single gallium driver and use gallium to support X acceleration. This commit contains patches from: Tom Stellard <thomas.stellard@amd.com> Michel Dänzer <michel.daenzer@amd.com> Alex Deucher <alexander.deucher@amd.com> Vadim Girlin <vadimgirlin@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> The following commits were squashed in: ====================================================================== radeonsi: Remove unused winsys pointer This was removed from r600g in commit: commit 96d882939d612fcc8332f107befec470ed4359de Author: Marek Olšák <maraeo@gmail.com> Date: Fri Feb 17 01:49:49 2012 +0100 gallium: remove unused winsys pointers in pipe_screen and pipe_context A winsys is already a private object of a driver. ====================================================================== radeonsi: Copy color clamping CAPs from r600 Not sure if the values of these CAPS are correct for radeonsi, but the same changed were made to r600g in commit: commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc Author: Marek Olšák <maraeo@gmail.com> Date: Mon Jan 23 03:11:17 2012 +0100 st/mesa: do vertex and fragment color clamping in shaders For ARB_color_buffer_float. Most hardware can't do it and st/mesa is the perfect place for a fallback. The exceptions are: - r500 (vertex clamp only) - nv50 (both) - nvc0 (both) - softpipe (both) We also have to take into account that r300 can do CLAMPED vertex colors only, while r600 can do UNCLAMPED vertex colors only. The difference can be expressed with the two new CAPs. ====================================================================== radeonsi: Remove PIPE_CAP_OUTPUT_READ This CAP was dropped in commit: commit 04e324008759282728a95a1394bac2c4c2a1a3f9 Author: Marek Olšák <maraeo@gmail.com> Date: Thu Feb 23 23:44:36 2012 +0100 gallium: remove PIPE_SHADER_CAP_OUTPUT_READ r600g is the only driver which has made use of it. The reason the CAP was added was to fix some piglit tests when the GLSL pass lower_output_reads didn't exist. However, not removing output reads breaks the fallback for glClampColorARB, which assumes outputs are not readable. The fix would be non-trivial and my personal preference is to remove the CAP, considering that reading outputs is uncommon and that we can now use lower_output_reads to fix the issue that the CAP was supposed to workaround in the first place. ====================================================================== radeonsi: Add missing parameters to rws->buffer_get_tiling() call This was changed in commit: commit c0c979eebc076b95cc8d18a013ce2968fe6311ad Author: Jerome Glisse <jglisse@redhat.com> Date: Mon Jan 30 17:22:13 2012 -0500 r600g: add support for common surface allocator for tiling v13 Tiled surface have all kind of alignment constraint that needs to be met. Instead of having all this code duplicated btw ddx and mesa use common code in libdrm_radeon this also ensure that both ddx and mesa compute those alignment in the same way. v2 fix evergreen v3 fix compressed texture and workaround cube texture issue by disabling 2D array mode for cubemap (need to check if r7xx and newer are also affected by the issue) v4 fix texture array v5 fix evergreen and newer, split surface values computation from mipmap tree generation so that we can get them directly from the ddx v6 final fix to evergreen tile split value v7 fix mipmap offset to avoid to use random value, use color view depth view to address different layer as hardware is doing some magic rotation depending on the layer v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on evergreen, align bytes per pixel to a multiple of a dword v9 fix handling of stencil on evergreen, half fix for compressed texture v10 fix evergreen compressed texture proper support for stencil tile split. Fix stencil issue when array mode was clear by the kernel, always program stencil bo. On evergreen depth buffer bo need to be big enough to hold depth buffer + stencil buffer as even with stencil disabled things get written there. v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen, old ddx overestimate those. Fix linear case when pitchheight < 64. Fix r300g. v12 Fix linear case when pitchheight < 64 for old path, adapt to libdrm API change v13 add libdrm check Signed-off-by: Jerome Glisse <jglisse@redhat.com> ====================================================================== radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY This was removed in commit: commit 62f44f670bb0162e89fd4786af877f8da9ff607c Author: Marek Olšák <maraeo@gmail.com> Date: Mon Mar 5 13:45:00 2012 +0100 Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY" This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc. It was decided to refactor the transfer API instead of adding workarounds to address the performance issues. ====================================================================== radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT. Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90. ====================================================================== radeonsi: nuke the fallback for vertex and fragment color clamping Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853. ====================================================================== radeonsi: don't expose transform_feedback2 without kernel support Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48. ====================================================================== radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL. Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f. ====================================================================== radeonsi: set minimum point size to 1.0 for non-sprite non-aa points. Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc. ====================================================================== radeonsi: rework and consolidate stencilref state setting. Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070. ====================================================================== radeonsi: cleanup setting DB_SHADER_CONTROL. Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b. ====================================================================== radeonsi: Get rid of register masks. Ported from r600g commits 3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2. ====================================================================== radeonsi: get rid of r600_context_reg. Ported from r600g commits 9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f. ====================================================================== radeonsi: Fix regression from 'Get rid of register masks'. ====================================================================== radeonsi: optimize r600_resource_va. Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174. ====================================================================== radeonsi: remove u8,u16,u32,u64 types. Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5. ====================================================================== radeonsi: merge r600_context with r600_pipe_context. Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0. ====================================================================== radeonsi: Miscellaneous context cleanups. Ported from r600g commits e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888. ====================================================================== radeonsi: add a new simple API for state emission. Ported from r600g commits 621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e. ====================================================================== radeonsi: Also remove sbu_flags member of struct r600_reg. Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions, so some code needs to be disabled for now. ====================================================================== radeonsi: Miscellaneous simplifications. Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and b0337b679ad4c2feae59215104cfa60b58a619d5. ====================================================================== radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION. Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a. ====================================================================== radeonsi: Use a fake reloc to sleep for fences. Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4. ====================================================================== radeonsi: adapt to get_query_result interface change. Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11. MDGPU.h MDGPUConstants.pm MDGPUConvertToISA.cpp MDGPUGenInstrEnums.pl MDGPUGenShaderPatterns.pl MDGPUISelLowering.cpp MDGPUISelLowering.h MDGPUInstrInfo.cpp MDGPUInstrInfo.h MDGPUInstructions.td MDGPUIntrinsics.td MDGPULowerShaderInstructions.cpp MDGPULowerShaderInstructions.h MDGPURegisterInfo.cpp MDGPURegisterInfo.h MDGPURegisterInfo.td MDGPUReorderPreloadInstructions.cpp MDGPUTargetMachine.cpp MDGPUTargetMachine.h MDGPUUtil.cpp MDGPUUtil.h MDIL.h MDIL.td MDIL789IOExpansion.cpp MDIL7XXDevice.cpp MDIL7XXDevice.h MDIL7XXIOExpansion.cpp MDILAlgorithms.tpp MDILAsmBackend.cpp MDILAsmBackend.h MDILAsmPrinter7XX.cpp MDILAsmPrinterEG.cpp MDILBarrierDetect.cpp MDILBase.td MDILCFGStructurizer.cpp MDILCallingConv.td MDILCodeEmitter.h MDILCompilerErrors.h MDILCompilerWarnings.h MDILConversions.td MDILDevice.cpp MDILDevice.h MDILDeviceInfo.cpp MDILDeviceInfo.h MDILDevices.h MDILEGIOExpansion.cpp MDILELFWriterInfo.cpp MDILELFWriterInfo.h MDILEnumeratedTypes.td MDILEvergreenDevice.cpp MDILEvergreenDevice.h MDILFormats.td MDILFrameLowering.cpp MDILFrameLowering.h MDILGlobalManager.cpp MDILGlobalManager.h MDILIOExpansion.cpp MDILIOExpansion.h MDILISelDAGToDAG.cpp MDILISelLowering.cpp MDILISelLowering.h MDILImageExpansion.cpp MDILInliner.cpp MDILInstrInfo.cpp MDILInstrInfo.h MDILInstrInfo.td MDILInstrPatterns.td MDILInstructions.td MDILIntrinsicInfo.cpp MDILIntrinsicInfo.h MDILIntrinsics.td MDILKernel.h MDILKernelManager.cpp MDILKernelManager.h MDILLiteralManager.cpp MDILMCCodeEmitter.cpp MDILMachineFunctionInfo.cpp MDILMachineFunctionInfo.h MDILMachinePeephole.cpp MDILModuleInfo.cpp MDILModuleInfo.h MDILMultiClass.td MDILNIDevice.cpp MDILNIDevice.h MDILNodes.td MDILOperands.td MDILPatterns.td MDILPeepholeOptimizer.cpp MDILPointerManager.cpp MDILPointerManager.h MDILPrintfConvert.cpp MDILProfiles.td MDILRegisterInfo.cpp MDILRegisterInfo.h MDILRegisterInfo.td MDILSIDevice.cpp MDILSIDevice.h MDILSubtarget.cpp MDILSubtarget.h MDILTargetMachine.cpp MDILTargetMachine.h MDILTokenDesc.td MDILUtilityFunctions.cpp MDILUtilityFunctions.h MDILVersion.td ICENSE.TXT CTargetDesc/AMDILMCAsmInfo.cpp CTargetDesc/AMDILMCAsmInfo.h CTargetDesc/AMDILMCTargetDesc.cpp CTargetDesc/AMDILMCTargetDesc.h akefile akefile.sources rocessors.td 600CodeEmitter.cpp 600GenRegisterInfo.pl 600ISelLowering.cpp 600ISelLowering.h 600InstrFormats.td 600InstrInfo.cpp 600InstrInfo.h 600Instructions.td 600Intrinsics.td 600KernelParameters.cpp 600KernelParameters.h 600LowerInstructions.cpp 600LowerShaderInstructions.cpp 600OpenCLUtils.h 600RegisterInfo.cpp 600RegisterInfo.h 600Schedule.td IAssignInterpRegs.cpp ICodeEmitter.cpp IConvertToISA.cpp IGenRegisterInfo.pl IISelLowering.cpp IISelLowering.h IInstrFormats.td IInstrInfo.cpp IInstrInfo.h IInstrInfo.td IInstructions.td IIntrinsics.td ILowerShaderInstructions.cpp IMachineFunctionInfo.cpp IMachineFunctionInfo.h IPropagateImmReads.cpp IRegisterInfo.cpp IRegisterInfo.h ISchedule.td argetInfo/AMDILTargetInfo.cpp oader.cpp adeon_llvm.h adeon_llvm_emit.cpp adeon_setup_tgsi_llvm.c