| de2d8694e25a814696358e95141f4b1aa4d8847e |
20-Sep-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r275480
Bug: http://b/31320715
This merges commit 7dcf7f03e005379ef2f06db96aa93f06186b66d5 from
aosp/dev.
Test: Build AOSP and run RenderScript tests (host tests for slang and
libbcc, RsTest, CTS)
Change-Id: Iaf3738f74312d875e69f61d604ac058f381a2a1a
enericOpcodes.td
arget.td
argetCallingConv.h
argetCallingConv.td
argetFrameLowering.h
argetInstrInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetMachine.h
argetOpcodes.def
argetOpcodes.h
argetOptions.h
argetRecip.h
argetRegisterInfo.h
argetSchedule.td
argetSelectionDAG.td
argetSelectionDAGInfo.h
argetSubtargetInfo.h
|
| f3ef5332fa3f4d5ec72c178a2b19dac363a19383 |
04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
Change-Id: I1f29c4676a8abe633ab5707dded58d846c973d50
ostTable.h
arget.td
argetFrameLowering.h
argetInstrInfo.h
argetItinerary.td
argetLowering.h
argetLoweringObjectFile.h
argetMachine.h
argetOpcodes.h
argetOptions.h
argetRecip.h
argetRegisterInfo.h
argetSelectionDAG.td
argetSelectionDAGInfo.h
argetSubtargetInfo.h
|
| 6948897e478cbd66626159776a8017b3c18579b9 |
01-Jul-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r239765
Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.
Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
arget.td
argetCallingConv.h
argetFrameLowering.h
argetInstrInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetMachine.h
argetOpcodes.h
argetOptions.h
argetRecip.h
argetSelectionDAG.td
argetSubtargetInfo.h
|
| a18e6af1712fd41c4a705a19ad71f6e9ac7a4e68 |
20-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM with patches for fp16
Cherry-pick LLVM revisions r235191, r235215, r235220, r235341, r235363,
r235530, r235609, r235610, r237004
r235191 has a required bug-fix and the rest are all related to fp16.
Change-Id: I7fe8da5ffd8f2c06150885a54769abd18c3a04c6
argetLowering.h
|
| 0c7f116bb6950ef819323d855415b2f2b0aad987 |
06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
arget.td
argetMachine.h
argetOptions.h
argetRegisterInfo.h
argetSubtargetInfo.h
|
| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
arget.td
argetInstrInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetMachine.h
argetRegisterInfo.h
argetSelectionDAG.td
argetSubtargetInfo.h
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
arget.td
argetCallingConv.h
argetFrameLowering.h
argetInstrInfo.h
argetIntrinsicInfo.h
argetLibraryInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetMachine.h
argetOpcodes.h
argetOptions.h
argetRegisterInfo.h
argetSelectionDAG.td
argetSelectionDAGInfo.h
argetSubtargetInfo.h
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
arget.td
argetCallingConv.td
argetInstrInfo.h
argetIntrinsicInfo.h
argetJITInfo.h
argetLibraryInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetMachine.h
argetOpcodes.h
argetOptions.h
argetRegisterInfo.h
argetSchedule.td
argetSelectionDAG.td
argetSelectionDAGInfo.h
argetSubtargetInfo.h
|
| 0d30cfd0e95d828428d8fae164a4b567c005847a |
17-Oct-2014 |
Stephen Hines <srhines@google.com> |
am 281cc67b: Merge "Bring in fixes for Cortex-A53 errata + build updates."
* commit '281cc67b6ac794b1eb8232e6efca366d870dad43':
Bring in fixes for Cortex-A53 errata + build updates.
|
| bfc2d688b591c574c0cc788348c74545ce894efa |
17-Oct-2014 |
Stephen Hines <srhines@google.com> |
Bring in fixes for Cortex-A53 errata + build updates.
Bug: 18034609
Change-Id: I2cf0094eb9df801a84274ff29018431d75da89dd
argetInstrInfo.h
|
| f8e021ce4621688f8f57bf98302cba23f5d7e0f1 |
30-Sep-2014 |
Stephen Hines <srhines@google.com> |
Undefined fseeko/ftello for Windows builds.
Bug: 14416410
These are "defined" when building under mingw, so they can't be
used as identifiers in LLVM. Once we fix this in upstream, we can
pull the patch back and revert this one.
Change-Id: Ib576a9617ca685ab3625a2d2d66f652bcb7f2c3e
argetLibraryInfo.h
|
| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
arget.td
argetFrameLowering.h
argetInstrInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetOptions.h
argetRegisterInfo.h
argetSelectionDAGInfo.h
argetSubtargetInfo.h
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
arget.td
argetFrameLowering.h
argetInstrInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetOptions.h
argetRegisterInfo.h
argetSelectionDAGInfo.h
argetSubtargetInfo.h
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
arget.td
argetCallingConv.h
argetCallingConv.td
argetFrameLowering.h
argetInstrInfo.h
argetIntrinsicInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetMachine.h
argetOptions.h
argetRegisterInfo.h
argetSchedule.td
argetSubtargetInfo.h
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
angler.h
arget.td
argetCallingConv.h
argetCallingConv.td
argetLibraryInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetMachine.h
argetOpcodes.h
argetOptions.h
argetRegisterInfo.h
argetSchedule.td
argetSelectionDAG.td
argetSelectionDAGInfo.h
|
| ce9904c6ea8fd669978a8eefb854b330eb9828ff |
12-Feb-2014 |
Stephen Hines <srhines@google.com> |
Merge remote-tracking branch 'upstream/release_34' into merge-20140211
Conflicts:
lib/Linker/LinkModules.cpp
lib/Support/Unix/Signals.inc
Change-Id: Ia54f291fa5dc828052d2412736e8495c1282aa64
|
| f02a188899769cde2315c964f0fbed1d024b7514 |
25-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195491:
------------------------------------------------------------------------
r195491 | probinson | 2013-11-22 11:11:24 -0800 (Fri, 22 Nov 2013) | 11 lines
Teach ISel not to optimize 'optnone' functions (revised).
Improvements over r195317:
- Set/restore EnableFastISel flag instead of just running FastISel within
SelectAllBasicBlocks; the flag is checked in various places, and
FastISel won't run properly if those places don't do the right thing.
- Test looks for normal ISel versus FastISel behavior, and not
something more subtle that doesn't work everywhere.
Based on work by Andrea Di Biagio.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195604 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 54075bbea7e70fea6cdb9e5e89b066118c1d314b |
21-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195339:
------------------------------------------------------------------------
r195339 | chapuni | 2013-11-21 02:55:15 -0800 (Thu, 21 Nov 2013) | 5 lines
Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions."
It broke, at least, i686 target. It is reproducible with "llc -mtriple=i686-unknown".
FYI, it didn't appear to add either "-O0" or "-fast-isel".
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195375 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 0a0da619eb7a072836cf2c5debee1c5c7c8f5496 |
21-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195317:
------------------------------------------------------------------------
r195317 | probinson | 2013-11-20 22:33:32 -0800 (Wed, 20 Nov 2013) | 4 lines
Teach ISel not to optimize 'optnone' functions.
Based on work by Andrea Di Biagio.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195321 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| bb756ca24401e190e3b704e5d92759c7a79cc6b7 |
17-Nov-2013 |
Andrew Trick <atrick@apple.com> |
Added a size field to the stack map record to handle subregister spills.
Implementing this on bigendian platforms could get strange. I added a
target hook, getStackSlotRange, per Jakob's recommendation to make
this as explicit as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194942 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 509a492442b7e889d615d3b451629c81a810aef1 |
15-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add target hook to prevent folding some bitcasted loads.
This is to avoid this transformation in some cases:
fold (conv (load x)) -> (load (conv*)x)
On architectures that don't natively support some vector
loads efficiently casting the load to a smaller vector of
larger types and loading is more efficient.
Patch by Micah Villmow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 59d3ae6cdc4316ad338cd848251f33a236ccb36c |
15-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add addrspacecast instruction.
Patch by Michele Scandale!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194760 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 49837ef8111fbeace7ae6379ca733c8f8fa94cfe |
09-Nov-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move the old pass manager infrastructure into a legacy namespace and
give the files a legacy prefix in the right directory. Use forwarding
headers in the old locations to paper over the name change for most
clients during the transitional period.
No functionality changed here! This is just clearing some space to
reduce renaming churn later on with a new system.
Even when the new stuff starts to go in, it is going to be hidden behind
a flag and off-by-default as it is still WIP and under development.
This patch is specifically designed so that very little out-of-tree code
has to change. I'm going to work as hard as I can to keep that the case.
Only direct forward declarations of the PassManager class are impacted
by this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194324 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| d4f5a615674aaabeee4e444e708d1fa00a41495e |
09-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[Stackmap] Materialize the jump address within the patchpoint noop slide.
This patch moves the jump address materialization inside the noop slide. This
enables patching of the materialization itself or its complete removal. This
patch also adds the ability to define scratch registers that can be used safely
by the code called from the patchpoint intrinsic. At least one scratch register
is required, because that one is used for the materialization of the jump
address. This patch depends on D2009.
Differential Revision: http://llvm-reviews.chandlerc.com/D2074
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194306 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 623d2e618f4e672c47edff9ec63ed6d733ac81d3 |
09-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.
The idea of the AnyReg Calling Convention is to provide the call arguments in
registers, but not to force them to be placed in a paticular order into a
specified set of registers. Instead it is up tp the register allocator to assign
any register as it sees fit. The same applies to the return value (if
applicable).
Differential Revision: http://llvm-reviews.chandlerc.com/D2009
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194293 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 0de283dfa2686e30b44a3f6d7ce081588bf4910f |
05-Nov-2013 |
Todd Fiala <tfiala@google.com> |
Fixes for LLDB build to work around host 4.6.2+ compiler issues.
These fixes to the LLVM source add manual copy constructor and operator=()
methods for classes that use member bitfields and are used in templated
containers.
The intent is to keep this change (and related LLDB and clang changes)
local to android only until we either fix the compiler or use a new one
for host executable builds.
Change-Id: I8c6b31be0b3cfc79cb89b591c41cbbfdf0157c6c
argetOptions.h
|
| 5f5095e3dce0386658481353d93c11ca6123bb95 |
05-Nov-2013 |
Dmitri Gribenko <gribozavr@gmail.com> |
Convert comments to documentation comments (// -> ///)
Patch by MathOnNapkins
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194093 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 208130f11331eccab26c0a6f3146cd1891e53e33 |
03-Nov-2013 |
Bob Wilson <bob.wilson@apple.com> |
Convert calls to __sinpi and __cospi into __sincospi_stret
This adds an SimplifyLibCalls case which converts the special __sinpi and
__cospi (float & double variants) into a __sincospi_stret where appropriate to
remove duplicated work.
Patch by Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193943 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 2343e3b228c02896f4779962a91aaa659356fe2a |
31-Oct-2013 |
Andrew Trick <atrick@apple.com> |
Lower stackmap intrinsics directly to their target opcode in the DAG builder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193769 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetLowering.h
argetOpcodes.h
|
| f7c6da6fe8ba43205d2a1fb1152720bd72e7ea23 |
29-Oct-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Update comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193651 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2b0002b579dba5604a2673bbee2cd9969e183a71 |
29-Oct-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Workaround MSVC 32-bit miscompile of getCondCodeAction.
Use 32-bit types for the array instead of 64. This should
generally be better anyway.
In optimized + assert builds, I saw a failure when a
cond code / type combination that is never set was loading
a non-zero value and hitting the != Promote assert.
It turns out when loading the 64-bit value to do the shift,
the assembly loads the 2 32-bit halves from non-consecutive
addresses. The address the second half of the loaded uint64_t
doesn't include the offset of the array in the struct. Instead
of being offset + 4, it's just + 4.
I'm not entirely sure why this wasn't observed before.
setCondCodeAction isn't heavily used by the in-tree targets,
and not with the higher valued vector SimpleValueTypes. Only
PPC is using one of the > 32 valued types, and that is probably
never used by anyone on a 32-bit MSVC compiled host.
I ran into this when upgrading LLVM versions, so I guess the
value loaded from the nonsense address happened to work out
before.
No test since I'm not really sure if / how it can be reproduced
with the current in tree targets, and it's not supposed to change
anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193650 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 93cf0939f95b3d580d9c05375a7c84164e1ba72e |
29-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move getSymbol to TargetLoweringObjectFile.
This allows constructing a Mangler with just a TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193630 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
argetLoweringObjectFile.h
|
| d0716b064744598ba7df33b8b47de0375c450570 |
23-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
SelectionDAG: Pass along the original argument/element type in ISD::InputArg
For some targets, it is useful to be able to look at the original
type of an argument without having to dig through the original IR.
This also fixes a bug in SelectionDAGBuilder where InputArg.PartOffset
was not taking into account the offset of structure elements.
Patch by: Justin Holewinski
Tom Stellard:
- Changed the type of ArgVT to EVT, so it can store non-simple types
like v3i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193214 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.h
|
| e161dc28a8a58431e5e1df98834aaee72baada85 |
21-Oct-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Remove unused TargetLowering field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193113 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2d7d477d9469695a13c61d0e8b33776aed77f065 |
21-Oct-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Fix CodeGen for vectors of pointers with address spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193112 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| adbd3ae1dfa7530d23653b6fd910d28de8217fbd |
17-Oct-2013 |
Jack Carter <jack.carter@imgtec.com> |
[projects/test-suite] White space and long line fixes.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192863 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99 |
15-Oct-2013 |
Andrew Trick <atrick@apple.com> |
Fix the ExecutionDepsFix pass to handle AVX instructions.
This pass is needed to break false dependencies. Without it, unlucky
register assignment can result in wild (5x) swings in
performance. This pass was trying to handle AVX but not getting it
right. AVX doesn't have partial register defs, it has unused register
reads in which the high bits of a source operand are copied into the
unused bits of the dest.
Fixing this requires conservative liveness analysis. This is awkard
because the pass already has its own pseudo-liveness. However, proper
liveness is expensive, and we would like to use a generic utility to
compute it. The fix only invokes liveness on-demand. It is rare to
detect a case that needs undef-read dependence breaking, but when it
happens, it can be needed many times within a very large block.
I think the existing heuristic which uses a register window of 16 is
too conservative for loop-carried false dependencies. If the loop is a
reduction. The out-of-order engine may be able to execute several loop
iterations in parallel. However, I'll leave this tuning exercise for
next time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192635 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 83f743a4d5b4298893adaada0270ff2d832a50c7 |
11-Oct-2013 |
Quentin Colombet <qcolombet@apple.com> |
[DAGCombiner] Reapply load slicing (192471) with a test that explicitly set sse4.2 support.
This should fix the buildbots.
Original commit message:
[DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads
combining.
E.g., this optimization will transform something like this:
a = load i64* addr
b = trunc i64 a to i32
c = lshr i64 a, 32
d = trunc i64 c to i32
into:
b = load i32* addr1
d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.
One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.
<rdar://problem/14477220>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192476 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4351741a3b36bfe1ac1b385334fc5fa6f6ef5a11 |
11-Oct-2013 |
Quentin Colombet <qcolombet@apple.com> |
[DAGCombiner] Revert load slicing (r192471), until I figure out why it fails on ubuntu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192474 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c34693f6efc670b71e11f3479844c36d9696b535 |
11-Oct-2013 |
Quentin Colombet <qcolombet@apple.com> |
[DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads
combining.
E.g., this optimization will transform something like this:
a = load i64* addr
b = trunc i64 a to i32
c = lshr i64 a, 32
d = trunc i64 c to i32
into:
b = load i32* addr1
d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.
One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.
<rdar://problem/14477220>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192471 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4d91232df1f385f0f89c767f1d297b1088f26f67 |
10-Oct-2013 |
Sriram Murali <sriram87@gmail.com> |
test commit
- fix comments on vector type legalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192389 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 89dedc1b65cb09a652d251273e2eae938dead60b |
10-Oct-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Fix grammar / missing words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192380 91177308-0d34-0410-b5e6-96231b3b80d8
argetOpcodes.h
|
| d42730dc712026cbfb1322a979e0ac72cd31a19e |
30-Sep-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
IfConverter: Use TargetSchedule for instruction latencies
For targets that have instruction itineraries this means no change. Targets
that move over to the new schedule model will use be able the new schedule
module for instruction latencies in the if-converter (the logic is such that if
there is no itineary we will use the new sched model for the latencies).
Before, we queried "TTI->getInstructionLatency()" for the instruction latency
and the extra prediction cost. Now, we query the TargetSchedule abstraction for
the instruction latency and TargetInstrInfo for the extra predictation cost. The
TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if
an itinerary exists, otherwise it will use the new schedule model.
ATTENTION: Out of tree targets!
(I will also send out an email later to LLVMDev)
This means, if your target implements
unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
unsigned *PredCost);
and returns a value for "PredCost", you now also need to implement
unsigned getPredictationCost(const MachineInstr *MI);
(if your target uses the IfConversion.cpp pass)
radar://15077010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 3f4f420ab7acb10221ba971543a7eed5489fb626 |
28-Sep-2013 |
Robert Wilhelm <robert.wilhelm@gmx.net> |
Even more spelling fixes for "instruction".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| b6ac11cd03e9dd97b45dc97787171f942ef8e344 |
26-Sep-2013 |
Andrew Trick <atrick@apple.com> |
Added temp flag -misched-bench for staging in default changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191423 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| 070156437752179833b1e5fddd50caa03fd7c12f |
25-Sep-2013 |
Andrew Trick <atrick@apple.com> |
Mark the x86 machine model as incomplete. PR17367.
Ideally, the machinel model is added at the time the instructions are
defined. But many instructions in X86InstrSSE.td still need a model.
Without this workaround the scheduler asserts because x86 already has
itinerary classes for these instructions, indicating they should be
modeled by the scheduler. Since we use the new machine model for other
instructions, it expects a new machine model for these too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191391 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| 715d98d657491b3fb8ea0e14643e9801b2f9628c |
12-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.
The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
ComplexDeprecationPredicate<"MCR">
would mean you would have to define the following function:
bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info)
Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.
The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 38e61122f27a8ca4ef0578eaf6dc5242880d2918 |
06-Sep-2013 |
Andrew Trick <atrick@apple.com> |
Added MachineSchedPolicy.
Allow subtargets to customize the generic scheduling strategy.
This is convenient for targets that don't need to add new heuristics
by specializing the strategy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190176 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| d1d0d37a198df718b0fd1f838b7d9593b1636299 |
04-Sep-2013 |
Andrew Trick <atrick@apple.com> |
mi-sched: Load clustering is a bit to expensive to enable unconditionally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189990 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 19fdc268c316b3b0bdcb2b558449819f4f402d6a |
04-Sep-2013 |
Hao Liu <Hao.Liu@arm.com> |
Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
and 4 convert instructions:
scvtf,ucvtf,fcvtzs,fcvtzu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 738073c4aa474e27c9d3c991daf593bddce54718 |
29-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add useAA() to TargetSubtargetInfo
There are several optional (off-by-default) features in CodeGen that can make
use of alias analysis. These features are important for generating code for
some kinds of cores (for example the (in-order) PPC A2 core). This adds a
useAA() function to TargetSubtargetInfo to allow these features to be enabled
by default on a per-subtarget basis.
Here is the first use of this function: To control the default of the
-enable-aa-sched-mi feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189563 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| da25cd3e6de8f21005590c2de49868f883cf2410 |
26-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
SelectionDAG: Use correct pointer size when lowering function arguments v2
This adds minimal support to the SelectionDAG for handling address spaces
with different pointer sizes. The SelectionDAG should now correctly
lower pointer function arguments to the correct size as well as generate
the correct code when lowering getelementptr.
This patch also updates the R600 DataLayout to use 32-bit pointers for
the local address space.
v2:
- Add more helper functions to TargetLoweringBase
- Use CHECK-LABEL for tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189221 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 12d3dc73dc44acd8b11cca783b826ccbd66f44da |
23-Aug-2013 |
Andrew Trick <atrick@apple.com> |
PrintVRegOrUnit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189124 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| d93969c32a6bbae3326a1f485c4c85be1cb39406 |
23-Aug-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an OtherPreserved field to the CalleeSaved TableGen class.
This field specifies registers that are preserved across function calls,
but that should not be included in the generates SaveList array.
This can be used ot generate regmasks for architectures that save
registers through other means, like SPARC's register windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189084 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.td
|
| f7ab3a84b3e1b5a647ae9456a5edb99d86b35329 |
22-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.
TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 8c20158fb0e1e5d747077f065eb0170c5af1fbfa |
20-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use SRST to optimize memchr
SystemZTargetLowering::emitStringWrapper() previously loaded the character
into R0 before the loop and made R0 live on entry. I'd forgotten that
allocatable registers weren't allowed to be live across blocks at this stage,
and it confused LiveVariables enough to cause a miscompilation of f3 in
memchr-02.ll.
This patch instead loads R0 in the loop and leaves LICM to hoist it
after RA. This is actually what I'd tried originally, but I went for
the manual optimisation after noticing that R0 often wasn't being hoisted.
This bug forced me to go back and look at why, now fixed as r188774.
We should also try to optimize null checks so that they test the CC result
of the SRST directly. The select between null and the SRST GPR result could
then usually be deleted as dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188779 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
argetSelectionDAGInfo.h
|
| 19262ee0725a09b7c621a3d2eb66ba1513ae932a |
16-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use SRST to implement strlen and strnlen
It would also make sense to use it for memchr; I'm working on that now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188547 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
argetSelectionDAGInfo.h
|
| 4fc7355a21e1fa838406e15459aaf54a58fcf909 |
16-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use MVST to implement strcpy and stpcpy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188546 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
argetSelectionDAGInfo.h
|
| e1b2af731e2a45344a7c502232f66c55cd746da0 |
16-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use CLST to implement strcmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188544 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
argetSelectionDAGInfo.h
|
| 3add0679d24a00c4a585809c6ce54486f6a458f5 |
13-Aug-2013 |
Michael Gottesman <mgottesman@apple.com> |
Update makeLibCall to return both the call and the chain associated with the libcall instead of just the call. This allows us to specify libcalls that return void.
LowerCallTo returns a pair with the return value of the call as the first
element and the chain associated with the return value as the second element. If
we lower a call that has a void return value, LowerCallTo returns an SDValue
with a NULL SDNode and the chain for the call. Thus makeLibCall by just
returning the first value makes it impossible for you to set up the chain so
that the call is not eliminated as dead code.
I also updated all references to makeLibCall to reflect the new return type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188300 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ac168b8bc8773a083a10902f64e4ae57a925aee4 |
12-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use CLC and IPM to implement memcmp
For now this is restricted to fixed-length comparisons with a length
in the range [1, 256], as for memcpy() and MVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188163 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAGInfo.h
|
| fc6434a73d053c3e1d9c79034a267ae1434483ad |
09-Aug-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add a overload to CostTable which allows it to infer the size of the table.
Use it to avoid repeating ourselves too often. Also store MVT::SimpleValueType
in the TTI tables so they can be statically initialized, MVT's constructors
create bloated initialization code otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188095 91177308-0d34-0410-b5e6-96231b3b80d8
ostTable.h
|
| 41418d17cced656f91038b2482bc9d173b4974b0 |
08-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add ISD::FROUND for libm round()
All libm floating-point rounding functions, except for round(), had their own
ISD nodes. Recent PowerPC cores have an instruction for round(), and so here I'm
adding ISD::FROUND so that round() can be custom lowered as well.
For the most part, this is straightforward. I've added an intrinsic
and a matching ISD node just like those for nearbyint() and friends. The
SelectionDAG pattern I've named frnd (because ISD::FP_ROUND has already claimed
fround).
This will be used by the PowerPC backend in a follow-up commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187926 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
argetSelectionDAG.td
|
| d113448c1dd5f40522c3c02db96e87a9eb59eaf4 |
06-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
Refactor isInTailCallPosition handling
This change came about primarily because of two issues in the existing code.
Niether of:
define i64 @test1(i64 %val) {
%in = trunc i64 %val to i32
tail call i32 @ret32(i32 returned %in)
ret i64 %val
}
define i64 @test2(i64 %val) {
tail call i32 @ret32(i32 returned undef)
ret i32 42
}
should be tail calls, and the function sameNoopInput is responsible. The main
problem is that it is completely symmetric in the "tail call" and "ret" value,
but in reality different things are allowed on each side.
For these cases:
1. Any truncation should lead to a larger value being generated by "tail call"
than needed by "ret".
2. Undef should only be allowed as a source for ret, not as a result of the
call.
Along the way I noticed that a mismatch between what this function treats as a
valid truncation and what the backends see can lead to invalid calls as well
(see x86-32 test case).
This patch refactors the code so that instead of being based primarily on
values which it recurses into when necessary, it starts by inspecting the type
and considers each fundamental slot that the backend will see in turn. For
example, given a pathological function that returned {{}, {{}, i32, {}}, i32}
we would consider each "real" i32 in turn, and ask if it passes through
unchanged. This is much closer to what the backend sees as a result of
ComputeValueVTs.
Aside from the bug fixes, this eliminates the recursion that's going on and, I
believe, makes the bulk of the code significantly easier to understand. The
trade-off is the nasty iterators needed to find the real types inside a
returned value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187787 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 425b76c2314ff7ee7ad507011bdda1988ae481ef |
06-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
TargetLowering: Add getVectorIdxTy() function v2
This virtual function can be implemented by targets to specify the type
to use for the index operand of INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT,
INSERT_SUBVECTOR, EXTRACT_SUBVECTOR. The default implementation returns
the result from TargetLowering::getPointerTy()
The previous code was using TargetLowering::getPointerTy() for vector
indices, because this is guaranteed to be legal on all targets. However,
using TargetLowering::getPointerTy() can be a problem for targets with
pointer sizes that differ across address spaces. On such targets,
when vectors need to be loaded or stored to an address space other than the
default 'zero' address space (which is the address space assumed by
TargetLowering::getPointerTy()), having an index that
is a different size than the pointer can lead to inefficient
pointer calculations, (e.g. 64-bit adds for a 32-bit address space).
There is no intended functionality change with this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187748 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 61fc8d670f1e991804c2ab753e567981e60962cb |
01-Aug-2013 |
Bill Wendling <isanbard@gmail.com> |
Use function attributes to indicate that we don't want to realign the stack.
Function attributes are the future! So just query whether we want to realign the
stack directly from the function instead of through a random target options
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187618 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 588f408b95c83e9b59c0777925d2ae70ac445fae |
01-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187569 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| fdbea5107b5a8249421fd5e603a31f40f05ea25f |
29-Jul-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Use proper section suffix for COFF weak symbols
32-bit symbols have "_" as global prefix, but when forming the name of
COMDAT sections this prefix is ignored. The current behavior assumes that
this prefix is always present which is not the case for 64-bit and names
are truncated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187356 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| c572005d7be00b824a105a313532529c678bd0d3 |
25-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
Fix a comment cut-&-pasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187117 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f245ae5a4a78d5a02b3b9e2dae819077a56d81e7 |
25-Jul-2013 |
Bill Wendling <isanbard@gmail.com> |
Replace the "NoFramePointerElimNonLeaf" target option with a function attribute.
There's no need to specify a flag to omit frame pointer elimination on non-leaf
nodes...(Honestly, I can't parse that option out.) Use the function attribute
stuff instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187093 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 1f67c63cb23ba5d405452d72bb8892df6b7ccd4f |
24-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free
This commit also implements these functions for R600 and removes a test
case that was relying on the buggy behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0dcba2fadb990ba2298ba43d76372c754b240cee |
22-Jul-2013 |
Bill Wendling <isanbard@gmail.com> |
Recommit r186217 with testcase fix:
Use the function attributes to pass along the stack protector buffer size.
Now that we have robust function attributes, don't use a command line option to
specify the stack protecto buffer size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186863 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 72c8331ec1437f8c33fff1dac1ea0ebb11009411 |
22-Jul-2013 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Treat nothrow forms of ::operator delete and ::operator delete[] as
deallocation functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186798 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 9273151c3bbc96c9b2911caffe3e1a724261cd06 |
16-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch allows targets to define weather the instruction mnemonics in asm matcher tables will contain '.' character.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186388 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 12c74dc2c2ee306f60fb39a9b2a43000e23addcc |
13-Jul-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Revert commit r186217 -- this is breaking bots:
http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-nobootstrap-RAincremental/builds/4328
Original commit log:
Use the function attributes to pass along the stack protector buffer
size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186234 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 8a50013cc23810aa3e1ac8da66764fbb2d96147e |
13-Jul-2013 |
Bill Wendling <isanbard@gmail.com> |
Use the function attributes to pass along the stack protector buffer size.
Now that we have robust function attributes, don't use a command line option to
specify the stack protecto buffer size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186217 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 7042aa598dde44ef74eb3ba1ae729729e64c46cf |
11-Jul-2013 |
Michael Gottesman <mgottesman@apple.com> |
Fixed up comments in TargetLowering.h to conform to the LLVM Style Guide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186121 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e54885af9b54bfc7436a928a48d3db1ef88a2a70 |
09-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185956 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 71804149a3a6f6c081b874869b27fafe7d3288ce |
05-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Remove no-op MVCs
The stack coloring pass has code to delete stores and loads that become
trivially dead after coloring. Extend it to cope with single instructions
that copy from one frame index to another.
The testcase happens to show an example of this kicking in at the moment.
It did occur in Real Code too though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185705 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 7271ac2c0318043688ddc8686dd23777dca62c59 |
05-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Clean up register scavenging code
SystemZ wants normal register scavenging slots, as close to the stack or
frame pointer as possible. The only reason it was using custom code was
because PrologEpilogInserter assumed an x86-like layout, where the frame
pointer is at the opposite end of the frame from the stack pointer.
This meant that when frame pointer elimination was disabled,
the slots ended up being as close as possible to the incoming
stack pointer, which is the opposite of what we want on SystemZ.
This patch adds a new knob to say which layout is used and converts
SystemZ to use target-independent scavenging slots. It's one of the pieces
needed to support frame-to-frame MVCs, where two slots might be required.
The ABI requires us to allocate 160 bytes for calls, so one approach
would be to use that area as temporary spill space instead. It would need
some surgery to make sure that the slot isn't live across a call though.
I stuck to the "isFPCloseToIncomingSP - ..." style comment on the
"do what the surrounding code does" principle. The FP case is already
covered by several Systemz/frame-* tests, which fail without the
PrologueEpilogueInserter change, so no new ones are needed.
No behavioural change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185696 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameLowering.h
|
| f0f85eab0469ac93f9bb6c7d19aca2c35868d83a |
03-Jul-2013 |
Michael Gottesman <mgottesman@apple.com> |
Added posix function gettimeofday to LibFunc::Func for all platforms but Windows.
*NOTE* In a recent version of posix, they added the restrict keyword to the
arguments for this function. From some spelunking it seems that on some
platforms, the call has restrict on its arguments and others it does not. Thus I
left off the restrict keyword from the function prototype in the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185501 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 716a94f0c96d6bef575cd286bafb2cc507adc6b0 |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[DebugInfo] Allow getDebugThreadLocalSymbol to return MCExpr
This allows getDebugThreadLocalSymbol to return a generic MCExpr
instead of just a MCSymbolRefExpr.
This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185460 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 59eaa3874663f80ce111a4781b8f1db82995210c |
28-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
DebugInfo: PR14728: TLS support
Based on GCC's output for TLS variables (OP_constNu, x@dtpoff,
OP_lo_user), this implements debug info support for TLS in ELF. Verified
that this output is correct/sufficient on Linux (using gold - if you're
using binutils-ld, you'll need something with the fix for
http://sourceware.org/bugzilla/show_bug.cgi?id=15685 in it).
Support on non-ELF is sort of "arbitrary" at the moment - if Apple folks
want to discuss (or just go ahead & implement) how this should work in
MachO, etc, I'm open.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185203 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 898b9f020d1089f679d1b1939fd6aafa9de4b411 |
25-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184879 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| face8d901ebc2f3ac26e303603aae1b9304c4728 |
20-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Remove static, because it was messing everything up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184400 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 3b6e067f56db88509d9254ecc70951d77d51a2d7 |
20-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Make the '==' operator inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184375 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 8623ecb263ef2b2e13e34608d90dca52f21fd6db |
20-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Make this static inline to avoid duplicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184374 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 59aa54073848645cd20c828dfb1088127c541b36 |
20-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Make the comparison operators non-member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184373 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 2e1dc2d2650c64f8fa57d12eb194dcf57e85ebb7 |
19-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Add operator!= as the compliment to operator==. This is for a future change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184348 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| d10fa8b1caf010fe4943ae5526c2c3b921339f72 |
17-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Directly access objects which may change during compilation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184121 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 0187e7a9ba5c50b4559e0c2e0afceb6d5cd32190 |
16-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| a3d82ce19fd825cbf3bf85b5969424217fc40b45 |
15-Jun-2013 |
Andrew Trick <atrick@apple.com> |
Support BufferSize on ProcResGroup for unified MOp schedulers.
And add Sandybridge/Haswell resource buffers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184034 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| b86a0cdb674549d8493043331cecd9cbf53b80da |
15-Jun-2013 |
Andrew Trick <atrick@apple.com> |
Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize
These can be used to more precisely model instruction execution if desired.
Disabled some misched tests temporarily. They'll be reenabled in a few commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetSchedule.td
|
| 48d5e750a8189c55087333d2bbc5dd0e1e07ddfa |
10-Jun-2013 |
Duncan Sands <baldrick@free.fr> |
Avoid warnings about unused parameters that tend to come up a lot when
building outside projects with a different compiler than that used to build
LLVM itself (eg switching between gcc and clang).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183650 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetMachine.h
|
| 23ed37a6b76e79272194fb46597f7280661b828f |
01-Jun-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
Make SubRegIndex size mandatory, following r183020.
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 06f5ebc5a1604b01689cf2d482dd05f956538af6 |
31-May-2013 |
Quentin Colombet <qcolombet@apple.com> |
Loop Strength Reduce: Scaling factor cost.
Account for the cost of scaling factor in Loop Strength Reduce when rating the
formulae. This uses a target hook.
The default implementation of the hook is: if the addressing mode is legal, the
scaling factor is free.
<rdar://problem/13806271>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183045 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| bed23081860275c79137f65d592920e7991b8198 |
31-May-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
Add a way to define the bit range covered by a SubRegIndex.
NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.
In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| cc5a882c96af6e36bc029b7ff69f62f94e2d041d |
29-May-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't reach into the middle of TargetMachine and cache one of its ivars.
Not only does this break encapsulation, it's gross.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182876 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| b704d23062aa78b00999b75dcdcb628d4d84ee3f |
27-May-2013 |
Preston Gurd <preston.gurd@intel.com> |
Convert sqrt functions into sqrt instructions when -ffast-math is in effect.
When -ffast-math is in effect (on Linux, at least), clang defines
__FINITE_MATH_ONLY__ > 0 when including <math.h>. This causes the
preprocessor to include <bits/math-finite.h>, which renames the sqrt functions.
For instance, "sqrt" is renamed as "__sqrt_finite".
This patch adds the 3 new names in such a way that they will be treated
as equivalent to their respective original names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182739 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetSelectionDAGInfo.h
|
| f9c3ea31db080e361a96df0b11cee3e835c6a6a1 |
22-May-2013 |
Owen Anderson <resistor@mac.com> |
Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182450 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 997fa623fc14122153c58ddda8c90aa30f192cc8 |
16-May-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterInfo::getCoveringLanes().
This lane mask provides information about which register lanes
completely cover super-registers. See the block comment before
getCoveringLanes().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 4a971705bc6030dc2e4338b3cd5cffa2e0f88b7b |
13-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the MachineMove class.
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| e4496548155ba6606f107fbdc10ea17e58fd3401 |
07-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove exception handling support from the old JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181354 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 3e39731e88f2d4f597cebc74388fd6650ca4f604 |
23-Apr-2013 |
Eric Christopher <echristo@gmail.com> |
Move C++ code out of the C headers and into either C++ headers
or the C++ files themselves. This enables people to use
just a C compiler to interoperate with LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180063 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 94a720c73e11f8b2f532d3dfb4e145c6b35a2ea2 |
21-Apr-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Remove unused, undefined ArgFlagsTy::getArgFlagsString; add a comment about 'returned'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179983 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.h
|
| 8b71994fde0f0fcdf7a8260dc773fb7376b1231f |
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused ShouldFoldAtomicFences flag.
I think it's almost impossible to fold atomic fences profitably under
LLVM/C++11 semantics. As a result, this is now unused and just
cluttering up the target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6265d5c91a18b2fb6499eb581c488315880c044d |
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 456ca048af35163b9f52187e92a23ee0a9f059e8 |
20-Apr-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179925 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.h
argetLowering.h
|
| 88eb89b89f9426feb7be9b19d1a664b37c590bdb |
19-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
[asm parser] Add support for predicating MnemonicAlias based on the assembler
variant/dialect. Addresses a FIXME in the emitMnemonicAliases function.
Use and test case to come shortly.
rdar://13688439 and part of PR13340.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179804 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 05862c97887f66f5b58fda0f83e870a56d3babbe |
18-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
Fix comment spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179761 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| cd3d60c4505efad809a3d8b4ba9aed315568f8d8 |
07-Apr-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
TargetLowering: Fix getTypeConversion handling of extended vector types
The code in getTypeConversion attempts to promote the element vector type
before it trys to split or widen the vector.
After it failed finding a legal vector type by promoting it would continue using
the promoted vector element type. Thereby missing legal splitted vector types.
For example the type v32i32 that has a legal split of 4 x v3i32 on x86/sse2
would be transformed to: v32i256 and from there on successively split to:
v16i256, v8i256, v1i256 and then finally ends up as an i64 type.
By resetting the vector element type to the original vector element type that
existed before the promotion the code will attempt to split the vector type to
smaller vector widths of the same type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178999 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a36119beeceb125fe2097da2729dca886973b108 |
06-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a comment to TargetInstrInfo about FoldImmediate
This comment documents the current behavior of the ARM implementation of this
callback, and also the soon-to-be-committed PPC version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178959 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 13bbe1f52e8d57151e2730db49094e1c62a4c793 |
05-Apr-2013 |
Bill Wendling <isanbard@gmail.com> |
Use the target options specified on a function to reset the back-end.
During LTO, the target options on functions within the same Module may
change. This would necessitate resetting some of the back-end. Do this for X86,
because it's a Friday afternoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178917 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetOptions.h
|
| 78dd7a580c7ad7234395d2c0207c98e751378cd7 |
05-Apr-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Clean up some confusing language, and use more realistic examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178828 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 74a4533a4290b7c6f1fe04a30ca13ec25c529e0a |
29-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 64110ffc9eecbe999c29ac9d9f6697447a110036 |
15-Mar-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add SchedRW as an Instruction field.
Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:
let SchedRW = ... in {
...
}
Which is now possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| f8b0a08b6a2e2f4eacdb05eae9a8dd704b692b55 |
14-Mar-2013 |
Reed Kotler <rkotler@mips.com> |
Add a new method which enables one to change register classes.
See the Mips16ISetLowering.cpp patch to see a use of this.
For now now the extra code in Mips16ISetLowering.cpp is a nop but is
used for test purposes. Mips32 registers are setup and then removed and
then the Mips16 registers are setup.
Normally you need to add register classes and then call
computeRegisterProperties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177120 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1754aca83af1658c832706889c0e2933f8dfa8ee |
14-Mar-2013 |
Andrew Trick <atrick@apple.com> |
MachineModel: Add a ProcResGroup class.
This allows abitrary groups of processor resources. Using something in
a subset automatically counts againts the superset. Currently, this
only works if the superset is also a ProcResGroup as opposed to a
SuperUnit.
This allows SandyBridge to be expressed naturally, which will be
checked in shortly.
def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177112 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| 3080d23fde4981835d8a7faf46c152441fadb11f |
14-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Provide the register scavenger to processFunctionBeforeFrameFinalized
Add the current PEI register scavenger as a parameter to the
processFunctionBeforeFrameFinalized callback.
This change is necessary in order to allow the PowerPC target code to
set the register scavenger frame index after the save-area offset
adjustments performed by processFunctionBeforeFrameFinalized. Only
after these adjustments have been made is it possible to estimate
the size of the stack frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameLowering.h
|
| 4cb1f5f4064f2eec1420dc30bf32ac54bd40e222 |
13-Mar-2013 |
Bill Wendling <isanbard@gmail.com> |
Reset some of the target options which affect code generation.
This doesn't reset all of the target options within the TargetOptions
object. This is because some of those are ABI-specific and must be determined if
it's okay to change those on the fly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176986 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| cf70590c38ef580758c8a255519959fc7160fdb2 |
05-Mar-2013 |
Meador Inge <meadori@codesourcery.com> |
Add more functions to the TLI.
This patch adds many more functions to the target library information.
All of the functions being added were discovered while doing the migration
of the simplify-libcalls attribute annotation functionality to the
functionattrs pass. As a part of that work the attribute annotation logic
will query TLI to determine if a function should be annotated or not.
Signed-off-by: Meador Inge <meadori@codesourcery.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176514 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| a6b20ced765b67a85d9219d0c8547fc9c133e14f |
01-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
but TLI.getShiftAmountTy() so far only return scalar type. As a
result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
return target-specificed scalar type or the same vector type as the
1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 700ed80d3da5e98e05ceb90e9bfb66058581a6db |
21-Feb-2013 |
Eli Bendersky <eliben@google.com> |
Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.
There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.
The refactoring was OK'd by Anton Korobeynikov on llvmdev.
Note: this touches the target interfaces, so out-of-tree targets may
be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameLowering.h
argetRegisterInfo.h
|
| 3450f800aa65c91f0496816ba6061a422a74c1fe |
20-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 98fbe27ac8f0766ea94b89b8c03418131b72bea4 |
18-Feb-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175457 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameLowering.h
|
| 789cb5df9ca61f8a3794a4fbde7cc020fd00a02a |
15-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Use the 'target-features' and 'target-cpu' attributes to reset the subtarget features.
If two functions require different features (e.g., `-mno-sse' vs. `-msse') then
we want to honor that, especially during LTO. We can do that by resetting the
subtarget's features depending upon the 'target-feature' attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175314 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| ff9d058f2865bca72f63dd9d7d7067c49f95f33c |
14-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add deprecation of neverHasSideEffects to documentation comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175175 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 108fb3202af6f500073cdbb7be32c25d7a273a2e |
31-Jan-2013 |
Chad Rosier <mcrosier@apple.com> |
[PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| b3755e7fa2e386e9bd348eda6b1876ae09c1bf99 |
25-Jan-2013 |
Renato Golin <renato.golin@linaro.org> |
Moving Cost Tables up to share with other targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173382 91177308-0d34-0410-b5e6-96231b3b80d8
ostTable.h
|
| b09350d9a5639f55c46659b30be12a0c938378ab |
23-Jan-2013 |
Chad Rosier <mcrosier@apple.com> |
Initialize SSPBufferSize. PR14999. Patch by Vinson Lee.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173285 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 69e42dbd006c0afb732067ece7327988b1e24c01 |
11-Jan-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Split TargetLowering into a CodeGen and a SelectionDAG part.
This fixes some of the cycles between libCodeGen and libSelectionDAG. It's still
a complete mess but as long as the edges consist of virtual call it doesn't
cause breakage. BasicTTI did static calls and thus broke some build
configurations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172246 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 674be02d525d4e24bc6943ed9274958c580bcfbc |
10-Jan-2013 |
Jakub Staszak <kubastaszak@gmail.com> |
Fix include guards so they exactly match file names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172025 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| 73b984530f42d1b829a8de8824ae354a133d998a |
09-Jan-2013 |
David Tweed <david.tweed@arm.com> |
For some LLVM-as-library uses it is convenient to create a
subclass of TargetMachine which "forwards" all operations to an
existing internal TargetMachine member variable. In the usage context the
specific-machine class derived from TargetMachine is not visible,
only a reference to the generic base class TargetMachine. Although
getSubtargetImpl() is public in specific-machine classes derived from
TargetMachine, the TargetMachine class unfortunately has
getSubtargetImpl() protected (and accessing non-const members makes
abusing getSubtarget() unsuitable). Making it public in the base class
allows this forwarding pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171976 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 2c8cf4b404e549482f593f62f9e27e0bab4a8b3f |
09-Jan-2013 |
Tim Northover <Tim.Northover@arm.com> |
Refactor to expose RTLIB calls to targets.
fp128 is almost but not quite completely illegal as a type on AArch64. As a
result it needs to have a register class (for argument passing mainly), but all
operations need to be lowered to runtime calls. Currently there's no way for
targets to do this (without duplicating code), as the relevant functions are
hidden in SelectionDAG. This patch changes that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171971 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 47579cf390c42e0577519e0a2b6044baece9df00 |
09-Jan-2013 |
Andrew Trick <atrick@apple.com> |
MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.
I converted some in-order scheduling tests to A2. Hal is working on
more test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| 56d433dffe02e14cafaab44d2628e20dc0bf26fe |
07-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Sink AddrMode back into TargetLowering, removing one of the most
peculiar headers under include/llvm.
This struct still doesn't make a lot of sense, but it makes more sense
down in TargetLowering than it did before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171739 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| aeef83c6afa1e18d1cf9d359cc678ca0ad556175 |
07-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetMachine.h
argetTransformImpl.h
|
| 64e407be0d91916d71c9259f62ba5c1f4b2993ca |
05-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Refactor the ScalarTargetTransformInfo API for querying about the
legality of an address mode to not use a struct of four values and
instead to accept them as parameters. I'd love to have named parameters
here as most callers only care about one or two of these, but the
defaults aren't terribly scary to write out.
That said, there is no real impact of this as the passes aren't yet
using STTI for this and are still relying upon TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171595 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| e503319874f57ab4a0354521b03a71cf8e07b866 |
04-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
LoopVectorizer:
1. Add code to estimate register pressure.
2. Add code to select the unroll factor based on register pressure.
3. Add bits to TargetTransformInfo to provide the number of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171469 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| 82860f63e1678077fe665c21179b9df47fd313bb |
03-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a subtype parameter to VTTI::getShuffleCost
In order to cost subvector insertion and extraction, we need to know
the type of the subvector being extracted.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171453 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetLowering.h
argetLoweringObjectFile.h
argetRegisterInfo.h
|
| 8b62abdd7b9c8fc5d78dad86093f4afdfeba949d |
30-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171256 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3190be9c9a9f4c69591f78ed65dd7b06dd6c80c1 |
27-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
DAGCombinerInformation: add a getter that exposes the dagcombine level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171152 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 444b4bf5c84c80833ff283244de0885124091a13 |
27-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum.
Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171142 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4595528781b8bc9bb9cf6a6fc8ba557ef5bf7d96 |
26-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
white space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171090 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1e1c5f37c3a9b27c71d7d3a9e22f819200fb38b4 |
24-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
CostModel: We have API for checking the costs of known shuffles. This patch adds
support for the insert-subvector and extract-subvector kinds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171027 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| daf7b5c8f2889ddb923544565f07518d504aa574 |
24-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
Change the codegen Cost Model API for shuffeles. This patch removes the API for broadcast and adds a more general API that accepts an enum of known shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171022 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| 6f3d81a92919954d156c863d3aeb4ff09f701480 |
23-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
CostModel: Change the default target-independent implementation for finding
the cost of arithmetic functions. We now assume that the cost of arithmetic
operations that are marked as Legal or Promote is low, but ops that are
marked as custom are higher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171002 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d54fed27865dcbc69932e1e6c372bb5a932e662a |
23-Dec-2012 |
Nadav Rotem <nrotem@apple.com> |
Loop Vectorizer: Update the cost model of scatter/gather operations and make
them more expensive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170995 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| e188fb7dd91c6fee15aa18c877d664d63d736000 |
20-Dec-2012 |
Jim Grosbach <grosbach@apple.com> |
Move isSubRegister() and isSuperRegister to MCRegisterInfo.
These were defined on TargetRegisterInfo, but they don't use any information
that's not available in MCRegisterInfo, so sink them down to be available
at the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170608 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| c698d3a2a40f0909d16cbe857685f0f22cb9ae43 |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change AsmOperandInfo::ConstraintVT to MVT, instead of EVT.
Accordingly, add MVT::getVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170550 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 35d346294128038794637b384fcc5f97ff3d9978 |
19-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make TargetLowering::getTypeConversion more resilient against odd illegal MVTs.
- An MVT can become an EVT when being split (e.g. v2i8 -> v1i8, the latter doesn't exist)
- Return the scalar value when an MVT is scalarized (v1i64 -> i64)
Fixes PR14639ff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170546 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e5c65911a659e49320d214bf0702793ad37b5ed5 |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170537 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ee211d2b8da98a549f7c68401aba866fa2a0eee2 |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,
from EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170536 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| dfcf33a287d1756721f1f735af687595ce2f5a21 |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of
EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170535 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ff01277841b824128c74cdb66f74d8082d75e3f6 |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::TransformToType to contain MVTs, instead of
EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170534 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1317d26461a18424509ab1078ea361d1856e535d |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRepRegClassCostFor, getIndexedLoadAction,
getIndexedStoreAction, and addRegisterClass to take and MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170533 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0340557fb830e3669c4c48a2cd99d7703bdda452 |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170532 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 319bb399233d3ee67233aa29235c8ad2148fb77d |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getTypeToPromoteTo to take and return MVTs,
instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170529 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| fdbeb057b8a844b641f323fd27a61ffcb32b43da |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170524 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9c5ab9355e00686e120e12952908ea8ad981d776 |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getCondCodeAction to take an MVT, instead of
EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170522 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 88ef514cc63c3f22f78eaf4dd295d349b4070819 |
19-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170510 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 034b94b17006f51722886b0f2283fb6fb19aca1f |
19-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 702474dbb2d4fbaf7b93bcccd71b7b80a8ec2817 |
14-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getLoadExtAction to take an MVT, instead of
EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170183 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 009e1e21d4e4d26d4aeaeeb5063c0b4470572ef7 |
13-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170148 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 860e7cdab9d5eceda5ac52ae0ddfb4bdab0067f2 |
13-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.
Accordingly, change RegDefIter to contain MVTs instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170140 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a61b17c18a67f1b3faef2f2108379c4337ce9bb7 |
13-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.
This is the first, in a series of patches.
This is the second attempt. In the first attempt (r169837), a few
getSimpleVT() were hoisted too far, detected by bootstrap failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170104 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 946a3a9f22c967d5432eaab5fa464b91343477cd |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?
This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7d34267df63e23be1957f738de783c145febb7af |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
- Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 61f4dfe3693bf68b20748d82ac4dd9bf2f356699 |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Avoid using lossy load / stores for memcpy / memset expansion. e.g.
f64 load / store on non-SSE2 x86 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169944 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e07f85eb76a0254d3adbdf8b5d61ff5c07858cef |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Replace TargetLowering::isIntImmLegal() with
ScalarTargetTransformInfo::getIntImmCost() instead. "Legal" is a poorly defined
term for something like integer immediate materialization. It is always possible
to materialize an integer immediate. Whether to use it for memcpy expansion is
more a "cost" conceern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169929 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 34525f9ac098c1c6bc9002886d6da3039a284fd2 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 47fd10f2fc45d280308b77ed4eda16f3c9c88248 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.
Accordingly, add bitsLT (and similar) to MVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169850 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1d367e9bccf1f374a92c4337251ea541118fdcc9 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,
from EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169849 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2d916231ff503b995bf3b65a338c9bf0d84ee7c7 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of
EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169848 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 235c75cc2190c40f5785059ec1767e44da5c5401 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::TransformToType to contain MVTs, instead of
EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169847 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 78a70f3c60e77b33f9af142e6710ca544de54014 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRepRegClassCostFor, getIndexedLoadAction,
getIndexedStoreAction, and addRegisterClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169846 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| bade0345d190427a08b2b947bc94f4d8ca5d7717 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| bb2543bb0e38495cd655be3eadcb9dd008ac56d2 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getTypeToPromoteTo to take and return MVTs,
instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169844 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 204301f0459c1deb6c535723760c848ba2fcd42b |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169843 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| aff674331ebb54e74baa88532ee587d741a430a2 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getCondCodeAction to take an MVT, instead of
EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169842 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3166283ac169e86e9718bee69850b94c1bc27727 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169841 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ffa03b7981e322d6c9ba8b9cc18cae282ce3b587 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getLoadExtAction to take an MVT, instead of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169840 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 968947766b17bc1a6f27e556f9f340de2504e92d |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169839 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| aa7744d75fc1769ccc12c65c07bb5b82afa58330 |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.
Accordingly, change RegDefIter to contain MVTs instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169838 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8163ca76f0b0d336c5436364ffb3b85be1162e7a |
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.
This is the first, in a series of patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169837 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a98259eefad10455309ad5c7dc7bb1511a077ee2 |
11-Dec-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
llvm/Target/TargetMachine.h: Remove two dependent headers.
-#include "llvm/Target/TargetTransformImpl.h"
-#include "llvm/TargetTransformInfo.h"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169818 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 376642ed620ecae05b68c7bc81f79aeb2065abe0 |
11-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
if it's not possible to materialize an integer immediate with a single
instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
Also increase the threshold to something reasonable (8 for memset, 4 pairs
for memcpy).
This significantly improves Dhrystone, up to 50% on ARM iOS devices.
rdar://12760078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9171fb9cfb25b2e2db64131c15b497de459f69fc |
10-Dec-2012 |
Eric Christopher <echristo@gmail.com> |
Fix a coding style nit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169776 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 880166684e5af0f5b4bfe26870b9f7813e537354 |
09-Dec-2012 |
Paul Redmond <paul.redmond@intel.com> |
LoopVectorize: support vectorizing intrinsic calls
- added function to VectorTargetTransformInfo to query cost of intrinsics
- vectorize trivially vectorizable intrinsic calls such as sin, cos, log, etc.
Reviewed by: Nadav
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169711 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| 5518a1355b8b09bf92419b65ea4e4854734b0ebc |
09-Dec-2012 |
Shuxin Yang <shuxin.llvm@gmail.com> |
- Re-enable population count loop idiom recognization
- fix a bug which cause sigfault.
- add two testing cases which was causing crash
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169687 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| 7065a2bcec3b775da12cf8fbcd6fa972d5f2afeb |
08-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Revert the patches adding a popcount loop idiom recognition pass.
There are still bugs in this pass, as well as other issues that are
being worked on, but the bugs are crashers that occur pretty easily in
the wild. Test cases have been sent to the original commit's review
thread.
This reverts the commits:
r169671: Fix a logic error.
r169604: Move the popcnt tests to an X86 subdirectory.
r168931: Initial commit adding the pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169683 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| 2766a47310b05228e9bbc536d9f3a593fc31cd12 |
06-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Replace r169459 with something safer. Rather than having computeMaskedBits to
understand target implementation of any_extend / extload, just generate
zero_extend in place of any_extend for liveouts when the target knows the
zero_extend will be implicit (e.g. ARM ldrb / ldrh) or folded (e.g. x86 movz).
rdar://12771555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169536 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8a7186dbc2df4879f511b2ae6f2bce25ad37d965 |
06-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Let targets provide hooks that compute known zero and ones for any_extend
and extload's. If they are implemented as zero-extend, or implicitly
zero-extend, then this can enable more demanded bits optimizations. e.g.
define void @foo(i16* %ptr, i32 %a) nounwind {
entry:
%tmp1 = icmp ult i32 %a, 100
br i1 %tmp1, label %bb1, label %bb2
bb1:
%tmp2 = load i16* %ptr, align 2
br label %bb2
bb2:
%tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ]
%cmp = icmp ult i16 %tmp3, 24
br i1 %cmp, label %bb3, label %exit
bb3:
call void @bar() nounwind
br label %exit
exit:
ret void
}
This compiles to the followings before:
push {lr}
mov r2, #0
cmp r1, #99
bhi LBB0_2
@ BB#1: @ %bb1
ldrh r2, [r0]
LBB0_2: @ %bb2
uxth r0, r2
cmp r0, #23
bhi LBB0_4
@ BB#3: @ %bb3
bl _bar
LBB0_4: @ %exit
pop {lr}
bx lr
The uxth is not needed since ldrh implicitly zero-extend the high bits. With
this change it's eliminated.
rdar://12771555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169459 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a59ed5b156156224e97b4dbc32cfbe2101ce6e3c |
05-Dec-2012 |
Andrew Trick <atrick@apple.com> |
Remove two dead functions resulting from a bad rebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169401 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| eca1fcf3d2d8246c45648fea59bd21a4091f9115 |
05-Dec-2012 |
Andrew Trick <atrick@apple.com> |
RegisterPressure API. Add support for physical register units.
At build-time register pressure was always computed in terms of
register units. But the compile-time API was expressed in terms of
register classes because it was intended for virtual registers (and
physical register units weren't yet used anywhere in codegen).
Now that the codegen uses physreg units consistently, prepare for
tracking register pressure also in terms of live units, not live
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169360 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 83dbce2fc817fcb094a8958ca713fd3ba13758c5 |
05-Dec-2012 |
Andrew Trick <atrick@apple.com> |
Comment formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169358 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 69261a644298bff1497d46c8cd38d688670f307b |
04-Dec-2012 |
Manman Ren <mren@apple.com> |
Stack Alignment: when creating stack objects in MachineFrameInfo, make sure
the alignment is clamped to TargetFrameLowering.getStackAlignment if the target
does not support stack realignment or the option "realign-stack" is off.
This will cause miscompile if the address is treated as aligned and add is
replaced with or in DAGCombine.
Added a bool StackRealignable to TargetFrameLowering to check whether stack
realignment is implemented for the target. Also added a bool RealignOption
to MachineFrameInfo to check whether the option "realign-stack" is on.
rdar://12713765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169197 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameLowering.h
|
| f71415646053e66f8a5b63a74ac06287eeab53d5 |
04-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.
These functions have been replaced by TRI::getRegAllocationHints() which
provides the same capabilities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169192 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 7eafc3e7be067709c6fcdae7b7fc4994c7ec2377 |
03-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a new hook for providing register allocator hints more flexibly.
The TargetRegisterInfo::getRegAllocationHints() function is going to
replace the existing mechanisms for providing target-dependent hints to
the register allocator: ResolveRegAllocHint() and
getRawAllocationOrder().
The new hook is more flexible because it allows the target to provide
multiple preferred candidate registers for each virtual register, and it
is easier to use because targets are not required to return a reference
to a constant array like getRawAllocationOrder().
An optional VirtRegMap argument can be used to provide target-dependent
hints that depend on the provisional assignments of other virtual
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169154 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 255f89faee13dc491cb64fbeae3c763e7e2ea4e6 |
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort the #include lines for the include/... tree with the script.
AKA: Recompile *ALL* the source code!
This one went much better. No manual edits here. I spot-checked for
silliness and grep-checked for really broken edits and everything seemed
good. It all still compiles. Yell if you see something that looks goofy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169133 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameLowering.h
argetInstrInfo.h
argetJITInfo.h
argetLibraryInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetMachine.h
argetRegisterInfo.h
argetTransformImpl.h
|
| 33634833aa651cab5ea92b87822c038fb6e71778 |
29-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168937 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| a04d6c948cd6f273f6146fdb95a76e3bc587b9d4 |
29-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
Fix 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168936 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 84fca61ca5fba5c33a799d9133750b6832ddef7e |
29-Nov-2012 |
Shuxin Yang <shuxin.llvm@gmail.com> |
rdar://12100355 (part 1)
This revision attempts to recognize following population-count pattern:
while(a) { c++; ... ; a &= a - 1; ... },
where <c> and <a>could be used multiple times in the loop body.
TODO: On X8664 and ARM, __buildin_ctpop() are not expanded to a efficent
instruction sequence, which need to be improved in the following commits.
Reviewed by Nadav, really appreciate!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168931 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| 3d200255d5b93344c1ab0a5ba4b47a52cfa5893e |
29-Nov-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Allow targets to prefer TypeSplitVector over TypePromoteInteger when computing the legalization method for vectors
For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168882 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e26e8a64ab37e98c69801ac2028b187773bc1d1f |
29-Nov-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MCPhysReg typedef to replace naked uint16_t.
Use this type for arrays of physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168850 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| a9fa4fd9736f7d1066223f32fa54efbe86c0fceb |
28-Nov-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove all references to TargetInstrInfoImpl.
This class has been merged into its super-class TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| fa2d98632c77e5d9c305e97e5fa25d06f579127b |
28-Nov-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move the guts of TargetInstrInfoImpl into the TargetInstrInfo class.
The *Impl class no longer serves a purpose now that the super-class
implementation is in CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168759 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| af87dae12cab8d2e5cab033a5ab60af98e1837fe |
27-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Make PrintReg constructor explicit to prevent weird implicit conversions from accidentally being triggered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168686 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 6098c6b56be5a8e3c7ac5273110589f251b03573 |
22-Nov-2012 |
Meador Inge <meadori@codesourcery.com> |
Add more functions to the target library information.
I discovered a few more missing functions while migrating optimizations
from the simplify-libcalls pass to the instcombine (I already added some
in r167659).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168501 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 1358841e91695bd0e498c02d064c480dc53c566a |
16-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Work around a layering violation from Target to CodeGen.
Technically this is still a layering violation but it's header-only which makes
it less harmful. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168173 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 25efd6d556718295a63d37f5294985746af354f6 |
14-Nov-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use TARGET2 relocation for TType references on ARM.
Do some cleanup of the code while here.
Inspired by patch by Logan Chien!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| ad1cc1d1bfc0accd3f1af5c02ac367ff46a4bfdf |
13-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: Allow subtargets to enable misched and dependent options.
This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want to:
- Disable SelectionDAG scheduling (use the source order scheduler)
- Enable more aggressive coalescing (until we decide to always run the coalescer this way)
- Enable MachineScheduler pass itself.
Disabling PostRA sched may follow for some subtargets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167826 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| a7d2d564d918a9cb9105d3b2b4176b45af36a20e |
12-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: rename interfaceto avoid gcc warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167753 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 6996fd0b543cf8bd4a0d4e09e80a168f0ae052c5 |
12-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: Target-independent support for MacroFusion.
Uses the infrastructure from r167742 to support clustering instructure
that the target processor can "fuse". e.g. cmp+jmp.
Next step: target hook implementations with test cases, and enable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167744 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 9b5caaa9c452f262a52dd5ac7ebbc722da5a63de |
12-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: Target-independent support for load/store clustering.
This infrastructure is generally useful for any target that wants to
strongly prefer two instructions to be adjacent after scheduling.
A following checkin will add target-specific hooks with unit
tests. Then this feature will be enabled by default with misched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 939f5002027e3ccb710ac1c3050dc25471251565 |
10-Nov-2012 |
Meador Inge <meadori@codesourcery.com> |
Add more functions to the target library information.
In the process of migrating optimizations from the simplify-libcalls pass
to the instcombine pass I noticed that a few functions are missing from
the target library information. These functions need to be available for
querying in the instcombine library call simplifiers. More functions will
probably be added in the future as more simplifiers are migrated to
instcombine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167659 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| b3235b128f383559a7a9b9119896e406b347879c |
09-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
Revert r167620; this can be implemented using an existing CL option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167622 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| d054eda44114df411a2749e7b6b85d27509a0af1 |
09-Nov-2012 |
Chad Rosier <mcrosier@apple.com> |
Add support for -mstrict-align compiler option for ARM targets.
rdar://12340498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167620 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 887c1fe7010d6f487ce246df6e2fc18eeb4eaa05 |
06-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
Refactor the getTypeLegalizationCost interface. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167422 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| e623702c22e7cee4e02332b245a417a88ae6ffff |
05-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
Implement the cost of abnormal x86 instruction lowering as a table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167395 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| 87a1af4380da3d69d7d97d6ccda6843b565f7e34 |
05-Nov-2012 |
Eli Bendersky <eliben@google.com> |
PR14256: SelectionDAGLowering was renamed to SelectionDAGBuilder a long time ago. Fix references to it in documentation and comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167378 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b4b04c3fa0a5da15424de7818e9f72811495c65b |
03-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
X86 CostModel: Add support for a some of the common arithmetic instructions for SSE4, AVX and AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167347 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| 0a1544d2fd63d8101dc7d50974e65c95a0f6f98d |
02-Nov-2012 |
Manman Ren <mren@apple.com> |
OutputArg: added an index of the original argument to match the change to
InputArg in r165616.
This will enable us to get the actual type for both InputArg and OutputArg.
rdar://9932559
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167265 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.h
|
| ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cf |
01-Nov-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Generate a table-driven version of TRI::composeSubRegIndices().
Explicitly allow composition of null sub-register indices, and handle
that common case in an inlinable stub.
Use a compressed table implementation instead of the previous nested
switches which generated pretty bad code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167190 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 04d7d13d301df66f6c232e41611145c062183bf3 |
30-Oct-2012 |
Hans Wennborg <hans@hanshq.net> |
Use TargetTransformInfo to control switch-to-lookup table transformation
When the switch-to-lookup tables transform landed in SimplifyCFG, it
was pointed out that this could be inappropriate for some targets.
Since there was no way at the time for the pass to know anything about
the target, an awkward reverse-transform was added in CodeGenPrepare
that turned lookup tables back into switches for some targets.
This patch uses the new TargetTransformInfo to determine if a
switch should be transformed, and removes
CodeGenPrepare::ConvertLoadToSwitch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167011 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| 0d91c0b519e0053931bf9502ebeaf44d397812f0 |
28-Oct-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove TargetELFWriterInfo.
All the credit goes to Jan Voung for noticing it was dead!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166902 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
argetMachine.h
|
| f065a8467785015336432e3e6e584798d8b48d8e |
27-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
1. Fix a bug in getTypeConversion. When a *simple* type is split, we need to return the type of the split result.
2. Change the maximum vectorization width from 4 to 8.
3. A test for both.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166864 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a5a3a61c5fdcee972791d4e08441ba6edf131b88 |
27-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Refactor the VectorTargetTransformInfo interface.
Add getCostXXX calls for different families of opcodes, such as casts, arithmetic, cmp, etc.
Port the LoopVectorizer to the new API.
The LoopVectorizer now finds instructions which will remain uniform after vectorization. It uses this information when calculating the cost of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166836 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetTransformImpl.h
|
| f4a5a613faa1a0eca6b884a6dfe83e8b1eb957b2 |
26-Oct-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the canCombineSubRegIndices() target hook.
The new coalescer can already do all of this, so there is no need to
duplicate the efforts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166813 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 102a7c088c16b8bbed7cf56da9994fa52a9028c5 |
26-Oct-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add VectorTargetTransform::getNumberOfParts.
As discussed on IRC, add VectorTargetTransform::getNumberOfParts
to provide a stable interface to the vector legalization splitting factor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166751 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| becdf4d7cd0d5a3079339b6e177066b143d2f84c |
25-Oct-2012 |
Sebastian Pop <spop@codeaurora.org> |
add TableGen support to create relationship maps between instructions
Relationship maps are represented as InstrMapping records which are parsed by
TableGen and the information is used to construct mapping tables to represent
appropriate relations between instructions. These tables are emitted into
XXXGenInstrInfo.inc file along with the functions to query them.
Patch by Jyotsna Verma <jverma@codeaurora.org>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166685 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 2652c50f74bc4a874c6a2e4b34ff2d52d479183f |
25-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Implement a basic cost model for vector and scalar instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166642 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetTransformImpl.h
|
| 4332bdcb5f03787b7805ba70434138d6a50cc103 |
24-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Make LegalizeKind public so that we can use it outside of TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166623 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 270483466124fe1e19d5439e958fef63cebd43cd |
24-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Implement a basic VectorTargetTransformInfo interface to be used by the loop and bb vectorizers for modeling the cost of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166593 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| cbd9a19b5d6ff93efa82c467508ede78b8af3bac |
19-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166248 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetTransformImpl.h
|
| 3b9a911efcf280950f878a050728450423875639 |
18-Oct-2012 |
Bob Wilson <bob.wilson@apple.com> |
Temporarily revert the TargetTransform changes.
The TargetTransform changes are breaking LTO bootstraps of clang. I am
working with Nadav to figure out the problem, but I am reverting it for now
to get our buildbots working.
This reverts svn commits: 165665 165669 165670 165786 165787 165997
and I have also reverted clang svn 165741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166168 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetTransformImpl.h
|
| b52ba9f8a896b6717d6395ad59f6550e1fa475b0 |
16-Oct-2012 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Issue:
Stack is formed improperly for long structures passed as byval arguments for
EABI mode.
If we took AAPCS reference, we can found the next statements:
A: "If the argument requires double-word alignment (8-byte), the NCRN (Next
Core Register Number) is rounded up to the next even register number." (5.5
Parameter Passing, Stage C, C.3).
B: "The alignment of an aggregate shall be the alignment of its most-aligned
component." (4.3 Composite Types, 4.3.1 Aggregates).
So if we have structure with doubles (9 double fields) and 3 Core unused
registers (r1, r2, r3): caller should use r2 and r3 registers only.
Currently r1,r2,r3 set is used, but it is invalid.
Callee VA routine should also use r2 and r3 regs only. All is ok here. This
behaviour is guessed by rounding up SP address with ADD+BFC operations.
Fix:
Main fix is in ARMTargetLowering::HandleByVal. If we detected AAPCS mode and
8 byte alignment, we waste odd registers then.
P.S.:
I also improved LDRB_POST_IMM regression test. Since ldrb instruction will
not generated by current regression test after this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166018 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2c39b15073db81d93bb629303915b7d7e5d088dc |
15-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165941 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f117f93f6ecda058f546e01dc4b5d9fe7827cce6 |
12-Oct-2012 |
Nick Lewycky <nicholas@mxc.ca> |
Shuffle the virtual destructor down to the base. This should actually pacify
-Wnon-virtual-dtor for real.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165787 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| 863ff7c9037d06e77cd4d39c637707aa135db40d |
12-Oct-2012 |
Nick Lewycky <nicholas@mxc.ca> |
Give this class full of virtual functions a virtual destructor. Classes love
virtual destructors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165786 91177308-0d34-0410-b5e6-96231b3b80d8
argetTransformImpl.h
|
| fb384d61c78b60787ed65475d8403aee65023962 |
11-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Revert 165732 for further review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165747 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f3840d2c16a4ec4c879a8ded402835746de380f8 |
11-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Add in the first iteration of support for llvm/clang/lldb to allow variable per address space pointer sizes to be optimized correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165726 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e3d0e86919730784faaddcb5d9b0257c39b0804b |
11-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Add a new interface to allow IR-level passes to access codegen-specific information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetTransformImpl.h
|
| 661afe75e81431a66de3ed8e22d5aa91443367b3 |
10-Oct-2012 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Issue description:
SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack
objects and byval parameters. So loading byval parameters from stack may be
inserted *before* it will be stored, since these operations are treated as
independent.
Fix:
Currently ARMTargetLowering::LowerFormalArguments saves byval registers with
FixedStack MachinePointerInfo. To fix the problem we need to store byval
registers with MachinePointerInfo referenced to first the "byval" parameter.
Also commit adds two new fields to the InputArg structure: Function's argument
index and InputArg's part offset in bytes relative to the start position of
Function's argument. E.g.: If function's argument is 128 bit width and it was
splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index,
but different offset values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165616 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.h
|
| 412cd2f81374865dfa708bef6d5b896ca10dece0 |
10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.
Allows the HazardRecognizer to be disabled along with itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 3e2d76c946ba753c2b11af192a52e25b6f9b46ff |
09-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Use the attribute enums to query if a parameter has an attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165550 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7d661468682c333739a6f6ab7dc337463573c354 |
09-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Add in the first step of the multiple pointer support. This adds in support to the data layout for specifying a per address space pointer size.
The next step is to update the optimizers to allow them to optimize the different address spaces with this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165505 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 03753aa7598a0c313846fd49fc7eaf75c2d9f003 |
09-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165475 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| ad6aedc7d980d407da4452ff3ed4592d3df1a3f7 |
09-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Refactor the AddrMode class out of TLI to its own header file.
This class is used by LSR and a number of places in the codegen.
This is the first step in de-coupling LSR from TLI, and creating
a new interface in between them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165455 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 39817f9d393fdc29ec35fc8626d8b372415df414 |
08-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: remove the unused getSpecialAddressLatency hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165418 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| 3574eca1b02600bac4e625297f4ecf745f4c4f32 |
08-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
argetData.h
argetLowering.h
argetMachine.h
argetSelectionDAGInfo.h
|
| f420eeccbe6c004d8e607b94a26f70aa69ed352f |
05-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
Remove extraneous semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165319 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| bf07a512f2fd6bbcd0b217060656e9d12b9da5b0 |
05-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Implement TargetData with the DataLayout class, this will allow LLVM projects to transition to DataLayout without loosing functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165318 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 8d662b59f075da67e663ed142ecdd58e381eee98 |
04-Oct-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch corrects commit 165126 by using an integer bit width instead of
a pointer to a type, in order to remove the uses of getGlobalContext().
Patch by Tyler Nowicki.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165255 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 5d0061e0254b9b9b0720e3d9612dd2c53dadbf68 |
04-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Use attribute query methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165210 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 13745262a8db98d6c4513ff9934db4be75a8b26c |
04-Oct-2012 |
Andrew Trick <atrick@apple.com> |
Added instregex support to TableGen subtarget emitter.
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| 90012586f79895a8104e1e65689041fec52d788d |
01-Oct-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
TargetData: s/uint32_t/unsigned/ per Kuba's request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164935 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 01e872af2548144ab3df9c03f3b7cc69b9d758a8 |
29-Sep-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Shrink TargetAlignElem a bit, we do a lot of searches on them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164897 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 1a37d7e807ad6cc71fe3cffdf6674644c46a60eb |
25-Sep-2012 |
Sebastian Pop <spop@codeaurora.org> |
TargetLowering interface to set/get minimum block entries for jump tables.
Provide interface in TargetLowering to set or get the minimum number of basic
blocks whereby jump tables are generated for switch statements rather than an
if sequence.
getMinimumJumpTableEntries() defaults to 4.
setMinimumJumpTableEntries() allows target configuration.
This patch changes the default for the Hexagon architecture to 5
as it improves performance on some benchmarks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164628 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 92649883119aaa8edd9ccf612eaaff5ccc8fcc77 |
22-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Machine Model (-schedmodel only). Added SchedAliases.
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164451 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| 34301ceca8913f3126339f332d3dc6f2d7ac0d78 |
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TargetSchedModel API. Implement latency lookup, disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164098 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| ee290ba35af88393ba18dd19e6e39d50c7872534 |
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Remove unnecessary header dependence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164094 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| e127dfd0b175b5a336e61fecaad7fc2aec65d95c |
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| e1b53287179b4b9b5c3c549586f688d3fa2ae8ef |
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetSubtargetInfo.h
|
| 89a4058da1055ef5985007dc41dcf69c0a510336 |
18-Sep-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
llvm/Target/TargetSubtargetInfo.h: Fix case in #include, s#llvm/Codegen/#llvm/CodeGen#.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164070 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| 12886db4a7af74f17281695320c40248cb263f55 |
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TargetSchedModel API. Implement latency lookup, disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164065 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 021ba269b241e9394d652293d327813eb7766923 |
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164062 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| db7afac4575168c239ac9c570cb7897808f12e30 |
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| 001d3dc976d7cda8a3dd8c7fd4020b0b96033f4e |
17-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Mark unimplemented copy constructors and copy assignment operators as LLVM_DELETED_FUNCTION.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164016 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetIntrinsicInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetMachine.h
argetSelectionDAGInfo.h
argetSubtargetInfo.h
|
| 0303d92b73fdc7ee753e2d4c12104640070752f9 |
14-Sep-2012 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163932 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtargetInfo.h
|
| d15e6576903b3dc33a5418153aa7078a61ae6f04 |
14-Sep-2012 |
Micah Villmow <villmow@gmail.com> |
Add in comments that explain what the indexing and the size of the arrays is about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163904 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a2ed0e8e8b89f7e8374ed8b915ee9d4aadf3659a |
14-Sep-2012 |
Andrew Trick <atrick@apple.com> |
misched: Generic tablegen classes for the new machine model.
This is mostly documentation for the new machine model. It is designed
to be flexible, easy to incrementally refine for a subtarget, and
provide all the information that MachineScheduler will need.
If all goes well, I will follow up with an example of the new model in
use for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163877 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| 1008f8c789a9f821f6a2034781983b7747e78769 |
14-Sep-2012 |
Andrew Trick <atrick@apple.com> |
comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163876 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 8fa5319504d6990162fe9a3e35880e19282a3f81 |
14-Sep-2012 |
Andrew Trick <atrick@apple.com> |
comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163875 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| af40a5be77dd5a4613695b4adb17848bd8c6dd8d |
13-Sep-2012 |
Micah Villmow <villmow@gmail.com> |
The current implementation does not allow more than 32 types to be properly handled with target lowering. This doubles the size to 64bit types and easily allows extension to more types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163806 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 83c0eefa3b4698edd007a4cb24d550fd42566063 |
12-Sep-2012 |
Owen Anderson <resistor@mac.com> |
Improve tblgen code cleanliness: create an unknown_class, from which the unknown def inherits. Make tblgen check for that class, rather than checking for the def itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163664 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| a6035773d8d29827a124e65c258adbf0dcbb1a5a |
11-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TRI::getSubRegIndexLaneMask().
Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.
The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.
Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 59f45e4610e64b88bcee4cd46816ef64e815ff7e |
11-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.
Apparently, NumSubRegIndices was completely unused before. Adjust it by
one to include the null subreg index, just like getNumRegs() includes
the null register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163628 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 6d3d7656539188b496089a3313ed4d13759adba3 |
06-Sep-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Tablegen: Add OperandWithDefaultOps Operand type
This Operand type takes a default argument, and is initialized to
this value if it does not appear in a patter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163315 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| c05d30601ced172b55be81bb529df6be91d6ae15 |
06-Sep-2012 |
Nadav Rotem <nrotem@apple.com> |
Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetOpcodes.h
|
| 2e2efd960056bbb7e4bbd843c8de55116d52aa7d |
04-Sep-2012 |
Preston Gurd <preston.gurd@intel.com> |
Generic Bypass Slow Div
- CodeGenPrepare pass for identifying div/rem ops
- Backend specifies the type mapping using addBypassSlowDivType
- Enabled only for Intel Atom with O2 32-bit -> 8-bit
- Replace IDIV with instructions which test its value and use DIVB if the value
is positive and less than 256.
- In the case when the quotient and remainder of a divide are used a DIV
and a REM instruction will be present in the IR. In the non-Atom case
they are both lowered to IDIVs and CSE removes the redundant IDIV instruction,
using the quotient and remainder from the first IDIV. However,
due to this optimization CSE is not able to eliminate redundant
IDIV instructions because they are located in different basic blocks.
This is overcome by calculating both the quotient (DIV) and remainder (REM)
in each basic block that is inserted by the optimization and reusing the result
values when a subsequent DIV or REM instruction uses the same operands.
- Test cases check for the presents of the optimization when calculating
either the quotient, remainder, or both.
Patch by Tyler Nowicki!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9f40cb32ac31283f8636d516e7b10f3ad921955c |
02-Sep-2012 |
Nadav Rotem <nrotem@apple.com> |
Not all targets have efficient ISel code generation for select instructions.
For example, the ARM target does not have efficient ISel handling for vector
selects with scalar conditions. This patch adds a TLI hook which allows the
different targets to report which selects are supported well and which selects
should be converted to CF duting codegen prepare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163093 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b4e090dffc4bed40cee22b94560aa8dd3b4af013 |
30-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a bit of documentation to copyPhysReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162879 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8e0d1c03ca7fd86e6879b4e37d0d7f0e982feef6 |
29-Aug-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make MemoryBuiltins aware of TargetLibraryInfo.
This disables malloc-specific optimization when -fno-builtin (or -ffreestanding)
is specified. This has been a problem for a long time but became more severe
with the recent memory builtin improvements.
Since the memory builtin functions are used everywhere, this required passing
TLI in many places. This means that functions that now have an optional TLI
argument, like RecursivelyDeleteTriviallyDeadFunctions, won't remove dead
mallocs anymore if the TLI argument is missing. I've updated most passes to do
the right thing.
Fixes PR13694 and probably others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162841 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 36d29bc72345d882623b001c2692b9246a19688a |
28-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove extra MayLoad/MayStore flags from atomic_load/store.
These extra flags are not required to properly order the atomic
load/store instructions. SelectionDAGBuilder chains atomics as if they
were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on
the memory operands of all atomic operations.
The volatile bit is enough to order atomic loads and stores during and
after SelectionDAG.
This means we set mayLoad on atomic_load, mayStore on atomic_store, and
mayLoad+mayStore on the remaining atomic read-modify-write operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162733 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| c1f10fd5b9a780d1c42dca7143d7a8acd9bd9377 |
23-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Tristate mayLoad, mayStore, and hasSideEffects.
Keep track of the set/unset state of these bits along with their
true/false values, but treat '?' as '0' for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162461 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| f104bf65b9d748618d23caa37b2407fe9c2b174c |
23-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add CodeGenTarget::guessInstructionProperties.
Currently, TableGen just guesses instruction properties when it can't
infer them form patterns.
This adds a guessInstructionProperties flag to the instruction set
definition that will be used to disable guessing. The flag is intended
as a migration aid. It will be removed again when no more targets need
their properties guessed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162460 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| ffd2526fa4e2d78564694b4797b96236c9ba9d85 |
23-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Simplify the computeOperandLatency API.
The logic for recomputing latency based on a ScheduleDAG edge was
shady. This bypasses the problem by requiring the client to provide
operand indices. This ensures consistent use of the machine model's
API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162420 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 6871d1eceba0455707de29708c36ae3c2778c160 |
22-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
Add a few functions to TargetLibraryInfo as part of PR13574.
Patch by Weiming Zhao <weimingz@codeaurora.org>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162329 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 35907e98626b33f6406dc498201fc59ced282c8a |
21-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
Add support for the --param ssp-buffer-size= driver option.
PR9673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162284 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 72e9b6aeb48d9496bac9db8b02c88a618b464588 |
17-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add stub methods for mips assembly matcher.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162124 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| f2c64ef519b38a4328809b27b4a3a8e0c26e9709 |
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MCID::Select flag and TII hooks for optimizing selects.
Select instructions pick one of two virtual registers based on a
condition, like x86 cmov. On targets like ARM that support predication,
selects can sometimes be eliminated by predicating the instruction
defining one of the operands.
Teach PeepholeOptimizer to recognize select instructions, and ask the
target to optimize them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162059 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrInfo.h
|
| d024a20bf78086e2bbe7f03ceecbe26c095d7a31 |
15-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a CoveringSubRegIndices field to SubRegIndex records.
This can be used to tell TableGen to use a specific SubRegIndex instead
of synthesizing one when discovering all sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161982 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 43600e95ec3690b37d458a6d3d56941ad84cddcb |
13-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the TII::scheduleTwoAddrSource() hook.
It never does anything when running 'make check', and it get's in the
way of updating live intervals in 2-addr.
The hook was originally added to help form IT blocks in Thumb2 code
before register allocation, but the pass ordering has changed since
then, and we run if-conversion after register allocation now.
When the MI scheduler is enabled, there will be no less than two
schedulers between 2-addr and Thumb2ITBlockPass, so this hook is
unlikely to help anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161794 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 12864689d199209a3a5046f4570d92a252da7420 |
09-Aug-2012 |
Owen Anderson <resistor@mac.com> |
Allow legalization of target-specific SDNodes, provided that the target itself provide a legalization hook for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161536 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d43b5c97cff06d7840b974ca84fa0639d2567968 |
08-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Added MispredictPenalty to SchedMachineModel.
This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| 3c417554caedde3a333755916701c8380606342a |
08-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Minor cleanup of defaultDefLatency API
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161470 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| cbfce4557751acef4e7970d6e4b9583ced7e0e93 |
07-Aug-2012 |
Bill Wendling <isanbard@gmail.com> |
Revert r161371. Removing the 'const' before Type is a "good thing".
--- Reverse-merging r161371 into '.':
U include/llvm/Target/TargetData.h
U lib/Target/TargetData.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161394 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 121418e55191904b01eb9ec182ef62af5f38e861 |
07-Aug-2012 |
Bill Wendling <isanbard@gmail.com> |
Constify the Type parameter to some methods (which are const anyway).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161371 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 8cc3474f72388836fa4ca7d3622289fb9ee08b41 |
04-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add readcyclecounter lowering on PPC64.
On PPC64, this can be done with a simple TableGen pattern.
To enable this, I've added the (otherwise missing) readcyclecounter
SDNode definition to TargetSelectionDAG.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 982dc84762fc0c2ca35e6947d648a690dd22343c |
03-Aug-2012 |
Bob Wilson <bob.wilson@apple.com> |
Try to reduce the compile time impact of r161232.
The previous change caused fast isel to not attempt handling any calls to
builtin functions. That included things like "printf" and caused some
noticable regressions in compile time. I wanted to avoid having fast isel
keep a separate list of functions that had to be kept in sync with what the
code in SelectionDAGBuilder.cpp was handling. I've resolved that here by
moving the list into TargetLibraryInfo. This is somewhat redundant in
SelectionDAGBuilder but it will ensure that we keep things consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161263 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| d49edb7ab098fa0c82f59efbcf1b4eb2958f8dc3 |
03-Aug-2012 |
Bob Wilson <bob.wilson@apple.com> |
Fall back to selection DAG isel for calls to builtin functions.
Fast isel doesn't currently have support for translating builtin function
calls to target instructions. For embedded environments where the library
functions are not available, this is a matter of correctness and not
just optimization. Most of this patch is just arranging to make the
TargetLibraryInfo available in fast isel. <rdar://problem/12008746>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d1e672e0234b99dbff78baed0e47d033cf963abe |
03-Aug-2012 |
Bob Wilson <bob.wilson@apple.com> |
Add new getLibFunc method to TargetLibraryInfo.
This just provides a way to look up a LibFunc::Func enum value for a
function name. Alphabetize the enums and function names so we can use a
binary search.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161231 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 127eea87d666ccc9fe7025f41148c33af0f8c84b |
02-Aug-2012 |
Manman Ren <mren@apple.com> |
X86 Peephole: fold loads to the source register operand if possible.
Add more comments and use early returns to reduce nesting in isLoadFoldable.
Also disable folding for V_SET0 to avoid introducing a const pool entry and
a const pool load.
rdar://10554090 and rdar://11873276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161207 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 28897ca434892340f2e188a0331db92d5899409b |
02-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterInfo::hasRegUnit().
This trivial helper function tests if a register contains a register
unit. It is similar to regsOverlap(), but with asymmetric arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161180 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2d |
02-Aug-2012 |
Manman Ren <mren@apple.com> |
X86 Peephole: fold loads to the source register operand if possible.
Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.
This patch is a rework of r160919 and was tested on clang self-host on my local
machine.
rdar://10554090 and rdar://11873276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b7e22efa2b2a66b7d55c0297e45c217a465621ff |
30-Jul-2012 |
Eric Christopher <echristo@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160981 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| e8b4a4a9d173d67e35e4b1d32e20140381db6bde |
29-Jul-2012 |
Manman Ren <mren@apple.com> |
Revert r160920 and r160919 due to dragonegg and clang selfhost failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 0eb3edea9cb6819334173a7d288da85943201fe5 |
28-Jul-2012 |
Manman Ren <mren@apple.com> |
X86 Peephole: fold loads to the source register operand if possible.
Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.
rdar://10554090 and rdar://11873276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 2ca6b3c37498eebf1f729f85cee03aa38ea5bc65 |
27-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove support for 'CompositeIndices' and sub-register cycles.
Now that the weird X86 sub_ss and sub_sd sub-register indexes are gone,
there is no longer a need for the CompositeIndices construct in .td
files. Sub-register index composition can be specified on the
SubRegIndex itself using the ComposedOf field.
Also enforce unique names for sub-registers in TableGen. The same
sub-register cannot be available with multiple sub-register indexes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160842 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 51004dff923259c90591621e7151408ad94e0eb8 |
25-Jul-2012 |
Nuno Lopes <nunoplopes@sapo.pt> |
make all Emit*() functions consult the TargetLibraryInfo information before creating a call to a library function.
Update all clients to pass the TLI information around.
Previous draft reviewed by Eli.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160733 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 8d32463a9fa2aba9de552350a5019099edf0b90d |
24-Jul-2012 |
Nuno Lopes <nunoplopes@sapo.pt> |
add a few more functions to TargetLibraryInfo:
fputc, memchr, memcmp, putchar, puts, strchr, strncmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160690 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 0841e63ede092283d824843a068df3f7b0b90dd8 |
24-Jul-2012 |
Nuno Lopes <nunoplopes@sapo.pt> |
TargetLibraryInfo: add strn?cat, strn?cpy, and strn?len
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160678 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| c8e41c591741b3da1077f7000274ad040bef8002 |
23-Jul-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo (the the => the)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0fcaaafd1aa9714a95339d585cdceb4fa7f15f1b |
20-Jul-2012 |
Owen Anderson <resistor@mac.com> |
Make RegisterOperand a subclass of DAGOperand so that RegisterOperands can be passed into multiclasses that take DAGOperands as multiclass parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160540 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 8c51e3995d8b8fd1cd88ef18548be4b8f8e3d6f1 |
19-Jul-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160473 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ac915b48d8ba73a5d734be5c4a0e1d25cea93252 |
17-Jul-2012 |
Jim Grosbach <grosbach@apple.com> |
TableGen: Allow conditional instruction pattern in multiclass.
Define a 'null_frag' SDPatternOperator node, which if referenced in an
instruction Pattern, results in the pattern being collapsed to be as-if
'[]' had been specified instead. This allows supporting a multiclass
definition where some instaniations have ISel patterns associated and
others do not.
For example,
multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> {
def _x : myI<(outs rc:), (ins rc:), []>;
def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>;
}
defm foo : myMulti<GRa, not>;
defm bar : myMulti<GRb>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 2661b411ccc81b1fe19194d3f43b2630cbef3f28 |
07-Jul-2012 |
Andrew Trick <atrick@apple.com> |
I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.
MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.
These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.
This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetItinerary.td
argetSchedule.td
|
| 06495cd7f2a91c4f659eac5e55b1c08b014d0a08 |
07-Jul-2012 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159890 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 33242fd3ed5586091e73254b58dd1825e9d53c60 |
04-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an experimental early if-conversion pass, off by default.
This pass performs if-conversion on SSA form machine code by
speculatively executing both sides of the branch and using a cmov
instruction to select the result. This can help lower the number of
branch mispredictions on architectures like x86 that don't have
predicable instructions.
The current implementation is very aggressive, and causes regressions on
mosts tests. It needs good heuristics that have yet to be implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159694 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 769951f6cc6323821ce1e9f46a37817a541c884f |
03-Jul-2012 |
Evan Cheng <evan.cheng@apple.com> |
Target option DisableJumpTables is a gross hack. Move it to TargetLowering instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159611 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetOptions.h
|
| 30a507a1f5d6a5646dd3481eba6958424415c886 |
02-Jul-2012 |
Bob Wilson <bob.wilson@apple.com> |
Extend TargetPassConfig to allow running only a subset of the normal passes.
This is still a work in progress but I believe it is currently good enough
to fix PR13122 "Need unit test driver for codegen IR passes". For example,
you can run llc with -stop-after=loop-reduce to have it dump out the IR after
running LSR. Serializing machine-level IR is not yet supported but we have
some patches in progress for that.
The plan is to serialize the IR to a YAML file, containing separate sections
for the LLVM IR, machine-level IR, and whatever other info is needed. Chad
suggested that we stash the stop-after pass in the YAML file and use that
instead of the start-after option to figure out where to restart the
compilation. I think that's a great idea, but since it's not implemented yet
I put the -start-after option into this patch for testing purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159570 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 218ee74a011c0d350099c452810da0bd57a15047 |
02-Jul-2012 |
Andrew Trick <atrick@apple.com> |
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetSchedule.td
|
| de7266c611b37ec050efb53b73166081a98cea13 |
29-Jun-2012 |
Manman Ren <mren@apple.com> |
Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle Compare
instructions with two register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159465 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 3e4b3b9043b1ced24e07d8d1174feeee06c6912e |
29-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."
This reverts commit r159406. I noticed a performance regression so I'll back out for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetSchedule.td
|
| 0d9513c74f3e4c019406273cce49e43508dc4dcf |
29-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Make NumMicroOps a variable in the subtarget's instruction itinerary.
The TargetInstrInfo::getNumMicroOps API does not change, but soon it
will be used by MachineScheduler. Now each subtarget can specify the
number of micro-ops per itinerary class. For ARM, this is currently
always dynamic (-1), because it is used for load/store multiple which
depends on the number of register operands.
Zero is now a valid number of micro-ops. This can be used for
nop pseudo-instructions or instructions that the hardware can squash
during dispatch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetSchedule.td
|
| 2c5fbb9bcb5c1355e723be8c588ea0998d3d3720 |
25-Jun-2012 |
Owen Anderson <resistor@mac.com> |
Define DAGOperand, an empty base class for RegisterClass and Operand. This allows one to write multiclasses that are polymorphic over both registers and non-register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159162 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 4dbfdfba6c92b6224bf58364371569f5780844d3 |
23-Jun-2012 |
Jim Grosbach <grosbach@apple.com> |
TableGen: AsmMatcher support for better operand diagnostics.
"Invalid operand" may be a completely correct diagnostic, but it's often
insufficiently specific to really help identify and fix the problem in
assembly source. Allow a target to specify a more-specific diagnostic kind
for each AsmOperandClass derived definition and use that to provide
more detailed diagnostics when an operant of that class resulted in a
match failure.
rdar://8987109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159050 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| d85934b3e5a96040e199e1b098705eb56cde584a |
22-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Use "NoItineraries" for processors with no itineraries.
This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158963 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| e0231413225cf47aaf3238bf21afd0d59025028d |
22-Jun-2012 |
Lang Hames <lhames@gmail.com> |
Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from a
boolean flag to an enum: { Fast, Standard, Strict } (default = Standard).
This option controls the creation by optimizations of fused FP ops that store
intermediate results in higher precision than IEEE allows (E.g. FMAs). The
behavior of this option is intended to match the behaviour specified by a
soon-to-be-introduced frontend flag: '-ffuse-fp-ops'.
Fast mode - allows formation of fused FP ops whenever they're profitable.
Standard mode - allow fusion only for 'blessed' FP ops. At present the only
blessed op is the fmuladd intrinsic. In the future more blessed ops may be
added.
Strict mode - allow fusion only if/when it can be proven that the excess
precision won't effect the result.
Note: This option only controls formation of fused ops by the optimizers. Fused
operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic)
will always be honored, regardless of the value of this option.
Internally TargetOptions::AllowExcessFPPrecision has been replaced by
TargetOptions::AllowFPOpFusion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158956 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| d693cafcfb9e67ba7040cb810e4409a166421482 |
20-Jun-2012 |
Lang Hames <lhames@gmail.com> |
Add DAG-combines for aggressive FMA formation.
This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or
FSUB + FMUL. The combines are performed when:
(a) Either
AllowExcessFPPrecision option (-enable-excess-fp-precision for llc)
OR
UnsafeFPMath option (-enable-unsafe-fp-math)
are set, and
(b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of
the FADD/FSUB, and
(c) The FMUL only has one user (the FADD/FSUB).
If your target has fast FMA instructions you can make use of these combines by
overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for
types supported by your FMA instruction, and adding patterns to match ISD::FMA
to your FMA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| d6b43a317e71246380db55a50b799b062b53cdce |
19-Jun-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the support for using .init_array from ARM to the generic
TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM,
on X86 it is not easy to find out if .init_array should be used or not, so
the decision is made via TargetOptions and defaults to off.
Add a command line option to llc that enables it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158692 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 575e90e955064f60ac66230dce6c27653973c149 |
13-Jun-2012 |
Kay Tiong Khoo <kkhoo@perfwizard.com> |
*typo: Cyles changed to Cycles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158404 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 77592fe39c404f3c48b06fae48b965058b3a5ee8 |
09-Jun-2012 |
Dmitri Gribenko <gribozavr@gmail.com> |
Convert comments to proper Doxygen comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158248 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.h
argetData.h
|
| dddc1cf50b6dfe543f617426ac4eab55fbbdfecd |
09-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Removing strange "using" declarations form TargetInstrInfo.
I can't imagine why these were added. Trial and error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158247 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| eb81df7d95b8923ea99c0d4741a5aabf82d1c5ab |
08-Jun-2012 |
Andrew Trick <atrick@apple.com> |
TargetInstrInfo hooks implemented in codegen should be declared pure virtual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158233 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 397f4e3583b36b23047fec06b1648f0771cd6fe3 |
07-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158164 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 2afde7782dfa56b2e46f79598bdb5f1e09471941 |
07-Jun-2012 |
Manman Ren <mren@apple.com> |
Revert r157755.
The commit is intended to fix rdar://11540023.
It is implemented as part of peephole optimization. We can actually implement
this in the SelectionDAG lowering phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b7e0289fb320c8440ba5eed121a8b932dbd806a2 |
05-Jun-2012 |
Andrew Trick <atrick@apple.com> |
misched: API for minimum vs. expected latency.
Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 5afba6f00c3e2eef83aebbcff5fcfca2fa3c978e |
05-Jun-2012 |
Lang Hames <lhames@gmail.com> |
Add a new intrinsic: llvm.fmuladd. This intrinsic represents a multiply-add
expression (a * b + c) that can be implemented as a fused multiply-add (fma)
if the target determines that this will be more efficient. This intrinsic
will be used to implement FP_CONTRACT support and an aggressive FMA formation
mode.
If your target has a fast FMA instruction you should override the
isFMAFasterThanMulAndAdd method in TargetLowering to return true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158014 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| fc992996f751e0941951b6d08d8f1e80ebec1385 |
05-Jun-2012 |
Andrew Trick <atrick@apple.com> |
misched: Added MultiIssueItineraries.
This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| d05b46115f5049b7b094d4049aa88f09f7d6b65a |
05-Jun-2012 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157976 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| fcb2c3cf5e8ee421fd3a5639cc4a33036e9a614e |
04-Jun-2012 |
Nadav Rotem <nadav.rotem@intel.com> |
Remove the "-promote-elements" flag. This flag is now enabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157925 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 91c5346d91973a1d3458a20f8c6b0e899b732e38 |
31-May-2012 |
Manman Ren <mren@apple.com> |
X86: replace SUB with CMP if possible
This patch will optimize the following
movq %rdi, %rax
subq %rsi, %rax
cmovsq %rsi, %rdi
movq %rdi, %rax
to
cmpq %rsi, %rdi
cmovsq %rsi, %rdi
movq %rdi, %rax
Perform this optimization if the actual result of SUB is not used.
rdar: 11540023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157755 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 5ddc04caf25a649963c99be02646c3a9fc88d514 |
31-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a PrintRegUnit helper similar to PrintReg.
Reg-units are named after their root registers, and most units have a
single root, so they simply print as 'AL', 'XMM0', etc. The rare dual
root reg-units print as FPSCR~FPSCR_NZCV, FP0~ST7, ...
The printing piggybacks on the existing register name tables, so no
extra const data space is required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157754 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3 |
30-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add MCRegisterInfo::RegListIterator.
Also add subclasses MCSubRegIterator, MCSuperRegIterator, and
MCRegAliasIterator.
These iterators provide an abstract interface to the MCRegisterInfo
register lists so the internal representation can be changed without
changing all clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157695 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 96feada378dc9769644333ca9670b265fd15a2ef |
30-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use MCRegUnitIterator to compute regsOverlap().
The register unit lists are typically much shorter than the register
overlap lists, and the backing table for register units has better cache
locality because it is smaller.
This makes llc about 0.5% faster. The regsOverlap() function isn't that hot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157651 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| d2ea0e10cbd158c93fb870cdd03001b9cd1156b8 |
25-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2db0e9ebb600a2e6b8f651f66a1ef50e0d3c3c6b |
25-May-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Simplify code for calling a function where CanLowerReturn fails, fixing a small bug in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157446 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0a39d4e4c86540d7c89f6dbe511b70466e132715 |
25-May-2012 |
Andrew Trick <atrick@apple.com> |
misched: Added ScoreboardHazardRecognizer.
The Hazard checker implements in-order contraints, or interlocked
resources. Ready instructions with hazards do not enter the available
queue and are not visible to other heuristics.
The major code change is the addition of SchedBoundary to encapsulate
the state at the top or bottom of the schedule, including both a
pending and available queue.
The scheduler now counts cycles in sync with the hazard checker. These
are minimum cycle counts based on known hazards.
Targets with no itinerary (x86_64) currently remain at cycle 0. To fix
this, we need to provide some maximum issue width for all targets. We
also need to add the concept of expected latency vs. minimum latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157427 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 6b31d4ea3610b04d71e1eb38d8fc625eae7b759a |
24-May-2012 |
Owen Anderson <resistor@mac.com> |
Teach tblgen's set theory "sequence" operator to support an optional stride operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157416 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 68ef0382e4efe4a4c06e47a53a275b873ba0cff4 |
17-May-2012 |
Evandro Menezes <emenezes@codeaurora.org> |
[Hexagon] Clean up Hexagon ELF definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156996 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| 0ee07e013095e8c298fbcc5203e0bc9f334e15e1 |
15-May-2012 |
Jim Grosbach <grosbach@apple.com> |
TableGen'erate mapping physical registers to encoding values.
Many targets always use the same bitwise encoding value for physical
registers in all (or most) instructions. Add this mapping to the
.td files and TableGen'erate the information and expose an accessor
in MCRegisterInfo.
patch by Tom Stellard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156829 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| a6063c6e29746d9425bdf46d680e28a48dcf58f9 |
14-May-2012 |
Dan Gohman <gohman@apple.com> |
Rename @llvm.debugger to @llvm.debugtrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156774 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| d4347e1af9141ec9f8e3e527367bfd16c0cc4ffb |
11-May-2012 |
Dan Gohman <gohman@apple.com> |
Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),
but it generates int3 on x86 instead of ud2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 |
08-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).
So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetRegisterInfo.h
|
| fd87839a4888840ab5718fd116ab169ac04126af |
07-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TRI::getCommonSuperRegClass().
This function is a generalization of getMatchingSuperRegClass() to the
symmetric case where both sides are using a sub-register index. It will
find a super-register class and sub-register indexes that make this
diagram commute:
PreA
SuperRC ----------> RCA
| |
| |
PreB | | SubA
| |
| |
V V
RCB ----------> SubRC
SubB
This can be used to coalesce copies like:
%vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156317 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| aaf723dd2bccc052d2dd28e3cc4db76f2a3e2fb0 |
05-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add a new target hook "predictableSelectIsExpensive".
This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.
Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.
I'm not entirely happy with the name of this flag, suggestions welcome ;)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 338607ae0ddab00e197222e769748e2e0c0b4e18 |
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the SubRegClasses field from RegisterClass descriptions.
This information in now computed by TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 7855ec62c3b6b5b7e6d3fada589511abd964fdb3 |
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove TargetRegisterClass::SuperRegClasses.
This manually enumerated list of super-register classes has been
superceeded by the automatically computed super-register class masks
available through SuperRegClassIterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| e3ee49fb2728dcb9702b5be0c3c80f472ffccefc |
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use SuperRegClassIterator for findRepresentativeClass().
The masks returned by SuperRegClassIterator are computed automatically
by TableGen. This is better than depending on the manually specified
SuperRegClasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156147 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 89e38f87211f6cf34c8b2e88a06c275a70c05421 |
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a SuperRegClassIterator class.
This iterator class provides a more abstract interface to the (Idx,
Mask) lists of super-registers for a register class. The layout of the
tables shouldn't be exposed to clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156144 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| dd63a063e2df0d0bc52b50732e3462fd58a636c0 |
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use a shared implementation of getMatchingSuperRegClass().
TargetRegisterClass now gives access to the necessary tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 1a2a19dd3ce2b163837b5f0a1ea474c72527cad6 |
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterClass::getSuperRegIndices().
This is a pointer into one of the tables used by
getMatchingSuperRegClass(). It makes it possible to use a shared
implementation of that function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156121 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 1d61f283fad2e49d3e50a3585aac4cc9183a0d28 |
03-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix the type of SubClassMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156084 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 309076ff76c61e03ddd3a0fbbfded3042d2da2e5 |
03-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't override subreg functions in targets without subregisters.
Some targets have no sub-registers at all. Use the TargetRegisterInfo
versions of composeSubRegIndices(), getSubClassWithSubReg(), and
getMatchingSuperRegClass() for those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156075 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| f12f6dff9784805e8f89309787231c1ec53a8c6e |
03-May-2012 |
Andrew Trick <atrick@apple.com> |
Added TargetRegisterInfo::getAllocatableClass.
The ensures that virtual registers always belong to an allocatable class.
If your target attempts to create a vreg for an operand that has no
allocatable register subclass, you will crash quickly.
This ensures that targets define register classes as intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 14ce6fac242228dacc5c08040e544141a96880e5 |
25-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: improved assembler diagnostics for missing CPU features.
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.
rdar://11257547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 6a8c7bf8e72338e55f0f9583e1828f62da165d4a |
23-Apr-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.
This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.
This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.
The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().
It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.
It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.
Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.
Patch by Andy Zhang!
Thanks to Jakob and Anton for their reviews.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| d06c2decc2f5c296dfe914509ff841a639eb2a61 |
20-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Added TargetRegisterInfo::getRegPressureSetName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155235 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 2efd8acb3cc6ceb0ca32610389a53909896f99e5 |
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Add documentation comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155203 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| c1922c72adedadb414a3d19c3f150bfe1bc755a5 |
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
TableGen support for auto-generating assembly two-operand aliases.
Assembly matchers for instructions with a two-operand form. ARM is full
of these, for example:
add {Rd}, Rn, Rm // Rd is optional and is the same as Rn if omitted.
The property TwoOperandAliasConstraint on the instruction definition controls
when, and if, an alias will be formed. No explicit InstAlias definitions
are required.
rdar://11255754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155172 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| d5bda5ec663f43710fe462f44b77ddbcf8fe9d9e |
18-Apr-2012 |
Joe Groff <arcata@gmail.com> |
fix pr12559: mark unavailable win32 math libcalls
also fix SimplifyLibCalls to use TLI rather than compile-time conditionals to enable optimizations on floor, ceil, round, rint, and nearbyint
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154960 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 33d9e89e5f8d7656e50353b014d5bb1b52f15e13 |
17-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Typo in an unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154895 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| ec14cd7ddc66d47cd7927f18d8c11844c400367e |
11-Apr-2012 |
Andrew Trick <atrick@apple.com> |
TableGen's regpressure: emit per-registerclass weight limits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154518 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 21293ac192d84f51c0f75c37ba50d90becc3e008 |
11-Apr-2012 |
Duncan Sands <baldrick@free.fr> |
Comment typo fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154488 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2 |
10-Apr-2012 |
Andrew Trick <atrick@apple.com> |
Added a TargetRegisterInfo interface for accessing register pressure sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154375 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| bf010eb9110009d745382bf15131fbe556562ffe |
10-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a long standing tail call optimization bug. When a libcall is emitted
legalizer always use the DAG entry node. This is wrong when the libcall is
emitted as a tail call since it effectively folds the return node. If
the return node's input chain is not the entry (i.e. call, load, or store)
use that as the tail call input chain.
PR12419
rdar://9770785
rdar://11195178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154370 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 253933ee9ef2c413ecd782efeacc5d7b9bcda09a |
08-Apr-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Teach LLVM about a PIE option which, when enabled on top of PIC, makes
optimizations which are valid for position independent code being linked
into a single executable, but not for such code being linked into
a shared library.
I discussed the design of this with Eric Christopher, and the decision
was to support an optional bit rather than a completely separate
relocation model. Fundamentally, this is still PIC relocation, its just
that certain optimizations are only valid under a PIC relocation model
when the resulting code won't be in a shared library. The simplest path
to here is to expose a single bit option in the TargetOptions. If folks
have different/better designs, I'm all ears. =]
I've included the first optimization based upon this: changing TLS
models to the *Exec models when PIE is enabled. This is the LLVM
component of PR12380 and is all of the hard work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154294 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 34797136cb9fa9f450c0e1c47983482083979dd4 |
08-Apr-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Move the TLSModel information into the TargetMachine rather than hiding
in TargetLowering. There was already a FIXME about this location being
odd. The interface is simplified as a consequence. This will also make
it easier to change TLS models when compiling with PIE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154292 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetMachine.h
|
| 26c8dcc692fb2addd475446cfff24d6a4e958bca |
04-Apr-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 29f60f359b59032108cdabcde91217b6784c4e13 |
03-Apr-2012 |
Owen Anderson <resistor@mac.com> |
Add predicates for checking whether targets have free FNEG and FABS operations, and prevent the DAGCombiner from turning them into bitwise operations if they do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153901 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6c01492ac40bed9529a2f7c8d40da34b8f04365e |
25-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune some includes and forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153414 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
argetELFWriterInfo.h
argetFrameLowering.h
argetJITInfo.h
argetLowering.h
argetLoweringObjectFile.h
argetMachine.h
argetSubtargetInfo.h
|
| f210b68b41704cb602feffa4ebb334220abda407 |
13-Mar-2012 |
Pete Cooper <peter_cooper@apple.com> |
Target override to allow CodeGenPrepare to sink address operands to intrinsics in the same way it current does for loads and stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152666 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 33ca87affb81b60c4d50214eb7458bd26d397d53 |
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
MCRegisterInfo-ize getMatchingSuperReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152044 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 9ebfbf8b9fd5f982e0db9293808bd32168615ba9 |
05-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| e4fd907e72a599eddfa7a81eac4366b5b82523e3 |
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| b6632ba380cf624e60fe16b03d6e21b05dd07724 |
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 015f228861ef9b337366f92f637d4e8d624bb006 |
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers in callee saved register tables to reduce size of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 4b1212b4bfac98c688d484bf22ae158875f06ad5 |
01-Mar-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151821 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| b3acdcc00c9dfb01663780e858e586cc5f04423f |
01-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.
Allows us to de-virtualize the function and provides access to it in
the instruction printer, which is useful for handling composite
physical registers (e.g., ARM register lists).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151815 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| ccc8d3ba06408feff0ca6e58973c20d15010e3fc |
01-Mar-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make TargetRegisterClasses non-virtual by making the only virtual function a function pointer.
This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static
initializer and a ton of cruft from the generated code.
Shrinks ARMBaseRegisterInfo.o by ~100k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151806 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 |
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 20bd5296cec8d8d597ab9db2aca7346a88e580c8 |
28-Feb-2012 |
Daniel Dunbar <daniel@zuster.org> |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ec52aaa12f57896fc806e849fa21a61603050ac4 |
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 44d23825d61d530b8d562329ec8fc2d4f843bb8d |
22-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetSubtargetInfo.h
|
| 873fd5f75332023ee8d8b4f9a85351f25e7f1e90 |
20-Feb-2012 |
James Molloy <james.molloy@arm.com> |
Improve generated code for extending loads and some trunc stores on ARM.
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150956 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 057d521e3d91a894f6c38fcbc21ee5950fbdf7b1 |
15-Feb-2012 |
Bill Wendling <isanbard@gmail.com> |
Modify the code that emits the module flags to use the new module flags accessor
method. This allows the target lowering code to not have to deal with MDNodes.
Also, avoid leaking memory like a sieve by not creating a global variable for
the image info section, but just emitting the code directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150624 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| b464d3ff72790260e8c2068afe856fd7299a6834 |
14-Feb-2012 |
Bill Wendling <isanbard@gmail.com> |
Add code to the target lowering object file module to handle module flags.
The MachO back-end needs to emit the garbage collection flags specified in the
module flags. This is a WIP, so the front-end hasn't been modified to emit these
flags just yet. Documentation and front-end switching to occur soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150507 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 0796134bde31f6d58d077f556fd08ca3734a9e6e |
14-Feb-2012 |
Lang Hames <lhames@gmail.com> |
Rename getExceptionAddressRegister() to getExceptionPointerRegister() for consistency with setExceptionPointerRegister(...).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150460 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6a7df9aae620801d97da72d718e9aff76eebac9b |
12-Feb-2012 |
Nick Lewycky <nicholas@mxc.ca> |
Remove redundant getAnalysis<> calls in GlobalOpt. Add a few Itanium ABI calls
to TargetLibraryInfo and use one of them in GlobalOpt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150323 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 8dd26253f54247e77e5accfdd70e7b4bf27b39c2 |
10-Feb-2012 |
Andrew Trick <atrick@apple.com> |
RegAlloc superpass: includes phi elimination, coalescing, and scheduling.
Creates a configurable regalloc pipeline.
Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.
When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.
CodeGen transformation passes are never "required" as an analysis
ProcessImplicitDefs does not require LiveVariables.
We have a plan to massively simplify some of the early passes within the regalloc superpass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 2c6ae095b8a944c8355377498b9ad11bb94af2d5 |
09-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Store just the SimpleValueType in the generated VT tables for each register class, eliminating static ctors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150173 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 50bee42b54cd9aec5f49566307df2b0cf23afcf6 |
05-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149849 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetJITInfo.h
argetLowering.h
argetRegisterInfo.h
|
| 061efcfb3e79899493d857f49e50d09f29037e0a |
04-Feb-2012 |
Andrew Trick <atrick@apple.com> |
TargetPassConfig: confine the MC configuration to TargetMachine.
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.
Sorry for the target header churn. Attempting to stabilize them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 843ee2e6a46b2b2d74a84c2eea68dec35cb359cc |
03-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Added TargetPassConfig. The first little step toward configuring codegen passes.
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 478a8a02bc0f2e739ed8f4240152e99837e480b9 |
03-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Require non-NULL register masks.
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| b5af2d943ed568f2f4cac545b6dfb150ae9d73aa |
02-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Specify SubRegIndex components on the index itself.
It is simpler to define a composite index directly:
def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;
Than specifying the composite indices on each register:
CompositeIndices = [(ssub_2 dsub_1, ssub_0),
(ssub_3 dsub_1, ssub_1)] in ...
This also makes it clear that SubRegIndex composition is supposed to be
unique.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149556 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| ee498d3254b86bceb4f441741e9f442990647ce6 |
01-Feb-2012 |
Andrew Trick <atrick@apple.com> |
VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).
This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling.
Patch by Sergei Larin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149547 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetLowering.h
|
| 4a99f59aef358fb93eac180e49f6dcef03822046 |
25-Jan-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Properly emit ctors / dtors with priorities into desired sections
and let linker handle the rest.
This finally fixes PR5329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148990 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 5b52f6d655e34de5c6fedbb71b6c94775cc10032 |
24-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an (interleave A, B, ...) SetTheory operator.
This will interleave the elements from two or more lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148824 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
argetLowering.h
|
| 22de16dc7582dac43429ce0dcb374604020c01f5 |
19-Jan-2012 |
Nick Lewycky <nicholas@mxc.ca> |
Add a TargetOption for disabling tail calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148442 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 31867660cb81ea2b1d1a6ffa7d09c91acb754a8b |
18-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a CoveredBySubRegs property to Register descriptions.
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.
Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers. For example, the
ARM registers D8-D15 are callee-saved. This now automatically implies
that Q4-Q7 are call-preserved.
Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| ec572539dd5660f9ca42027ac04df3a3f8c0cab1 |
17-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TableGen support for callee saved registers.
Targets can now add CalleeSavedRegs defs to their *CallingConv.td file.
TableGen will use this to create a *_SaveList array suitable for
returning from getCalleeSavedRegs() as well as a *_RegMask bit mask
suitable for returning from getCallPreservedMask().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148346 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.td
|
| c1b1c7b205589c9a081e1cbd33fb56506fc287b3 |
17-Jan-2012 |
Andrew Trick <atrick@apple.com> |
Moving options declarations around.
More short term hackery until we have a way to configure passes that work on LiveIntervals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148289 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| bd6dc3be1dac2d153f29927cad517af9e579b204 |
14-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TRI::getCallPreservedMask() hook.
The hook returns a bit-mask of call-preserved registers that will
eventually replace the current list of implicit defs on call
instructions. This will make it possible to support multiple calling
conventions without duplicating call instruction descriptors.
The call-preserved mask is slightly different from the list returned by
the getCalleeSavedRegs() hook, it includes all aliases that are
preserved by calls.
The hook takes a CallingConv::ID argument instead of a MachineFunction
pointer, so it can provide information about calls to extern functions,
and even indirect function calls.
TRI::getCalleeSavedRegs() returns information about the function
currently being compiled. TRI::getCallPreservedMask() returns
information about the functions it is calling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148165 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 96f678f2d78ae9a2a8c99ca612bf59c056b36797 |
13-Jan-2012 |
Andrew Trick <atrick@apple.com> |
Added the MachineSchedulerPass skeleton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148105 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| b3fe88f8379c4c4193d5d84267ae1a304437f8fa |
13-Jan-2012 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148104 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| f0a95356d649dc0fb65691c4acebee450f3529b4 |
12-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
Allow targets to select source order pre-RA scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148033 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e5dafc395656645c3a5d90e7c1b55477800f2ab1 |
12-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
Move Sched::Preference out of TargetMachine.h where it is not referenced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148014 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetMachine.h
|
| 732f05c41f177a0bc4d47e93a5d02120f146cb4c |
10-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Add 'llvm_unreachable' to passify GCC's understanding of the constraints
of several newly un-defaulted switches. This also helps optimizers
(including LLVM's) recognize that every case is covered, and we should
assume as much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147861 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2bd335470f8939782f3df7f6180282d3825d4f09 |
10-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
Remove unnecessary default cases in switches that cover all enum values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0dbcadaa2fdf7038431931bab090f4467d8e308f |
09-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Split AsmParser into two components - AsmParser and AsmParserVariant
AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147787 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 2d24e2a396a1d211baaeedf32148a3b657240170 |
20-Dec-2011 |
David Blaikie <dblaikie@gmail.com> |
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
argetLibraryInfo.h
argetRegisterInfo.h
|
| 8787c5f24e175a36f645784d533384f9f7cd86fc |
19-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146914 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 638905d90cf8e2601b5609e549e3fca6676fff10 |
19-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add "using" to silence warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146913 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 1e2ec6abd4e150ac87d6cde3133fa9895f63c74c |
19-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Attempt to fix PR11607 by shuffling around which class defines which methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146897 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 570f9a972e02830d1ca223743dd6b4cc4fdf9549 |
19-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Emit a getMatchingSuperRegClass() implementation for every target.
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 020f4106f820648fd7e91956859844a80de13974 |
14-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Model ARM predicated write as read-mod-write. e.g.
r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146583 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 12dfdb424ddcfabb347f168f9332795ba443ccd3 |
14-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Allow target to specify register output dependency. Still default to one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146547 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 63974b2144c87c962effdc0508c27643c8ad98b6 |
13-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 531bb82556847cc85c1477f8a6f54f2e43d0e04c |
10-Dec-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Minimize #include's and forward-declares in Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146335 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.h
argetLowering.h
|
| 32f9763017f4329a0da75648655d63c9d7b91130 |
09-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move isUnpredicatedTerminator() default implementation to TargetInstrInfoImpl to break Target's dependency on CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146247 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 243eb9ecbbc6775e346e94025bd255bbceac9fca |
08-Dec-2011 |
Owen Anderson <resistor@mac.com> |
Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146193 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| a66512e59142f36ae653460891c058d5e78e07e3 |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Extend AsmMatcher token literal matching to allow aliasing.
For example, ARM allows:
vmov.u32 s4, #0 -> vmov.i32, #0
'u32' is a more specific designator for the 32-bit integer type specifier
and is legal for any instruction which accepts 'i32' as a datatype suffix.
We want to say,
def : TokenAlias<".u32", ".i32">;
This works by marking the match class of 'From' as a subclass of the
match class of 'To'.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145992 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 7c2a4a30e0e16762c75adacebd05ec9fcbccf16b |
06-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetOpcodes.h
|
| 1608769abeb1430dc34f31ffac0d9850f99ae36a |
05-Dec-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Add support for vectors of pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145801 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8a8d479214745c82ef00f08d4e4f1c173b5f9ce2 |
02-Dec-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetMachine.h
argetOptions.h
|
| a930f3d8a37fdcb21e1fd8a14c02cc25af026470 |
02-Dec-2011 |
Dylan Noblesmith <nobled@dreamwidth.org> |
TargetMachine: document unnamed bool argument
Its meaning was slightly mysterious without looking at
subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145705 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 32b6c59ad068d2bb2466dd33bc17d8c865760215 |
01-Dec-2011 |
Chad Rosier <mcrosier@apple.com> |
Add a few more functions to TargetLibraryInfo. More of rdar://10500969.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145596 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 8ff4115ef0bcad0a46750bb2bd4376a61b346362 |
30-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add a few functions to TargetLibraryInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145508 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 683e47b1dd8672b0b026a45022cf91f4faf7df9b |
30-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functional
change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145468 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 3d925d24e8c54cde05228258c25cc21687cad922 |
30-Nov-2011 |
Chad Rosier <mcrosier@apple.com> |
Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is
specified.
rdar://10466410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145460 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 9d434dbff3eb0501efc3457acec2401afdffef2f |
17-Nov-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom
names for fwrite and fputs.
Fixes <rdar://problem/9815881>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144876 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16 |
16-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| c2ecf3efbf375fc82bb1cea6afd7448498f9ae75 |
15-Nov-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Break false dependencies before partial register updates.
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.
The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.
The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144602 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| f9fd29ea34d841df7d43807e386c48c08bf83f13 |
13-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix comment for LegalizeTypeAction enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144511 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 19a4daff9bbe18dab2620e25ac6cbf0635639ec6 |
07-Nov-2011 |
Richard Osborne <richard@xmos.com> |
Don't introduce custom nodes after legalization in TargetLowering::BuildSDIV()
and TargetLowering::BuildUDIV(). Fixes PR11283
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143964 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 84a61269370138b68ae2bcd6711a9ae8004fd77a |
04-Nov-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add missing includes/decls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143722 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.h
argetOptions.h
|
| 15701f8969fcb36899a75ca2df6fdcbc52141106 |
27-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Rename NonScalarIntSafe to something more appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143080 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d5333d6922fa5ce8954df600a61605e4ca1d92f6 |
24-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Delete the Latency scheduling preference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142815 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 1dda3d511e19918c4487e9d5a45eb5856284494e |
20-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Haven't yet found a nice way to handle TargetData verification in the
AsmParser. This patch adds validation for target data layout strings upon
construction of TargetData objects. An attempt to construct a TargetData object
from a malformed string will trigger an assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142605 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 84dc1f0aaff02b7f60c655af6bd5ea0be5e72d9e |
20-Oct-2011 |
Duncan Sands <baldrick@free.fr> |
Comment out or remove unused parameter names so as to avoid a slew of
compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142574 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 90b7b12f012d9234488277a323231e0b7a8d12ac |
18-Oct-2011 |
Andrew Trick <atrick@apple.com> |
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142397 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 7f5f0dae33c8a105b51532d5ceb3339ac2ce0cbc |
18-Oct-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142394 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| d8ffe5bb162bf97a7b0a323d2edcf8b83ca5dada |
18-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Backing out patch. Will refactor to remove the AsmParser dependency on Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142323 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 5fa792e65a2da4f24c70772cecccb1e04d9a38e7 |
18-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Re-applying the target data layout verification patch from r142288, plus appropriate CMake dependencies.
Thanks to Raphael Espindola for tracking down the CMake issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142306 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 44d798d9763bc32aaf49fe7c10d604845f4b6685 |
18-Oct-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add support for a new extension to the .file directive:
.file filenumber "directory" "filename"
This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142300 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 10820d9a9754987533fd7a8b50b03831781cbd65 |
18-Oct-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
142288 broke the build:
Linking CXX executable ../../bin/llvm-as
../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)'
clang-3: error: linker command failed with exit code 1 (use -v to see invocation)
Revert "Validate target data layout strings."
This reverts commit 599d2d4c25d3aee63a21d9c67a88cd43bd971b7e.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142296 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 599d2d4c25d3aee63a21d9c67a88cd43bd971b7e |
18-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Validate target data layout strings.
Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142288 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 442bf7a64d9a514c7df46505a0b2ee09fd4b8692 |
17-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Add comments to TargetLowering.h indicating that the set*Alignment functions take arguments in log2(bytes)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142213 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6509f50c69b26b88a77bcae6b9ba84c7e6122b73 |
12-Oct-2011 |
Chris Lattner <sabre@nondot.org> |
improve some of the documentation around target data layout strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141733 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| bb5b3f33594cfa40e9f53bf9a71af359b080a697 |
11-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Add a natural stack alignment field to TargetData, and prevent InstCombine from
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.
The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141599 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 5a57168a55f23cff1f0d1c7ba4183b4182665e46 |
10-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Mark the standard pseudos as isPseudo = 1.
The difference between isPseudo and isCodeGenOnly is a bit murky, but
isCodeGenOnly should eventually go away. It is used for instructions
that are clones of real instructions with slightly different properties.
The standard pseudo-instructions never mirror real instructions, so they
are definitely in the isPseudo category.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141567 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| cf2adb945ab8b86996424d7e6d3f742d78c91e1e |
06-Oct-2011 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141269 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d9c1fa5205cc31474f9f9a6d715af32098a1a719 |
06-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the TRI::getSubRegisterRegClass() hook.
This restores my karma after I added TRI::getSubClassWithSubReg().
Register constraints are applied 'backwards'. Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.
We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in? The
getSubRegisterRegClass() hook did that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 845d2c0c776abce551d16f7b1b7dc1f4d4df1a27 |
05-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TRI::getSubClassWithSubReg(RC, Idx) function.
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.
For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.
The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.
The version provided by TableGen is usually adequate, but targets can
override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| c8e2bb68bbc4a71cc10084c8f89565b9f05e12ef |
01-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Store sub-class lists as a bit vector.
This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| e27e1ca3c90b69e78242c98a669337f84ccded7f |
01-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move getCommonSubClass() into TRI.
It will soon need the context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140896 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 92fb79b7a611ab4c1043f04e8acd08f963d073ad |
29-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Expand the x86 V_SET0* pseudos right after register allocation.
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140776 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 98e933f9ad3cc2ede3a0a337144a504265d614cd |
28-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.
I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass. They are essentially doing the same
thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140652 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| c291e2f5780c3a8470113a2a58c1fa680cd54b20 |
25-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add target hook for pseudo instruction expansion.
Many targets use pseudo instructions to help register allocation. Like
the COPY instruction, these pseudos can be expanded after register
allocation. The early expansion can make life easier for PEI and the
post-ra scheduler.
This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 3be654f8082dcbdff011a6716a7c90486e28fc9e |
21-Sep-2011 |
Andrew Trick <atrick@apple.com> |
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| fbad25e12073e2cbe192b2c4cc4f0bbb26148c9c |
11-Sep-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
CR fixes per Bruno's request.
Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 28b77e968d2b01fc9da724762bd8ddcd80650e32 |
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 76927d758657b3a511c73467ec5a7288795c1513 |
30-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Emit segmented-stack specific code into function prologues for
X86. Modify the pass added in the previous patch to call this new
code.
This new prologues generated will call a libgcc routine (__morestack)
to allocate more stack space from the heap when required
Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138812 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameLowering.h
|
| 0f9827cd9417c7385c92fa4a0d8d8b4242b3729d |
30-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Command line option to enable support for segmented stacks:
-segmented-stacks.
Patch by Sanjoy Das!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138811 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 37fefc20d3a1e3934a377567d54a141f67752227 |
30-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetLowering.h
|
| 327236cd6c211e54fc6288b0ac2b413901cc0611 |
24-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Basic x86 code generation for atomic load and store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138478 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 |
24-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
argetSelect.h
|
| 7801136b95d1fbe515b9655b73ada39b05a33559 |
23-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Some refactoring so TargetRegistry.h no longer has to include any files
from MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| c66d36028b21077aa1715331c22347b47b4da94f |
10-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Trim an unneeded header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137184 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 2df3f58a0b3937f2cbd76d3417d2905ca86cf8fa |
08-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Hoist hasLoadFromStackSlot and hasStoreToStackSlot.
These the methods are target-independent since they simply scan the
memory operands. They can live in TargetInstrInfoImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137063 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 41ab14b725c8f2bb3e54553d0d7d96ff184786b1 |
08-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137059 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 1203486d92bb1f9a82533ff0a4572d5a23fb5f9a |
04-Aug-2011 |
Duncan Sands <baldrick@free.fr> |
Fix a place that was clearly forgotten when the type legalization
logic moved over to its own enum. Noticed by Andrey Karpov with
the PVS-studio tool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136881 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 26689ac37ebec3b358588089415509285e558de9 |
03-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 14648468011c92a4210f8118721d58c25043daf8 |
28-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Code generation for 'fence' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 28c85a81a17dd719a254dc00cbeb484774893197 |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136031 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 94b9550a32d189704a8eae55505edf62662c0534 |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 78c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5c |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136010 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 1b0fc9b4182d6bd0703cdfb3b0b91d1e093c946c |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix last bits of MC layer issues. llvm-mc doesn't need to initialize TargetMachine's anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135963 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 9df8567548e15c6cd91e8a5851784574c4f09528 |
23-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Turn the DenseSet in MCRegisterClass into a tblgenerated bit field. This should be faster and smaller.
Goodbye static ctors and dtors!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135836 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| f496d68493acf8d178afbbe8c3146ea09bd7776b |
23-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Give TargetRegisterClass a pointer to the MCRegisterClass and use it to access its data.
This makes TargetRegisterClass slightly slower. Next step will be making contains faster.
Eventually TargetRegisterClass will be killed entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135835 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| a7cfc08ebe737062917b442830eb5321b0f79e89 |
23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135833 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
argetAsmLexer.h
argetAsmParser.h
|
| e78085a3c03de648a481e9751c3094c517bd7123 |
22-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135812 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| 077c40871780136f7016a496703b20ebea9c0978 |
22-Jul-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Move the logic for printing the registered targets into a static
function on the TargetRegistry. Also clean it up and use the modern LLVM
utility libraries available instead of rolling a few things manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135756 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 8ca9a862038e8c4e9a2ca73b3b75e1be3425155f |
22-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Teach tblgen to emit MCRegisterClasses.
- This currently introduces more instances of the static DenseSet dtor, but that should be fixable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135735 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| a50c175fe3c7a3034df18747cfacb3b153c493c8 |
21-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Sink parts of TargetRegisterClass into MCRegisterClass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135683 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 16da7366d598dd863cd3c05c81ab089e830bbafe |
21-Jul-2011 |
Bill Wendling <isanbard@gmail.com> |
Remove the now defunct getCompactUnwindEncoding method from the frame lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135634 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameLowering.h
|
| 203576aa0cb9d8bf2d2e4d910ebab4b7a63262ae |
20-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.
There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135611 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| 34ad6db8b958fdc0d38e122edf753b5326e69b03 |
20-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
code model for JIT. This eliminates the ugly hack in TargetMachine where
code model is changed after construction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetRegistry.h
|
| e76a33b9567d78a5744dc52fcec3a6056d6fb576 |
20-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add MCObjectFileInfo and sink the MCSections initialization code from
TargetLoweringObjectFileImpl down to MCObjectFileInfo.
TargetAsmInfo is done to one last method. It's *almost* gone!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| f1a009007374d8ae1c1565f34d9cea3b83665e5f |
19-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135524 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 8fbbb3980755d74539a0aed02bc18842ed2bd18d |
19-Jul-2011 |
Jay Foad <jay.foad@gmail.com> |
Convert TargetData::getIndexedOffset to use ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135478 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 439661395fd2a2a832dba01c65bc88718528313c |
19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetRegistry.h
argetSelect.h
|
| 9710f06d668bd790a2a18a6c2cd65b35414d66ab |
19-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make isLoadExtLegal and isTruncStoreLegal check what the name says. :) This might have some minor effect on CellSPU, but all other targets should be unaffected. Fixing per report from Damien Vincent on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135462 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c8c3acfea439998da4fae895becce7c1468e3c63 |
19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate TargetAsmInfo::getCompactUnwindEncoding. This get rid of the
use of TargetFrameLowering in TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135439 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 2d28617de2b0b731c08d1af9e830f31e14ac75b4 |
19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for
better location welcome).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetFrameLowering.h
|
| 0e6a052331f674dd70e28af41f654a7874405eab |
18-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetRegisterInfo.h
argetRegistry.h
argetSelect.h
|
| 39b5abf507b43da6b92f68b86406e0015ead18e9 |
18-Jul-2011 |
Frits van Bommel <fvbommel@gmail.com> |
Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used.
Mostly mechanical with some manual reformatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135390 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| db125cfaf57cc83e7dd7453de2d509bc8efd0e5e |
18-Jul-2011 |
Chris Lattner <sabre@nondot.org> |
land David Blaikie's patch to de-constify Type, with a few tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
argetIntrinsicInfo.h
argetLowering.h
|
| ef58218b8dd9afc0251eeb673c10d448da45d281 |
15-Jul-2011 |
Chris Lattner <sabre@nondot.org> |
remove the InvalidateStructLayoutInfo API, which is dead and unnecessary now
that type refinement is toast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135245 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 1be0e271a07925b928ba89848934f1ea6f1854e2 |
15-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatest
solution but it is a small step towards removing the horror that is
TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135237 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 1abf2cb59b8d63415780a03329307c0997b2670c |
15-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
argetSelect.h
|
| 5196c12e9fdec9ef3c63d96cb529c1c1cb732773 |
14-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add a new field to MCOperandInfo that contains information about the type of the Operand.
- The actual values are from the MCOI::OperandType enum.
- Teach tblgen to read it from the instruction definition.
- This is a better implementation of the hacks in edis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135197 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 16884415db751c75f2133bd04921393c792b1158 |
14-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| d5efb1eee65cbee06722341869e5c88d2f648fa3 |
13-Jul-2011 |
Bill Wendling <isanbard@gmail.com> |
There is a cyclic dependency between MC and Target if this method is out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135006 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| e3f5ae7b9e68953635f604a8b437d440678bb18e |
12-Jul-2011 |
Tobias Grosser <grosser@fim.uni-passau.de> |
Remove IntegerType constness from TargetData
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134978 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 2280ebd61416b73d0b6137f275b25af82e268d1f |
12-Jul-2011 |
Bill Wendling <isanbard@gmail.com> |
Revert r134893 and r134888 (and related patches in other trees). It was causing
an assert on Darwin llvm-gcc builds.
Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\
ne 2067.
etc.
http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354
--- Reverse-merging r134893 into '.':
U include/llvm/Target/TargetData.h
U include/llvm/DerivedTypes.h
U tools/bugpoint/ExtractFunction.cpp
U unittests/Support/TypeBuilderTest.cpp
U lib/Target/ARM/ARMGlobalMerge.cpp
U lib/Target/TargetData.cpp
U lib/VMCore/Constants.cpp
U lib/VMCore/Type.cpp
U lib/VMCore/Core.cpp
U lib/Transforms/Utils/CodeExtractor.cpp
U lib/Transforms/Instrumentation/ProfilingUtils.cpp
U lib/Transforms/IPO/DeadArgumentElimination.cpp
U lib/CodeGen/SjLjEHPrepare.cpp
--- Reverse-merging r134888 into '.':
G include/llvm/DerivedTypes.h
U include/llvm/Support/TypeBuilder.h
U include/llvm/Intrinsics.h
U unittests/Analysis/ScalarEvolutionTest.cpp
U unittests/ExecutionEngine/JIT/JITTest.cpp
U unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp
U unittests/VMCore/PassManagerTest.cpp
G unittests/Support/TypeBuilderTest.cpp
U lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp
U lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp
U lib/VMCore/IRBuilder.cpp
G lib/VMCore/Type.cpp
U lib/VMCore/Function.cpp
G lib/VMCore/Core.cpp
U lib/VMCore/Module.cpp
U lib/AsmParser/LLParser.cpp
U lib/Transforms/Utils/CloneFunction.cpp
G lib/Transforms/Utils/CodeExtractor.cpp
U lib/Transforms/Utils/InlineFunction.cpp
U lib/Transforms/Instrumentation/GCOVProfiling.cpp
U lib/Transforms/Scalar/ObjCARC.cpp
U lib/Transforms/Scalar/SimplifyLibCalls.cpp
U lib/Transforms/Scalar/MemCpyOptimizer.cpp
G lib/Transforms/IPO/DeadArgumentElimination.cpp
U lib/Transforms/IPO/ArgumentPromotion.cpp
U lib/Transforms/InstCombine/InstCombineCompares.cpp
U lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
U lib/Transforms/InstCombine/InstCombineCalls.cpp
U lib/CodeGen/DwarfEHPrepare.cpp
U lib/CodeGen/IntrinsicLowering.cpp
U lib/Bitcode/Reader/BitcodeReader.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134949 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| eeb64ae6e52ac2a7980884fe89c01508014af6a9 |
11-Jul-2011 |
Jay Foad <jay.foad@gmail.com> |
De-constify Types in StructType::get() and TargetData::getIntPtrType().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134893 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 59ee62d2418df8db499eca1ae17f5900dc2dcbba |
11-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
argetSelect.h
|
| f81b7f6069b27c0a515070dcb392f6828437412f |
10-Jul-2011 |
Jakub Staszak <jstaszak@apple.com> |
Use BranchProbability instead of floating points in IfConverter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134858 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| ffc0e73046f737d75e0a62b3a83ef19bcef111e3 |
09-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
argetSelect.h
|
| 97cd3cf9b0e856e7a35bd8c8e6d302d18858577f |
09-Jul-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add an fma TableGen node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134762 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 480cee5d4396a380ada6ffd03551b5700d041fe0 |
08-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
TargetAsmParser doesn't need reference to Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134721 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
argetRegistry.h
|
| 86f9adb8becf5da6962bd89301e96bccba26f72a |
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
TableGen'erated MC lowering for simple pseudo-instructions.
This allows the (many) pseudo-instructions we have that map onto a single
real instruction to have their expansion during MC lowering handled
automatically instead of the current cumbersome manual expansion required.
These sorts of pseudos are common when an instruction is used in situations
that require different MachineInstr flags (isTerminator, isBranch, et. al.)
than the generic instruction description has. For example, using a move
to the PC to implement a branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134704 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 9c64030445cbe6ac486b90c5f459f91e06770474 |
08-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Emit a more efficient magic number multiplication for exact sdivs.
We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.
struct foo { char x[24]; };
long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
movl 4(%esp), %eax
subl 8(%esp), %eax
sarl $3, %eax
imull $-1431655765, %eax, %eax
instead of
movl 4(%esp), %eax
subl 8(%esp), %eax
movl $715827883, %ecx
imull %ecx
movl %edx, %eax
shrl $31, %eax
sarl $2, %edx
addl %eax, %edx
movl %edx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134695 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ebdeeab812beec0385b445f3d4c41a114e0d972f |
08-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
to generate asm matcher subtarget feature queries. e.g.
"ModeThumb,FeatureThumb2" is translated to
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetMachine.h
argetRegistry.h
|
| 4ae970b393f9518eb4a0c2e6b2c16ec3bee570d0 |
07-Jul-2011 |
Bill Wendling <isanbard@gmail.com> |
Move a function out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134640 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 0ddff1b5359433faf2eb1c4ff5320ddcbd42f52f |
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Compute feature bits at time of MCSubtargetInfo initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| b99e412650d25776686b46e743751f4ba97a2e4e |
07-Jul-2011 |
Bill Wendling <isanbard@gmail.com> |
Use ArrayRef instead of a std::vector&.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134595 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameLowering.h
|
| 6a6b8c3e96b9e1ca7092eafd0cfb219cbbfbdfc4 |
07-Jul-2011 |
Bill Wendling <isanbard@gmail.com> |
Add a target hook to encode the compact unwind information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134577 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetFrameLowering.h
|
| 806fcc040e0bc7962891f12d6e09fc86f0bc2184 |
06-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Don't require pseudo-instructions to carry encoding information.
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 486dd90696545421c55346570b88fa03f6dd464f |
06-Jul-2011 |
Bill Wendling <isanbard@gmail.com> |
Constify getCompactUnwindRegNum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134527 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetRegisterInfo.h
|
| b262799d49891b036daa00eddf51947487346c98 |
06-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
createMCInstPrinter doesn't need TargetMachine anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134525 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| ce795dc92f693a855dbf1450570e6aeb69774bcc |
02-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add MCSubtargetInfo target registry stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134279 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 5b1b4489cf3a0f56f8be0673fc5cc380a32d277b |
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetSubtarget.h
argetSubtargetInfo.h
|
| 94214703d97d8d9dfca88174ffc7e94820a85e62 |
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtarget.h
|
| 4db3cffe94a5285239cc0056f939c6b74a5ca0b6 |
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 5cd2791513919ee7504c309151321e4e37a05a58 |
01-Jul-2011 |
Bill Wendling <isanbard@gmail.com> |
Add target a target hook to get the register number used by the compact unwind
encoding for the registers it knows about. Return -1 if it can't handle that
register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134202 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetRegisterInfo.h
|
| 276365dd4bc0c2160f91fd8062ae1fc90c86c324 |
30-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.
The fix is to just have the clients explictly pass the CPU name!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 5244c4cc2fd31e49bae2b192bd824a94b6ad5331 |
30-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Remove getRegClassForInlineAsmConstraint and all dependencies.
Fixes rdar://9643582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134123 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ab8be96fd30ca9396e6b84fdddf1ac6208984cad |
29-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
argetInstrItineraries.h
argetMachine.h
|
| d807674c8b1a8d191a4e52795fd6a3a6de184116 |
29-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Trim include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134048 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| a01b58af85cebd7d7bcf94d48317f8cc8a4bdf57 |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak every backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134031 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| d5b03f252c0db6b49a242abab63d7c5a260fceae |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetRegisterInfo.h
|
| 94b01f688256fca49decb239a8c84b003f18cdbc |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add MCInstrInfo registeration machinery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134026 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
argetInstrInfo.h
argetRegisterInfo.h
|
| 4db3748fcf39ac0001b9d02eb6bf803e309a5c19 |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove RCBarriers from TargetInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133964 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| 15993f83a419950f06d2879d6701530ae6449317 |
27-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
argetInstrInfo.h
|
| bea6f615eefae279e53bbb63a31d2c3c67274c45 |
27-Jun-2011 |
Owen Anderson <resistor@mac.com> |
Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 2ca7f4d2f3782db8b9f1a264fc558a72b0fd4fa0 |
27-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename unnecessary forward declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133928 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 5e6b4605bd620a864055276a6d454e5a18f9fee8 |
25-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetRegisterDesc to MCRegisterDesc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133845 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| f5fa52ed064098be7130aa4ec1236037907ce3fa |
24-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Add MCRegisterInfo registration machinery. Also added x86 registration routines.
- Rename TargetRegisterDesc to MCRegisterDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
argetRegistry.h
|
| a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d |
24-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
argetRegistry.h
|
| f05589d0430a543e8158b912dcb8117bf5cb376e |
23-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetOptions::StackAlignment to StackAlignmentOverride.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133739 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 4c0c446d7458ffcfbe108ea71f1915f387e150e7 |
23-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the presence of the __compact_unwind section to indicate that a target
supports compact unwind info instead of having a separate flag indicating this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133685 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| 533c9ac02196fbb911d90e129631ed7c97d9c449 |
23-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Allow the AsmInfo to query for the compact unwind section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133670 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| de0cea7e495849659a079ddcec8e299cbbcad90a |
23-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Allow the AsmInfo to query the TLOF to see if it supports compact unwind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133669 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 1a3ab63cb59d7f7726b47cdda3b9509e999d1653 |
23-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Add a flag that indicates whether a target supports compact unwind info or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133662 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| aa0a8f317791b4de07a6c7a2b9705c4183052b54 |
23-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Add a __LD,__compact_unwind section.
If the linker supports it, this will hold the CIE and FDE information in a
compact format. The implementation of the compact unwinding emission is coming
soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133658 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 4ce25d5d69704a7a4aa4bcecbe4c7345b50b771a |
20-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a RegisterTuples class to Target.td and TableGen.
A RegisterTuples instance is used to synthesize super-registers by
zipping together lists of sub-registers. This is useful for generating
pseudo-registers representing register sequence constraints like 'two
consecutive GPRs', or 'an even-odd pair of floating point registers'.
The RegisterTuples def can be used in register set operations when
building register classes. That is the only way of accessing the
synthesized super-registers.
For example, the ARM QQ register class of pseudo-registers could have
been formed like this:
// Form pairs Q0_Q1, Q2_Q3, ...
def QQPairs : RegisterTuples<[qsub_0, qsub_1],
[(decimate QPR, 2),
(decimate (shl QPR, 1), 2)]>;
def QQ : RegisterClass<..., (add QQPairs)>;
Similarly, pseudo-registers representing '3 consecutive D-regs with
wraparound' look like:
// Form D0_D1_D2, D1_D2_D3, ..., D30_D31_D0, D31_D0_D1.
def DSeqTriples : RegisterTuples<[dsub_0, dsub_1, dsub_2],
[(rotl DPR, 0),
(rotl DPR, 1),
(rotl DPR, 2)]>;
TableGen automatically computes aliasing information for the synthesized
registers.
Register tuples are still somewhat experimental. We still need to see
how they interact with MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133407 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 54c47c1ce94b9e549ef768e80fd004788d13ce85 |
18-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove MethodProtos/MethodBodies and allocation_order_begin/end.
Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.
The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.
It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetRegisterInfo.h
|
| b4c704877d1600852a55ab7bef2918a7c0af5e0d |
18-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Provide AltOrders for specifying alternative allocation orders.
A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.
This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133320 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| e266ce6c6eaf52ebe2b18d85b5e23788cf2f6ef4 |
17-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the verbose asm flag instead of a new flag for decoding the LSDA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133292 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| da26ad501b9125c323f58f756826cf17114a9e6f |
17-Jun-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Fix a bug in the type-lowering of integer-promoted elements. Add a check that
the newly created simple type is valid before checking its legality.
Re-commit the test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133291 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 916a94b870042772568fca7995cf45aef7a6e333 |
17-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Add an option that allows one to "decode" the LSDA.
The LSDA is a bit difficult for the non-initiated to read. Even with comments,
it's not always clear what's going on. This wraps the ASM streamer in a class
that retains the LSDA and then emits a human-readable description of what's
going on in it.
So instead of having to make sense of:
Lexception1:
.byte 255
.byte 155
.byte 168
.space 1
.byte 3
.byte 26
Lset0 = Ltmp7-Leh_func_begin1
.long Lset0
Lset1 = Ltmp812-Ltmp7
.long Lset1
Lset2 = Ltmp913-Leh_func_begin1
.long Lset2
.byte 3
Lset3 = Ltmp812-Leh_func_begin1
.long Lset3
Lset4 = Leh_func_end1-Ltmp812
.long Lset4
.long 0
.byte 0
.byte 1
.byte 0
.byte 2
.byte 125
.long __ZTIi@GOTPCREL+4
.long __ZTIPKc@GOTPCREL+4
you can read this instead:
## Exception Handling Table: Lexception1
## @LPStart Encoding: omit
## @TType Encoding: indirect pcrel sdata4
## @TType Base: 40 bytes
## @CallSite Encoding: udata4
## @Action Table Size: 26 bytes
## Action 1:
## A throw between Ltmp7 and Ltmp812 jumps to Ltmp913 on an exception.
## For type(s): __ZTIi@GOTPCREL+4 __ZTIPKc@GOTPCREL+4
## Action 2:
## A throw between Ltmp812 and Leh_func_end1 does not have a landing pad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133286 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| dd5a8471526ceadf9bceb1a1221299b3db49c33a |
17-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Rename TRI::getAllocationOrder() to getRawAllocationOrder().
Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.
The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133216 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 1300f3019e5d590231bbc3d907626708515d3212 |
16-Jun-2011 |
Owen Anderson <resistor@mac.com> |
Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133178 91177308-0d34-0410-b5e6-96231b3b80d8
argetOpcodes.h
|
| 79c890f64f3b67f9b11341aa452c4302b75184aa |
16-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterInfo::getRawAllocationOrder().
This virtual function will replace allocation_order_begin/end as the one
to override when implementing custom allocation orders. It is simpler to
have one function return an ArrayRef than having two virtual functions
computing different ends of the same array.
Use getRawAllocationOrder() in place of allocation_order_begin() where
it makes sense, but leave some clients that look like they really want
the filtered allocation orders from RegisterClassInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133170 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| f28987b76e758b5f2fcc2c5d2c8e073df54ca91e |
16-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 1e56a2a85fbafce5ceee72f72d41b84a71876844 |
15-Jun-2011 |
Owen Anderson <resistor@mac.com> |
Replace the statically generated hashtables for checking register relationships with just scanning the (typically tiny) static lists.
At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries. Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan.
With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time. It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133051 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 9a767330f555f21d6ef311d3a348d3a44f306d35 |
14-Jun-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach
autoupgrade.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 65255b98ad5b35b14df8aebcda38e9d5cc646886 |
12-Jun-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Bugfix: When looking for a legal vector type, stop looking when a non-simple
element type is found.
This fix addresses some of the tests in Duncan's testcase (forthcoming).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132891 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b95fd2d5fd4818a601dd1df05f38863e3ca5c920 |
12-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Tweak hash function and compress hash tables.
Make the hash tables as small as possible while ensuring that all
lookups can be done in less than 8 probes.
Cut the aliases hash table in half by only storing a < b pairs - it
is a symmetric relation.
Use larger multipliers on the initial hash function to ensure that it
properly covers the whole table, and to resolve some clustering in the
very regular ARM register bank.
This reduces the size of most of these tables by 4x - 8x. For instance,
the ARM tables shrink from 48 KB to 8 KB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132888 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 026dc223aeef2579d63f395007491e37d6cde3a0 |
12-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Compute lists of sub-regs, super-regs, and overlapping regs.
Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:
- Sub-register lists come from a pre-order traversal of the graph
defined by the SubRegs lists in the .td files.
- Super-register lists are topologically ordered so no register comes
before any of its sub-registers. When the sub-register graph is not a
tree, independent super-registers appear in numerical order.
- Lists of overlapping registers are ordered according to register
number.
This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.
The old computations are still there, but will be removed shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 471e4224809f51652c71f319532697a879a75a0d |
09-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Add a parameter to CCState so that it can access the MachineFunction.
No functional change.
Part of PR6965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 100c83341676d8aae8fc34b5452563ed08b14f3e |
03-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f462e3fac7ac67503657d63dc35330d0b19359b3 |
03-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make it possible to have unallocatable register classes.
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.
TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.
The goal here is to eliminate use cases for overriding allocation_order_*
methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetRegisterInfo.h
|
| 0be9f5dde4f2eb47b0fcf0bedc4db96ac9df512c |
01-Jun-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Initialize IssueWidth to zero.
Fixes valgrind errors in the CellSPU backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132405 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 1f9a09c61489a83360238032b6756395bd69b620 |
01-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix PR10059 and future variations by handling all register subclasses.
Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132398 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| b6fbec3a546fd04bb2e79040db2436b0bd629162 |
01-Jun-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
This patch is another step in the direction of adding vector select. In this
patch we add a flag to enable a new type legalization decision - to promote
integer elements in vectors. Currently, the rest of the codegen does not support
this kind of legalization. This flag will be removed when the transition is
complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132394 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4fd0dee3bfe8a35bbb62c9e9dea511cbc06cec2d |
01-Jun-2011 |
Stuart Hastings <stuart@apple.com> |
FGETSIGN support for x86, using movmskps/pd. Will be enabled with a
patch to TargetLowering.cpp. rdar://problem/5660695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132388 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 6e032942cf58d1c41f88609a1cec74eb74940ecd |
30-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use the dwarf->llvm mapping to print register names in the cfi
directives.
Fixes PR9826.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetRegisterInfo.h
|
| 7a067cc6e0b980b186696c13fe847929fbc0d373 |
30-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Introduce the DwarfRegAlias class for declaring that two registers have the
same dwarf number. This will be used for creating a dwarf number to register
mapping.
The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132314 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| b6aacae9413adde66d9686cd9e561eb836b3ee34 |
28-May-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Refactor the type legalizer. Switch TargetLowering to a new enum - LegalizeTypeAction.
This patch does not change the behavior of the type legalizer. The codegen
produces the same code.
This infrastructural change is needed in order to enable complex decisions
for vector types (needed by the vector-select patch).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132263 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2d6dcb34b7f39682f3eed08180631189fb4b6636 |
27-May-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'
code in one place. Re-apply 131534 and fix the multi-step promotion of integers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132217 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7b06b7357aa5a7cbdd769edbf6edb10fa055ea09 |
27-May-2011 |
Charles Davis <cdavis@mines.edu> |
Add a parameter to the Win64 EH section getters to get a section with a
suffix (e.g. .xdata$myfunc). The suffix part isn't implemented yet, but
I'll get to it in the next patch.
Fix up all callers of the affected functions. Make them pass said suffix to
the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132205 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| fc2bb8c4448fa884d79e437cc2d2627a7d7740a8 |
25-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Replace the -unwind-tables option with a per function flag. This is more
LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132033 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 3b32d0240c820a8aa829a950628586512a406ea0 |
24-May-2011 |
Charles Davis <cdavis@mines.edu> |
Implement the rest of the SEH directive-parsing methods in the COFFAsmParser.
Add a size alignment check to the .seh_stackalloc directive parser. Add a
more descriptive error message to the .seh_handler directive parser.
Add methods to the TargetAsmInfo struct in support of all this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131992 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 6b918b84661687f7b5fc92dabd6d58e258bf39f2 |
24-May-2011 |
Charles Davis <cdavis@mines.edu> |
Add a method to TargetRegisterInfo to get the register number that the Win64 EH
scheme uses internally. Implement it for x86 (the only architecture that LLVM
supports for which this matters right now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131969 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| dfa178bc2a21667aab745ba9a182cd3e702fec3b |
24-May-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Work around code generation bug in Visual Studio 2010.
See http://llvm.org/pr9976 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131954 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| ba55b8f3e48e9ac326cdb601768cb1ded9ffefa2 |
22-May-2011 |
Charles Davis <cdavis@mines.edu> |
Allow access to the .pdata and .xdata sections through the TargetAsmInfo
class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131816 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 40f5fbcc5c95bb96c43ce2d06d57ae9b7f852539 |
21-May-2011 |
Chris Lattner <sabre@nondot.org> |
add a copy ctor to TargetLibraryInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131806 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| f3ffc2cd76267b7901088ec5e46e875a2701bda9 |
21-May-2011 |
Charles Davis <cdavis@mines.edu> |
Add .pdata and .xdata sections to the COFF TLOF implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131763 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| d6dde76090dd673a673ce363c982c22ea924502a |
18-May-2011 |
Duncan Sands <baldrick@free.fr> |
Revert commit 131534 since it seems to have broken several buildbots.
Original log entry:
Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'
code in one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131536 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| fe3f5d7538954474731dbbed70430016600fa477 |
18-May-2011 |
Nadav Rotem <nadav.rotem@intel.com> |
Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'
code in one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131534 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 40a7dbbeff44c4cbd8c7e4f07f28dd614f8a5d08 |
10-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for producing .deubg_frame sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131121 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| aec038fa8418d21755e22ff749969bddd4428da9 |
07-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix comments per Duncan's review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131055 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| fc5d305597ea6336d75bd7f3b741e8d57d6a5105 |
06-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make the logic for determining function alignment more explicit. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 087aad44cb37b361e8ed84f197138b366c764f9a |
05-May-2011 |
Bill Wendling <isanbard@gmail.com> |
Remove a flag that would set the ".eh" symbol as .globl. MachO was the only one
who used this flag, and it now emits CFI and doesn't emit this anymore. All
other targets left this flag "false".
<rdar://problem/8486371>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130918 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| cca82149adef8306a295abdc963213ae3b11bbb6 |
03-May-2011 |
Dan Gohman <gohman@apple.com> |
Add an unfolded offset field to LSR's Formula record. This is used to
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 149f5283f93ec85b96888c284f56099a72cc2731 |
01-May-2011 |
Chris Lattner <sabre@nondot.org> |
enhance memcpyopt to obey -fno-builtin and friends. This addresses a
problem reported on cfe-dev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130661 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 5426a9ee37667660935d80841c5392d78e254318 |
01-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
GCC uses a different encoding of pointers in the FDE when using
-fno-dwarf2-cfi-asm. Implement the same behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130637 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| f1a5c7ec04002769f1638e64f7439589f0f926e6 |
30-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add all the plumbing needed for MC to expand cfi to the old tables in
the final assembly. It is the same technique used when targeting
assemblers that don't support .loc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130587 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetRegistry.h
|
| 8f232d307ace42180961856f69541b95b3278295 |
28-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Let the immediate leaf pattern take transforms and switch the signed
immediate patterns in arm to using the pattern.
Handles rdar://9299434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130386 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| a8cfb87fa2176fae2d62785a0dd606e4143cefae |
28-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Forward isFunctionEHFrameSymbolPrivate. If it is false, produce the foo.eh
symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130375 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 60246a96224c8b790177253bf25433b93b335d2b |
28-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove unnecessary argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130343 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 7afec9cc0ff1654619d30b6f30e2a4d13369c8bf |
28-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Rename getPersonalityPICSymbol to getCFIPersonalitySymbol, document it, and
give it a bit more responsibility. Also implement it for MachO.
If hacked to use cfi, 32 bit MachO will produce
.cfi_personality 155, L___gxx_personality_v0$non_lazy_ptr
and 64 bit will produce
.cfi_presonality ___gxx_personality_v0
The general idea is that .cfi_personality gets passed the final symbol. It is
up to codegen to produce it if using indirect representation (like 32 bit
MachO), but it is up to MC to decide which relocations to create.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130341 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| c9e5015dece0a1a73bec358e11bc87594831279d |
26-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation.
The hook will be used by the register allocator when recomputing register
classes after removing constraints.
Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure
that the spill size doesn't change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130228 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| d94d8468c95c14cba0a28e68908cb038a74d4488 |
22-Apr-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
include/llvm/Target/TargetAsmInfo.h: Fix a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129972 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| abf9af60add19a0f037bb2a05433769bfd1e7f6f |
22-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Compute the size of the FDE encoding instead of hard coding it. Update
X8664_ELFTargetObjectFile::getFDEEncoding to match reality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129959 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 69ba413057fe5d73d95e7b51ddfe16a8b0def23c |
21-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't allow per-register spill size and alignment.
These values were not used for anything. Spill size and alignment is a property
of the register class, not the register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129906 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| c8578948c9b35080dedd6527abf4f48fc4de43d3 |
21-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove -use-divmod-libcall. Let targets opt in when they are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129884 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 6bfba2e5af163442a1c6b11fe14aa9df9101cfd7 |
20-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Prefer cheap registers for busy live ranges.
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.
Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.
Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetRegisterInfo.h
|
| c73158730d43e7c8bdef32b2107566a6e78a8538 |
20-Apr-2011 |
Stuart Hastings <stuart@apple.com> |
ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/7662569>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129858 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4788c3e839203dc75ba9fe2026f315095677715c |
20-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove unused arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129844 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| f6a4d3c2f3e1029af252a0f6999edfa3c2f326ee |
19-Apr-2011 |
Bob Wilson <bob.wilson@apple.com> |
Avoid write-after-write issue hazards for Cortex-A9.
Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.
This is currently disabled by default. We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 202a7a1e3fa661bf78b98d77de7e2d575facd9ee |
18-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Add a new bit that ImmLeaf's can opt into, which allows them to duck out of
the generated FastISel. X86 doesn't need to generate code to match ADD16ri8
since ADD16ri will do just fine. This is a small codesize win in the generated
instruction selector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129692 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 4447d6506cdae78037226ef52c0824a42cf6baa6 |
18-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
since the VT is fixed for a ImmLeaf, there is no reason to expose it to the matching code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129677 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 7ed1391ff66012e4963081cfb20b6166e8784f50 |
18-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
now that predicates have a decent abstraction layer on them, introduce a new
kind of predicate: one that is specific to imm nodes. The predicate function
specified here just checks an int64_t directly instead of messing around with
SDNode's. The virtue of this is that it means that fastisel and other things
can reason about these predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129675 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 543790673c747ab2793fc657e239ce5f78419dc0 |
17-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Rework our internal representation of node predicates to expose more
structure and fix some fixmes. We now have a TreePredicateFn class
that handles all of the decoding of these things. This is an internal
cleanup that has no impact on the code generated by tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129670 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 30deafc84adf88f643cdc39dc97a37537155347f |
16-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Put each personality function in a section. This fixes the gnu ld warning:
error in foo.o; no .eh_frame_hdr table will be created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129635 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| b6a638898a92d5cd782209fbeb673fe7846a29eb |
15-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129590 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetLowering.h
|
| eef965f04bab483a7d2fd46a7d51559197eda5cf |
14-Apr-2011 |
Bill Wendling <isanbard@gmail.com> |
Add an option to not print the alias of an instruction. It defaults to "print
the alias".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129485 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 87896d9368e08d93493427ce7bf8272d1e5cca35 |
13-Apr-2011 |
Andrew Trick <atrick@apple.com> |
Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
Additional fixes:
Do something reasonable for subtargets with generic
itineraries by handle node latency the same as for an empty
itinerary. Now nodes default to unit latency unless an itinerary
explicitly specifies a zero cycle stage or it is a TokenFactor chain.
Original fixes:
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make the ndoe latency adjustments work, I also
needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129421 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 4da0c7c0c9081107bea5f6bac440f0f1eb47748f |
08-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 2c69f8eec6a51114799e3e80fa4903c5e3fc429c |
07-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change -arm-divmod-libcall to a target neutral option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| ed3caf90866e183380a06c0ae49101204a9f3c28 |
02-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add a RemoveFromWorklist method to DCI. This is needed to do some complicated
transformations in target-specific DAG combines without causing DAGCombiner to
delete the same node twice. If you know of a better way to avoid this (see my
next patch for an example), please let me know.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128758 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a7b8c2b6a416052bd7b48d3c0d702d266c6ac3a2 |
29-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
Integrated-As: Add support for setting the AllowTemporaryLabels flag via
integrated-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128431 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 0891d99b8758feaf3107b9a6333f1baa9450c799 |
21-Mar-2011 |
Eric Christopher <echristo@apple.com> |
Fix unused param warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128005 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| a5c177e70a42f48e4885075c4c48aad0816a2817 |
21-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
We need to pass the TargetMachine object to the InstPrinter if we are printing
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.
This is part of a work-in-progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127986 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 485fafc8406db8552ba5e3ff871a6ee32694ad90 |
21-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply r127953 with fixes: eliminate empty return block if it has no predecessors; update dominator tree if cfg is modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127981 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7a90e04fc76392972bd8bd0ddee5c934c22c1393 |
19-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessors
to canonicalize IR", it broke a lot of things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127954 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ae16d6b9722dd6ff4a606308e3a14d200f3a903f |
19-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IR
to have single return block (at least getting there) for optimizations. This
is general goodness but it would prevent some tailcall optimizations.
One specific case is code like this:
int f1(void);
int f2(void);
int f3(void);
int f4(void);
int f5(void);
int f6(void);
int foo(int x) {
switch(x) {
case 1: return f1();
case 2: return f2();
case 3: return f3();
case 4: return f4();
case 5: return f5();
case 6: return f6();
}
}
=>
LBB0_2: ## %sw.bb
callq _f1
popq %rbp
ret
LBB0_3: ## %sw.bb1
callq _f2
popq %rbp
ret
LBB0_4: ## %sw.bb3
callq _f3
popq %rbp
ret
This patch teaches codegenprep to duplicate returns when the return value
is a phi and where the phi operands are produced by tail calls followed by
an unconditional branch:
sw.bb7: ; preds = %entry
%call8 = tail call i32 @f5() nounwind
br label %return
sw.bb9: ; preds = %entry
%call10 = tail call i32 @f6() nounwind
br label %return
return:
%retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ]
ret i32 %retval.0
This allows codegen to generate better code like this:
LBB0_2: ## %sw.bb
jmp _f1 ## TAILCALL
LBB0_3: ## %sw.bb1
jmp _f2 ## TAILCALL
LBB0_4: ## %sw.bb3
jmp _f3 ## TAILCALL
rdar://9147433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127953 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 31649e61bcead26a63c7cd452da90fff5e000b91 |
18-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Beginnings of MC-JIT code generation.
Proof-of-concept code that code-gens a module to an in-memory MachO object.
This will be hooked up to a run-time dynamic linker library (see: llvm-rtdyld
for similarly conceptual work for that part) which will take the compiled
object and link it together with the rest of the system, providing back to the
JIT a table of available symbols which will be used to respond to the
getPointerTo*() queries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127916 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 7bbf0ee97c77f7712154648a44ac6eeb57886462 |
17-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move more logic into getTypeForExtArgOrReturn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127809 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 44579680111b807613703ab401db3b8c0148e36c |
17-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127807 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ebe8173941238cfbabadb1c63bca7fb7dcf2adbe |
16-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byte
rather than an int. Thankfully, this only causes LLVM to miss optimizations, not
generate incorrect code.
This just fixes the zext at the return. We still insert an i32 ZextAssert when
reading a function's arguments, but it is followed by a truncate and another i8
ZextAssert so it is not optimized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127766 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 82bae7dafcada8c30df26befc724f625198666c0 |
16-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add TargetData::fitsInLegalInteger().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127714 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 0f040a258ff6a2372fc232212b5e4189e8e7185d |
15-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Add "Bitcast" target instruction property for instructions which perform
nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127667 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| b0519e15f70cef7ba16b712f258d4782ade17e13 |
10-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit 127368 and 127371. They are exonerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127380 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 02d7c9298298f7f8fba1427f249deb2106126e9c |
10-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert 127368 and 127371 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127376 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 0f24d49acae52fc66f72136bbe4891a9a8c9cd36 |
10-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Restore the default implementation of getCrossCopyRegClass: no need for cross-regclass copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127371 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 17adafc6c179f3bad757f932a13522851ee5171f |
09-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more
flexible.
If it returns a register class that's different from the input, then that's the
register class used for cross-register class copies.
If it returns a register class that's the same as the input, then no cross-
register class copies are needed (normal copies would do).
If it returns null, then it's not at all possible to copy registers of the
specified register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127368 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| d1cba8727a1ee713030d9e6bbd72523a9f9e2a60 |
09-Mar-2011 |
Jan Sjödin <jan_sjodin@yahoo.com> |
Add createELFObjectTargetWriter method to TargetAsmBackend, which enables construction of non-standard ELFObjectWriters that can be used in MCJIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127346 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| dd54ffda263a17bddb0ad04a670916125972929a |
09-Mar-2011 |
Jan Sjödin <jan_sjodin@yahoo.com> |
Add InitializeNativeAsmParser function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127341 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| be2119e8e2bc7006cfd638a24367acbfda625d16 |
07-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetRegisterInfo.h
|
| ece96f5713e14b705d415eb95fe57c5fff841626 |
05-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Missing "virtual" keyword. Jakob's review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127070 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| e0ef509aeb47b396cf1bdc170ca4f468f799719f |
05-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Increased the register pressure limit on x86_64 from 8 to 12
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.
Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.
Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 0f657b156f3d0890584bedda7294932a20b2ea16 |
03-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Allow a target to choose whether to prefer the scavenger emergency spill slot
be next to the frame pointer or the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126956 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 022708f221e2a9ea1a42c07c7cd7817a8de881dc |
03-Mar-2011 |
Richard Osborne <richard@xmos.com> |
Optimize fprintf -> iprintf if there are no floating point arguments
and siprintf is available on the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126940 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 419454ad3720b8cf4613d9e790669c8beaccd1a4 |
03-Mar-2011 |
Richard Osborne <richard@xmos.com> |
Optimize sprintf -> siprintf if there are no floating point arguments
and siprintf is available on the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126937 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 3649824bec09768cbdee7aa7cfbbcdd865373626 |
03-Mar-2011 |
Richard Osborne <richard@xmos.com> |
Optimize printf -> iprintf if there are no floating point arguments
and iprintf is available on the target. Currently iprintf is only
marked as being available on the XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126935 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 5bff585ef70e70e66a9da0c3a59d6f97ac3ec06c |
28-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Fix warning when building with clang++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126679 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f222e595c0137b8a9571408257f7000c2fb95473 |
28-Feb-2011 |
Stuart Hastings <stuart@apple.com> |
Support for byval parameters on ARM. Will be enabled by a forthcoming
patch to the front-end. Radar 7662569.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126655 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 95771afbfd604ad003fa3723cac66c9370fed55d |
25-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f7e9ad7172f3e4a0531e39c31f691542d228161b |
24-Feb-2011 |
Duncan Sands <baldrick@free.fr> |
Rewrite the vector part of getExtendedTypeAction to make it more
understandable (at least I find it easier to understand like this).
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126382 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 188a7e00e784f78d6b5b250a64ac5c374f0fd3f0 |
18-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
add a way to disable all builtins, wire it up to opt's -disable-simplifylibcalls flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125978 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| 398c0d8b7417dedbe244020ffb67abb54aaa1c59 |
18-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
add memset and memcpy, though they are always available for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125973 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| d8c87888a71c4433d76b48bca6c3e03a17890648 |
18-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fixed-length instruction encodings.
A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks
provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen
like the existing disassembly emitters do.
The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove
some of the hacks the old one introduced to tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125966 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| ce99120084f549a523213064648662a704e8b789 |
18-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
introduce a new TargetLibraryInfo pass, which transformations can use to
query about available library functions. For now this just has
memset_pattern16, which exists on darwin, but it can be extended for a
bunch of other things in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125965 91177308-0d34-0410-b5e6-96231b3b80d8
argetLibraryInfo.h
|
| ef1860a117b4a35918eb9793a7b94715e12a3a42 |
11-Feb-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove std::string version of getNameWithPrefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125363 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| e02db88816185c5a4cff8c08c34a6e055d2b824a |
10-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Clean trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125304 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| e7a54520b3435c006c4f97c56fe970350981ea3c |
07-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Implement support for custom target specific asm parsing of operands.
Motivation: Improve the parsing of not usual (different from registers or
immediates) operand forms.
This commit implements only the generic support. The ARM specific modifications
will come next.
A table like the one below is autogenerated for every instruction
containing a 'ParserMethod' in its AsmOperandClass
static const OperandMatchEntry OperandMatchTable[20] = {
/* Mnemonic, Operand List Mask, Operand Class, Features */
{ "cdp", 29 /* 0, 2, 3, 4 */, MCK_Coproc, Feature_IsThumb|Feature_HasV6 },
{ "cdp", 58 /* 1, 3, 4, 5 */, MCK_Coproc, Feature_IsARM },
A matcher function very similar (but lot more naive) to
MatchInstructionImpl scans the table. After the mnemonic match, the
features are checked and if the "to be parsed" operand index is
present in the mask, there's a real match. Then, a switch like the one
below dispatch the parsing to the custom method provided in
'ParseMethod':
case MCK_Coproc:
return TryParseCoprocessorOperandName(Operands);
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125030 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| cf12067ae08dc7911c860070eaf2830dc1dc4ff7 |
04-Feb-2011 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmMatcher: Add support for custom conversion functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124870 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 31959b19a72608051888160514977875a8027dfc |
02-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Given a pair of floating point load and store, if there are no other uses of
the load, then it may be legal to transform the load and store to integer
load and store of the same width.
This is done if the target specified the transformation as profitable. e.g.
On arm, this can transform:
vldr.32 s0, []
vstr.32 s0, []
to
ldr r12, []
str r12, []
rdar://8944252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124708 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 63f8659d6936077c5e8e34eecb55ff1de0db5686 |
02-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Fix comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124705 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| bf7553210ae44f05e7460edeae1ee499d8a22dcb |
27-Jan-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Introduce virtual ParseRegister method in TargetAsmParser.
Create override of this method in X86/ARM/MBlaze.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124378 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| cfe33c46aa50f04adb0431243e7d25f79b719ac6 |
26-Jan-2011 |
David Greene <greened@obbligato.org> |
[AVX] Add INSERT_SUBVECTOR and support it on x86. This provides a
default implementation for x86, going through the stack in a similr
fashion to how the codegen implements BUILD_VECTOR. Eventually this
will get matched to VINSERTF128 if AVX is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 91585098eff1f0acdefa2667e091742b60dcbf15 |
26-Jan-2011 |
David Greene <greened@obbligato.org> |
[AVX] Support EXTRACT_SUBVECTOR on x86. This provides a default
implementation of EXTRACT_SUBVECTOR for x86, going through the stack
in a similr fashion to how the codegen implements BUILD_VECTOR.
Eventually this will get matched to VEXTRACTF128 if AVX is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124292 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| e13359732addeaa2682aaf96e293d6d8c4f8b36c |
25-Jan-2011 |
David Greene <greened@obbligato.org> |
[AVX] Fix a typo in the extract subvector type constraints to specify
the correct number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124234 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| b5b80a93f611ee63788b10d89989b3644642cba5 |
25-Jan-2011 |
David Greene <greened@obbligato.org> |
[AVX] Add TableGen classes for vector/subvector type constraints.
This will be used to check patterns referencing a forthcoming
INSERT_SUBVECTOR SDNode and will also be used to check
EXTRACT_SUBVECTOR nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124191 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 96aa78c8c5ef1a5f268539c9edc86569b436d573 |
23-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for the --noexecstack option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetRegistry.h
|
| 0cf5e3d51dd455a174a8f00cfa6b63c11e535434 |
23-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Delay the creation of eh_frame so that the user can change the defaults.
Add support for SHT_X86_64_UNWIND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124059 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4 |
21-Jan-2011 |
Andrew Trick <atrick@apple.com> |
Convert -enable-sched-cycles and -enable-sched-hazard to -disable
flags. They are still not enable in this revision.
Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.
Generalized unit tests to work with sched-cycles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 9fe2009956fc40f3aea46fb3c38dcfb61c4aca46 |
20-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.
Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.
ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
to re-materialize the instruction, allow machine LICM to hoist the set of
instructions out of the loop and make it possible to CSE them. It's a bit
hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.
With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| bdf466c27de213d5d1b8115ce8fd4973e3061e61 |
15-Jan-2011 |
Chris Lattner <sabre@nondot.org> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123519 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 16c29b5f285f375be53dabaa73e3e91107485fe4 |
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetFrameInfo.h
argetFrameLowering.h
argetMachine.h
|
| b79cb79a46fd4d870897f5e2fd0c50beb96dc30a |
10-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove TargetRegisterInfo::NoRegister.
Fix the TargetRegisterInfo::NoRegister places where someone preferred
typing 'TargetRegisterInfo::NoRegister' instead of typing '0'.
Note that TableGen is already emitting xx::NoRegister in xxGenRegisterNames.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123140 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| da1f1f495066f95957fd1c19ad44d4453e47aff4 |
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Change virtual register numbering to make more space for physical registers.
The numbering plan is now:
0 NoRegister.
[1;2^30) Physical registers.
[2^30;2^31) Stack slots.
[2^31;2^32) Virtual registers. (With -1u and -2u used by DenseMapInfo.)
Each segment is filled from the left, so any mistaken interpretation should
quickly cause crashes.
FirstVirtualRegister has been removed. TargetRegisterInfo provides predicates
conversion functions that should be used instead of interpreting register
numbers manually.
It is now legal to pass NoRegister to isPhysicalRegister() and
isVirtualRegister(). The result is false in both cases.
It is quite rare to represent stack slots in this way, so isPhysicalRegister()
and isVirtualRegister() require that isStackSlot() be checked first if it can
possibly return true. This allows a very fast implementation of the common
predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123137 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| be97e906e03dd9b22e14f6749157c9d5f9701dd5 |
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual and
physical register numbers.
This makes the hack used in LiveInterval official, and lets LiveInterval be
oblivious of stack slots.
The isPhysicalRegister() and isVirtualRegister() predicates don't know about
this, so when a variable may contain a stack slot, isStackSlot() should always
be tested first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123128 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 43a566519b85ddffa482695d6a5a3dc4a02e267f |
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123125 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 4314268128be6d54c9a7f0709680e5a5b40f3ab3 |
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance.
Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123107 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| c7d67f90d36375f1ff512a3857c887b7e4246adb |
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix VirtRegMap to use TRI::index2VirtReg and TRI::virtReg2Index instead of
depending on TRI::FirstVirtualRegister.
Also use TRI::printReg instead of printing virtual registers directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123101 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| b421c566f512ed0ec87851866d335e9086c3f8be |
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use an IndexedMap for LiveVariables::VirtRegInfo.
Provide MRI::getNumVirtRegs() and TRI::index2VirtReg() functions to allow
iteration over virtual registers without depending on the representation of
virtual register numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123098 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| c36b7069b42bece963b7e6adf020353ce990ef76 |
08-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.
This allows memory instructions to be moved around INLINEASM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 30a343aeedf777f9b8b6be9823da750afbf765b1 |
07-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
DBG_VALUE does not have any side effects; it also makes no sense to mark it cheap as a copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123031 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 5e8b833707e6d59576d91b23a2c24e596eace60e |
07-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
Add ARM patterns to match EXTRACT_SUBVECTOR nodes.
Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle
vectors from being translated to EXTRACT_SUBVECTOR.
Patch by Tim Northover.
The test changes are needed to keep those spill-q tests from testing aligned
spills and restores. If the only aligned stack objects are spill slots, we
no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR
was legalized by loading from the stack, which created an aligned frame index.
Now, however, there is nothing except the spill slot in the stack frame, so
I added an aligned alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122995 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 0521928ae7cc492f3f45ef0e0cedc349102489c5 |
06-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy
etc. takes an option OptSize. If OptSize is true, it would return
the inline limit for functions with attribute OptSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122952 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2da8bc8a5f7705ac131184cd247f48500da0d74e |
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetInstrItineraries.h
|
| 6e8f4c404825b79f9b9176483653f1aa927dfbde |
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetInstrItineraries.h
|
| 036609bd7d42ed1f57865969e059eb7d1eb6c392 |
23-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
Flag -> Glue, the ongoing saga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 1ec5bd31fe491e610839ea448bd99fd171785837 |
18-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the MCObjectFormat class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122147 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 976ef86689ed065361a748f81c44ca3510af2202 |
18-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
During local stack slot allocation, the materializeFrameBaseRegister function
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.
Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)
<rdar://problem/8782198>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 7b62afac0a6f967e7466e60ceb26bfdcff2e59f4 |
17-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Target: Remove HasScatteredSymbols target hook variable, which has been
superceded and was effectively dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122024 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 2761fc427082215c2affcc9d8db8491400bc9e5d |
16-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Move target specific fixup info descriptors to TargetAsmBackend instead of
the MCCodeEmitter, which seems like a better organization.
- Also, cleaned up some magic constants while in the area.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121953 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 745dacc91d7ee9531bfba76b21beb5d4eef93a7d |
16-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Make TargetAsmBackend available to the AsmStreamer.
- Treaty talks on the non-proliferation of MC objects broke down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121949 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| b83ff84193d44bb9aa75e1264ffaff55f468a303 |
15-Dec-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of all
registers that alias Reg, including itself. This is almost the same as the
existing getAliasSet() method, except for the inclusion of Reg.
The name matches the reflexive TRI::regsOverlap(x, y) relation.
It is very common to do stuff to a register and all its aliases:
stuff(Reg)
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
stuff(*Alias);
That can now be written as the simpler:
for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias)
stuff(*Alias);
This change requires a bit more constant space for the alias lists because Reg
is included and because the empty alias list cannot be shared any longer.
If the getAliasSet method is eventually removed, this space can be reclaimed by
sharing overlap lists. For instance, %rax and %eax have identical overlap sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121800 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 414e5023f8f8b22486313e2867fdb39c7c4f564b |
14-Dec-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterInfo::printReg() to pretty-print registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121780 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 89b9372605db2ce3b0085c84089e389f7bc1fbdd |
10-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fixed version of 121434 with no new memory leaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121471 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
argetAsmInfo.h
argetRegistry.h
|
| f7fd4aa2610f46467369de07f3ec669561d79be0 |
10-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert my previous patch to make the valgrind bots happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121461 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
argetAsmInfo.h
argetRegistry.h
|
| 1c952b9cc98e84b28f68f0f6cf11197263f89863 |
10-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Initial support for the cfi directives. This is just enough to get
f:
.cfi_startproc
nop
.cfi_endproc
assembled (on ELF).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121434 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
argetAsmInfo.h
argetRegistry.h
|
| 5be6d2af38c29e3653998978345220974cc40c01 |
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Let target asm backends see assembler flags as they go by. Use that to handle
thumb vs. arm mode differences in WriteNopData().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121219 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 179821ac1f282ef6f8d24d5ea346028aee8ba4c7 |
06-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the instruction fragment to data fragment lowering since it was causing
freed data to be read. I will open a bug to track it being reenabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121028 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 3d2125c9dbac695c93f42c0f59fd040e413fd711 |
01-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable sibling call optimization of libcalls which are expanded during
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120501 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| de189be53f5831737f38e720f10dbcdcce6876c6 |
30-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add TLI support indicating that jumps are more expensive than logical operations
and use this to disable a specific optimization. Patch by Micah Villmow!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120435 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1f6efa3996dd1929fbc129203ce5009b620e6969 |
29-Nov-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Merge System into Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120298 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
argetAsmBackend.h
argetData.h
argetInstrDesc.h
argetJITInfo.h
|
| 94c5ae08750f314bc3cf1bf882b686244a3927d9 |
28-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move more PEI-related hooks to TFI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
argetRegisterInfo.h
|
| cd775ceff0b25a0b026f643a7990c2924bd310a3 |
28-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move callee-saved regs spills / reloads to TFI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
argetInstrInfo.h
|
| fd46797d0da4970a40f8b5648b8f9b186ce5adb9 |
26-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the unused TheTarget member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120168 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| bf17cfa3f904e488e898ac2e3af706fd1a892f08 |
23-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 82f58740c76b42af8370247b23677a0318f6dde8 |
20-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move some more hooks to TargetFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119904 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
argetRegisterInfo.h
|
| 76eb5f2401125c358eaf5e97a223a78ad4cc99e9 |
19-Nov-2010 |
Dale Johannesen <dalej@apple.com> |
Prefetch has a MemOperand now. FileCheckize a test.
This finishes up 8460971.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119848 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 195a0ce484cd12a5adae9184188f6d0fb52b84c0 |
19-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Change some methods in MCDwarf.cpp to be able to handle an arbitrary
MCStreamer instead of just MCObjectStreamer. Address changes cannot
be as efficient as we have to use DW_LNE_set_addres, but at least
most of the logic is shared.
This will be used so that, with CodeGen still using EmitDwarfLocDirective,
llvm-gcc is able to produce debug_line sections without needing an
assembler that supports .loc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119777 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| d9e3385ced2dc887e2fe8e1c071bd2611e4d3ede |
19-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move getInitialFrameState() to TargetFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119754 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
argetRegisterInfo.h
|
| d0c38176690e9602a93a20a43f1bd084564a8116 |
18-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move hasFP() and few related hooks to TargetFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
argetRegisterInfo.h
|
| c4af4638dfdab0dc3b6257276cfad2ee45053060 |
17-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
argetInstrInfo.h
|
| f2dc4aa562e2478a73fe5aeeeec16b1e496a0642 |
17-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
make isVirtualSection a virtual method on MCSection. Chris' suggestion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119547 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| eb96a2f6c03c0ec97c56a3493ac38024afacc774 |
15-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up. The peephole pass should be the one updating the instruction
iterator, not TII->OptimizeCompareInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119186 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 2ac190238e88b21e716e2853900b5076c9013410 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add fields to the .td files unconditionally, simplifying tblgen a bit.
Switch the ARM backend to use 'let' instead of 'set' with this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 33464912237efaa0ed7060829e66b59055bdd48b |
15-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
argetRegisterInfo.h
|
| 6da24ca51d0a0483b4ff1537a177bd172997f129 |
08-Nov-2010 |
Che-Liang Chiou <clchiou@gmail.com> |
Add registry hook for assembly text output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118394 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| f788854d20b12c60fd8b43c587adb3227b6b1bff |
06-Nov-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Prune includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118342 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 662e5a30e864e71111b885d3da3cdd184772035d |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Reimplement BuildResultOperands to be in terms of the result instruction's
operand list instead of the operand list redundantly declared on the alias
or instruction.
With this change, we finally remove the ins/outs list on the alias. Before:
def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
def : InstAlias<"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118329 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| cdfad36b401be6fc709ea4051f9de58e1a30bcc9 |
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Simplify uses of MVT and EVT. An MVT can be compared directly
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetRegisterInfo.h
|
| 1440e8b918d7116c3587cb95f4f7ac7a0a0b65ad |
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Inside the calling convention logic LocVT is always a simple
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.h
|
| dfed19fe2c34c1209108afa58e8ab014ffd894e2 |
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 8239daf7c83a65a189c352cce3191cdc3bbfe151 |
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Two sets of changes. Sorry they are intermingled.
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 9a376a8003c486054ea4d7c2465cb90b501c9893 |
02-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Tweak to fix spelling and grammar in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117985 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| f78081145695baa5d0b004e674c4561245b13b52 |
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the old InstFormatName which is always "AsmString",
simplify CodeGenInstruction. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117891 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| a33b93f7f162fe85dfe4fc1f16e1afb254393ab9 |
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
sketch out the planned instruction alias mechanism, add some comments about
how the push/pop mnemonic aliases are wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117857 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 0f899c78e18e39a8ccd08386aaa493a1b9a712a3 |
30-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
Resolve a terrible hack in tblgen: instead of hardcoding
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117831 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 693173feefaa326fad0e386470846fb3199ba381 |
30-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
Implement (and document!) support for MnemonicAlias's to have Requires
directives, allowing things like this:
def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
Move the rest of the X86 MnemonicAliases over to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117830 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 674c1dcca21f5edf9f7380902971fc5471c0bd4a |
30-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
implement (and document!) the first kind of MC assembler alias, which
just remaps one mnemonic to another. Convert a few of the X86 aliases
from .cpp to .td code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117815 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| cf000c130ffc49ee2c2f82bc0187dafb73acae73 |
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117784 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 47245422a45e1a2e89f402e745c6fbfa63d25c6e |
30-Oct-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Mult-alt constraint incremental development step 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117746 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 44ab89eb376af838d1123293a79975aede501464 |
29-Oct-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0ae |
26-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use instruction itinerary to determine what instructions are 'cheap'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| e93d99cf0742eebab859022e4cfdcf03cb9d5dfa |
20-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Remove Synthesizable from the Type system; as MMX vector
types are no longer Legal on X86, we don't need it.
No functional change. 8499854.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116947 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2312842de0c641107dd04d7e056d02491cc781ca |
19-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-enable register pressure aware machine licm with fixes. Hoist() may have
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 98694138025fdb0cec0cda5727201ad00ded3d63 |
19-Oct-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r116781 "- Add a hook for target to determine whether an instruction def
is", which breaks some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 11e8b74a7ae9ecd59b64180a59143e39bc3b9514 |
19-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add a hook for target to determine whether an instruction def is
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b41ee96d76ccf1eec2fd898def4cfd7c16868708 |
18-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Don't recompute MachineRegisterInfo in the Optimize* method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116750 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| f230df9af4012f9510de664b6d62b128e26a5861 |
16-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCObjectFormat class so that code common to all targets that use a
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116675 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| e70c526d59e92048c89281d1b7011af0b1d9ee95 |
16-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Whitespace!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116664 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| cbc549e81cc7ecde8f5e2beb5030aa50fe9c9115 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116557 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 82df5096eabeef337d691f97974ba32631106088 |
07-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
add a common SDPatternOperator base class to SDNode and PatFrag for
stuff that wants to take one or the other. These can both be used
as the operation of a dag in a pattern match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115877 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| a0792de66c8364d47b0a688c7f408efb7b10f31b |
06-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 0febc4657b0edbf16b55ca5365d2b6aab45be7c5 |
03-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
so and also change X86 for consistency.
Investigating if this can be improved a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| e3cc84a43d6a4bb6c50f58f3dd8e60e28787509e |
02-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115364 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| a56927e3ffed66007b4f9d095ff4425425452a15 |
01-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Comments about operand cycles and pipeline forwarding pathes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115214 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| 8ebf66236e1a0a3f6796abcbf6be83eb6a55e3fa |
30-Sep-2010 |
Kevin Enderby <enderby@apple.com> |
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
for the dwarf .loc support to emit dwarf line number tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115153 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| ca96a861655d3fcfc5ff047e249703930c8330bc |
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Let a target specify whether it wants an assembly printer to be the MC version
or not. TableGen needs to generate the printInstruction() function as taking
an MCInstr* or a MachineInstr*, depending. Default to the old non-MC
version so that everything not yet using MC continues to just work without
fidding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115126 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 3881cb7a5d54c0011b40997adcd742e1c7b91abd |
30-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
pipeline forwarding path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 7c51a3172cf5104ebeaef22f1366fa634ca00d85 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement rdar://8456378 and PR7557 - support for the fstsw,
an instruction that requires a WHOLE NEW wonderful kind of alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115015 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| 7036f8be4df8a1a830ca01afe9497b035a5647d6 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
change the protocol TargetAsmPArser::MatchInstruction method to take an
MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115014 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| 63d66eed16a6ee4e838f2f7a4c8299def0722c20 |
29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add support to model pipeline bypass / forwarding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| b20b85168c0e9819e6545f08281e9b83c82108f0 |
28-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114973 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8048ebe91d76f5ee58f5c2c7535151d782af4b29 |
27-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
the latest assembler that runs on powerpc 10.4 machines doesn't
support aligned comm. Detect when compiling for 10.4 and don't
emit an alignment for comm. THis will hopefully fix PR8198.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114817 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
argetMachine.h
|
| f523e476c2e199220306b367b7bd834978fb93d6 |
24-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| 5716180b1a863d345127fa8f9dfe0a931ab7370c |
24-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Add an TargetInstrDesc bit to indicate that a given instruction is a conditional move.
Not intended functionality change, as nothing uses this yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114702 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| 52a261b3c1391c5fec399ddeb3fc6ee9541e8790 |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 04ac81d5db058a3a9492e1aff1f398a8643bfda9 |
21-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
Move the search for the appropriate AND instruction
into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| e72f2027e9116c55a5b39ac72732df8d6c45d37c |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAGInfo.h
|
| 064312de8641043b084603aa9a6b409bc794eed2 |
15-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Spelling fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113978 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 12ea76563276b656b4bcf7ff38a404c10b0a675f |
13-Sep-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix linux/msvc build, move include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113776 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| eac6e1d0c748afc3d1496be0753ffbe5f5a4279b |
13-Sep-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Added skeleton for inline asm multiple alternative constraint support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113766 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a65568676d0d9d53dd4aae8f1c58271bb4cfff10 |
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename ConvertToSetZeroFlag to something more general.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113670 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 3665661a5708c8adc2727be38b56d1d87ddeb661 |
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
No need to recompute the SrcReg and CmpValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113666 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 92ad57f066e9f256e4e3d72febf152e68caa80c7 |
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Move some of the decision logic for converting an instruction into one that sets
the 'zero' bit down into the back-end. There are other cases where this logic
isn't sufficient, so they should be handled separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113665 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 220e240bdf3235252c2a1fc8fcc5d4b8e8117918 |
10-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Modify the comparison optimizations in the peephole optimizer to update the
iterator when an optimization took place. This allows us to do more insane
things with the code than just remove an instruction or two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113640 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| cc38399ea9aceb459a8d7e4bbc6deba9125ea869 |
10-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
add a comment explicitly calling out that allocation orders may include
reserved regs and that register allocators need to explicitly check for
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113593 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetInstrItineraries.h
argetMachine.h
|
| 5f54ce347368105260be2cec497b6a4199dc5789 |
09-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
For each instruction itinerary class, specify the number of micro-ops each
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetInstrItineraries.h
argetSchedule.td
|
| 2429e2ac23cc1a5cb8154ed4fc44a16e725aa252 |
04-Sep-2010 |
Eric Christopher <echristo@apple.com> |
Reapply this increase to the number of virtual registers. All of the
various breakages appear to be dealt with.
Patch by Pekka Jääskeläinen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113024 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 753f3265dafdcfeec07b561ca278524c35477583 |
30-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Fix LLVM target initialization to deal with sociopathic outside projects
that like to randomly define things like "X86", regenerate autoconf bits
and update cmake.
Fixes PR7852.
Patch by Xerxes Rånby!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112499 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| b5b21e5672bde8dd3fd05c56f5aac3817575fe40 |
27-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Fix a couple of typos.
Patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112297 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.td
|
| fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341a |
27-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
to try to re-use scavenged frame index reference registers. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 1ab3f16f06698596716593a30545799688acccd7 |
26-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
tidy up a bit. no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112228 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| cd11e9db35cf4817869ea46ba736f133a9700b28 |
26-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
add a specialization for the MVT form of getTypeAction, since it is
trivial.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112105 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| aafe626c7fa9f99150cccd27d0151a2cf7c8c00b |
26-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
remove some llvmcontext arguments that are now dead post-refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112104 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e6f7c267df11a44679c35dec79787fbc276839fb |
26-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
Change handling of illegal vector types to widen when possible instead of
expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This
affects two places in the code: handling cross block values and handling
function return and arguments. Since vectors are already widened by
legalizetypes, this gives us much better code and unblocks x86-64 abi
and SPU abi work.
For example, this (which is a silly example of a cross-block value):
define <4 x float> @test2(<4 x float> %A) nounwind {
%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%C = fadd <2 x float> %B, %B
br label %BB
BB:
%D = fadd <2 x float> %C, %C
%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %E
}
Now compiles into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
addps %xmm0, %xmm0
ret
previously it compiled into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
pshufd $1, %xmm0, %xmm1
## kill: XMM0<def> XMM0<kill> XMM0<def>
insertps $0, %xmm0, %xmm0
insertps $16, %xmm1, %xmm0
addps %xmm0, %xmm0
ret
This implements rdar://8230384
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112101 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3197380143cdc18837722129ac888528b9fbfc2b |
24-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM heuristic for when to allocate a virtual base register for stack
access. rdar://8277890&7352504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111968 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| a273442891ae20fd8192526132e3819ea9e5eda9 |
24-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Move enabling the local stack allocation pass into the target where it belongs.
For now it's still a command line option, but the interface to the generic
code doesn't need to know that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| e2f556933e1a19cddf6d4f370e2770c0f763b025 |
20-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Better handling of offsets on frame index references. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111585 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 638ff6d315be1df432e42f1c2068a2e6b464c4f4 |
19-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Re-re-revert this patch. It seems to be causing performance
and correctness regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111527 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| e81043a7df0c7902758322a3000b7cb2048b71df |
19-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Reapply the virtual register patch from 109102. The places where we were
depending on the number of virtual registers appear to have all been handled
now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111499 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 74d803a58c7935c067397bb19afc05ec464d8159 |
18-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add hook for re-using virtual base registers for local stack slot access.
Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.
ongoing saga of rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111374 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| dc140c6e7b8350ca51aa1d408c10e25a27826e2c |
18-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add materialization of virtual base registers for frame indices allocated into
the local block. Resolve references to those indices to a new base register.
For simplification and testing purposes, a new virtual base register is
allocated for each frame index being resolved. The result is truly horrible,
but correct, code that's good for exercising the new code paths.
Next up is adding thumb1 support, which should be very simple. Following that
will be adding base register re-use and implementing a reasonable ARM
heuristic for when a virtual base register should be generated at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111315 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 8708ead5a46f4ec8f2d5f832be23381924d72b8d |
17-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Add hook to examine an instruction referencing a frame index to determine
whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.
In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.
rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111262 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| f1e29d4c21d15f9e1e3a64f3b92b1aa9908e4f63 |
12-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Push the burdon of emitting diagnostics about unmatched
instructions onto the target specific parser, which can do a better job.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110889 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| 4f98f834593f0a107268d19a557b63f0da33a751 |
12-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl',
target specific parsers can adapt the TargetAsmParser to this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| b68f274b6d63ffcf4391304e7e133b7913f17d96 |
11-Aug-2010 |
Dan Gohman <gohman@apple.com> |
Don't use unsigned char for alignments in TargetData. There aren't
that many of these things, so the memory savings isn't significant,
and there are now situations where there can be alignments greater
than 128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110836 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 9db3ea46cb7bd6bdf108d314daffd0dfd50a73fe |
10-Aug-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement register class inflation.
When splitting a live range, the new registers have fewer uses and the
permissible register class may be less constrained. Recompute the register class
constraint from the uses of new registers created for a split. This may let them
be allocated from a larger set, possibly avoiding a spill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110703 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| c98af3370f899a0d1570b1dff01a2e36632f884f |
08-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the "isCompare" machine instruction attribute instead of calling the
relatively expensive comparison analyzer on each instruction. Also rename the
comparison analyzer method to something more in line with what it actually does.
This pass is will eventually be folded into the Machine CSE pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110539 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| eec5008e77ebfff7fd0723f4a21b88fde5d04b87 |
08-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Fix PR7809 by creating a header for just llvm variables that can be
included in exported interfaces. Update a couple of exported interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110532 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| 73739d0bf19af3944aff6afaea2c4eda61061652 |
08-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Add back in r109901, which adds a Compare flag to the target instructions. It's
useful after all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110531 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| 90c579de5a383cee278acc3f7e7b9d0a656e6a35 |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Reapply r110396, with fixes to appease the Linux buildbot gods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| e6f60645c7aa208e03b3804bcf8489e08dacff0a |
06-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
spelling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110457 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 55e958746901ef8c04f370e746a7538137d0bcf8 |
06-Aug-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix eabi calling convention when a 64 bit value shadows r3.
Without this what was happening was:
* R3 is not marked as "used"
* ARM backend thinks it has to save it to the stack because of vaarg
* Offset computation correctly ignores it
* Offsets are wrong
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110446 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.td
|
| 5b55ff0c1555031c1c85f88d67c3b566750a9319 |
06-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn't
need the Compare flag after all.
--- Reverse-merging r109901 into '.':
U include/llvm/Target/TargetInstrDesc.h
U include/llvm/Target/Target.td
U utils/TableGen/InstrInfoEmitter.cpp
U utils/TableGen/CodeGenInstruction.cpp
U utils/TableGen/CodeGenInstruction.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110424 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| e4ddbdfd3cf031034020671d03626f0373fbd5ca |
06-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Add the Optimize Compares pass (disabled by default).
This pass tries to remove comparison instructions when possible. For instance,
if you have this code:
sub r1, 1
cmp r1, 0
bz L1
and "sub" either sets the same flag as the "cmp" instruction or could be
converted to set the same flag, then we can eliminate the "cmp" instruction all
together. This is a important for ARM where the ALU instructions could set the
CPSR flag, but need a special suffix ('s') to do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110423 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 1f74590e9d1b9cf0f1f81a156efea73f76546e05 |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Revert r110396 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 9ccaf53ada99c63737547c0235baeb8454b04e80 |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 6387176c31d7a294f4a62e11255ded531bacb3e2 |
06-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Revert my last commit, apparently it's a runtime issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110387 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| 436843662d74434e98267edfbded9a3769cc0ea6 |
06-Aug-2010 |
Eric Christopher <echristo@apple.com> |
Remove unnecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110385 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| b1247c313dc319313fffec57e7b68532cb6a2d12 |
03-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
build: Add LLVM_NATIVE_ARCHNAME, which has the sensible value, without "Target"
appended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110109 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| b7a56ad907e036c74ee1cb91769622c2db5c3f96 |
02-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
Targets: Add InitializeNativeTargetAsmPrinter(), patch by Jan Sjodin, although
rewritten by me to not require updating all the target initialization routine
names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109996 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| 1844b1a5a483b8f01f29500a8d0d552447cbb7e5 |
31-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Add a "Compare" flag to the target instruction descriptor. This will be used
later to identify and possibly remove superfluous compare instructions -- those
that are testing for and setting a status flag that should already be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109901 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| c728ad43497935c0ae292ffdb2776b15c7a9a5c5 |
29-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109775 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 1abcd06856df324eac98d4bf5ba673fb77ae6a11 |
29-Jul-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Plug the remaining MC leaks by giving MCObjectStreamer/MCAsmStreamer ownership of the TargetAsmBackend and the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109767 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| cec36f4c1118dc8388910d4753fe7cbf88d2d793 |
24-Jul-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Hook in GlobalMerge pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109359 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8c64b9766e654079339ea7f3a2da152f18d00179 |
24-Jul-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add hook to insert late LLVM=>LLVM passes just before isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109354 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 70017e44cdba1946cc478ce1856a3e855a767e28 |
24-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add an ILP scheduler. This is a register pressure aware scheduler that's
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.
On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 3144687df78731ac4ddbc716a24b951678a73f57 |
24-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Allow target to specify when is register pressure "too high". In most cases,
it's too late to start backing off aggressive latency scheduling when most
of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
For ARM, this is almost always a win on # of instructions. It's runtime
neutral for most of the tests. But for some kernels with high register
pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
54 and sped up by 20%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3012e2213bd29bd9202bf17d4053eae25311ecd7 |
23-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Revert r109102 for now as it's causing JIT miscompilations.
I'll try to track down why a bit later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109223 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| ed2b84087f4ff1df77b73afaf2003c97816fe7ec |
22-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Warnings patrol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109174 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 2062875a7d8f7dd94a20d9e3a298e9e216efb4b5 |
22-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the TargetInstrInfo::GetInstSizeInBytes hook.
ARM/PPC/MSP430-specific code (which are the only targets that
implement the hook) can directly reference their target-specific
instrinfo classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109171 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 134d8eec8789184c7a7290ee101ca3d6f62f384a |
22-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
remove the JIT "NeedsExactSize" feature and supporting logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109167 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 907cd1a569c4b3aa8451ea509f6b1018134884d3 |
22-Jul-2010 |
Duncan Sands <baldrick@free.fr> |
Increase the max physreg size. Patch by Pekka Jääskeläinen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109102 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| c96a82a53415fd0b6cb1bbea2593dc18683c70cc |
22-Jul-2010 |
Reid Kleckner <reid@kleckner.net> |
Initial modifications to MCAssembler and TargetMachine for the MCJIT.
Patch by Olivier Meurant!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109080 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 4f6b4674be5473319ac5e70c76fd5cb964da2128 |
21-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 735317c0e83bd52bd3ab3e6d574a0640f722af47 |
20-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108814 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 72852a8cfb605056d87b644d2e36b1346051413d |
20-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Constify some arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| d70f57b254114841892425a40944268d38ae0bcd |
20-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 46dcb57e18884099ca6ad2aebb81fd7e1513c1f6 |
19-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64.
This property will be used by the register pressure tracking instruction scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108735 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 54074b5f04f5affc77b5c6f3e5d8062b50384831 |
19-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher.
- Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108677 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| d73ada7d24832bc2a4c3965b8f00ffd951341acf |
19-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
Target: Give the TargetAsmParser access to the TargetMachine.
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108664 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 78e6e009223a38739797629ca2d217acf86dda93 |
17-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 7431beaba2a01c3fe299c861b2ec85cbf1dc81c4 |
17-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetOpcodes.h
|
| af462c4b4f59429d993b10607a0c31deb8a8156f |
16-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove remaining calls to TII::isMoveInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108556 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 60108e96bbc5432f4fe06ba313e64448e97a0e15 |
16-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Split -enable-finite-only-fp-math to two options:
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 5a3eb8f0e1141825634be38165e40871ce60b3d5 |
15-Jul-2010 |
Eric Christopher <echristo@apple.com> |
80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108420 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 38e59891ee4417a9be2f8146ce0ba3269e38ac21 |
15-Jul-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Don't pass StringRef by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108366 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| db20d257bcd246f17f250928221bf6449a004f6d |
13-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108272 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 9d544d04166b971ab5ca1ee7ee37465b4af6bbf5 |
12-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix a typo and fit in 80 columns. Found by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108164 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 53131982d6290e3a865f400174778deaac452ff3 |
12-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Add MCAsmParserExtension, a base class for all the target/object specific
classes which want to extend the basic asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108158 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| 7e1b566322ecb5ff752c9a5f2feb503b6fb75262 |
12-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert the last use of getPhysicalRegisterRegClass and remove it.
AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An
instruction might be using a register that can only be replaced with one from
a subclass of getPhysicalRegisterRegClass.
With this patch we use getMinimalPhysRegClass. This is correct, but
conservative. We should check the uses of the register and select the
largest register class that can be used in all of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108122 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 744b3a5acdbd4d0fac9c6a7c9ad702502cc3cc37 |
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove TargetInstrInfo::copyRegToReg entirely.
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetOpcodes.h
|
| d6d7abaf4ebbabb850aa9c20e1617f897608fe62 |
11-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| b0a258be2f154e83ef6ffe5f2437aa648a1279ca |
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove copyRegToReg from TargetInstrInfo so it is not longer accesible.
Use a COPY instruction instead for register copies, or TII::copyPhysReg() after
COPY instructions are lowered.
Targets should implement copyPhysReg instead of copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108075 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| cbeeae23c31d32b833c9c7c3e8984e4cbcf22f45 |
11-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.
The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:
* The 's' in target data: If this is set to the minimal alignment of any
argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
example.
* The getTransientStackAlignment method. It is possible for an architecture to
have argument less aligned than what we maintain the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 84023e0fbefc406a4c611d3d64a10df5d3a97dd7 |
10-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
- Eschew ST0 and ST1 for return values.
- Fix the PIC base register initialization so that it doesn't ever
fail to end up the top of the entry block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1f32340d95ac480bfc74bcfd00fd5cffbe078652 |
09-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Automatically fold COPY instructions into stack load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| e05442d50806e2850eae1571958816028093df85 |
09-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Change TII::foldMemoryOperand API to require the machine instruction to be
inserted in a MBB, and return an already inserted MI.
This target API change is necessary to allow foldMemoryOperand to call
storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot
reference in a target independent way.
The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait
until COPY folding is actually implemented. Most targets only fold copies and
won't need to specialize this hook at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107991 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 02266e29f9250d74c5ec720aff23add3410ae920 |
09-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
--- Reverse-merging r107947 into '.':
U utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-loads.ll
U include/llvm/Target/TargetLowering.h
U include/llvm/Support/PassNameParser.h
U include/llvm/CodeGen/FunctionLoweringInfo.h
U include/llvm/CodeGen/CallingConvLower.h
U include/llvm/CodeGen/FastISel.h
U include/llvm/CodeGen/SelectionDAGISel.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/CallingConvLower.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
U lib/Target/XCore/XCoreISelLowering.cpp
U lib/Target/XCore/XCoreISelLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86ISelLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| bf87e2491789d6ff788629e22e93d0c1ca02ae85 |
09-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 320bdcbfe2691021702085f718db1617b1d4df49 |
08-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement X86InstrInfo::copyPhysReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107898 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 0bc25f40402f48ba42fc45403f635b20d90fabb3 |
08-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 3651d92d91062ea4b1ee8b2a88eca03bd39e1968 |
08-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetInstrInfo::copyPhysReg hook and use it from LowerSubregs.
This target hook is intended to replace copyRegToReg entirely, but for now it
calls copyRegToReg.
Any remaining calls to copyRegToReg wil be replaced by COPY instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107854 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| f59514152511694d46ca8b8d2db466d256ab5759 |
08-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Revert 107840 107839 107813 107804 107800 107797 107791.
Debug info intrinsics win for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f423a69839c4810b890f8a8b09fb8cfbd6bf0139 |
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Add X86FastISel support for return statements. This entails refactoring
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107800 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a4160c3434b08288d1f79f1acbe453d1b9610b22 |
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Simplify FastISel's constructor by giving it a FunctionLoweringInfo
instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107789 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c9403659a98bf6487ab6fbf40b81628b5695c02e |
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.h
argetLowering.h
|
| ce5172098d5eaae22244c925b608fe62a23baaf2 |
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Move ArgFlagsTy, OutputArg, and InputArg out of SelectionDAGNodes.h and
into a new header, TargetCallingConv.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107782 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.h
argetLowering.h
|
| c9af33c6854afe7b082af2d892ec5f05dfa383c7 |
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
SelectBasicBlock doesn't needs its BasicBlock argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107712 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c2af869d629b338861e1c6f0b360a233c0c0f9c4 |
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Make getMinimalPhysRegClass' comment mention what makes it different
from getPhysicalRegisterRegClass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107660 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| f7a0c7bf8bc8318ed28d889c9a56437ab3e91385 |
06-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Fix up -fstack-protector on linux to use the segment
registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107640 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a4e1ba53ddedd08669886b2849926bb33facc198 |
03-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a new target independent COPY instruction and code to lower it.
The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.
COPY is lowered to native register copies by LowerSubregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107529 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetOpcodes.h
|
| 65766ce7df779ac0e7f6ee0171562b56769ae1dd |
02-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Clean up TargetOpcodes.h a bit, and limit the number of places where the full
list of predefined instructions appear. Add some consistency checks.
Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetOpcodes.h
|
| 07d317711781d8c9268f7d6afcf1ba7eadf1d127 |
30-Jun-2010 |
Bill Wendling <isanbard@gmail.com> |
Revert r107205 and r107207.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107215 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| 207855cff9b4811004b9720f28a5bd0adf3784b7 |
29-Jun-2010 |
Bill Wendling <isanbard@gmail.com> |
Introducing the "linker_weak" linkage type. This will be used for Objective-C
metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:
.globl l_objc_msgSend_fixup_alloc
.weak_definition l_objc_msgSend_fixup_alloc
.section __DATA, __objc_msgrefs, coalesced
.align 3
l_objc_msgSend_fixup_alloc:
.quad _objc_msgSend_fixup
.quad L_OBJC_METH_VAR_NAME_1
This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107205 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| d31f972bd33de85071c716f69bf5c6d735f730f2 |
29-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 13151432edace19ee867a93b5c14573df4f75d24 |
26-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change if-conversion block size limit checks to add some flexibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetLowering.h
|
| 1784d160e4efa75782884d451d0788b9457e67dc |
25-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f0e1b8942157f4344cce36e98c7dabb230d52bf8 |
24-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Edit and clarify comments for TargetInstrInfo methods:
None of the existing implementations of commuteInstruction create new
instructions unless the NewMI parameter is true, but the comment had
implied otherwise.
findCommutedOpIndices returns false, not true, when it doesn't know
how to commute the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106761 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 4e39e9da0f3a435445261d0f796bb0913f3c2bf0 |
24-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Reapply r106634, now that the bug it exposed is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| cbe762b5d165c565feb98b745e93b71d208a1e36 |
23-Jun-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106634 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9a526495e0c06c4014d7500788cad1929fd244d3 |
23-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Some targets don't require the fencing MEMBARRIER instructions surrounding
atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106630 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b9cd499dec44397571b682c9de3f132df2721bb5 |
23-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106628 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855 |
22-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Tail merging pass shall not break up IT blocks. rdar://8115404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 1f4a1493fb1f60547f84d2f3454c8ccd02895f83 |
21-Jun-2010 |
Eric Christopher <echristo@apple.com> |
Remove isTwoAddress from llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106470 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92 |
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| a606d955de3b0f777131d74162eb6f11b5f95d75 |
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
argetRegisterInfo.h
|
| 8a7f7426eeb18fef58c3471db23fc829b67bc350 |
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
which is faster, simpler, and less surprising.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3bf912593301152b65accb9d9c37a95172f1df5a |
18-Jun-2010 |
Stuart Hastings <stuart@apple.com> |
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 754f680c1fcde09a3d36bb8562e1433fdb87018e |
14-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix a comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105944 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 5ca96988b01c4c332a7e4a6dba40949c1766465f |
12-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
declare a class with 'class' instead of struct to avoid tag mismatch
warnings, and don't shift by a bool. Patch by Rizky Herucakra!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105886 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 729aab3dd3a6ea5ca23430936270154090fcc10b |
12-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow target to provide its own hazard recognizer to post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105862 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 68fc2daf8fa446be04d2ed2b3cbb1b00c382458f |
09-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| d8ab9b415de10320315644a72ce6c5d3b8f6bc9b |
09-Jun-2010 |
Bill Wendling <isanbard@gmail.com> |
- Fix description of SUBREG_TO_REG. It's not going to generate a zext. But it
is used to assert that an *implicit* zext is performed.
- Fix grammar-o in INSERT_SUBREG. (required reformatting)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105735 91177308-0d34-0410-b5e6-96231b3b80d8
argetOpcodes.h
|
| 99405df044f2c584242e711cc9023ec90356da82 |
09-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| 1087f54ddb70bd2a7ab62608161e4a3f0c345935 |
05-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| 3eca98bb3ab1ec27ab8763298c416d282cdaa261 |
05-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| 9edf7deb37f0f97664f279040fa15d89f32e23d9 |
03-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Slightly change the meaning of the reMaterialize target hook when the original
instruction defines subregisters.
Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.
Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:
%reg1234:foo = FLAP %reg1234<imp-def>
will reMaterialize(%reg3333, bar) like this:
%reg3333:bar-foo = FLAP %reg333:bar<imp-def>
Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 91a74da036d3a9442953ae1de3e797a50da4ccf0 |
02-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename canCombinedSubRegIndex method to something more grammatically correct
and tidy up the comment describing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| ce48c1de828688b34cf5c2038fde23368a0a45f4 |
02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove uses of getCalleeSavedRegClasses from outside the
backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105321 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 2da53370241fdd1b5c291483311b34e609f06c73 |
28-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a TargetRegisterInfo::composeSubRegIndices hook with a default
implementation that is correct for most targets. Tablegen will override where
needed.
Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104985 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| cb8326dc09d900688b2d15bd9c977d1c3b722427 |
26-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Add TargetMachine support for setting the value of MCRelaxAll with
-filetype=obj.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104747 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 95506d40c5bafc72aeebd96dca2b0f92bd0480f1 |
26-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Change RelaxInstruction to only take the input and output instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104713 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 84882528551bd816464a0657ad581c1fed0ac865 |
26-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it
before encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104707 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| ca561ffcf320e9dbfafcac5efcee81471f3259c3 |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| c90e30aa6f3792a460202017523171f435e2ba34 |
26-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Eliminate MCAsmFixup, replace with MCFixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104699 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| b555609e73f5091bf8180c0875fb1fa6c5ad0e7a |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 6a45d681e53a99b4c4f63e0b1664626a596a8151 |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 76f0ad7bf5c05d6056b3bf335d0c3fb7e72de5d6 |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Drop the SuperregHashTable. It is essentially the same as SubregHashTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 1fc8e759a767077726f9be35b93767e68bdf101f |
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Print symbolic SubRegIndex names on machine operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 4fda9670f0a9cd448d1905ab669421316b8864c5 |
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove NumberHack entirely.
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 33276d95ef4191663d8e6b972481f9faf37ce541 |
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch SubRegSet to using symbolic SubRegIndices
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 09bc0298650c76db1a06e20ca84c1dcb34071600 |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetRegisterInfo.h
|
| 73ea7bf4509663267317ec3911aac00ca35a2f2c |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add the SubRegIndex TableGen class.
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 54ddf3d9c756881021afcb869a6ec892a21aef5b |
22-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 2457f2c66184e978d4ed8fa9e2128effff26cb0b |
22-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 46099f14dca0f72c53984f1562c1fc5f5082e748 |
22-May-2010 |
Eric Christopher <echristo@apple.com> |
Add a new section and accessor for TLS data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104411 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| d8a33ddcfeb29e7ec792b14be946a05ab998a38e |
21-May-2010 |
Matt Fleming <matt@console-pimps.org> |
Currently, createMachOStreamer() is invoked directly in llvm-mc which
isn't ideal if we want to be able to use another object file format.
Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104318 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 1cc3984148be113c6e5e470f23c9ddbd37679c5f |
21-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetMachine.h
|
| 4072886a690a853c57c79a87a6423a7bfe0ce61f |
20-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 15a16def6e70c8f7df1023da80ceb89887203b40 |
20-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add a hybrid bottom up scheduler that reduce register usage while avoiding
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 211ffa13519cadfb7f9baf4c8447fa055bf38fe8 |
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetMachine.h
|
| 06b666c7056376b8aaf40be0dc00b97b2cfceb6c |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b990a2f249196ad3e0cc451d40a45fc2f9278eaf |
15-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 0ebf356ddf29a38934ca3f5e49b43e0656de2053 |
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of the bit twiddling to read / set OpActions and ValueTypeActions. The small saving in memory isn't worth the increase in runtime and code complexity in my opinion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103768 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b9c0e332b31c8834ef455dcf5fbd73803720110c |
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate use of magic numbers to access OpActions. It also has the effect of allowing more than 31 scalar value types. MAX_ALLOWED_VALUETYPE had already been updated to 64 a while back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103743 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b21f5a55117b1fb8640aebb431c8d10e1719e509 |
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix up LoadExtActions, TruncStoreActions, and IndexedModeActions representation and setter and getter's so they will continue to work if the number of scalar ValueType's exceeds 31.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103742 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1e5a6c46b8f8cca0e4e6d582289bfd13cb462e39 |
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103733 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a5f1d57f65ae601ec181c0f4e36cf0df5e8d79d8 |
12-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can
be diced into atoms, and adjust getAtom() to take this into account.
- This fixes relocations to symbols in fixed size literal sections, for
example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103532 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 99dca4fde746eb76253e737cca166261c767412d |
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Remove the "WantsWholeFile" concept, as it's no longer needed. CBE
and the others use the regular addPassesToEmitFile hook now, and
llc no longer needs a bunch of redundant code to handle the
whole-file case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103492 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 038df88e28b88dfea7e95d6331ffcdc03e71d8e4 |
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Trim #includes and forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103489 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 17c4a621fe61a70b106548d168271f37fce1e89d |
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103483 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAGInfo.h
|
| ff7a562751604a9fe13efc75bd59622244b54d35 |
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Implement a bunch more TargetSelectionDAGInfo infrastructure.
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetSelectionDAGInfo.h
|
| 419e4f92635cfaa409282691437aff99062e4e0b |
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Remove the TargetLowering::getSubtarget() virtual function, which
was unused. TargetMachine::getSubtarget() is used instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 81043ee5dc4cca470db8d45e080ba0a38efbffc2 |
11-May-2010 |
Bill Wendling <isanbard@gmail.com> |
The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a
string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.
Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103451 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 746ad69e088176819981b4b2c5ac8dcd49f5e60e |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 4f83e73a6d4d96a1a83bfd258b3bf937297c2957 |
04-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Matcher: Add support for over-riding the default MatchInstruction function
name (for example, to allow targets to interpose the actual MatchInstruction
function).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102987 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 57b6e9eb6ccb757b74beeb377c7c16d08468d3e8 |
02-May-2010 |
Duncan Sands <baldrick@free.fr> |
Remove the -enable-sjlj-eh option, which doesn't do anything.
Remove the -enable-eh option which is only used by the JIT,
and replace it with -jit-enable-eh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102865 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| b55c8bed9d0f3eaa454a657746d8ec11aae9dea3 |
01-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add a pseudo instruction REG_SEQUENCE that takes a list of registers and
sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.
This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.
This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.
Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
= use v1024
= use v1028
But this adds pseudo live interval overlap between v1024 and v1025.
We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
= use v1024
= use v1026
After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
= use v1026<3>
= use v1026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetOpcodes.h
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8601a3d4decff0a380e059b037dabf71075497d3 |
29-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| ee9eb411fffddbb8fe70418c05946a131889b487 |
27-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
on darwin empty functions need to codegen into something of non-zero length,
otherwise labels get incorrectly merged. We handled this by emitting a
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This
is more gross than it should be because arm/ppc are not fully mc'ized yet.
This fixes rdar://7908505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102400 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| efc3a6348addd7c9158348fa01f4602e0e0b1688 |
26-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Add PPC AsmPrinter handling for target-specific form of
DBG_VALUE, and a cautionary comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102371 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 962021bc7f6721c20c7dfe8ca809e2d98b1c554a |
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetLowering.h
|
| f822e733aff93b34e6cd85b2f92d86e71fe67f87 |
25-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Stop abusing EmitInstrWithCustomInserter for target-dependent
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets. Add a new hook instead.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f81eca0ab908fdcf98ae0efaa75acccc8ba40dc2 |
22-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
and into SelectionDAGBuilder and FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e566763b1915c7a4821ce95937b763724d271fec |
21-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| f0757b0edc1ef3d1998485d3f74cadaa3f7180a0 |
21-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers on TargetMachine and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101977 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7609017dc3112337c3098e7d04dcd437549f8b14 |
21-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Because of the EMMS problem, right now we have to support
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own. This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e08b320f15b95eb3279fddba6ccb615eafbc4225 |
20-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Document that TargetRegisterInfo::contains does not cover virtual registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101903 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 928eb49cae286c95dceecf4442997dd561c6e3b7 |
18-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetMachine.h
|
| e5b51ac7708402473f0a558f4aac74fab63d4f7e |
17-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
More work to allow dag combiner to promote 16-bit ops to 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| abf0c3475a72d2ecf3c06256254bdb3da0c41225 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add a getSelectionDAGInfo member to TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101567 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 8c0e89925d6b76b7671fe904a97c618d155dea42 |
16-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Create a new TargetSelectionDAGInfo class. This will eventually acquire
SelectionDAG-specific parts of TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101537 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAGInfo.h
|
| 37f32ee7ffe77d7c2bc1b185802e98979612f041 |
16-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101531 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7f506a9c7f8f32ea6429109b2205bebf308257ce |
16-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Fix this code to avoid implicit assumptions about the length of the array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101530 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 64b7bf71e84094193b40ab81aa7dacad921ecbea |
16-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
x86 support is off by default. It can be enabled with -promote-16bit.
Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101448 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 46510a73e977273ec67747eb34cbdb43f815e451 |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2520864773dcb73d76d297605f4bc41c0cf3fa39 |
14-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Factor out EH landing pad code into a separate function, and constify
a bunch of stuff to support it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101273 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 43ac721e3b35341e7cf59d5982ad702ca8d27433 |
13-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
add llvm codegen support for -ffunction-sections and -fdata-sections,
patch by Sylvere Teissier!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101106 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| c3b0c341e731b27b550ee9dcded9c17232b296b8 |
08-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100751 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2dbc8bdfe9191c2078daccbeefba9e69a690feb6 |
08-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100726 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 4b38debf597a22e2db02aafdaa40264d7770c1ad |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove late ARM codegen optimization pass committed by accident.
It is not ready for public yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 9ad709b523b2cde67ffe20625fd5e2da9e9e0225 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100667 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| 391b3431e2a9049fb1a5d51b6cca1c9a86d636c1 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100646 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| 96085a36dbb9cf251c81bc150e41ea9c952c99c0 |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Initial support for different kinds of FU reservation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100645 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
argetSchedule.td
|
| 977dfcefa1b139de56fd17e108b263e39e16504f |
07-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add hook to insert late LLVM=>LLVM passes just before isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100640 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| ed3a8067a60ecf2c215e77327a57904c3ebc3355 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
unthread MMI from FastISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100416 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ea761868b5e4c0166721daf259f86c3816b44f42 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
trim some spurious references to DwarfWriter. SDIsel really doesn't
need it anymore, so don't addRequire it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100400 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| fddb7667ca4d8fe83f96b388295849281ddaa5b4 |
05-Apr-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| d850ac79b57e6e0bf68ee93a94d0b3dcd9f6ca35 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fastisel doesn't need DwarfWriter, remove some tendricles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100381 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b23569aff0a6d2b231cb93cc4acd0ac060ba560f |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
Momentous day: remove the "O" member from AsmPrinter. Now all
"asm printering" happens through MCStreamer. This also
Streamerizes PIC16 debug info, which escaped my attention.
This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100327 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| d374087be5360a353a4239a155b1227057145f48 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fix an ugly wart in the MCInstPrinter api where the
raw_ostream to print an instruction to had to be specified
at MCInstPrinter construction time instead of being able
to pick at each call to printInstruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100307 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 20adc9dc4650313f017b27d9818eb2176238113d |
04-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f28f8bc40eedc6304ab25dd8bed486fa08f51f70 |
02-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Correctly lower memset / memcpy of undef. It should be a nop. PR6767.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100208 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e754d3fb852abdeaf910c7331eed60f6303597c1 |
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Revert r100191 since it breaks objc in clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e33c848fa481b038d5ad0c7c898c33b2b27ec71e |
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 42642d06c915a26af1400de6ce6a53c333e5c247 |
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add comments about DstAlign and SrcAlign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100132 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 94107ba9ceaa199f8e5c03912511b0619c84226d |
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Avoid using floating point stores to implement memset unless the value is zero.
- Do not try to infer GV alignment unless its type is sized. It's not possible to infer alignment if it has opaque type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100118 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 255f20f7f76e4ca1ac1c73294852cb6fcb18c77d |
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix sdisel memcpy, memset, memmove lowering:
1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
ops more effectively.
rdar://7774704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100090 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 100f090adde26005b9f1eca96871dff52825b27b |
31-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 808bab0169ab7d2e8dfdc72dd2c991cd8ff2396d |
30-Mar-2010 |
Mon P Wang <wangmp@apple.com> |
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| caa8870fe09f5526e611434b6bb9f7040c7dfa60 |
28-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
finally remove the immAllOnesV_bc/immAllZerosV_bc patterns
and those derived from them. These are obnoxious because
they were written as: PatLeaf<(bitconvert). Not having an
argument was foiling adding better type checking for operand
count matching up with what was required (in this case,
bitconvert always requires an operand!)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99759 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| e7700999b8d4569db47a02db5afee4b5dad685f1 |
28-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
add some node definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99745 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 310adf1c6f58921b30fde145fd15cb1798050205 |
27-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
remove parallel support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99703 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 1f2ae40efd5167cfe5dde34c310138933307691b |
25-Mar-2010 |
Eric Christopher <echristo@apple.com> |
Fix unused parameter warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99463 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 6a4824c466bbfbcbe7dc4d95ec1e23a14ec73d87 |
25-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Docuemntation corrections from John Myers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99454 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 375cf52638cc5330abf0fe95dfa63a013a97a5f5 |
25-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
add a convenient TargetInstrDesc::getNumImplicitUses/Defs method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99446 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| 0f920e55fcdc5c678a389e2aa4c792be5062c4ea |
24-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Remove the ConvertActions table and associated code, which is unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99372 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| bc7a902713c4e3f13a93c383e647d2a18712f447 |
23-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Revert 99335. getTypeToExpandTo's iterative behavior is actually
needed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99339 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 349074896f17cdebf484f6be97248c6545ecf93b |
23-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Remove getTypeToExpandTo, since it isn't adding much value
beyond just calling getTypeToTransformTo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99335 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 337055e62f28f18a9a8c4a090633cae1c2256ae1 |
23-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99249 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 8f9b80e5df12779a56d763ebf20864dad2bc72da |
23-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99248 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 829680048cdfea7498587a03f815915f1c0e1965 |
23-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Add TargetAsmBackend::RelaxInstruction callback, and custom X86 implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99245 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 5d067fe1580772a8e012ff0acc06e21e9b95d340 |
20-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 1a9158c301b58d8119664f416461d5a5549170c4 |
19-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Add TargetAsmBackend::createObjectWriter.
- MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98955 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| cc5b84c6fba79a798e86ea604e54ca9429273a13 |
19-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Add TargetAsmBackend::isVirtualSection hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98950 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 87190c473c216e481e0a70475577e496b3a3449e |
19-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MCAssembler: Move ApplyFixup to the TargetAsmBackend, this is a target specific not object writer specific task.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98947 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| e8cabf3c2eb835f9189a39c810654d9bd302f7ee |
19-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
add a new SDNPVariadic SDNP node flag, and use it in
dag isel gen instead of instruction properties. This
allows the oh-so-useful behavior of matching a variadic
non-root node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 09a2769a7f709baf2d6fa9204e529b2e18aee4dd |
18-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
use ins/outs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98867 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 8cc9c0c487128c4d675d45803a0711c3e43534af |
18-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmMatcher: Add support for target specific "instruction cleanup" functions,
to allow custom post-processing of matched instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98857 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 0682951b4f569b9a162ddfcffaa90a3ba5adb231 |
18-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Darwin: Add a new target hook for whether the target uses "reliable" symbol differences, basically whether the assembler should attempt to understand atoms when using scattered symbols.
Also, avoid some virtual call overhead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98789 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| f9cf8b35bb525ba68cb8e49bab8a960094e0891a |
17-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove an unnecessary (and misspelled) typedef. Tweak whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98753 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b095ba439ddc9199d2340e55b29a93050fae7639 |
17-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
remove dead variable, patch by Nathan Howell!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98704 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| d6e59084d07500f68548652b8197325809a0c0c2 |
15-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/x86_64: Temporary labels in cstring sections require symbols (and external relocations, but we don't have x86_64 relocations yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98583 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 927411b7ce0b7852fe4f392d8cd4faaa3881f852 |
14-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make default expansion for FP16 <-> FP32 nodes into libcalls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98501 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 11d53c129fc9c2a4510605ec0a1696f58750af52 |
13-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
rearrange MCContext ownership. Before LLVMTargetMachine created it
and passing off ownership to AsmPrinter. Now MachineModuleInfo
creates it and owns it by value. This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code. This also allows MachineFunction to
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98450 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetRegistry.h
|
| b87c305fa77650ee581d4a8c65a0757f88002441 |
12-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
give Mangler access to TargetData.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98378 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| 73ff564d65e9c748562c5734d1f72a2a233f0275 |
12-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
finally give Mangler a getSymbol method, which returns an MCSymbol
for a global instead of messing around with string buffers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98366 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| 5ef31a039dbb9c36cfd78442b3554d1b6974ec4c |
12-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
make the mangler take an MCContext instead of an MAI.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98363 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| f789d26f810243ffd6db79e15a6f10821d785308 |
12-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
make TargetLoweringObjectFile::getExprForDwarfReference
just make unnamed temp symbols instead of having to come
up with its own names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98324 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| 42263e2e407ab7d1d805e7b41cffd7217134d3b6 |
11-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix a fixme in TargetLoweringObjectFile::getExprForDwarfReference
where we used ot create an MCSymbol for ".". Now emit an assembler
temporary label and reference it instead of "." textually.
rdar://7739457
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98292 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
argetLoweringObjectFile.h
|
| a257095ebb29fd223be2fdbf86d542c5bdfe05f0 |
11-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Remove getWidenVectorType, which is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98289 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3192d14076dbe5724ce85b9d48644bb3c081f0e5 |
11-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
rename getSymbolForDwarf* to getExprForDwarf* since it returns
an MCExpr and not an MCSymbol. Change it to take an MCStreamer,
which is currently unused.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98278 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 18e2c021a937f78b8d16619cd377f0c72c542470 |
11-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
Fix (unused) RegisterAsmBackend template, clang++ isn't happy about this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98226 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 1f3e445184e5ca2aa4295c2a77f2a4e0b957fea1 |
11-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Provide MCAssembler with a TargetAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98222 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 23ac7c78e4f009e0baa6d42f4fd0143769fbed4a |
11-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Sketch some TargetAsmBackend hooks we are going to need.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98221 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
|
| 6c27f5e5743481c6a519c60135cf85ac238c150a |
11-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Provide the target triple to AsmBackend constructors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98220 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 09d53fecfcc93377627b6ee7b4d92f8a6ff152e9 |
10-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
move three lowering hooks from MAI to TLOF and make one of them
semantic instead of syntactic. This completes MCization of
darwin/x86[-64]!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98145 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630 |
09-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| acee647b13d6e3e92cdbfe9657622a3daa2a6da1 |
07-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Use Other as a sentinel instead of iAny.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97914 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 506049f29f4f202a8e45feb916cc0264440a7f6d |
03-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97628 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 46ada19645c981a0b7932487d163f7582074a4d9 |
02-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove dead parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97536 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2516d0d7b1062f512bd57d142c966b3ae18ada7c |
01-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Use Doxygen comment syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97451 91177308-0d34-0410-b5e6-96231b3b80d8
argetOpcodes.h
|
| 8772f5041ce8e98695655a72a54b952583630617 |
28-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Add a flag to addPassesToEmit* to disable the Verifier pass run
after LSR, so that clients can opt in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97357 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| bc9d98b52d008d857c7423d7b43fb32022b926a2 |
28-Feb-2010 |
Dan Gohman <gohman@apple.com> |
The mayHaveSideEffects flag is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| bb82b146e9794f4f0ac8fa2e6a02263bc971b0ac |
25-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove a dead PatLeaf, I previously changed all uses to use -1 instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97148 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| aa9d854b334cab2f29ca6d95413a0946b8a38429 |
25-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Revert r97064. Duncan pointed out that bitcasts are defined in
terms of store and load, which means bitcasting between scalar
integer and vector has endian-specific results, which undermines
this whole approach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97137 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| c382bc3c0f476bf94303d9892af4e2cee173bfe5 |
24-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Make getTypeSizeInBits work correctly for array types; it should return
the number of value bits, not the number of bits of allocation for in-memory
storage.
Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and
vectors.
Fix several places in CodeGen which compute offsets into in-memory vectors
to use TargetData information.
This fixes PR1784.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97064 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 4642ad3af1cf508ac320b9afd25b065f08b36574 |
23-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Updated version of r96634 (which was reverted due to failing 176.gcc and
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96822 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| fb76fe09297ee292129e44d723127f2408602a3d |
22-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Fix various doxygen warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96779 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| e7bd886cb8b69b8f787e7aadd097663632153436 |
21-Feb-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Sketch registry support for target specific assembler backends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96762 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmBackend.h
argetRegistry.h
|
| 24b54250728986e87a21d2d65d46c3b87d7a6c5a |
21-Feb-2010 |
Daniel Dunbar <daniel@zuster.org> |
Formatting tweaks (trailing whitespace, ordering, comments).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96761 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| d76fe6649c9af1c4526e1d0735ef2d8dff7d6e25 |
21-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
Eliminate some uses of immAllOnes, just use -1, it does
the same thing and is more efficient for the matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96713 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 1a2e8686f8137a1a2329952ffd1e21969ea1658c |
19-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in
the armv6 nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96691 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| cf43e60544041c127bb875fe4cf0d0ae96cd6c78 |
19-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Radar 7636153. In the presence of large call frames, it's not sufficient
for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96634 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 49cf3a71734b4dc6545c279fb8236bef5758b2d5 |
18-Feb-2010 |
Eric Christopher <echristo@apple.com> |
Fix a few unused parameter warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96533 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 362dd0bef5437f85586c046bc53287b6fbe9c099 |
15-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move TLOF implementations to libCodegen to resolve layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96288 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 9184b25fa543a900463215c11635c2c014ddb623 |
15-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96285 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
argetMachine.h
|
| 86020e46289643de2f8c7603b550ffc8b6aff376 |
13-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
give MCCodeEmitters access to the current MCContext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96038 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| b917c47c98614a0bfbc3e79e378da6b15c18bef3 |
11-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
refactor x86 conditional branches to use a multipattern
that generates the 1-byte and 4-byte immediate versions
from one definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95902 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| f7ea6c3ee89e605c8d0bb7cdb0ade79706c750e8 |
11-Feb-2010 |
Mon P Wang <wangmp@apple.com> |
The previous fix of widening divides that trap was too fragile as it depends on custom
lowering and requires that certain types exist in ValueTypes.h. Modified widening to
check if an op can trap and if so, the widening algorithm will apply only the op on
the defined elements. It is safer to do this in widening because the optimizer can't
guarantee removing unused ops in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95823 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f451cb870efcf9e0302d25ed05f4cac6bb494e42 |
10-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Fix "the the" and similar typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetRegisterInfo.h
|
| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrInfo.h
argetOpcodes.h
|
| 1797ed50f488f2030f9f9a0ac7426262abf5220a |
08-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Rename the PerformTailCallOpt variable to GuaranteedTailCallOpt to reflect
its current purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95564 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 5669e3009761dff20b67e18a382c334041887928 |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
change addPassesToEmitFile to return true on failure instead of its input,
add -filetype=null for performance testing and remove -filetype=dynlib,
which isn't planned to be implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95202 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 022d9e1cef7586a80a96446ae8691a37def9bbf4 |
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 56591ab218639d8a6e4c756ca37adaf20215c3b6 |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
refactor code so that LLVMTargetMachine creates the asmstreamer and
mccontext instead of having AsmPrinter do it. This allows other
types of MCStreamer's to be passed in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95155 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 3813d8adf3788dd01a4cb9db01c122cd5e6a13b9 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
Remove a bunch of stuff around the edges of the ELF writer.
Now the only use of the ELF writer is the JIT, which won't be
easy to fix in the short term. :( :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95148 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| f1d6b107d2ea4518d240ee93bf4bffd53e71206d |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate all the dead addSimpleCodeEmitter implementations.
eliminate random "code emitter" stuff in Alpha, except for
the JIT path. Next up, remove the template cruft.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95131 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 942619695f4bd77934c09a1cae0fb39ae59edac3 |
02-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 211edae4843f5c2ee9c376e88e4cf0ecc8745f03 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate FileModel::Model, just use CodeGenFileType. The client
of the code generator shouldn't care what object format a target
uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95124 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 4db361395b762b1de6059827a6fabb1952373f98 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove the remnants of TargetMachOWriterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95114 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachOWriterInfo.h
argetMachine.h
|
| b5c5160a554cb0debeb7913287d9c099a753a59e |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate all forms of addPassesToEmitMachineCode except
the one used by the JIT. Remove all forms of
addPassesToEmitFileFinish except the one used by the static
code generator. Inline the remaining version of
addPassesToEmitFileFinish into its only caller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95109 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 0823d2a654cb3a075016f6efd21359ed4f5aca21 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
Inline addAssemblyEmitter into its one real caller and delete
the -print-emitted-asm option. The JIT shouldn't have to pull
in the asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95100 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 39bdc78e6fcc2a152c6143952c23fba5db983227 |
02-Feb-2010 |
Nate Begeman <natebegeman@mac.com> |
Kill the Mach-O writer, and temporarily make filetype=obj an error.
The MCStreamer based assemblers will take over for this functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95033 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 894c1af05fb3f0d8e2ee6565816fa220b260ed9d |
31-Jan-2010 |
Sean Callanan <scallanan@apple.com> |
Moved InstallLexer() from the X86-specific AsmLexer
to the TargetAsmLexer class so that clients can
actually use the TargetAsmLexer they get from a
Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94940 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmLexer.h
|
| dee740d1950af5014d4016ba9f39c0fc64b23162 |
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove a dead target hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94646 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0c439eb2c8397996cbccaf2798e598052d9982c8 |
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 30c6b75ac2eef548c18110a38c9798ea5314caba |
27-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
constify a method argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94612 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| ee49ad79fd437b2df04f7e25f08db5dc39324578 |
26-Jan-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove warning about non return on a non-void function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94532 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f1214cbf3c2d151d3a2353d82143da186313a42a |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the TargetLowering::UsesGlobalOffsetTable bool, which is
subsumed by TargetLowering::getJumpTableEncoding(). Change uses of
it to be more specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94529 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 589c6f620e8dcf3d59af1ae0e15372c934647c82 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Move getJTISymbol from MachineJumpTableInfo to MachineFunction,
which is more convenient, and change getPICJumpTableRelocBaseExpr
to take a MachineFunction to match.
Next, move the X86 code that create a PICBase symbol to
X86TargetLowering::getPICBaseSymbol from
X86MCInstLower::GetPICBaseSymbol, which was an asmprinter specific
library. This eliminates a 'gross hack', and allows us to
implement X86ISelLowering::getPICJumpTableRelocBaseExpr which now
calls it.
This in turn allows us to eliminate the
X86AsmPrinter::printPICJumpTableSetLabel method, which was the
only overload of printPICJumpTableSetLabel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94526 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 13e97a29d9dfa5602f93a8c546f112c5d029e8f7 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
stub out a new target hook, need some refactoring before I can
implement it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94521 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b8da4ac698dbb219e093b3159e2b5519063b011c |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
this hook should be const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94508 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 85fe07866a3b240d9facef3b2f2ea81a0a8db018 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Add support for target-specific 32-bit custom-lowered
jump table entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94505 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 071c62fad0b25ad4131e7f984173a796c1e63f61 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Rearrange handling of jump tables. Highlights:
1. MachineJumpTableInfo is now created lazily for a function the first time
it actually makes a jump table instead of for every function.
2. The encoding of jump table entries is now described by the
MachineJumpTableInfo::JTEntryKind enum. This enum is determined by the
TLI::getJumpTableEncoding() hook, instead of by lots of code scattered
throughout the compiler that "knows" that jump table entries are always
32-bits in pic mode (for example).
3. The size and alignment of jump table entries is now calculated based on
their kind, instead of at machinefunction creation time.
Future work includes using the EntryKind in more places in the compiler,
eliminating other logic that "knows" the layout of jump tables in various
situations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94470 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| da63b3ad6307cb4094383fad9695e4bb32ccac01 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a method to get the alignment of an integer type even
when we don't have one laying around. Useful if you don't
have an llvmcontext handy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94468 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 563515620336138c108febe0f5179594b071c896 |
22-Jan-2010 |
Sean Callanan <scallanan@apple.com> |
Filled out the skeleton of the TargetAsmLexer to behave
exactly like an MCAsmLexer. (The difference is that the
TargetAsmLexer knows how to handle target-specific stuff
like registers, whereas the MCAsmLexer is fully generic.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94237 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmLexer.h
|
| 96dc115ef3ee019cb91d7c112358a77536c38a53 |
22-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add two target hooks to determine whether two loads are near and should be scheduled together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94147 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| a27f64f3e34ee82f87f9cb197d02504a8b2cdae7 |
22-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
allow registering target lexers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94127 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
argetRegistry.h
|
| af0d301f43ddc61582c5ceb3b9e0492d71dc4330 |
22-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
stub out a new TargetAsmLexer interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94125 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmLexer.h
|
| 1548b863ce316c0b3be81d50d6388147df9aba72 |
21-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
remove a couple of asserts that use RTTI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94068 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 814819f6ea7fb0638fe73920299fda0da941a59e |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
stop using the .lcomm pseudoop on darwin, instead, directly use the
.zerofill directive. Streamerize its generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93868 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| c1ef06ac5264cb43f148590091606f0ed90a72e9 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
use BSSLocal classifier to identify 'lcomm' data instead of
duplicating the logic (differently) in lots of different targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93847 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 6e3be14be4eadd9aefea654611c808eea9eb8aea |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
change an accessor to a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93839 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| aac138e84dee1cb3ffc1035b2a1e4361fe0b4f80 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Cleanup handling of .zerofill on darwin:
1. TargetLoweringObjectFileMachO should decide if something
goes in zerofill instead of having every target do it.
2. TargetLoweringObjectFileMachO should assign said symbols to
the right MCSection, the asmprinters should just emit to the
right section.
3. Since all zerofill stuff goes through mcstreamer anymore,
MAI can have a bool "haszerofill" instead of having the textual
directive to emit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93838 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 48814681d72242e0179d7100f263952fdf4f51d6 |
18-Jan-2010 |
Bill Wendling <isanbard@gmail.com> |
- Add getLSDAEncoding to the PowerPC backend.
- Greatly improve the comments to the getLSDAEncoding method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93796 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| a8c18890da312e810c687b78658dcd4c989b9776 |
18-Jan-2010 |
Bill Wendling <isanbard@gmail.com> |
- Add a comment to the callback indicating that it's *extremely* not a good
idea, but unfortunately necessary.
- Default to using 4-bytes for the LSDA pointer encoding to agree with the
encoded value in the CIE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93753 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 971fd79067babb76619c8a0360166669df3a6863 |
18-Jan-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Unnamed symbol index should be >= 1. This was lost during the mangler refactoring. Fixes PR6067.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93724 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| 0bd58b0e81961313828aa9ac484ab6b0d6c8d970 |
17-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
stop the CBE from using Mangler::appendMangledName, which is a private function, it is mangling types, which don't matter how they are done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93692 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| 753fb624fb90e77f53b69afa44b7abe99a919b60 |
17-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
fix uninit member, thanks to Benjamin Kramer for identifying the bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93691 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| acd03ae6791fc0fb9f1b05247a1dc082b46b8d8b |
17-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Get MCSymbol out of the mangling business, and move all the logic
to Mangler. Now MCSymbol just decides whether to slap quotes around
a symbol when printing it.
This also fixes some weirdness where two MCSymbols could be created
for the same symbol, if one needed to be mangled and got mangled to
the other one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93690 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| c0dba723d119adc8c7b49c6d0e97d10eac4428fc |
17-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
now that mangler is in libtarget, it can use MCAsmInfo instead of clients
having to pass various fields from it in. Simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93686 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| 45111d160cf0910030eeb6a949c69273502e5ad5 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
move the mangler into libtarget from vmcore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93664 91177308-0d34-0410-b5e6-96231b3b80d8
angler.h
|
| d58e9cb42d7f5cf83c9b982df7e2c822b2e285e9 |
16-Jan-2010 |
Bill Wendling <isanbard@gmail.com> |
Retrying r91337:
The CIE says that the LSDA point in the FDE section is an "sdata4". That's fine,
but we need it to actually be 4-bytes in the FDE for some platforms. Allow
individual platforms to decide for themselves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93616 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 23cdb0bdcf8e7ded8ee5017592b6face579a2a7f |
15-Jan-2010 |
Dale Johannesen <dalej@apple.com> |
DEBUG_VALUE is now variable sized, as it has a
target-dependent memory address representation in it.
Restore X86 printing of DEBUG_VALUE; lowering is
done in X86RegisterInfo using the normal algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93565 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 3fe980b127a61608bd6d44c0939ba716ca21625c |
15-Jan-2010 |
Nate Begeman <natebegeman@mac.com> |
Hook up llc's -filetype=obj to use MCStreamer if an MCCodeEmitter is available.
Remove most of old Mach-O Writer support, it has been replaced by MCMachOStreamer
Further refactoring to completely remove MachOWriter and drive the object file
writer with the AsmPrinter MCInst/MCSection logic is forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93527 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 243a32f96b364811e2f9feadecfefb21b640321f |
15-Jan-2010 |
Dale Johannesen <dalej@apple.com> |
Remove DEBUG_DECLARE, looks like we don't need it.
Also, DEBUG_VALUE has side effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93498 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrInfo.h
|
| 9898671a74d3fc924347e679c45edaa685b3fe6e |
14-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Split the TargetAsmParser "ParseInstruction" interface in half:
the new ParseInstruction method just parses and returns a list of
target operands. A new MatchInstruction interface is used to
turn the operand list into an MCInst.
This requires new/deleting all the operands, but it also gives
targets the ability to use polymorphic operands if they want to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93469 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| f007e853e26845cd6866b52d646455fc69f4e0af |
14-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
prune #includes in TargetAsmParser.h
Pass in SMLoc of instr opcode into ParseInstruction.
Make AsmToken be a class, not a struct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93457 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| 4813035b726e7f0a3fd17bec437185fc72a50988 |
13-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
change Mangler::makeNameProper to return its result in a SmallVector
instead of returning it in an std::string. Based on this change:
1. Change TargetLoweringObjectFileCOFF::getCOFFSection to take a StringRef
2. Change a bunch of targets to call makeNameProper with a smallstring,
making several of them *much* more efficient.
3. Rewrite Mangler::makeNameProper to not build names and then prepend
prefixes, not use temporary std::strings, and to avoid other crimes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93298 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| c49a10aca1e31351c2e11b25ba636a23b93c46c8 |
13-Jan-2010 |
Dale Johannesen <dalej@apple.com> |
Fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93284 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 7da9ecf9677b751d81515f95168ae3cb2df54160 |
13-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.
For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93278 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2 |
12-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified
instruction is copy like where the source and destination registers can
overlap. This is to be used by the coalescable to coalesce the source and
destination registers of instructions like X86::MOVSX64rr32. Apparently
some crazy people believe the coalescer is too simple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93210 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| d2035203a0359eedbc1cf4ae77d43176e8455cd4 |
09-Jan-2010 |
Dale Johannesen <dalej@apple.com> |
Add DEBUG_DECLARE. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93040 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrInfo.h
|
| 87563b39370d7adfd42b0f531409ff9bc2bfcc56 |
09-Jan-2010 |
Dale Johannesen <dalej@apple.com> |
Add DEBUG_VALUE. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93030 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrInfo.h
|
| d1862037f04954f00cd6e6066ee213cfdc292877 |
07-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92883 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 30ac0467ced4627a9b84d8a1d3ca5e8706ddad63 |
07-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add Target hook to duplicate machine instructions.
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| d40d03e1bd1d51857fc2f9f9230e334c3a32b249 |
06-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach dag combine to fold the following transformation more aggressively:
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))
Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.
This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92849 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 537ab90d8de19b9f9cd758188947bde2edfd0358 |
04-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Remove the CPAttrParentAsRoot code, which is unused, and inconvenient
for a refactoring I'm working on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92503 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 8f17a36d3107bdc4ffed53ce782c1724ef6460e7 |
28-Dec-2009 |
Sanjiv Gupta <sanjiv.gupta@microchip.com> |
Allow targets to specify the return type of libcalls that are generated for floating point comparisons, rather than hard-coding them as i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92199 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3ea3c2461932d96d3defa0a9aa93ffaf631bb19d |
22-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Add more plumbing. This time in the LowerArguments and "get" functions which
return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f4f43cb5011611d44219ffb1caa988f5adf305bf |
21-Dec-2009 |
Eric Christopher <echristo@apple.com> |
Fix setting and default setting of code model for jit. Do this
by allowing backends to override routines that will default
the JIT and Static code generation to an appropriate code model
for the architecture.
Should fix PR 5773.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91824 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 1fef0c4962cbde6c9ab6a94e3361343f0ed9959b |
19-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Delete unused code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91743 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b4e6a5df5dada0cd919cc6e2717eb3118db9cc45 |
19-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Changes from review:
- Move DisableScheduling flag into TargetOption.h
- Move SDNodeOrdering into its own header file. Give it a minimal interface that
doesn't conflate construction with storage.
- Move assigning the ordering into the SelectionDAGBuilder.
This isn't used yet, so there should be no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91727 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 06801722a43c697eff0acee905de6b50257ce19b |
16-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Add @earlyclobber TableGen constraint
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91554 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| 83644f6b6d6d81f97a62ce60b4a5d8d0f2ded3a5 |
15-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Fix these asserts to check the invariant that the code actually
depends on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91360 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 85de1e5bade2f3755e47ed6fd43c92fcf99ff08b |
14-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Whitespace changes, comment clarification. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91274 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 1e8c6934f2d71c06816063b41f398a402e4b826e |
09-Dec-2009 |
Eric Christopher <echristo@apple.com> |
Silence conversion warning from 64 to 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90962 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 64fa4a9584113f63eccc1a650e7e0cc4ddbab3f6 |
09-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's primary used by selectdag passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90922 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e8b0915b21026cd2314c1802bd2ccd4c91f4a83d |
08-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert 90789 for now. It caused massive compile time regression. Post-ra scheduler slowed down dramatically with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90868 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| fb28579c568fcafaa4fb2a573b510deb6a6074e9 |
07-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Apply Pekka Jääskeläinen's patch to raise the first virtual register
number in order to accomodate targets with more than 1024 registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90789 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 864e2efce2cb5d02e376933933d96074723fe77c |
05-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 63be493b52e3558f2c579fef78d194c76c99eb8b |
05-Dec-2009 |
David Greene <greened@obbligato.org> |
Remove an unneeded include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90627 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 03c8406fc19658a3a8dc8ee00fddc88160038683 |
05-Dec-2009 |
David Greene <greened@obbligato.org> |
Fix a bad merge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90616 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 5e3363255912c559e8251121491a2a9e901f07ac |
05-Dec-2009 |
David Greene <greened@obbligato.org> |
Update the TargetInstrInfo interfaces so hasLoad/StoreFrom/ToStackSlot
can return a MachineMemOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90615 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 35e86af8e5cc76b94690d8e06517b7daa254d314 |
03-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
remove some dead std::ostream using code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90366 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| dd5eb023048d0ac69721eb919d3ef1bbaee2e1ce |
03-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
This initial code is meant to convert TargetData to use an AbstractTypesUser so
that it doesn't have dangling pointers when abstract types are resolved. This
modifies it somewhat to address comments: making the "StructLayoutMap" an
anonymous structure, calling "removeAbstractTypeUser" when appropriate, and
adding asserts where helpful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90362 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 15217e63bce6c161b355b63d6496c7c327d15817 |
30-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90144 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 308f6630a3f413ab32763bc78ab7802df372751d |
25-Nov-2009 |
Viktor Kutuzov <vkutuzov@accesssoftek.com> |
Rollback changes r89516: Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89893 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| f87ea4dd9ac9816131ee52ee6393c7b4012f2e68 |
25-Nov-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add the rest of the build system logic for optional target disassemblers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89841 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| f8c4cfb7cc330234112e1378dac6424d9956add0 |
25-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Refactor target hook for tail duplication as requested by Chris.
Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation. I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size. ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89814 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 108c838093704650378b194fe9afc5ebb9e91455 |
24-Nov-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
* Move stub allocation inside the JITEmitter, instead of exposing a
way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816.
* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89715 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 735afe14eea8049bf69210ce8a3512e391fc643f |
24-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| a2f20b20a8dc7f053599840557405554a0848aec |
22-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Add getFrameIndexReference() to TargetRegisterInfo, which allows targets to
tell debug info which base register to use to reference a frame index on a
per-index basis. This is useful, for example, in the presence of dynamic
stack realignment when local variables are indexed via the stack pointer and
stack-based arguments via the frame pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89620 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| e54cb16308ad40d0f0b257de47efaa0ee5a47004 |
21-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Allow target to disable if-converting predicable instructions. e.g. NEON instructions under ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89541 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 1f8f4d2db734d9881467a5706acac73660842d43 |
21-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Maintain stylistic consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89535 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 054b52c366256e7cde9c937006df944372e09acc |
21-Nov-2009 |
Viktor Kutuzov <vkutuzov@accesssoftek.com> |
Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89516 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 00621efb40edb7fe16bf2af6d4699c9d024a28e7 |
21-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Restructure code to allow renaming of multiple-register groups for anti-dep breaking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89511 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| e823db8bae7fe42cd4f1fa861bec8c36a636702b |
18-Nov-2009 |
Viktor Kutuzov <vkutuzov@accesssoftek.com> |
Added getDefaultSubtargetFeatures method to SubtargetFeatures class which returns a correct feature string for given triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89236 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 834b08af8d3d8fc6c76ac6ca40674565689e8d7f |
18-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a target hook to allow changing the tail duplication limit based on the
contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89187 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 5eea34267376e76aceb53b6c3dfead816021258f |
18-Nov-2009 |
Bill Wendling <isanbard@gmail.com> |
The llvm-gcc front-end and the pass manager use two separate TargetData objects.
This is probably not confined to *just* these two things.
Anyway, the llvm-gcc front-end may look up the structure layout information for
an abstract type. That information will be stored into a table with the FE's
TD. Instruction combine can come along and also ask for information on that
abstract type, but for a separate TD (the one associated with the pass manager).
After the type is refined, the old structure layout information in the pass
manager's TD file is out of date. If a new type is allocated in the same space
as the old-unrefined type, then the structure type information in the pass
manager's TD file will be wrong, but won't know it.
Fix this by making the TD's structure type information an abstract type user.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89176 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| fae3e923452b85e72b2c03dd6eacc063f59d81b1 |
14-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88753 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| d57cdd5683ea926e489067364fb7ffe5fd5d35ee |
14-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 87d21b92fc42f6b3bd8567a83fc5b5191c1205e5 |
13-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow target to specify regclass for which antideps will only be broken along the critical path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtarget.h
|
| dda3978d7877d2d60390833c73ed24857295e89c |
13-Nov-2009 |
David Greene <greened@obbligato.org> |
Fix a bootstrap failure.
Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE
interfaces to explicitly request checking for post-frame ptr elimination
operands. This uses a heuristic so it isn't reliable for correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87047 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b9c2fd964ee7dd7823ac71db8443055e4d0f1c15 |
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Make the MachineFunction argument of getFrameRegister const.
This also fixes a build error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87027 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| b87bc95db075dae3033a3c541b55b4cb711c332c |
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a
machine instruction loads or stores from/to a stack slot. Unlike
isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be
something other than a pure load/store (e.g. it may be an arithmetic
operation with a memory operand). This helps AsmPrinter determine when
to print a spill/reload comment.
This is only a hint since we may not be able to figure this out in all
cases. As such, it should not be relied upon for correctness.
Implement for X86. Return false by default for other architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87026 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 777bdad579081f0d5dfef8e6aeb251c4d3ec762a |
12-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Mark DBG_LABEL, EH_LABEL, and GC_LABEL as not-duplicable, since
they really are not duplicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87009 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 06b53c0d51f029eb754b40350faf5ba4b33c4bcb |
12-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
isLegalICmpImmediate should take a signed integer; code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86964 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 77e4751011da2d6afa930ab91f7baee39e7c7e89 |
11-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86858 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30 |
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Fixed to address code review. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtarget.h
|
| 0855dee564f80160abf95497475306af38ab7f84 |
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtarget.h
|
| 0dd3b7645b47118f7bea9d676a4176f96f76c457 |
09-Nov-2009 |
Chris Lattner <sabre@nondot.org> |
fix some bogus asserts, PR5049
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86514 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9e496d223102cb3d5e37c513a697e30532e71bc0 |
07-Nov-2009 |
Chris Lattner <sabre@nondot.org> |
all targets should be required to declare legal integer types. My plan to
make it optional doesn't work out. If you don't want to specify this, don't
specify a TD string at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86394 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| e82bdc4809240ab59977b9950288174b2f2dd852 |
07-Nov-2009 |
Chris Lattner <sabre@nondot.org> |
add the ability for TargetData to return information about legal integer
datatypes on a given CPU. This is intended to allow instcombine and other
transformations to avoid converting big sequences of operations to an
inconvenient width, and will help clean up after SRoA. See also "Adding
legal integer sizes to TargetData" on Feb 1, 2009 on llvmdev, and PR3451.
Comments welcome.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86370 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 2e07494170d5f56805b7a6c1b70808fc2a157052 |
07-Nov-2009 |
Chris Lattner <sabre@nondot.org> |
more cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86369 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| b7aadfac5e1b31f68be6c9afbdc2578a6415b00d |
07-Nov-2009 |
Chris Lattner <sabre@nondot.org> |
rewrite TargetData to use StringRef/raw_ostream instead of thrashing std::strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86366 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 12749db1503c2beed58ddcfba5f1b323611fb2ce |
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Missed this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86331 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b4997aeab74934ffa6fc0409afc4d8704245e372 |
07-Nov-2009 |
Kenneth Uildriks <kennethuil@gmail.com> |
Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers. Coming soon, code to perform sret-demotion if return values cannot be lowered to registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86324 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2928c83b010f7cfdb0f819199d806f6942a7d995 |
06-Nov-2009 |
Daniel Dunbar <daniel@zuster.org> |
Pass StringRef by value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86251 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
argetRegistry.h
|
| 82c443655d0b840d909bc0dc153ce02614a75f07 |
05-Nov-2009 |
Mon P Wang <wangmp@apple.com> |
Reintroduce support for overloading target intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86114 91177308-0d34-0410-b5e6-96231b3b80d8
argetIntrinsicInfo.h
|
| 8e46141e9ea48dcaee5b0d1e7a08f119bc1f3a58 |
03-Nov-2009 |
Nate Begeman <natebegeman@mac.com> |
Add a couple more target nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85857 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 0115e164bad632572e2cfbaf72f0f0882d5319de |
30-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Fix MachineLICM to use the correct virtual register class when
unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85622 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8c2b52552c90f39e4b2fed43e309e599e742b6ac |
30-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Initial target-independent CodeGen support for BlockAddresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85556 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 533297b58da8c74bec65551e1aface9801fc2259 |
29-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
argetLowering.h
|
| a1eaa3c52b75d4fe2bcd4f7c52e56c405ee91d3c |
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a second ValueType argument to isFPImmLegal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85361 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| eb2f969a4ddfb0bc8fdcb5bce3b52e53abff321d |
27-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85281 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a5dc45e3c8fa26e62b187284a240adf3879b56e2 |
26-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Revert some changes from 85044, 85045, and 85047 that broke x86_64 tests and
bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
common for targets to operate on registers where the top bits are undef. e.g.
s0 =
d0 = insert_subreg d0<undef>, s0, 1
...
= d0
When the insert_subreg is eliminated by the coalescer, the scavenger used to
complain. The previous fix was to keep to insert_subreg around. But that's
brittle and it's overly conservative when we want to use the scavenger to
allocate registers. It's actually legal and desirable for other instructions
to use the "undef" part of d0. e.g.
s0 =
d0 = insert_subreg d0<undef>, s0, 1
...
s1 =
= s1
= d0
We probably need add a "partial-undef" marker on machine operand so the
machine verifier would not complain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85091 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8b67f774e9c38b7718b2b300b628388f966df4e0 |
26-Oct-2009 |
Chandler Carruth <chandlerc@gmail.com> |
Move DataTypes.h to include/llvm/System, update all users. This breaks the last
direct inclusion edge from System to Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85086 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
argetData.h
argetJITInfo.h
|
| f5fe5e4e79689933ae9da99e5b62fc661e5421dd |
25-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add isIdentityCopy to check for identity copy (or extract_subreg, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85044 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| c9dfeb1be841045427d71b85e95ac7355b64e8b1 |
24-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Identity copies should not contribute to spill weight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84978 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 4c3715c2e5e17d7216a96ac2baf9720630f04408 |
23-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtarget.h
|
| 2685a29a8d4ced7791bb671e28f9fe51c74eb3bb |
20-Oct-2009 |
Daniel Dunbar <daniel@zuster.org> |
Wire up the ARM MCInst printer, for llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84600 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| d482f55af135081aee7f7ab972bb8973f189c88f |
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Adjust the scavenge register spilling to allow the target to choose an
appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84554 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| fa16354e0370fe884830286923352268b036737d |
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change createPostRAScheduler so it can be turned off at llc -O1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtarget.h
|
| bf57b52ba424bbaaa6e2d25dd4df731deb59f959 |
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a CodeGenOpt::Less level to match -O1. It'll be used by clients which do not want post-regalloc scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84272 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 0383606b657aa9770e6aee126b358afe9328ac4a |
15-Oct-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Clean up TargetIntrinsicInfo API. Add pure virtual methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84192 91177308-0d34-0410-b5e6-96231b3b80d8
argetIntrinsicInfo.h
|
| 3a6b9eb868f579b945aa8ec8fadf65e4dd913555 |
12-Oct-2009 |
Dale Johannesen <dalej@apple.com> |
Revert the kludge in 76703. I got a clean
bootstrap of FSF-style PPC, so there is some
reason to believe the original bug (which was
never analyzed) has been fixed, probably by
82266.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83871 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 3731bc026cc6c4fb7deb7ac67e2c3be0c22498be |
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Replace X86's CanRematLoadWithDispOperand by calling the target-independent
MachineInstr::isInvariantLoad instead, which has the benefit of being
more complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83696 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| a70dca156fa76d452f54829b5c5f962ddfd94ef2 |
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.
This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 769b7f89534caed11d7595b5c84aa47d3de30ad9 |
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Add a const qualifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83677 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 65c58daa8b8985d2116216043103009815a55e77 |
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Re-enable register scavenging in Thumb1 by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83521 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 9f3a559dff691bc1ed85089cb0870cf30a4a2d96 |
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
reverting thumb1 scavenging default due to test failure while I figure out what's up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83501 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| bafa3d9f6aaf24d721476ded7b1211ad57dd46c3 |
08-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Enable thumb1 register scavenging by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83496 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| e33f44cfc547359bc28526e4c5e1852b600b4448 |
07-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Replace TargetInstrInfo::isInvariantLoad and its target-specific
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83475 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b58f498f7502e7e1833decbbbb4df771367c7341 |
07-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Add register-reuse to frame-index register scavenging. When a target uses
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 540b05d227a79443b2a7b07d5152a35cb6392abf |
06-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
In Thumb1, the register scavenger is not always able to use an emergency
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83336 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 95923d70d90e0b9901d63ec3e35bf94be260e4f0 |
01-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83213 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 799d697bf8d45ec404d0d105fc788ea5cf81c841 |
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When
set, these flags indicate the instructions source / def operands have special
register allocation requirement that are not captured in their register classes.
Post-allocation passes (e.g. post-alloc scheduler) should not change their
allocations. e.g. ARM::LDRD require the two definitions to be allocated
even / odd register pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83196 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| 29e066965fb84b3aad2840815c6d0602dafb0b17 |
01-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use OutStreamer.SwitchSection instead of writing out textual section directives.
Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to
get access to that section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83178 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 629adde69953fa53362d20ddb7b4e67ed78b8ae3 |
30-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a target hook to add pre- post-regalloc scheduling passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83144 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 0dad89fa94536284d51f60868326294b725a0c61 |
30-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtarget.h
|
| 26207e5bf1123a793bd9b38bcda2f569a6b45ef2 |
28-Sep-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.
KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrInfo.h
|
| 8ff95de83cbe85d939535d2f4fb5f9b2b721081a |
27-Sep-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Use explicit structs instead of std::pair to map callee saved regs to spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82909 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 0035f9c3b9982eeef098b608fceb7572df969b3e |
25-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack
alignment is just always 4 bytes. For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.
After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo. This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4. (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 1f528956921561f277a8c697e0202ac1e9a9c1d5 |
24-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Make the end-of-itinerary mark explicit. Some cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82709 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 2763217fbd2f1c54a7a25fd3ae9e997ea6ece0cb |
21-Sep-2009 |
Reid Kleckner <reid@kleckner.net> |
Implement the JIT side of the GDB JIT debugging interface. To enable this
feature, either build the JIT in debug mode to enable it by default or pass
-jit-emit-debug to lli.
Right now, the only debug information that this communicates to GDB is call
frame information, since it's already being generated to support exceptions in
the JIT. Eventually, when DWARF generation isn't tied so tightly to AsmPrinter,
it will be easy to push that information to GDB through this interface.
Here's a step-by-step breakdown of how the feature works:
- The JIT generates the machine code and DWARF call frame info
(.eh_frame/.debug_frame) for a function into memory.
- The JIT copies that info into an in-memory ELF file with a symbol for the
function.
- The JIT creates a code entry pointing to the ELF buffer and adds it to a
linked list hanging off of a global descriptor at a special symbol that GDB
knows about.
- The JIT calls a function marked noinline that GDB knows about and has put an
internal breakpoint in.
- GDB catches the breakpoint and reads the global descriptor to look for new
code.
- When sees there is new code, it reads the ELF from the inferior's memory and
adds it to itself as an object file.
- The JIT continues, and the next time we stop the program, we are able to
produce a proper backtrace.
Consider running the following program through the JIT:
#include <stdio.h>
void baz(short z) {
long w = z + 1;
printf("%d, %x\n", w, *((int*)NULL)); // SEGFAULT here
}
void bar(short y) {
int z = y + 1;
baz(z);
}
void foo(char x) {
short y = x + 1;
bar(y);
}
int main(int argc, char** argv) {
char x = 1;
foo(x);
}
Here is a backtrace before this patch:
Program received signal SIGSEGV, Segmentation fault.
[Switching to Thread 0x2aaaabdfbd10 (LWP 25476)]
0x00002aaaabe7d1a8 in ?? ()
(gdb) bt
#0 0x00002aaaabe7d1a8 in ?? ()
#1 0x0000000000000003 in ?? ()
#2 0x0000000000000004 in ?? ()
#3 0x00032aaaabe7cfd0 in ?? ()
#4 0x00002aaaabe7d12c in ?? ()
#5 0x00022aaa00000003 in ?? ()
#6 0x00002aaaabe7d0aa in ?? ()
#7 0x01000002abe7cff0 in ?? ()
#8 0x00002aaaabe7d02c in ?? ()
#9 0x0100000000000001 in ?? ()
#10 0x00000000014388e0 in ?? ()
#11 0x00007fff00000001 in ?? ()
#12 0x0000000000b870a2 in llvm::JIT::runFunction (this=0x1405b70,
F=0x14024e0, ArgValues=@0x7fffffffe050)
at /home/rnk/llvm-gdb/lib/ExecutionEngine/JIT/JIT.cpp:395
#13 0x0000000000baa4c5 in llvm::ExecutionEngine::runFunctionAsMain
(this=0x1405b70, Fn=0x14024e0, argv=@0x13f06f8, envp=0x7fffffffe3b0)
at /home/rnk/llvm-gdb/lib/ExecutionEngine/ExecutionEngine.cpp:377
#14 0x00000000007ebd52 in main (argc=2, argv=0x7fffffffe398,
envp=0x7fffffffe3b0) at /home/rnk/llvm-gdb/tools/lli/lli.cpp:208
And a backtrace after this patch:
Program received signal SIGSEGV, Segmentation fault.
0x00002aaaabe7d1a8 in baz ()
(gdb) bt
#0 0x00002aaaabe7d1a8 in baz ()
#1 0x00002aaaabe7d12c in bar ()
#2 0x00002aaaabe7d0aa in foo ()
#3 0x00002aaaabe7d02c in main ()
#4 0x0000000000b870a2 in llvm::JIT::runFunction (this=0x1405b70,
F=0x14024e0, ArgValues=...)
at /home/rnk/llvm-gdb/lib/ExecutionEngine/JIT/JIT.cpp:395
#5 0x0000000000baa4c5 in llvm::ExecutionEngine::runFunctionAsMain
(this=0x1405b70, Fn=0x14024e0, argv=..., envp=0x7fffffffe3c0)
at /home/rnk/llvm-gdb/lib/ExecutionEngine/ExecutionEngine.cpp:377
#6 0x00000000007ebd52 in main (argc=2, argv=0x7fffffffe3a8,
envp=0x7fffffffe3c0) at /home/rnk/llvm-gdb/tools/lli/lli.cpp:208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82418 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 19e74991f304a67c4dddbea12f1d9f71446ba2a0 |
21-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
remove a dead method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82413 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| f00a7d91c04db14cb0fd180c57482fe121eccfad |
20-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
add a helper method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82376 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 0002e506de922b6f8b830674316aa8e5428f7049 |
19-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Update comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82313 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| fb2e752e4175920d0531f2afc93a23d0cdf4db14 |
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8609c7c931c0213d6d29f665df2110cf3c709e4c |
17-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
pass machinemoduleinfo down into getSymbolForDwarfGlobalReference,
currently unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82157 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 8c6ed05157e9c97ff8f3ccb211dd797e53228da1 |
16-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
Big change #1 for personality function references:
Eliminate the PersonalityPrefix/Suffix & NeedsIndirectEncoding
fields from MAI: they aren't part of the asm syntax, they are
related to the structure of the object file.
To replace their functionality, add a new
TLOF::getSymbolForDwarfGlobalReference method which asks targets
to decide how to reference a global from EH in a pc-relative way.
The default implementation just returns the symbol. The default
darwin implementation references the symbol through an indirect
$non_lazy_ptr stub. The bizarro x86-64 darwin specialization
handles the weird "foo@GOTPCREL+4" hack.
DwarfException.cpp now uses this to emit the reference to the
symbol in the right way, and this also eliminates another
horrible hack from DwarfException.cpp:
- if (strcmp(MAI->getPersonalitySuffix(), "+4@GOTPCREL"))
- O << "-" << MAI->getPCSymbol();
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81991 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 75144f93eb7e4dbf22d308d21581ae255dd520c6 |
15-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Fix apostrophos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81856 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedule.td
|
| 90edac0e8b35f766599362b6301863229f0ddcdb |
14-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
Change MCAsmStreamer to take an MCInstPrinter instead of a
full AsmPrinter, and change TargetRegistry to keep track
of registered MCInstPrinters.
llvm-mc is still linking in the entire
target foo to get the code emitter stuff, but this is an
important step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81754 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| e7f3107772b1c8c2b9397ab19106b8451d31e8ab |
14-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate the TargetRegisterDesc::AsmName field, the asmprinters now have this table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81728 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 762ccea600158bb317dcccdff3303e942426cb71 |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
remove all but one reference to TargetRegisterDesc::AsmName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81714 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 9c656450d65034c4cd3597fff61ef17376cff090 |
10-Sep-2009 |
Kevin Enderby <enderby@apple.com> |
Added the ParseInstruction() hook for target specific assembler directives so
that things like .word can be parsed as target specific. Moved parsing .word
out of AsmParser.cpp into X86AsmParser.cpp as it is 2 bytes on X86 and 4 bytes
for other targets that support the .word directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81461 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| 251ef612a812ac99edeab6c08a752bf8ca220921 |
10-Sep-2009 |
Sean Callanan <scallanan@apple.com> |
Added an abstract superclass, MCDisassembler, for
all disassemblers.
Modified the MemoryObject to support 64-bit address
spaces, regardless of the LLVM process's address
width.
Modified the Target class to allow extraction of a
MCDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81392 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 59bf4fcc0680e75b408579064d1205a132361196 |
06-Sep-2009 |
Duncan Sands <baldrick@free.fr> |
Public and private corrections, warned about by icc (#304).
Patch by Erick Tryzelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81107 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 5026274ba8e311aa86d3bf950eefa76c8c9aa008 |
05-Sep-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove an unneeded call to c_str().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81051 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 3f2f3f5341374c85955cfaffa71886724999762d |
03-Sep-2009 |
Lang Hames <lhames@gmail.com> |
Fixed a test that ensures the LocalRewriter does not attempt to
avoid reloads by reusing clobbered registers.
This was causing issues in 256.bzip2 when compiled with PIC for
a while (starting at r78217), though the problem has since been masked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80872 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 65c3c8f323198b99b88b109654194540cf9b3fa5 |
02-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c69d74a5d41a6c5e92f9d947f2fa181f48626ca5 |
31-Aug-2009 |
Duncan Sands <baldrick@free.fr> |
Revert commit 80428. It completely broke exception
handling on x86-32 linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80592 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9b35a09e7e5b1aa26588e3852fe00a42b4f383ba |
29-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
- Add target lowering methods to get the preferred format for the FDE and LSDA
encodings.
- Make some of the values emitted by the FDEs dependent upon the pointer
size. This is in line with how GCC does things. And it has the benefit of
working for Darwin in 64-bit mode now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80428 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 04baf9094ada38a518ba7eda87d4c478a874dbb1 |
27-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Tweak MCCodeEmitter skeleton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80193 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 4a0abd80f18f9c2a10bf5b14cd6731d51972a426 |
27-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Sketch TargetRegistry support for MCCodeEmitter abstract interface.
- Of course, nothing actually can provide this interface yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80188 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| e0c86afac63a2dbbcff0ad79ed7b93d860451385 |
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Switch SubtargetFeature off of ostreams
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79864 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 33adcfb4d217f5f23d9bde8ba02b8e48f9605fc5 |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
rename TAI -> MAI, being careful not to make MAILJMP instructions :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79777 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetRegistry.h
|
| 82d748d55c549dd055528ed10dbb534618ca8115 |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move the MCAsmInfo .cpp/.h files into the right
directories and rename them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79768 91177308-0d34-0410-b5e6-96231b3b80d8
OFFTargetAsmInfo.h
arwinTargetAsmInfo.h
argetAsmInfo.h
|
| af76e592c7f9deff0e55c13dbb4a34f07f1c7f64 |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79763 91177308-0d34-0410-b5e6-96231b3b80d8
OFFTargetAsmInfo.h
arwinTargetAsmInfo.h
argetAsmInfo.h
argetInstrInfo.h
argetLoweringObjectFile.h
argetMachine.h
argetRegistry.h
|
| 24f20e083280d979e8fa1bc88959ae9e8339ee99 |
22-Aug-2009 |
Devang Patel <dpatel@apple.com> |
Record variable debug info at ISel time directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79742 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 9085750d3126618ab1b3a4104c34bc504f8b09f4 |
21-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Try again at privatizing the layout info map, with a rewritten patch.
This preserves the existing behavior much more closely than my previous attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79663 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 2ea20154cef8ecfb8803bcfe5223e1c199d61858 |
21-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Re-revert r79555. Apparently it's not just buildbot weirdness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79578 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 28998d1806f5717c841c614f5c6c08fd6de4cdbb |
21-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Reapply r79555 for testing. Daniel's trying to work out some buildbot weirdnesss.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79572 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 607abd262edfa23f7b342f377b444881f4429377 |
21-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
--- Reverse-merging r79555 into '.':
U include/llvm/Target/TargetData.h
U lib/Target/TargetData.cpp
Temporarily revert 79555. It was causing hangs and test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79568 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| d9b207122eeb740a3878f8389cb38b81d9388734 |
20-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Make the StructType->StructLayout table private to TargetData, allowing us to avoid locking on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79555 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| a5595b02daae4641f7120b44ef05ba9c494bb461 |
20-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Reword a few comments for AnalyzeBranch and InsertBranch, and fix
a few typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79503 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| dc4bdcdef1c8dd1a28b82deb08df039e5c0ffc5a |
19-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79425 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
argetSubtarget.h
|
| fac8541dd40e01aa2b52962516f9ae67c99720cc |
17-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Extend the instruction itinerary model to include the ability to indicate the def and use cycle for each operand. This additional information is optional, so existing itineraries do not need to be changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79247 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
argetSchedule.td
|
| af5663405834ca7cf4a847f2efa2d624ce99b1d8 |
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Reapply r79127. It was fixed by d0k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f865ea85bd9d3e04aa795ee03cfc8db339f8c9b9 |
15-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
Revert r79127. It was causing compilation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 088880cb192fb6dd5b1bf85af62023c5ca3da38f |
15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change allowsUnalignedMemoryAccesses to take type argument since some targets
support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79127 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 72977a45a8ad9d9524c9b49399e89fb9a3a676ed |
14-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Allow targets to specify their choice of calling conventions per
libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.
Patch by Sandeep!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79033 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 789457847002f5289dbbc5cfce9d68c72e00bed1 |
14-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
TargetRegistry: Change AsmPrinter constructor to be typed as returning an
AsmPrinter instance (instead of just a FunctionPass)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78962 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 011e4db845b5c4166142338c77adc8ac03e5e041 |
14-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Add dummy MCStreamer implementation, (eventually) for use in profiling.
- Currently unused.
- A few other random comment fixes lumped in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78960 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| fdf229eda95a542fc34d5182e1a91a22789ba122 |
14-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove HasCrazyBSS and add a flag in TAI to indicate that '.section'
must be emitted for PowerPC-Linux '.bss' section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78958 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| 1d0be15f89cb5056e20e2d24faa8d6afb1573bca |
13-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Push LLVMContexts through the IntegerType APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| b8e1055f41526a852dec2c9565ba1afd2706eee8 |
13-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add a method to return BSSSection from TargetLoweringObjectFile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78939 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 67d894ea64bc52245abf3f2ba89122a749d99c53 |
13-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
TargetRegistry: Reorganize AsmPrinter construction so that clients pass in the
TargetAsmInfo. This eliminates a dependency on TargetMachine.h from
TargetRegistry.h, which technically was a layering violation.
- Clients probably can only sensibly pass in the same TargetAsmInfo as the
TargetMachine has, but there are only limited clients of this API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78928 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| b42dad4761968b4b052e72494ce1bf0c7b3aba3e |
13-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Revert 78892 and 78895, these break generating working executables on
x86_64-apple-darwin10.
--- Reverse-merging r78895 into '.':
U test/CodeGen/PowerPC/2008-12-12-EH.ll
U lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U include/llvm/Target/DarwinTargetAsmInfo.h
U lib/Target/X86/X86TargetAsmInfo.cpp
U lib/Target/X86/X86TargetAsmInfo.h
U lib/Target/ARM/ARMTargetAsmInfo.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/ARMTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.h
U lib/Target/PowerPC/PPCTargetMachine.cpp
G lib/Target/DarwinTargetAsmInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78919 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
|
| 710461688bba935f0ad5c75da7fec2ad0f225c00 |
13-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Add callback to allow target to adjust latency of schedule dependency edge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78910 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtarget.h
|
| b2d3169d96ee780e6b8f43230e36e41d97ed3140 |
13-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
fix a minor fixme. When building with SL and later tools, the ".eh" symbols
don't need to be exported from the .o files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78892 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
|
| b808588a3a5febe931896b3779d159ba90d836f7 |
13-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Change MCSectionELF to represent a section semantically instead of
syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78890 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 38cff389af1d78bd80df0479ef258493e0c5897e |
13-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
sink uniquing of sections out of MCContext into the ELF and PECOFF TLOF implementations.
MCContext no longer maintains a string -> section map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78874 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| e309cfa0d8945af47dd798357549c815164d53d6 |
13-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
reject invalid code like:
int x __attribute__((section("_foo, _bar"))) = 4;
int y __attribute__((section("_foo, _bar, 4byte_literals"))) = 1;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78867 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 5dc47ff03975b9adde9dd833db2b646eb4295710 |
13-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
implement support for uniquing MachO sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78866 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| d3c4486f46226fb328ceb16d55927472fb3e0f6d |
13-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
reduce #includage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78860 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 36e3e668be0c4914660575d7cea800b0d51a4116 |
13-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a new "SDTCisVec" SDTypeConstraint. This complements the vAny type.
There have been a few times where I've wanted this but ended up leaving the
operand type unconstrained. It is easy to add this now and should help
catch errors in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78849 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| 1a8f36e3ce5b9c230781b66600c81536128abfb5 |
12-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78827 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
argetSchedule.td
|
| a7ac47cee1a0b3f4c798ecaa22ecf9d1be9c07e6 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple
pair instead of from a virtual method on TargetMachine. This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use
TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78802 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetRegistry.h
|
| 23b9b19b1a5a00faa9fce0788155c7dbfd00bfb1 |
12-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78759 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7417b761c2d88335bd77d38911ff8d323fc4a4f2 |
12-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add 'isCodeGenOnly' bit to Instruction .td records.
- Used to mark fake instructions which don't correspond to an actual machine
instruction (or are duplicates of a real instruction). This is to be used for
"special cases" in the .td files, which should be ignored by things like the
assembler and disassembler. We still need a good solution to handle pervasive
duplication, like with the Int_ instructions.
- Set the bit on fake "mov 0" style instructions, which allows turning an
assembler matcher warning into a hard error.
- -2 FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78731 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 59fc42debd571bbafc52c20bc418fdc3f4d00188 |
11-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/AsmParser: Allow target to specific a comment delimiter, which will be
used to strip hard coded comments out of .td assembly strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78716 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetRegisterInfo.h
argetSelectionDAG.td
|
| 0a31d2f6456069adba19b8aeca66c68b633c38b4 |
11-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
pass the TargetTriple down from each target ctor to the
LLVMTargetMachine ctor. It is currently unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78711 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| dfab291702a9c6e88981047bf6a3fe42f7d508b0 |
11-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
split "JumpTableDirective" (an existing hack) into a PIC and nonPIC
version. This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.
The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78709 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 1b747ad8a0694b86e8d98a8b9a05ddfe74ec0cd3 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
SjLj based exception handling unwinding support. This patch is nasty, brutish
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78625 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetOptions.h
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetRegisterInfo.h
argetSelectionDAG.td
|
| 5c468e3d7006e854fd41b29d5539a7adcee53904 |
10-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/AsmParser: Allow .td users to redefine the names of the methods to call
on target specific operands for testing class membership and converting to
MCInst operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78597 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| d6662add687f20cffa0755e410efbb40de4dcf23 |
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
SimpleValueType-ify a few more methods on TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78595 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 70671845adce8ab36ae596bb06d0375459a7a2af |
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Continue the SimpleValueType-ification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78593 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 77547befdc430633aaedf4130ddf17d953ed552e |
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78584 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 338825c1928b956b2cbcc2c165a60afddd100398 |
10-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78581 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| d94a4e5d8de1145be200ff7223f98b0928462b94 |
10-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78563 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| ff4bc460c52c1f285d8a56da173641bf92d49e3f |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Make the big switch: Change MCSectionMachO to represent a section *semantically*
instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78547 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 98164afb019a6c9e92e043fa64b902b9d026c9a9 |
09-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Extend comment on ParserMatchClass .td field, and add some missing
classes for X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78524 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 6745d42e8e51ba6b9546d6fa62e0c1b1e0f3982a |
09-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/AsmParser: Define match classes in the .td file.
-2 FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78523 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 892e18239308f8a02a4c83758616be84a459c19d |
09-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
1. Make MCSection an abstract class.
2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78510 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| 5277b22687d3513dd29d5a9c8510cac740f933f6 |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate TargetLoweringObjectFileSparc in favor of a TAI hook.
A TAI hook is appropriate in this case because this is just an
asm syntax issue, not a semantic difference. TLOF should model
the semantics of the section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78498 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| 0c0cb7123346beab4e0d3ad6ce9570560b14971e |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
now that getOrCreateSection is all object-file specific,
give the impls an object-file-specific name. In the future
they can take different arguments etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78495 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| fbf1d271e6a7157c1b5432e84d5633f63869b5a8 |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
sink getOrCreateSection down into all the object file implementations,
now that they create *all* the sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78494 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| db0a9706e76fde6f3076f2baa1cb5bd0e47c8ee3 |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove a bunch of now-dead crud from the asmprinter and TAI interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78428 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 59e8677b1927e9e1573ce94defc35537dfa7ae64 |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
fix the column output stuff in the asmwriter from being dynamic and
driven by TAI to being static, driven by tblgen. This means that a
target doesn't get impacted by this stuff at all if it doesn't opt
into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78427 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| b124be4f979acb8b3584de392bf28786fd8a5e76 |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
fix comment pastos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78422 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 24f654c8a4d14066233480f683d3b0dececf374a |
06-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Fix several fixmes and clean up code by sinking *all* section
creation activity into the target-specific subclasses of TLOF.
Before this, globals with explicit sections could be created by
the base class.
1. make getOrCreateSection protected, add a new getExplicitSectionGlobal
pure virtual method to assign sections to globals with a specified
section.
2. eliminate getSpecialCasedSectionGlobals, which is now PIC specific.
3. eliminate the getKindForNamedSection virtual method, which is
now just a static method for ELF.
4. Add implementions of getExplicitSectionGlobal for ELF/PECOFF/Darwin/PIC16.
They are now all detangled and understandable, woo! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78319 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| a5bb59f85613e8ce481351803e7388f5ab466e72 |
05-Aug-2009 |
David Greene <greened@obbligato.org> |
Fix some column padding bugs, reorganize things as suggested by Chris
and eliminate complexity. Yay!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78243 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| cafbdc5c095f4cc84e74e0286651cf8daa6efa2a |
05-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove the 'DataSectionStartSuffix' and 'TextSectionStartSuffix' knobs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78242 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 892fe182c83ae58fe6318527912fc71ebd687a23 |
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Delete an obsolete sentance from a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78206 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 52d0851446afe2ae923fc7e7ee56aa4c9d61c1e1 |
05-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Remove custom handling of jumptables by the elf writter (this was
a dirty hack and isn't need anymore since the last x86 code emitter patch)
- Add a target-dependent modifier to addend calculation
- Use R_X86_64_32S relocation for X86::reloc_absolute_word_sext
- Use getELFSectionFlags whenever possible
- fix getTextSection to use TLOF and emit the right text section
- Handle global emission for static ctors, dtors and Type::PointerTyID
- Some minor fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78176 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| 58bed8fc29b6e55e7014dcb537808043c946cd73 |
05-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
expose SectionKindForGlobal to curious clients, named as
getKindForGlobal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78156 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 98ca4f2a325f72374a477f9deba7d09e8999c29b |
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetSelectionDAG.td
|
| f9c1ccf28020add0b3e1d633684debf3e3dc294f |
04-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
rip out SectionEndDirectiveSuffix support, only uses by
the masm backend. If anyone cares about masm in the future,
we'll have semantic sections it can hang off of.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78096 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| ec409759e94cc395e4896ba6ade3fa77200c5cfd |
04-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
enhance codegen to put 16-bit character strings into the
__TEXT,__ustring section on darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78068 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 7e88a50428377813606c66ac47111d9c3ea44feb |
04-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
fix a fixme: don't create an explicit "CStringSection" for ELF,
it is just being used as a prefix, so forward substitute it directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78067 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| a277f4e33dac3d0d6eea32996950800113566714 |
04-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78046 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 214e22396fe86aa20c587d5c7df9ce63bfd4549e |
04-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove now unused Module argument to createTargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78043 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 11e9657eeb76dff6baaab1cbac0b1fb7e1abb439 |
03-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Eliminate textual section switching from the x86 backend, one
more step towards "semantics sections"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78002 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 38c398808cff7defdf013fa750dfac8e66302975 |
03-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
make getObjFileLowering() return a non-const reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77984 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d5fe92efbc1774ada25a1cfa18009bfc5c6e625c |
03-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77971 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 4ab15535e7028a48d75c9d08ed57e9b3b05b1f53 |
03-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add 'Indirect' LocInfo class and use to pass __m128 on win64. Also minore fixes here and there (mostly __m64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77964 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.td
|
| 4bd03abe593222b26e84066223feb321bf738625 |
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove now unused arguments from TargetRegistry::lookupTarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77950 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 3c2d4bf97fa96fe171883cd80e4ea93fc43563e6 |
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Pass target triple string in to TargetMachine constructor.
This is not just a matter of passing in the target triple from the module;
currently backends are making decisions based on the build and host
architecture. The goal is to migrate to making these decisions based off of the
triple (in conjunction with the feature string). Thus most clients pass in the
target triple, or the host triple if that is empty.
This has one important change in the way behavior of the JIT and llc.
For the JIT, it was previously selecting the Target based on the host
(naturally), but it was setting the target machine features based on the triple
from the module. Now it is setting the target machine features based on the
triple of the host.
For LLC, -march was previously only used to select the target, the target
machine features were initialized from the module's triple (which may have been
empty). Now the target triple is taken from the module, or the host's triple is
used if that is empty. Then the triple is adjusted to match -march.
The take away is that -march for llc is now used in conjunction with the host
triple to initialize the subtarget. If users want more deterministic behavior
from llc, they should use -mtriple, or set the triple in the input module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77946 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| e28039cfd1a9c43b5fa9274bf19372d96f58f460 |
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Move most targets TargetMachine constructor to only taking a target triple.
- The C, C++, MSIL, and Mips backends still need the module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77927 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 18a4c16726db2b8874c7b84d04650dda80746074 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move dwarf debug info section selection stuff from TAI to
TLOF, unifying all the dwarf targets at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77889 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| 35039ac24163e99cfab161620a9fb41f944a63d5 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
convert EHFrameSection to be managed by TLOF instead of TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77888 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| d90183d25dcbc0eabde56319fed4e8d6ace2e6eb |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Move the getInlineAsmLength virtual method from TAI to TII, where
the only real caller (GetFunctionSizeInBytes) uses it.
The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetInstrInfo.h
|
| b6bbfebdc683a6a123410bca1175e14d264d4bc2 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move a virtual method body to its .cpp file to avoid a #include
in a header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77874 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 9ba8c6872dc722d0f9f804fcd67bace4acfe67ba |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove the dead ELFTargetAsmInfo.h/cpp file. TargetAsmInfo
defaults to being ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77866 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
|
| 8d4a0a328a89d1f3c7ad83048e04ace53b6ba781 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove TargetAsmInfo::TM, which is now dead. The basic TAI class now
no longer depends on TM!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77863 91177308-0d34-0410-b5e6-96231b3b80d8
OFFTargetAsmInfo.h
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 05e5fcab0910b7e0ebdd03cb4c1960ae8ba219fd |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move an enum from TM -> TargetOptions. This makes TargetOptions.h
be self contained, and it isn't used from TM.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77857 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetOptions.h
|
| b6d667403fed489ef92174b3f19d4b87db5c39f7 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove the dead PreferredEHDataFormat TAI hook: its now dead
even considering #if 0 code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77856 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| d5bbb07ec806e6fa1e804afd7073987fdacc83e4 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move getDwarfExceptionSection from TAI to TLOF and rename it to
getLSDASection() to be more specific. This makes it pretty obvious
that the ELF LSDA section is being specified wrong in PIC mode. We're
probably getting a lot of startup-time relocations to a readonly page,
which is expensive and bad.
Someone who cares about ELF C++ should investigate this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77847 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| 80ec2792b2b271eca55743a3cc4c8bca214fa705 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
convert ctors/dtors section to be in TLOF instead of
TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77842 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| 83d77faf6e8fc2c1c2377d037283dc162d8667a1 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Remove "JumpTableDataSection" from TAI, instead, have AsmPrinter
compute it based on what it knows. As part of this, rename getSectionForMergeableConstant
to getSectionForConstant because it works for non-mergable constants also.
The only functionality change from this is that Xcore will start dropping
its jump tables into readonly section instead of data section in -static mode.
This should be fine as the linker resolves the relocations. If this is a
problem, let me know and we'll come up with another solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77833 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| b80610cd13e7accf6db0924c75d0914bf566922b |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
REmove dead fields of TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77820 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 824583844a8f334dd261894a3fac7ad476531667 |
01-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
fix a fixme by sinking various target-specific directives down into
the appropriate subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77815 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| f9650c061ee89ac55740555530ca5c2842c28738 |
01-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
it turns out that isWeak() was basically dead anyway. Kill off SectionInfo :-/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77812 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 0064e85050e3a324aa66ee29af56546e0c31f6cc |
01-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
fix a layering violation by moving SectionKind out to its own header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77808 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| f17008844adfeb3716969a6004e28dcf176a38b2 |
01-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Minor whitespace tidiness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77807 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 423d190dbe04d14782bbf9aa1e8ecb896870adb7 |
01-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
with the previous refactoring, fixme fixed!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77805 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 968ff1196768c0b6dbcc5508025a2923bfa73fab |
01-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Change SectionKind to be a property that is true of a *section*, it
should have no state that is specific to particular globals in the
section. In this case, it means the removal of the "isWeak" and
"ExplicitSection" bits. MCSection uses the new form of SectionKind.
To handle isWeak, I introduced a new SectionInfo class, which is
SectionKind + isWeak, and it is used by the part of the code generator
that does classification of a specific global.
The ExplicitSection disappears. It is moved onto MCSection as a new
"IsDirective" bit. Since the Name of a section is either a section
or directive, it makes sense to keep this bit in MCSection. Ultimately
the creator of MCSection should canonicalize (e.g.) .text to whatever
the actual section is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77803 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 7a01e959156ba4e0a15b45a1f153f67d1646c0a5 |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
PreferredEHDataFormat is always call with data and global, but this whole
thing is #if0'd out anyway. Just simplify the code by reducing the interface.
Not deleting this is essential for Bill's continuing happiness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77736 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 26630c1180502d07c9b2b4a9a4ba06bc5ddf180b |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
move emitUsedDirectiveFor to TargetLoweringObjectFile and rename it to
indicate that it is a predicate, not an emitter. This eliminates TAI
dependencies on Mangler and GlobalValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77726 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
argetAsmInfo.h
argetLoweringObjectFile.h
|
| 548f8cbb94473afdcf1766f4cb5e0b12739acf5d |
31-Jul-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77711 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| a87dea4f8c546ca748f1777a8d1cabcc06515d91 |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
switch off of 'Section' onto MCSection. We're not properly using
MCSection subclasses yet, but this is a step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| f26e03bc7e30162197641406e37e662a15d80f7e |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
refactor section construction in TLOF to be through an explicit
initialize method, which can be called when an MCContext is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77687 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 23b6ecffe1ee5992cc1e057850bb1f36bc237ac0 |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
move the sectionkind and section classes to TargetLoweringObjectFile.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77681 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLoweringObjectFile.h
|
| 2a3868849438a0a0ad4f9a50f2b94eb1639b554e |
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
inline the global 'getInstrOperandRegClass' function into its callers
now that TargetOperandInfo does the heavy lifting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77508 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| cb778a8634454c70d88955b3732f330a6cbe5b07 |
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
1. Introduce a new TargetOperandInfo::getRegClass() helper method
and convert code to using it, instead of having lots of things
poke the isLookupPtrRegClass() method directly.
2. Make PointerLikeRegClass contain a 'kind' int, and store it in
the existing regclass field of TargetOperandInfo when the
isLookupPtrRegClass() predicate is set. Make getRegClass pass
this into TargetRegisterInfo::getPointerRegClass(), allowing
targets to have multiple ptr_rc things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77504 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| a938ac6223c5fd315ab745086d843df5e0604e09 |
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make ptr_rc derive from a new PointerLikeRegClass tblgen class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77503 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 2cfd52c507bd5790457a171eb9bcb39019cc6860 |
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Give getPointerRegClass() a "kind" value so that targets can
support multiple different pointer register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| e53a600f065075731d0aeb9dc8f4f3d75f5a05f8 |
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
pass the mangler down into the various SectionForGlobal methods.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77432 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| 0e2771f4c4a6e1ffc664eb23487087f824340255 |
29-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Match X86 register names to number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77404 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 16cdcb38b2a5c5cdc216f9abafabd20e1ef7a254 |
29-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Move X86 instruction parsing into X86/AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77384 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| 1da5860b041a84744790878d1cd42e0d33afbd12 |
28-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Remove unused parameter name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77371 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| a2edbabcb86f213eca6daeda5d801f8c7b1e44b2 |
28-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Provide generic MCAsmParser when constructing target specific parsers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77362 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 4bb253c60f895131371aa2ad1bfa5a2bea213f78 |
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
the apple "ld_classic" linker doesn't support .literal16 in 32-bit
mode, and "ld64" (the default linker) falls back to it in -static
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77334 91177308-0d34-0410-b5e6-96231b3b80d8
argetLoweringObjectFile.h
|
| f0144127b98425d214e59e4a1a4b342b78e3642b |
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rip all of the global variable lowering logic out of TargetAsmInfo. Since
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8
OFFTargetAsmInfo.h
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
argetLowering.h
argetLoweringObjectFile.h
|
| 9a7e2ccf574368b60455f8c8975030475a1f3ce0 |
27-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Move AsmLexer::getCurStrVal to StringRef based API.
- My DFS traversal of LLVM is, at least for now, nearly complete! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77258 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| 3b07b5214ccf545ff6638d1327946c3300f1ee5f |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Sink getSectionPrefixForUniqueGlobal down into the TAI
implementations that need it, rearrange ELFTAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77236 91177308-0d34-0410-b5e6-96231b3b80d8
OFFTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 40412e7e909150af56a95c827e7de245ba52054a |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make COFF work like ELF and macho, by splitting out into its own
header even though there is only one COFF target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77204 91177308-0d34-0410-b5e6-96231b3b80d8
OFFTargetAsmInfo.h
LFTargetAsmInfo.h
|
| 33ae7a453bcb32c4ed4e8202743a4b6c875cbe73 |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
inline a method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77198 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
|
| e346694a81cbead3289d11057111fba46aa30aae |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Eliminate getNamed/getUnnamedSection, adding a new and unified getOrCreateSection
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77186 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 5fe575ff4fdefc1b003a009b1b9282526a26c237 |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Eliminate SectionFlags, just embed a SectionKind into Section
instead and drive things based off of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77184 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 0fcf4dc6d367216ff51501af282e33e93da8586f |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
untangle a TargetAsmInfo hack where ELFTargetAsmInfo would create a
'unnamed' bss section, but some impls would want a named one. Since
they don't have consistent behavior, just make each target do their
own thing, instead of doing something "sortof common" then having
targets change immutable objects later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77165 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
argetAsmInfo.h
|
| f40761d5229322c08701049f89aa10f7f7b8b743 |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove a densemap from TargetAsmInfo that was uniquing the targetflags strings,
just use a smallstring instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77144 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 37088b3f82112b1c28c713190606cf040fb056c9 |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make SectionKind keep track of whether a global had an explicit
section specified for it or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77142 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 4c50922f6be96fdb1e9a924aeeecf91638e2c52b |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make SectionKind know whether a symbol is weak or not in addition
to its classification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77140 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 37939c910fe17eef328736b3c09b6cd262095a87 |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Make the kind actually be private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77139 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 2ceb60a677065e08ec436dcb79a9d445e628a5c9 |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
rename Mergable -> Mergeable and Writable -> Writeable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77138 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 2c5815d09064dd3a03497583be3a4ec2c40853cc |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove a bunch of helper functions, just use SectionKind::get instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77135 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 5c2f789952ff315021afb10381f141f2ac3b1a6b |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
simplify getSectionForMergableConstant to take a SectionKind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77134 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| f15327290e624472a7565ac5d022767a78912ab6 |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
precreate 4/8/16 byte mergable sections to simplify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77133 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
|
| 8ca520944e1924f487561be5cd8369da0a53d8ae |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
introduce specialized mergable const sectionkinds for elements of size 4/8/16 to
simplify targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77132 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| e346e180f339ad15322f0430aab8d812cf2fe4de |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rearrange all the SectionKinds and structure them into a hierarchical
group instead of a bunch of random unrelated ideas. Provide predicates
to categorize a SectionKind into a group, and use them instead of
getKind() throughout the code.
This also renames a ton of SectionKinds to be more consistent and
evocative, and adds a huge number of comments on the enums so that
I will hopefully be able to remember how this stuff works long from
now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77129 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 8977d087c693fd581db82bcff134d12da0f48bd3 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Factor commonality in triple match routines into helper template for registering
classes, and migrate existing targets over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77126 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 38b77f8c936ca7133cf03ec8ff0decf089774244 |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
fix isReadOnly predicate to not include data that has to be
writable because of teh dynamic linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77122 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| f2769906255e47b4ce816b732096c8b1b379930f |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove a dead enum case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77121 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| abb477f66364fcaff1a79acf9d666dfdf6272a19 |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
put normal data into .data instead of .data.rel on elf systems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77116 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| fa27ff296d3694a68e7abb3b6b7629588def3e58 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill Target specific ModuleMatchQuality stuff.
- This was overkill and inconsistently implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77114 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| a5881e3060aee9f82aef3747a97650e5eafe893a |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add TargetRegistry::lookupTarget.
- This is a simplified mechanism which just looks up a target based on the
target triple, with a few additional flags.
- Remove getClosestStaticTargetForModule, the moral equivalent is now:
lookupTarget(Mod->getTargetTriple, true, false, ...);
- This no longer does the fuzzy matching with target data (based on endianness
and pointer width) that getClosestStaticTargetForModule was doing, but this
was deemed unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77111 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 30c4a3b9a896e2cbb4ef91d46f751a9c48558da4 |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
finish simplifying DarwinTargetAsmInfo::SelectSectionForGlobal
for now. Make the section switching directives more consistent
by not including \n and including \t for them all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77107 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| d60123983380532979c7ca5eef072c74b3185704 |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
simplify some predicates, add isMergableString()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77103 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 460d51e0c029814cd901a2642bcaa7d776ff5929 |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make SectionKind be a first-class pod struct instead of just
an enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77096 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| b4fc419d83bc4afc8ce5a204dd226d5ae58f5896 |
25-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
this is (unfortunately) several changes mixed together:
1. Spell SectionFlags::Writeable as "Writable".
2. Add predicates for deriving SectionFlags from SectionKinds.
3. Sink ELF-specific getSectionPrefixForUniqueGlobal impl into
ELFTargetAsmInfo.
4. Fix SectionFlagsForGlobal to know that BSS/ThreadBSS has the
BSS bit set (the real fix for PR4619).
5. Fix isSuitableForBSS to not put globals with explicit sections
set in BSS (which was the reason #4 wasn't fixed earlier).
6. Remove my previous hack for PR4619.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77085 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 4f05591e616497d88053c6b2c72d94b1365f10bd |
25-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
document some invariants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77084 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| d6fd377f3333922c4e928019cdfa124ff7f4dd2e |
25-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Simplify JIT target selection.
- Instead of requiring targets to define a JIT quality match function, we just
have them specify if they support a JIT.
- Target selection for the JIT just gets the host triple and looks for the best
target which matches the triple and has a JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77060 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 0c795d61878156817cedbac51ec2921f2634c1a5 |
25-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add new helpers for registering targets.
- Less boilerplate == good.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77052 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
argetRegistry.h
|
| fbd3d4a5c3738591b26a1a0374a8c0302f3ee991 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
fix some predicates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76999 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 0d4960c3caf64a4d83a237eaa55228c25a87bf2b |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
change SectionKindForGlobal from being a public (and
previously virtual) function to being a static function
in the .cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76997 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| b303504a562c98b3ce465d0bfcbd3d9334193e1f |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make SectionKindForGlobal target independent, and therefore non-virtual.
It's classifications now include elf-specific discriminators. Targets
that don't have these features (like darwin and pecoff) simply treat
data.rel like data, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76993 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
argetAsmInfo.h
|
| f20f250b6f1b3d4c873c4f6fa368a6ab5ace39b7 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
we already know the sectionkind when invoking SelectSectionForGlobal,
pass it in instead of recomputing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76990 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 7420ab2191432494c780dd659a3053096d6cfe53 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make SectionForGlobal non-virtual, add a hook for pic16 to do its "address=" hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76989 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 78d12644b905dc54cf6cf984af02a49d30d29744 |
24-Jul-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add support for promoting SETCC operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76987 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2dcafe4b8f84cdb0d084421f11cdca08cd6b951d |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
move ELF-specific code into ELFTargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76976 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 8adc547a91b423472148877ca5a4b5b5a0fd2f64 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make SectionFlagsForGlobal a private static function instead of a public
virtual one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76973 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 23ed52752bb40a9085c9d36bbc6603972c3e0080 |
24-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove unused member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 78717cb63dbc65f76ef2debb72ab48bbf227ef1e |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Implement getSectionPrefixForUniqueGlobal to return null, indicating that
darwin does it's own unique and special and wonderful thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76952 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
|
| 55acc6807f3349228afac27fa1a11cecd11c51b5 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Replace UniqueSectionForGlobal with getSectionPrefixForUniqueGlobal.
The later doesn't depend on any crazy LLVM IR stuff, and this
pulls the concatenation of prefix with GV name (the root problem behind
PR4584) out one level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76948 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
argetAsmInfo.h
|
| 837f3323729f91be2d62b4074fedafd7fb1ce451 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
document SectionFlags::Named better and make it more easily greppable by
eliminating isNamed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76946 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| c440cc7f2c1e1e02fb4526babc9ab99986beb6e0 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
use section flags more correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76944 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| ad733cd851efbb17cf3a4a70ec49acfc0f1c68fe |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove more bits of small section support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76937 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 013e6b63099eed7743150a57dd9eed6868b013d6 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Remove SectionKind::Small*. This was only used on mips, and is apparently
a sad mistake that is regretted. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76935 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| d2cb3d2c32b8f53bf94d56fbdd48503ace28df4b |
24-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Remove the IA-64 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76920 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 819c4f365fe2bf9be75faafa667fb22366dabaf5 |
23-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove SectionFlags::Small: it is only used on Xcore, and we'll find
a better solution for it in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76818 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| f1581564b60d3e73777545e3b10147f351614e83 |
22-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
inline the two MergeableConstSection implementations into their
only caller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76710 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
|
| 298414ec1891ce8d3a1b69e6019ad8765c8e69dc |
22-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove the SelectSectionForMachineConst hook, replacing it with
a new getSectionForMergableConstant hook. This removes one dependence
of TAI on Type, and provides the hook with enough info to make the
right decision based on whether the global has relocations etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76705 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| fc6ad402fb267cba1625801444aad30da43d383a |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it.
This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76703 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 97d2cae44bb012b51d7781fd24fdbb4e73553b61 |
22-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Now that RelocBehaviour() is never overloaded, it doesn't need to be
virtual. Just inline it into its two current call sites in preparation
for simplifying the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76686 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 82a70ccb24a09dd38ab8eaf55428880781fe9006 |
22-Jul-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Change ELFCodeEmitter logic to emit the constant pool and jump tables to
their appropriate sections before the code itself. They need to be emitted
before the function because on some targets (x86 but not x86_64) the later
may reference a JT or CP entry address
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76672 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| 939a8907eda969687bc2b28be85f8f4fc204c982 |
22-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make some stuff private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76661 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
|
| bdf7a3ade1041e10b2f94f4ef093d040dc32663a |
22-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
improve comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76660 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 7886ae9e3ca7ec20eceb213523a6788d368cfc73 |
21-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
inline a trivial method into its only call site and fix indentation of cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76654 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
|
| 42b6418cc0ed26123a7b838182d41aa940481c04 |
21-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Remove some overridden functions in XCoreTargetAsmInfo that are
implemented exactly the same way as its ELFTargetAsmInfo subclass
has them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76653 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
|
| b3e717192635873a0d8491fc45ddb64c0e4bda15 |
21-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove shift amount flavor. It isn't actually complete enough to
be useful, and it's currently unused. (Some issues: it isn't actually
rich enough to capture the semantics on many architectures, and
semantics can vary depending on the type being shifted.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76633 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 90f8b7073dd472afb21bc33be0f24391e7a4505b |
21-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rename LessPrivateGlobalPrefix -> LinkerPrivateGlobalPrefix to match the
LLVM IR concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76590 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 76081c4ef7ac6f085253a4af3af740333b6dfc5b |
21-Jul-2009 |
David Greene <greened@obbligato.org> |
Re-apply 75490, 75806 and 76177 with fixes and tests. Efficiency comes
next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76486 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 2f70f1a1d8946a55b99ade6fd1c01ae18211fbd7 |
20-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove FIXME that was already fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76457 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a3af370dc12f6d5100da5d614ab0a62da135569a |
20-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add MCAsmParser interface.
- This provides the AsmParser interface to the target specific assembly
parsers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76453 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
|
| 1902fd9605ab33798408405e840be3d9bdebbd90 |
20-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove TargetAsmInfo::ExpandInlineAsm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76445 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| b8105651527670cb456eb46dd4346bacd3905361 |
20-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Copy ExpandInlineAsm to TargetLowering from TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76441 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ff3d3adddbb6ef6ea4897b52d24c09e57596bb3c |
20-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add some fixme's and cleanups. TargetAsmInfo shouldn't depend on VMCore eventually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76439 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 8f4e22ff9a17b750fef179ed1572e9bfd01ed9a2 |
20-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove dead forward decl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76433 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 83757c7fb51bd60a8c264fba24a0b6f1b01efdd3 |
20-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
rename TargetAsmInfo::getASDirective -> getDataASDirective
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76431 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 0a38dc5fda9a22aceecccbad2f024b118ce1d5d8 |
20-Jul-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
For PC relative relocations where symbols are defined in the same section they
are referenced, ignore the relocation entry and patch the relocatable field with
the computed symbol offset directly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76414 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| e2b0ecd8be031685a4fe63633235eceae7f1c4fa |
19-Jul-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use R_X86_64_32S to handle Jump Table Index relocation entries. Hide TAI usage inside getSection* functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76347 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| edcb540496ca798003d9fece8cf4e57d536afa38 |
19-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add some missing includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76346 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 617dd7baa6dfd3a7b5ee72ace37f6b6aeaa6006b |
18-Jul-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use a better name for the label relocations while emitting them for Jump Tables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76334 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| 171375f73a733edcd7a5f839491cc8da4fdeddfe |
18-Jul-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support to properly reference private symbols on relocation entries.
Use proper relocation type to build relocations for JumpTables (rodata
sections).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76326 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| 5248468473f0488a652b545ad95f7abda302b7b5 |
18-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable cross register class coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76281 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 3837b64f4152bd074013c19b024b94ff52157a65 |
18-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert 76177 for now. It's messing up ARM asm printing. Also this significant debate about its efficiency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76279 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| cbdf0e2455d78b047aec4141ec84cf96095bee16 |
18-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add llvm::InitializeAllTargetInfos and llvm::InitializeAllAsmParsers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76253 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| e2cf37b88c089a71727b3ecd466856f0cd638813 |
17-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Untangle a snarl that I discovered when updating the mangler,
starting in getCurrentFunctionEHName. Among other problems,
we would try to privative a "foo.eh" label, but end up emitting
the label as _Lfoo.eh instead of L_foo.eh on darwin. This is really
bad, and the linker has always tolerated these labels existing.
For now, just emit them as _foo.eh.
This patch also fixes problems with ".eh" labels on unnamed
functions and eliminates two strangely defined TargetAsmInfo
hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76231 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 092a9dda2d13918a6410db26f41c7b5aa97ff989 |
17-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Sketch support for target specific assembly parser.
- Not fully enabled yet, need a configure regeneration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76230 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmParser.h
argetRegistry.h
|
| ab9238e876dcf6da101d8ae626925bcd9e537a7e |
17-Jul-2009 |
David Greene <greened@obbligato.org> |
Add logic to align instruction operands to columns for pretty-printing.
No target uses this currently. This patch only adds the mechanism so
that local installations can choose to enable this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76177 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 378445303b10b092a898a75131141a8259cff50b |
16-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| ff9834ab9daeee25dbb67ae5e2341930cde46c86 |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill off last uses of TargetMachineRegistry class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75892 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| c981da0192ab42d28f1034f2a7fa9cbab096425a |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix gcc 4.0 build failure, can't rely on access inside nested friended class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75891 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 603bea32743dc9914a1d32ae36fc64fe497af801 |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add registered target list to --version output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75889 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 4ce78ee3be4dd55e2ab7df7e6ad32f92e3749c45 |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add explicit comment that clients can call target initialization functions
multiple times.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75880 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| 5d77cad60bd82dfa2d00f78e26443d667922efbf |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Lift addAssemblyEmitter into LLVMTargetMachine.
- No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75859 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| cfe9a605eea542d91e3db74289b69b7e317d90a6 |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Lift DumpAsm / -print-emitted-asm functionality into LLVMTargetMachine.
- No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75848 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 51b198af83cb0080c2709b04c129a3d774c07765 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Reapply TargetRegistry refactoring commits.
--- Reverse-merging r75799 into '.':
U test/Analysis/PointerTracking
U include/llvm/Target/TargetMachineRegistry.h
U include/llvm/Target/TargetMachine.h
U include/llvm/Target/TargetRegistry.h
U include/llvm/Target/TargetSelect.h
U tools/lto/LTOCodeGenerator.cpp
U tools/lto/LTOModule.cpp
U tools/llc/llc.cpp
U lib/Target/PowerPC/PPCTargetMachine.h
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/PowerPC/PPCTargetMachine.cpp
U lib/Target/PowerPC/PPC.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/ARMTargetMachine.h
U lib/Target/ARM/ARM.h
U lib/Target/XCore/XCoreTargetMachine.cpp
U lib/Target/XCore/XCoreTargetMachine.h
U lib/Target/PIC16/PIC16TargetMachine.cpp
U lib/Target/PIC16/PIC16TargetMachine.h
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/Alpha/AlphaTargetMachine.cpp
U lib/Target/Alpha/AlphaTargetMachine.h
U lib/Target/X86/X86TargetMachine.h
U lib/Target/X86/X86.h
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.h
U lib/Target/CppBackend/CPPTargetMachine.h
U lib/Target/CppBackend/CPPBackend.cpp
U lib/Target/CBackend/CTargetMachine.h
U lib/Target/CBackend/CBackend.cpp
U lib/Target/TargetMachine.cpp
U lib/Target/IA64/IA64TargetMachine.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/IA64/IA64TargetMachine.h
U lib/Target/IA64/IA64.h
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/CellSPU/SPUTargetMachine.h
U lib/Target/CellSPU/SPU.h
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/CellSPU/SPUTargetMachine.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
U lib/Target/Mips/MipsTargetMachine.cpp
U lib/Target/Mips/MipsTargetMachine.h
U lib/Target/Mips/Mips.h
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Sparc/SparcTargetMachine.cpp
U lib/Target/Sparc/SparcTargetMachine.h
U lib/ExecutionEngine/JIT/TargetSelect.cpp
U lib/Support/TargetRegistry.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75820 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetMachineRegistry.h
argetRegistry.h
argetSelect.h
|
| 2286f8dc4cec0625f7d7a14e2570926cf8599646 |
15-Jul-2009 |
Stuart Hastings <stuart@apple.com> |
Revert 75762, 75763, 75766..75769, 75772..75775, 75778, 75780, 75782 to repair broken LLVM-GCC build.
Will revert 75770 in the llvm-gcc trunk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75799 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetMachineRegistry.h
argetRegistry.h
argetSelect.h
|
| 8cb6626df19ab54531717b419839c2a42d61f180 |
15-Jul-2009 |
Duncan Sands <baldrick@free.fr> |
Remove StringConstantPrefix now that the only user
(llvm-gcc) has gone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75781 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 6c05796294a7a0693d96c0c87194b9d5ddf55a94 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill off old (TargetMachine level, not Target level) match quality functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75780 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 03f4bc5d6cf777c8aa559c299ef7f85126872881 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Provide TargetMachine implementations with reference to Target they were created
from.
- This commit is almost entirely propogating the reference through the
TargetMachine subclasses' constructor calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75778 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetMachineRegistry.h
argetRegistry.h
|
| 6501145ec6b4e555d23a835631a848ea35b59226 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill off unused TargetMachineRegistry methods and ivars.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75774 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
argetRegistry.h
|
| 54785e6df01aa239759a5717d7cc115387e34559 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Migrate llc and the JIT to using the TargetRegistry for lookups.
- They still use the TargetMachineRegistry to populate the contents of the
-march option (via the listener interface). We can't just populate it in the
option parser because we can't expect the TargetRegistry to be populated yet
(we no longer rely on static constructors).
- There are a couple ways to finish killing off TargetMachineRegistry, but I
haven't figured out the cleanest one yet...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75773 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 4d1be777f81137bab98025d1c37c08ef0ec2f204 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Include the Target& in the TargetMachineRegisterEntry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75772 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| 3fb7eee9c210bcfd674e78c70244e3f42473c19b |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Allow multiple registrations of the same target.
- This doesn't necessarily seem like a good idea, but the JIT unittest
currently relies on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75769 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| aca81c49d9644105551e129d8b12758a08a1deb2 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Initialize the target info via the InitializeNativeTarget() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75768 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| e0bda7df1abc5772228ecd287401806f19faae2a |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Reimplement TargetMachineRegistry in terms of TargetRegistry.
- This is a temporary hack to aid in incremental refactoring, for now we
allocate a new TargetMachineRegistryEntry on every getClosest... call.
- No intended functionality change, other than the leaked memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75766 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 488363036029c3743f3e28122f8e7237c01e4df5 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Mark Target's creation routines as const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75763 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 4246790aa84a530b0378d917023584c2c7adb4a9 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Register Target's TargetMachine and AsmPrinter in the new registry.
- This abuses TargetMachineRegistry's constructor for now, this will get
cleaned up in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75762 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| 7a46d7898e3eff918c945131ca2ca705885f2552 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix thinko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75760 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 6461716b508d9e086641dac727a6e918b833f583 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Include Target specific Info initialization routine when initializing all
targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75756 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| 73b3ec41349511dbf28c18997e3f64761ff0f114 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Address some review comments on TargetRegistry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75753 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| bb061291406b1b9f0c976e9845f69f9faf985606 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add new TargetRegistry.
Targets implement a single global Target structure which will live in a new
<Target>/TargetInfo library; this will be present in any image which the target
is usable in.
- Optional target specific classes can then be registered and attached to the
Target description.
- Registration for normal Targets will be done via the initialization functions
instead of using static constructors.
- This allows clients to use a single interface to obtain target data, without
requiring the code generator be linked in. It also provides a natural
extension point for adding new optional target data (assembler parser,
disassembler, etc.).
- This also provides a new entry point for obtaining a target for a particular
triple (without a module).
- Not yet used, however this should eventually replace the TargetMachineRegistry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75739 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegistry.h
|
| 71847813bc419f7a0667468136a07429c6d9f164 |
14-Jul-2009 |
David Greene <greened@obbligato.org> |
Have asm printers use formatted_raw_ostream directly to avoid a
dynamic_cast<>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75670 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| c23197a26f34f559ea9797de51e187087c039c42 |
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 2e4da5e4abbccafd1a79eed57829826072a275be |
13-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Delete a spurious const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75493 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 014700c1a8cba203fd21ff129426ba8a426ab244 |
13-Jul-2009 |
David Greene <greened@obbligato.org> |
Add infrastructure to allow post instruction printing action triggers.
We'll eventually use this to print comments in asm files and do other
fun things.
This adds interfaces to the AsmPrinter and changes TableGen to invoke
the postInstructionAction when appropriate. It also add parameters to
TargetAsmInfo to control comment layout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75490 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| ee787ff01a09e8d47b4ae179fedc1622df441612 |
12-Jul-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add CCIfSRet calling convention predicate.
The blackfin calling convention uses a different register for sret arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75417 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.td
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
argetInstrInfo.h
|
| 261ce1d5f89155d2e6f914f281db2004c89ee839 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove TargetInstrInfo::CommuteChangesDestination and added findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75264 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| bfa5cf144a6e2e53442418746a495f22ba8c72d2 |
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75226 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 910139f9ca53fc20a680d51ae61bb1e072095141 |
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Targets sometimes assign fixed stack object to spill certain callee-saved
registers based on dynamic conditions. For example, X86 EBP/RBP, when used as
frame register has to be spilled in the first fixed object. It should inform
PEI this so it doesn't get allocated another stack object. Also, it should not
be spilled as other callee-saved registers but rather its spilling and restoring
are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75116 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| ac57e6e498abccb117e0d61c2fa0f733845e50cb |
06-Jul-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add the Object Code Emitter class. Original patch by Aaron Gray, I did some
cleanup, removed some #includes and moved Object Code Emitter out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74813 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 98749f851d64f6387caeeb0780d1750341e3a6a0 |
03-Jul-2009 |
Duncan Sands <baldrick@free.fr> |
In this unreachable code, return an initialized value.
This stops gcc warning about possible uses of an uninitialized
value when compiling with assertions turned off.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74775 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ffd0200abfd63177257f949a3674b91dcf87bf23 |
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Implement the SVR4 ABI for PowerPC.
Implement LowerFORMAL_ARGUMENTS_SVR4().
Implement LowerCALL_SVR4().
Add support for split arguments.
Implement by value parameter passing for aggregates.
Add support for variable argument lists.
Create the spill area for argument registers of variable argument functions no longer at a fixed offset.
Make sure callee saved registers are spilled to the correct stack offsets.
Change allocation order of non-volatile floating-point registers.
Add VRSAVE to the list of callee-saved registers, add CallConvLowering for vararg calls.
Add support for variable argument calls with Vector arguments.
Add support for VR and VRSAVE save area, improve allocation order for non-volatile vector registers.
Stop creating illegal i8 values in LowerVASTART().
Add memory access width hints.
Make sure to reserve space on the stack for the frame pointer.
When using the SVR4 ABI, reserve r13 for the Small Data Area pointer.
Assure that the frame pointer is spilled to the correct location on the stack.
Some FP registers were not marked as volatile.
Make sure the i64 words from a long double are passed either both in registers or both on the stack.
Only put integer arguments in registers which are not marked with the inreg flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74765 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.td
|
| 6b61cd185eeb90bec93f042535594132ae1f0f41 |
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.
With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74764 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3d62a412fbe517fbbbf5661ef1a748a39f382aa3 |
02-Jul-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove getFunctionAlignment from TargetELFInfo and use new MachineFunction alignment method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74686 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| b4202b84d7e54efe5e144885c7da63e6cc465f80 |
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 20c568f366be211323eeaf0e45ef053278ec9ddc |
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 02a6218774832508a4d1ef2998dc60f69a55729a |
25-Jun-2009 |
David Greene <greened@obbligato.org> |
Increase limit for OpActions array
The OpActions array had a limit of 32 value types, so change it to use
MVT::MAX_ALLOWED_VALUETYPE in its declaration and change the accesses to
this array to work with a VT.getSimpleVT() that is larger than 32.
Also, add a comment to the place where MVT::MAX_ALLOWED_VALUETYPE is
defined indicating that it must be a multiple of 32.
This is part of the work allow MVT::LAST_VALUETYPE be greater than 32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74130 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f2e19d5dcfa13472493bb18339555686182b7df9 |
24-Jun-2009 |
David Greene <greened@obbligato.org> |
This increases the maximum for MVT::LAST_VALUETYPE
This change doubles the allowable value for MVT::LAST_VALUETYPE. It does
this by doing several things.
1. Introduces MVT::MAX_ALLOWED_LAST_VALUETYPE which in this change has a
value of 64. This value contains the current maximum for the
MVT::LAST_VALUETYPE.
2. Instead of checking "MVT::LAST_VALUETYPE <= 32", all of those uses
now become "MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_LAST_VALUETYPE"
3. Changes the dimension of the ValueTypeActions from 2 elements to four
elements and adds comments ahead of the declaration indicating the it is
"(MVT::MAX_ALLOWED_LAST_VALUETYPE/32) * 2". This at least lets us find
what is affected if and when MVT::MAX_ALLOWED_LAST_VALUETYPE gets
changed.
4. Adds initializers for the new elements of ValueTypeActions.
This does NOT add any types in MVT. That would be done separately.
This doubles the size of ValueTypeActions from 64 bits to 128 bits and
gives us the freedom to add more types for AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74110 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a96751fc8ff1cc9a225ffbba73de53e2b9e1ae35 |
24-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Provide InitializeAllTargets and InitializeNativeTarget functions in the
C bindings. Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74026 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| bcba7f95c2c79eb6526b3729b08f9e881a11e858 |
23-Jun-2009 |
Douglas Gregor <dgregor@apple.com> |
Work around build problem with OpenJDK, which defines X86 as a
macro. Fixes PR 4427. Patch by Xerxes Rånby!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73961 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| 0d3193ef3ce7377eeaa1d38ca08f8a62ebcd5f63 |
22-Jun-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add more methods to gather target specific elf stuff
Support for .text relocations, implementing TargetELFWriter overloaded methods for x86/x86_64.
Use a map to track global values to their symbol table indexes
Code cleanup and small fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73894 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| c12430644a9f49a056286f8ebe0e55ccc23bdde0 |
20-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
implement support for lowering subregs when preparing to print
LEA64_32r, eliminating a bunch of modifier logic stuff on addr modes.
Implement support for printing mbb labels as operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73817 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
|
| 1e86a66b00b94adc4ad6977ef6b47c516ac62cec |
20-Jun-2009 |
Devang Patel <dpatel@apple.com> |
mv CodeGen/DebugLoc.h Support/DebugLoc.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73786 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4e0f25b603c96ce43474441e99252c5cd88c2e2e |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
merge the common darwin settings from the X86/PPC/ARM targets
into DarwinTargetAsmInfo.cpp. The remaining differences should
be evaluated. It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73742 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
argetAsmInfo.h
|
| a93ca92379129e87e0130609ac78422fcf6dd21e |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
move mangler quote handling from asm printers to TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73738 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| b839c3f577e03467bce8904eb2a02b124ec19ec8 |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
simplify macro debug info directive handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73736 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4 |
18-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 5f1a5c7f57ce37e4fd6cca09d3c03ce9a34b6282 |
17-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
Add a utility header that makes it easy to link in the right set
of targets for various purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73610 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelect.h
|
| 0d492bdf4d07db79e240c3c21c5321416f1463d1 |
16-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Address more comments :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73430 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 52edfc7a6d320482e17b1e03b39217f2e167efc9 |
15-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Document ABIType enum. Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73427 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 358dec51804ee52e47ea3a47c9248086e458ad7c |
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 90f95f88c6ce09c6744777dc9d140c3c77203b92 |
14-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| ae9163f0e24d032f99b978d31ea810a1d441f7e2 |
14-Jun-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Introduce new BinaryObject (blob) class, ELF Writer modified to use it. BinaryObject.h by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73333 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| d00d4159d4fb7208cd4207a3d1e4ccf5bc02f74f |
12-Jun-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use forward declarations and move TargetELFWriterInfo impl to a new file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73209 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| c997d45ae5d2e25643d3ccc2c4ae44dcca6cdf5b |
11-Jun-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Support for ELF Visibility
Emission for globals, using the correct data sections
Function alignment can be computed for each target using TargetELFWriterInfo
Some small fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73201 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| f5aefbdb79886e64878500e13506fe61389b4c7b |
09-Jun-2009 |
David Greene <greened@obbligato.org> |
Change IndexedModeAction representation.
This changes the IndexedModeAction representation to remove the
limitation on the number of value types in MVT. This limitation
prevents us from specifying AVX types.
Prior to this change IndexedModActions was represented as follows...
uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
the first dimension was used to represent loads, then stores. This
imposed a limitation of 32 on the number of value types that could be
handled with this method. The value type was used to shift the two bits
into and out of the approprate bits in the uint64_t.
With this change the array is now represented as ...
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
Takes more space but removes the limitation on MVT::LAST_VALUETYPE. The
first dimension is now the value_type for the reference. The second
dimension is the load [0] vs. store[1]. The third dimension represents
the various modes for load store. Accesses are now direct, no shifting
or masking.
There are other limitations that need to be removed, so that
MVT::LAST_VALUETYPE can be greater than 32. This is merely the first
step towards that goal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73104 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 63ec51d86ba6d6ae7bdd795bf783e3f27b9e16f8 |
09-Jun-2009 |
David Greene <greened@obbligato.org> |
Oops, didn't mean to commit 73102 yet. Revert it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73103 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9df4eb8cfecec9dd15b6fde5983e046d81e646dc |
09-Jun-2009 |
David Greene <greened@obbligato.org> |
Change IndexedModeAction representation.
This changes the IndexedModeAction representation to remove the
limitation on the number of value types in MVT. This limitation
prevents us from specifying AVX types.
Prior to this change IndexedModActions was represented as follows...
uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
the first dimension was used to represent loads, then stores. This
imposed a limitation of 32 on the number of value types that could be
handled with this method. The value type was used to shift the two bits
into and out of the approprate bits in the uint64_t.
With this change the array is now represented as ...
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
Takes more space but removes the limitation on MVT::LAST_VALUETYPE. The
first dimension is now the value_type for the reference. The second
dimension is the load [0] vs. store[1]. The third dimension represents
the various modes for load store. Accesses are now direct, no shifting
or masking.
There are other limitations that need to be removed, so that
MVT::LAST_VALUETYPE can be greater than 32. This is merely the first
step towards that goal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73102 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0eebf653a7b2978e7761f8d068b6fbec22aea0f6 |
09-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetOptions.h
|
| e1b469170bb3ab259fd488fb95c29efe802cdd6a |
08-Jun-2009 |
David Greene <greened@obbligato.org> |
Make IntInits and ListInits typed. This helps deduce types of !if and
other operators. For the rare cases where a list type cannot be
deduced, provide a []<type> syntax, where <type> is the list element
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73078 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| f5b0c5a1c735dd2a6027edcca83cddc6d755bdc2 |
06-Jun-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove elf specific info from ELFWriter.h to Elf.h. Code cleanup and more comments added
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72982 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| 578efa920abd218ba75a0fb3c9b8398f4c0a774b |
05-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Add new function attribute - noimplicitfloat
Update code generator to use this attribute and remove NoImplicitFloat target option.
Update llc to set this attribute when -no-implicit-float command line option is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72959 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetOptions.h
|
| abc019968067736a499467f7db7fb758a425ca06 |
05-Jun-2009 |
Nate Begeman <natebegeman@mac.com> |
Adapt the x86 build_vector dagcombine to the current state of the legalizer.
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.
Teach the build_vector dag combine in x86 back end to recognize consecutive
loads producing the low part of the vector.
Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.
Add a testcase for the transform.
Old:
subl $28, %esp
movl 32(%esp), %eax
movl 4(%eax), %ecx
movl %ecx, 4(%esp)
movl (%eax), %eax
movl %eax, (%esp)
movaps (%esp), %xmm0
pmovzxwd %xmm0, %xmm0
movl 36(%esp), %eax
movaps %xmm0, (%eax)
addl $28, %esp
ret
New:
movl 4(%esp), %eax
pmovzxwd (%eax), %xmm0
movl 8(%esp), %eax
movaps %xmm0, (%eax)
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72957 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d18e31ae17390d9c6f6cf93d18badf962452031d |
05-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Add new function attribute - noredzone.
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72894 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 874ae251c317788391f9c3f113957802d390a063 |
02-Jun-2009 |
Dale Johannesen <dalej@apple.com> |
Revert 72707 and 72709, for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetSelectionDAG.td
|
| 4150d83abe90a5da4ddf86433b7bf4329acfa57c |
02-Jun-2009 |
Dale Johannesen <dalej@apple.com> |
Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.
Most targets will still produce a Flag-setting target-dependent
version when selection is done. X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted. All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly. The
same can be done on other targets.
The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetSelectionDAG.td
|
| a3f99f90338d89354384ca25f53ca4450a1a9d18 |
30-May-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
First patch in the direction of splitting MachineCodeEmitter in two subclasses:
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
argetMachine.h
|
| 4d4eab219a96203f58452b39b4e94e234dfe4007 |
30-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72603 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| abdbc57abb2e2d0df4145d7abb06883a33512684 |
29-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Default isNarrowingProfitable to false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72561 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8b944d39b356135676459152385f05c496951f6c |
28-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
e.g.
orl $65536, 8(%rax)
=>
orb $1, 10(%rax)
Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 41a024385f1220eadc48b48cb4c044a5fbc1b361 |
23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate CPU string out of SubtargetFeatures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 6ebf7bc7405ee79d27d50b70f0c1a474cbea820d |
13-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Run code placement optimization for targets that want it (arm and x86 for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71726 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f46ef0450f5136b4e5267c084451e3786f817b64 |
12-May-2009 |
Dan Gohman <gohman@apple.com> |
Clarify a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71561 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 8d730fbde54b7ac9809fc12852c2a8d30f5bec3d |
11-May-2009 |
Jay Foad <jay.foad@gmail.com> |
Don't #include DerivedTypes.h from TargetData.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71468 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 20b7ca1eb9ed1f7bbc6e1b263fbf2b9ad364db9e |
11-May-2009 |
Dan Gohman <gohman@apple.com> |
Add a comment about the special meaning of VoidTy in this context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71466 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7524b5906267e8ea8322c2ef4334f6e3bf0e6d24 |
11-May-2009 |
Jay Foad <jay.foad@gmail.com> |
Change TargetData::getIntPtrType() to return an IntegerType instead of
just a Type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71426 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 777d2306b36816a53bc1ae1244c0dc7d998ae691 |
09-May-2009 |
Duncan Sands <baldrick@free.fr> |
Rename PaddedSize to AllocSize, in the hope that this
will make it more obvious what it represents, and stop
it being confused with the StoreSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71349 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 2a6e0a2140f3fc3597fdefa8c4179a230b29b267 |
08-May-2009 |
Duncan Sands <baldrick@free.fr> |
Add some examples to show the difference between
the various notions of type size used in LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71230 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| d923fc621ff5b5e500977edf9236c9e34e8d7ebc |
05-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70950 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| c781a243a3d17e7e763515794168d8fa6043f565 |
03-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.
Not yet enabled. This is part 1. More coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70787 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetRegisterInfo.h
|
| ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357 |
30-Apr-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
getCommonSubClass() - Calculate the largest common sub-class of two register
classes.
This is implemented as a function rather than a method on TargetRegisterClass
because it is symmetric in its arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70512 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 581b93415ef207a2103913e24874889426b1063e |
30-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Remove unused flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70459 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| b8cb0bb08c7f9f2dfcdfa5f7d72a4c56a9c93228 |
30-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Remove LTO optimization level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70445 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 98a366d547772010e94609e4584489b3e5ce0043 |
30-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| b27fa0afe282d74b919259fe83b2979b4f5c308b |
29-Apr-2009 |
Sanjiv Gupta <sanjiv.gupta@microchip.com> |
Add directive to declare external globals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70379 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 5a5ca1519e04310f585197c20e7ae584b7f2d11f |
29-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
Implement review feedback for vector shuffle work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70372 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b |
29-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| a24d1b155831d25f543e0e4ece9b572cefda2f17 |
29-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Correct comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70340 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 8a8a0dfc3b200e193db14ea1e6f1a18bf4187866 |
28-Apr-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getMatchingSuperReg() out of coalescer and into TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70309 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| fa4677b483b85217ac216f7e8d401c40cbe348aa |
28-Apr-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move getSubRegisterRegClass from ScheduleDagSDNodesEmit.cpp to a TargetRegisterClass method.
Also make the method non-asserting. It will return NULL when given an invalid subreg index.
The method is needed by an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70296 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| c69d56f1154342a57c9bdd4c17a10333e3520127 |
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
r70270 isn't ready yet. Back this out. Sorry for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetOptions.h
|
| 2e9d5f912a9841d3685ba0241abe1131943fed29 |
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetOptions.h
|
| 9008ca6b6b4f638cfafccb593cbc5b1d3f5ab877 |
27-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetSelectionDAG.td
|
| 15684b29552393553524171bff1913e750f390f8 |
24-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert 69952. Causes testsuite failures on linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetSelectionDAG.td
|
| b706d29f9c5ed3ed9acc82f7ab46205ba56b92dc |
24-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetSelectionDAG.td
|
| 276944ef309ce43286120fb580eda78d6762a67e |
17-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Delete an unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69375 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 1f595bb42950088ccb8246e6b065a96027b46ec6 |
17-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use CallConvLower.h and TableGen descriptions of the calling conventions
for ARM. Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
argetCallingConv.td
|
| 7beace5d061b05bbe5fff24ad46c9d1bbafc2675 |
15-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Fix doxygen comment syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69128 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 88c7af096b09ad26cbcebfdf40151e04094b7460 |
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrInfo.h
|
| 0f7fef3872a37d09c806f52f1d03d74ebc73c171 |
13-Apr-2009 |
Devang Patel <dpatel@apple.com> |
Reapply 68847.
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68964 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| f8c7394781f7cf27ac52ca087e289436d36844da |
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.
Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.
Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrInfo.h
argetRegisterInfo.h
|
| 73099b105869f02ece79c2cea982286744635c4a |
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Add comments to INSERT_SUBREG, EXTRACT_SURBEG, SUBREG_TO_REG,
and IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68949 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| ddeed50d76e2ad52d3ccb3664d21dfe1463179c6 |
13-Apr-2009 |
Owen Anderson <resistor@mac.com> |
Use a hashtable for TargetRegisterClass::contains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68922 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 0461c0a8f5b476794a061e995210906670a4542d |
12-Apr-2009 |
Chris Lattner <sabre@nondot.org> |
Add new TargetInstrDesc::hasImplicitUseOfPhysReg and
hasImplicitDefOfPhysReg methods. Use them to remove a
look in X86 fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68886 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| c6fa3ff0bddca92e443ef9ff454d2a74cac867bd |
11-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Revert r68847. It breaks the build on non-Darwin targets, with this message
from the assembler:
Error: unknown pseudo-op: `.debug_inlined'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68863 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 2057532679fc1045cfeb38b477ac9e749e6b1dd8 |
11-Apr-2009 |
Devang Patel <dpatel@apple.com> |
Keep track of inlined functions and their locations. This information is collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.)
Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68847 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 3ca15c989ca0e09085648771db368d8c94ee1f19 |
10-Apr-2009 |
Owen Anderson <resistor@mac.com> |
Give register alias checking the hash table treatment too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68730 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| d9df5017040489303acb57bdd8697ef0f8bafc08 |
09-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| 7d770be047059d624f37c6fb1e5b1d0f2b4961b3 |
09-Apr-2009 |
Owen Anderson <resistor@mac.com> |
Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68669 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 97121ba2afb8d566ff1bf5c4e8fc5d4077940a7f |
08-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 30eae3c02244e18747f9f0dca6946d86d0ccb7f5 |
07-Apr-2009 |
Jim Grosbach <grosbach@apple.com> |
PR2985 / <rdar://problem/6584986>
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 41c90738e9e7e2111fbc31944b5ce2676830f267 |
03-Apr-2009 |
Chris Lattner <sabre@nondot.org> |
"This adds a getName() method to TargetRegisterClass, just like in TargetRegisterInfo.
This makes debugging register classes a bit easier."
Patch by Jakob Stoklund Olesen!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68400 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 8f9643f0f768d5dcff0ffea1de6191dba1b5b083 |
03-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.
Note that these are distinct from TargetInstrInfo::INSERT_SUBREG
and TargetInstrInfo::EXTRACT_SUBREG, which are used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68355 91177308-0d34-0410-b5e6-96231b3b80d8
argetSelectionDAG.td
|
| fca82deecb1e1909a97db41cf324bf70e39af1e5 |
30-Mar-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Do not propagate ELF-specific stuff (data.rel) into other targets. This simplifies code and also ensures correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68032 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
|
| 71a7c6cde01fb516f0cbdbd831e07cda063fed4e |
30-Mar-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add data.rel stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68031 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
argetAsmInfo.h
|
| db2323148b959ffcaf7a3498f94de5fa6d3e6eb7 |
29-Mar-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Honour relocation behaviour stuff for ro objects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68005 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| e75fd69f15dc1b35d20b12d0e765ea6f2b9ffe0b |
28-Mar-2009 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Enable tail call optimization for functions that return a struct (bug 3664) and for functions that return types that need extending (e.g i1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67934 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0b0cd9113af42c422c829563c3b12e6e52bd2d79 |
28-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
x * 40
=>
shlq $3, %rdi
leaq (%rdi,%rdi,4), %rax
This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq (%rdi,%rdi,2), %rax
leaq (%rsi,%rax,8), %rax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67917 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 42bf74be1402df7409efbea089310d4c276fde37 |
25-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetOptions.h
|
| bc65ca8de591e278fc613b5dc0e178b2ddcd215e |
20-Mar-2009 |
Mon P Wang <wangmp@apple.com> |
Added option to enable generating less precise mad (multiply addition)
for those architectures that support the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67363 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| f9abd7e33ea6e8f57176d0069d61595c1347a5ff |
11-Mar-2009 |
Bill Wendling <isanbard@gmail.com> |
Add a -no-implicit-float flag. This acts like -soft-float, but may generate
floating point instructions that are explicitly specified by the user.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66719 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 0f8b53f19d29013ab18f3d444cea1e6305405611 |
03-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of Doxygen syntax issues. Escape special characters,
and put @file directives on their own comment line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65920 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9a58023c6ce1e77447a21d07a3de4c1ac98a3d24 |
27-Feb-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Refactor TLS code and add some tests. The tests and expected results are:
pic | declaration | linkage | visibility |
!pic | declaration | external | default | tls1.ll tls2.ll | local exec
pic | declaration | external | default | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default | tls3.ll tls4.ll | initial exec
pic | !declaration | external | default | tls3-pic.ll tls4-pic.ll | general dynamic
!pic | declaration | external | hidden | tls7.ll tls8.ll | local exec
pic | declaration | external | hidden | X | local dynamic
!pic | !declaration | external | hidden | tls9.ll tls10.ll | local exec
pic | !declaration | external | hidden | X | local dynamic
!pic | declaration | internal | default | tls5.ll tls6.ll | local exec
pic | declaration | internal | default | X | local dynamic
The ones marked with an X have not been implemented since local dynamic is not implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65632 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0d52ff1f7b993750a74a5d4432273092de9af069 |
25-Feb-2009 |
Mon P Wang <wangmp@apple.com> |
Added support to have TableGen provide information if an intrinsic (core
or target) can be overloaded or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65404 91177308-0d34-0410-b5e6-96231b3b80d8
argetIntrinsicInfo.h
|
| c1c9d7e6a95e2090d74f271209fc9337e74ab9bf |
19-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Describe tail merging's use of InsertBranch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65062 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| d6b7a242d345fd79a337afd384bb586c5619cfe7 |
18-Feb-2009 |
Nate Begeman <natebegeman@mac.com> |
Add support to the JIT for true non-lazy operation. When a call to a function
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT. The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd. A new interface for allocating and
updating empty stubs is provided.
Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.
Add support under a new ExecutionEngine flag for emitting the infomration
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue. This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64906 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 865f006bb45a609e1cb6acb653af3fe5442ee4dc |
18-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Eliminate several more unnecessary intptr_t casts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64888 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| dc54d317e7a381ef8e4aca80d54ad1466bb85dda |
09-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 1fdbc1dd4e9cb42c79a30e8dc308c322e923cc52 |
07-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 37059d52b7e51577ad2970e0ed00f230788fde18 |
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
We don't really need the abort here. This unbreak x86_64 linux build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63940 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 770bcc7b15adbc978800db70dbb1c3c22913b52c |
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetRegisterInfo.h
|
| 4350eb86a7cdc83fa6a5f4819a7f0534ace5cd58 |
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63936 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b3a021cdb3d26ddb2985e326ba0cb96761b86f69 |
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change -1 => negative number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63935 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 6f8d762e6bad72b2ab9ff710cca3abb0a658fdf0 |
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Document the meaning of -1 for getCopyCost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63933 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 758d20f653302ca2fd64f2c13b501156525093d2 |
05-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Clarify comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63851 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| 49de98214b82fefeb8f16efbf8cdd8813a85469b |
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Reapply 63765. Patches for clang and llvm-gcc to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63812 91177308-0d34-0410-b5e6-96231b3b80d8
argetIntrinsicInfo.h
argetMachine.h
|
| 4d452de1506344bf1d28bb4a8c4ddb78c51a28c8 |
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Reverting 63765. This broke the build of both clang
and llvm-gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63786 91177308-0d34-0410-b5e6-96231b3b80d8
argetIntrinsicInfo.h
argetMachine.h
|
| d24479730a8790d82c4859dc477bc2416d7a6bda |
04-Feb-2009 |
Nate Begeman <natebegeman@mac.com> |
New feature: add support for target intrinsics being defined in the
target directories themselves. This also means that VMCore no longer
needs to know about every target's list of intrinsics. Future work
will include converting the PowerPC target to this interface as an
example implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63765 91177308-0d34-0410-b5e6-96231b3b80d8
argetIntrinsicInfo.h
argetMachine.h
|
| e20e790074f6a8274f5c8ad607ed3fbd1c6626c6 |
04-Feb-2009 |
Chris Lattner <sabre@nondot.org> |
add a friend needed by a stringmap change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63706 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 0f502f6f44f2756f5cb7b17d8f1d8eae000d51b4 |
03-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Add some DL propagation to places that didn't
have it yet. More coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63673 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ff97d4fe81ef0dcee9fe490bed8ab08e40251905 |
03-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Propagation in TargetLowering. Includes passing a DL
into SimplifySetCC which gets called elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63583 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3b020feb571960f76f4d402e4efcffb8daf48e5a |
02-Feb-2009 |
Sanjiv Gupta <sanjiv.gupta@microchip.com> |
Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in non-default address spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63521 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| f8a0a763d5370917212454744ca666f1dc3b815d |
31-Jan-2009 |
Dale Johannesen <dalej@apple.com> |
Fix build on case-sensitive filesystems (i.e. everybody else)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63448 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7d2ad624fa749a6d3edac0d94e9c107989c16304 |
31-Jan-2009 |
Dale Johannesen <dalej@apple.com> |
Make LowerCallTo and LowerArguments take a DebugLoc
argument. Adjust all callers and overloaded versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c8d7bc850ddf5a5df503a173b0bc0f8c03ffec96 |
30-Jan-2009 |
Sanjiv Gupta <sanjiv.gupta@microchip.com> |
Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63377 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| e5af2d3a224d4b38760a26d237cde040cb6e14eb |
29-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Make x86's BT instruction matching more thorough, and add some
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63266 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f560ffae1f1f6591859c7b70636a3eca6c03f083 |
28-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Make isOperationLegal do what its name suggests, and introduce a
new isOperationLegalOrCustom, which does what isOperationLegal
previously did.
Update a bunch of callers to use isOperationLegalOrCustom
instead of isOperationLegal. In some case it wasn't obvious
which behavior is desired; when in doubt I changed then to
isOperationLegalOrCustom as that preserves their previous
behavior.
This is for the second half of PR3376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63212 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 210de72cd7b139378f48dafbdac3d3379dd93c56 |
26-Jan-2009 |
Scott Michel <scottm@aero.org> |
Make the Dwarf macro information section optional; CellSPU's assembler
doesn't support it. The default is set to 'true', so this should not
impact any other target backends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63058 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 92f4f16a19c8d5edafad700a22e76eb2f22b4b31 |
26-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Implement Red Zone utilization on x86-64. This is currently
disabled by default; I'll enable it when I hook it up with
the llvm-gcc flag which controls it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63056 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 8c08d8c77c45d4721e7d3ef746cca9e39b28e379 |
23-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Cross register class coalescing. Not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62832 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 536ab130ec95cbb7bf30530251dafa7dfecc8471 |
22-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 9fbc7e2e7a765298fb4326885b407e0962f7ab62 |
21-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Cleanup whitespace and comments, and tweak some
prototypes, in operand type legalization. No
functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62680 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| bb326bbe88d0b243d5d9d224308eb0c028d4d4af |
21-Jan-2009 |
Sanjiv Gupta <sanjiv.gupta@microchip.com> |
Allow targets to legalize operations (with illegal operands) that produces multiple values. For example, a load with an illegal operand (a load produces two values, a value and chain).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62663 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 |
20-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 2388a588bdf32610e18a66c0c6ef248087fd1cdc |
16-Jan-2009 |
Mikhail Glushenkov <foldr@codedgers.com> |
Registry.h should not depend on CommandLine.h.
Split Support/Registry.h into two files so that we have less to
recompile every time CommandLine.h is changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62312 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| 5c1799b29375fcd899f67a31fb4dda4ef3e2127f |
16-Jan-2009 |
Mikhail Glushenkov <foldr@codedgers.com> |
Delete trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62307 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| c13cf130c45c5675ea879e1c5454298dfbe5e02f |
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Make getWidenVectorType const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62265 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 73e0914848662404cf2aa18eb049ff5aae543388 |
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Const-qualify getPreIndexedAddressParts and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62259 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 83489bb7700c69b7a4a8da59365c42d3f5c8129b |
13-Jan-2009 |
Devang Patel <dpatel@apple.com> |
Use DebugInfo interface to lower dbg_* intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62127 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ceb4d1aecb9deffe59b3dcdc9a783ffde8477be9 |
12-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Rename getABITypeSize to getTypePaddedSize, as
suggested by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62099 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 6688d75114f8adbfdc9a337bfa4eb3a046eb946d |
09-Jan-2009 |
Chris Lattner <sabre@nondot.org> |
fit in 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61977 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| d60de5187833d7d818edaab6351244255e1a1007 |
05-Jan-2009 |
Bill Wendling <isanbard@gmail.com> |
Revert r61415 and r61484. Duncan was correct that these weren't needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61765 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 676b9dfe2f7d7af7c93daac230aaac353e37d59d |
05-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Add a note about passing MVT::Other to getSetCCResultType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61756 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 50b84f44e4bf4099d62a86abd4f553a095305eac |
05-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Add <climits>, to get the definition of CHAR_BIT. This should fix
build errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61736 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 11df7e5157352d082bcb556907c3c8239228ae7f |
05-Jan-2009 |
Dan Gohman <gohman@apple.com> |
TargetLowering.h #includes SelectionDAGNodes.h, so it doesn't need its
own OpActionsCapacity magic number; it can just use ISD::BUILTIN_OP_END,
as long as it takes care to round up when needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61733 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d68a07650cdb2e18f18f362ba533459aa10e01b6 |
05-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Tidy up #includes, deleting a bunch of unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetELFWriterInfo.h
argetFrameInfo.h
argetInstrDesc.h
argetJITInfo.h
argetLowering.h
argetMachine.h
argetRegisterInfo.h
|
| 5480c0469e5c0323ffb12f1ead2abd169d6cc0e7 |
01-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType. In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61542 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 998dee96d3ca506cf73a617c0b7fc7f0e467a127 |
29-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Linux wants the FDE initial location and address range to be forced to 32-bit.
Darwin doesn't. Make this optional for platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61484 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 722f5f1cfb9a5e59a4c00986d81b04b0c015703d |
24-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Darwin likes for the EH frame to be non-local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61420 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| d4121bef3cf3af51b80c2d499085a96aca5982ed |
24-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
GCC doesn't emit DW_EH_PE_sdata4 for the FDE encoding on Darwin. I'm not sure
about other platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61415 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 0b1d4a798d1dd2f39521b6b381cd1c1911c9ab52 |
23-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Clean up the atomic opcodes in SelectionDAG.
This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.
This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61389 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetSelectionDAG.td
|
| b5544940c17720f51a74fea9fba33f26fafe4819 |
22-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Clarify a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61338 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| 2f6fea90a54787d873cfc25f33668cb4cc7d6e1e |
19-Dec-2008 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix bug 3202.
The EH_frame and .eh symbols are now private, except for darwin9 and earlier.
The patch also fixes the definition of PrivateGlobalPrefix on pcc linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61242 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 87c8a8f304d1ee72829086ce2c41a8fa3813ba6a |
18-Dec-2008 |
Mon P Wang <wangmp@apple.com> |
Added support for vector widening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61209 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8749b61178228ba1fb2668034d79da1b247173d7 |
16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add initial support for back-scheduling address computations,
especially in the case of addresses computed from loop induction
variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61075 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtarget.h
|
| 2b00aebda9705b7d76e90e632a5de511e59c739d |
15-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61035 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 5788d1a169db3346a612a13113348d2709bdd15b |
10-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids some overflow issues. Patch by Thomas Jablin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60828 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 74c376529101acbe141a256d0bf23a44eb454c84 |
09-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Add sub/mul overflow intrinsics. This currently doesn't have a
target-independent way of determining overflow on multiplication. It's very
tricky. Patch by Zoltan Varga!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60800 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 5fb580efd699b220a13cd017bb246a3e63481cf4 |
09-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Fix the name of ISD::TokenFactor in a comment. Thanks Gabor!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60736 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| bedb8c1d35e420165fca7455d4025bf82913a38f |
08-Dec-2008 |
Chris Lattner <sabre@nondot.org> |
introduce a new RoundUpAlignment helper function, use it to
remove some more 64-bit divs and rems from the StructLayout
ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60692 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 0a3ba71a0576fbde5b8ce1ff276f63f3f3d16229 |
08-Dec-2008 |
Chris Lattner <sabre@nondot.org> |
Speed up getABITypeSize by turning a i64 mul and div into an
AND. This is speedup on any reasonable target, but particularly
on 32-bit targets where this often turns into a libcall like udivdi3.
We know that alignments are a power of two but the compiler doesn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60688 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| fb4b58c9aadeedb675e000d5654201a7e2ae843d |
08-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Clarify a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60685 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c54baa2d43730f1804acfb4f4e738fba72f966bd |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 15511cf1660cfd6bb8b8e8fca2db9450f50430ee |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| 952b839ce9bc0c6d605d8b202c9cd76f7f05a77d |
03-Dec-2008 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix bug 3140.
Print a single parameter .file directive if we have an ELF target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60480 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 62c939d7d5572e57963a5f26fb6fe802e13dc0bf |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's
foldMemoryOperand how to "fold" them, by converting them into constant-pool
loads. When they aren't folded, they use xorps/cmpeqd, but for example when
register pressure is high, they may now be folded as memory operands, which
reduces register pressure.
Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will
remat it instead of copying zeros around (V_SETALLONES was already marked).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60461 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetInstrDesc.h
|
| 1607f05cb7d77d01ce521a30232faa389dbed4e2 |
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
Change the interface to the type legalization method
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 25cf2275ff7de3de3bc0e508abaf457413d74725 |
24-Nov-2008 |
Duncan Sands <baldrick@free.fr> |
If the type legalizer actually legalized anything
(this doesn't happen that often, since most code
does not use illegal types) then follow it by a
DAG combiner run that is allowed to generate
illegal operations but not illegal types. I didn't
modify the target combiner code to distinguish like
this between illegal operations and illegal types,
so it will not produce illegal operations as well
as not producing illegal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59960 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 027fdbe3ba6762b9867c6f891d64f76b7d6a4557 |
24-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
arget.td
argetCallingConv.td
argetSchedule.td
argetSelectionDAG.td
|
| 03228089d5235f8c90477f88809139464e9c6ea5 |
23-Nov-2008 |
Duncan Sands <baldrick@free.fr> |
Rename SetCCResultContents to BooleanContents. In
practice these booleans are mostly produced by SetCC,
however the concept is more general.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59911 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c8c2827993204207ca70a93f62f233fbe81b97ef |
21-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Implement ComputeLatency for MachineInstr ScheduleDAGs. Factor
some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59761 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| eb3904bc25ec7840c3e9f02d051c83f308515657 |
20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Delete redundant inline keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59754 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 33372a18c5e2d66c2b9c4cbe7361cce197bc63b5 |
20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Doxygenate comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59753 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2 |
18-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers. This fixes build breakage from r59540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 330169fa3e9c46c46bf130746d38e6ec2fac303a |
13-Nov-2008 |
Dale Johannesen <dalej@apple.com> |
Extend InlineAsm::C_Register to allow multiple specific registers
(actually, code already all worked, only the comment
changed). Use this to implement 'A' constraint on x86.
Fixes PR 1779.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59266 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9ed2f80910160bbf8051d91cd74c82d4619885b4 |
10-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename isGVNonLazyPtr to isIndirectSym to reflect how it will be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58949 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 47c01a0099c10c031f8c544baf44b1c3a1de3fad |
07-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Jump tables may be emitted by target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58835 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| c96a8e7df1ffeebc5fb876f5eef380e8547ce14f |
05-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename isGVLazyPtr to isGVNonLazyPtr relocation. This represents Mac OS X
indirect gv reference. Please don't call it lazy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58746 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| b0b53491ef32b85bd90c8590faeb8a3fb4b17a95 |
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements.
This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58688 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 8f092252d3fe75064abe330e0e6f75e213f4ac06 |
03-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Refactor various TargetAsmInfo subclasses' TargetMachine members away
adding a TargetMachine member to the base TargetAsmInfo class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58624 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 3efcd4a65cdf41ec72205757421dca6026e92a19 |
01-Nov-2008 |
Mon P Wang <wangmp@apple.com> |
Added interface to allow clients to create a MemIntrinsicNode for
target intrinsics that touches memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58548 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8fe95356dd487a79145ec07a9f46cd743b4c9bdd |
31-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Revert errant deletion. The target needs to be able to specify that it doesn't want the generic constant pool to be emitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58475 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 0c39719bfc7d0b3e61fbd55e1115184a1d5f6ae7 |
30-Oct-2008 |
Mon P Wang <wangmp@apple.com> |
Add initial support for vector widening. Logic is set to widen for X86.
One will only see an effect if legalizetype is not active. Will move
support to LegalizeType soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58426 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 46281865724c8836de538995e97168db3b06edfc |
30-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
This is not needed anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58406 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| bc6d876adf01b368c6bdd5984d9dac32589d356e |
28-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Support for constant islands in the ARM JIT.
Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the
instruction stream.
Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.
For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58338 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 23066288fdf4867f53f208f9aaf2952b1c049394 |
27-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| ac1cfa09d73923082ac7fd9bbd2c1f056bc02455 |
26-Oct-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
Return something (i.e. NULL) from an unimplemented virtual function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58183 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 95a3f0d99e9551404c217f62d0991b922ead22a9 |
26-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add storeRegTo{StackSlot|Addr} and loadRegFrom{StackSlot|Addr} descriptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58164 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 46fa139e26be6ebc00be2fb45820c2560dd22a32 |
25-Oct-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Support for allocation of TLS variables in the JIT. Allocation of a global
variable is moved to the execution engine. The JIT calls the TargetJITInfo
to allocate thread local storage. Currently, only linux/x86 knows how to
allocate thread local global variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58142 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| f89cfaea7a759c1a6c945852440a8d450f7e8af0 |
20-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
This forward declaration is unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57843 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 9a2c1d3c46e6f24f978513244daad5c9b94e4556 |
20-Oct-2008 |
Duncan Sands <baldrick@free.fr> |
Teach getTypeToTransformTo to return something
sensible for vectors being scalarized. Note
that this method can't return anything very
sensible when splitting non-power-of-two vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57839 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8c8b2a89f9173aaa06e91ff43c3a46276f23b355 |
20-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57832 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 2bbeccdee1937f6cef9f8762595246f447162a4f |
20-Oct-2008 |
Matthijs Kooijman <matthijs@stdin.nl> |
Fix typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57829 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 1ad70c09c890c3abcc147503f2e23082f683790c |
20-Oct-2008 |
Matthijs Kooijman <matthijs@stdin.nl> |
Remove another stale comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57828 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 854255361ed5a8f009d64c4869ed2a85cf0d8fae |
20-Oct-2008 |
Matthijs Kooijman <matthijs@stdin.nl> |
Remove an inappropriate (probably outdated) comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57827 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 6520e20e4fb31f2e65e25c38b372b19d33a83df4 |
18-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b89be6150a8ea38fdaa2a242f6442e2d73326dab |
17-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers.
TableGen has been taught to generate the lists from instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57722 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| 6bdcda3d3e30003fb6cef1d4e2fd3a5d5b40d3fc |
17-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
Keep track of *which* input constraint matches an output
constraint. Reject asms where an output has multiple
input constraints tied to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57687 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 58f15c482a7129c78ca809792b46befa20ea337d |
17-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
add an assert so that PR2356 explodes instead of running off an
array. Improve some minor comments, refactor some helpers in
AsmOperandInfo. No functionality change for valid code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57686 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f522068412218cd14b2c2df74a3437717d255381 |
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Trim #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57649 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 8e8b8a223c2b0e69f44c0639f846260c8011668f |
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Const-ify several TargetInstrInfo methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 7f042681764c6f8eae22781d8b4cb4c218a86b76 |
15-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Add target lowering hooks that specify which setcc conditions are illegal,
i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57542 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| dd5b58ad7be78be90390074f0df138778af5c895 |
15-Oct-2008 |
Dan Gohman <gohman@apple.com> |
FastISel support for exception-handling constructs.
- Move the EH landing-pad code and adjust it so that it works
with FastISel as well as with SDISel.
- Add FastISel support for @llvm.eh.exception and
@llvm.eh.selector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57539 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0329466b6b4927f4e6f5d144891fef06a027fec5 |
14-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename LoadX to LoadExt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57526 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a6548d0f29d848ce5e2c10ebd6aae196ce3d8651 |
13-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Clarify meaning of copyRegToReg's return value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57449 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 585457e37effc1f065281d0dad7858305b304fcb |
08-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
(re)Put const weak strings in appropriate section on Darwin.
g++dg/abi/key2.C
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57309 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
|
| 95dad830bbf975cb4cea4e1ac685781a18676a7a |
07-Oct-2008 |
Owen Anderson <resistor@mac.com> |
Add an option to enable StrongPHIElimination, for ease of testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57259 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 4ae641f4d12c60ee1aaca5e42b6de231c6a02c40 |
02-Oct-2008 |
Devang Patel <dpatel@apple.com> |
Remove OptimizeForSize global. Use function attribute optsize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56937 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 6158d8492cc021bb47caee6d4755135ef1d855a4 |
01-Oct-2008 |
Bill Wendling <isanbard@gmail.com> |
Implement the -fno-builtin option in the front-end, not in the back-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56900 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6f287b22d2e57600b4cd5dc209d0d869e7736c0b |
30-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Add the new `-no-builtin' flag. This flag is meant to mimic the GCC
`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56885 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 86098bd6a63d2cdf0c9be9ef3151bd2728281fd7 |
26-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add "inreg" field to CallSDNode (doesn't increase
its size). Adjust various lowering functions to
pass this info through from CallInst. Use it to
implement sseregparm returns on X86. Remove
X86_ssecall calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56677 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 32b952a2a60d1091e0e17bb6ce788cd1d41e6f8b |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Reapply 56585:56589 with proper fix for some gcc versions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56621 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 688535e005f370a98e82c10be7346eb981b3dfc7 |
25-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Temporarily backing out 56585:56589 to unbreak the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56607 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 2c4bf119be8aa05cdc3dc88c57006353f07f0d2c |
25-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Enable DeadMachineInstructionElim when Fast-ISel is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56604 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 02dae4ba06a05d28b24b3c1b39d54de751271c95 |
25-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Refactor the code that adds standard LLVM codegen passes into
a separate function, eliminating duplication between the
add-passes-for-file and add-passes-for-machine-code code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56599 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| b7679bd0cb45b020f8c6288fdc094808db657e9b |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Finally get rid of virtual inheritance in TAI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56589 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
|
| 8490322fa9d4c3359015510e772e231273476739 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use crazy template-based inheritance instead of virtual one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56585 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 00181a33d87d0c7676547d979b2faa1c08c91732 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of ReadOnlySection duplicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56582 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 6481873dc042d33c974399a7761a72524d1fe957 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of now unused {Four,Eight,Sixteen}ByteConstantSection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56580 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
argetAsmInfo.h
|
| 36133dd324a0583979cb9e219306726428270096 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of duplicate char*/Section* stuff for TLS sections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56577 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 315690ec2a99e1c0867853955f81d99f548178be |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of duplicate char*/Section* DataSection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56575 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| d7ca416d6c9ae1966e0df8193112e3c5f430a053 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of duplicate char*/Section* TextSection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56574 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| c25e1ea5e9aa54952b6736a9579e25a5c2d8139f |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move actual section printing stuff to AsmPrinter from TAI reducing heap traffic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56573 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| b5a32e2e8ce2f3de3a340c5a2dfcd3a159968466 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide direct function to switch to Section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56571 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| da43bcf624acb56a3d77bb5ae9a02728af032613 |
24-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d57dd5f4e6740520820bc0fca42a540e31c27a73 |
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Arrange for FastISel code to have access to the MachineModuleInfo
object. This will be needed to support debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56508 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 095cc29f321382e1f7d295e262a28197f92c5491 |
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56183 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ffeecd65e3766ed3ace4e81a8f190dbbd7758bea |
11-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate some unused methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56108 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| dd595c5998214c6ee07ed46f5db551b2abbfbbb3 |
11-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Change getSubReg semantics. It now returns zero if the specified register doesn't have a subreg of the specified index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56099 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 0586d91bb3e516d5826826522d9a90ed6ef74d86 |
10-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Add X86FastISel support for static allocas, and refences
to static allocas. As part of this change, refactor the
address mode code for laods and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56066 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d2e51af0358b571367a9f1e5175b87e9dd72edf8 |
10-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Move the uglier parts of deciding not to emit a
UsedDirective for some symbols in llvm.used into
Darwin-specific code. I've decided LessPrivateGlobal
is potentially a useful abstraction and left it in
the target-independent area, with improved comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56024 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
argetAsmInfo.h
|
| b2dfb89e0e7f1ee3e4fe4a3a1b3af148f0aec34f |
09-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Fix logic for not emitting no-dead-strip for some
objects in llvm.used (thanks Anton). Makes visible
the magic 'l' prefix for symbols on Darwin which are
to be passed through the assembler, then removed at
linktime (previously all references to this had been
hidden in the ObjC FE code, oh well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55973 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 1ed49fb74ba5127c92d837f147ccb26840c29675 |
08-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Accidental commit of partial 'stack canaries' code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55937 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| a425e0073df51ab99665062a8c00d704e89d2ef8 |
08-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r55898 to r55909. One of these patches was causing an ICE during the full bootstrap on Darwin:
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_negdi2_s.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) &&
TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical
register live information"), function runOnMachineFunction, file
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp,
line 311.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_lshrdi3_s.o
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:unknown:Undefined local symbol LBB21_11
{standard input}:unknown:Undefined local symbol LBB21_12
{standard input}:unknown:Undefined local symbol LBB21_13
{standard input}:unknown:Undefined local symbol LBB21_8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55928 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 3df24e667f04a7003342b534310919abc9c87418 |
04-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Create HandlePHINodesInSuccessorBlocksFast, a version of
HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.
This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55746 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 92362680c1d4c23670d1a7888ae272450eca2476 |
30-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
fix some 80-col violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55565 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ba36cb5242eb02b12b277f82b9efe497f7da4d7f |
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e00a8a2a2e11a37fd1ddf2504bd22d225d0994d0 |
28-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Split the ATOMIC NodeType's to include the size, e.g.
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.
This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad. This is the alternative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c93457053cfecb24105ee3800c8e53921b950d8f |
26-Aug-2008 |
Cedric Venet <cedric.venet@laposte.net> |
- small bug corrected: incorrect iterator type.
- fix to please VS: add a return after an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55380 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 940f83e772ca2007d62faffc83094bd7e8da6401 |
26-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| cb3718832375a581c5ea23f15918f3ea447a446c |
21-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Use raw_ostream throughout the AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55092 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| bb466331e7e50d03497ce40ee344870236fd9c32 |
20-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Simplify FastISel's constructor argument list, make the FastISel
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55076 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d4641a254ce3413b1542b8efb8bb30f27b5022c7 |
19-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Add a TargetLowering hook for creating a FastISel object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55009 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 328da65bd14045d3e229cbc5549835cebf6ff703 |
16-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add interface for section override. Use this for Sparc, since it should use named BSS section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54844 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| ffe31d7bf1e070650b0ff9ebfac815ea172a82bb |
16-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move SLEB/ULEB size calculation routines from AsmPrinter to TargetAsmInfo. This makes JIT asmprinter-free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54843 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| d0c1e29aecdaaa67ffabbaf2dd255809e6df4978 |
16-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Reduce heap trashing due to std::string construction / concatenation via caching of section flags string representations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54842 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 44eb65cf58e3ab9b5621ce72256d1621a18aeed7 |
15-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 42ccc21ce7ae392d9a5c2958786190943fe9aae0 |
08-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Undo most of r54519.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54534 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 711b6dce246c87b5d830966bed823d0e7aa15300 |
08-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54519 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
argetAsmInfo.h
|
| 4578862dcc71ddff55b66a819a44c0df7953bc71 |
07-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide convenient helpers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54451 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 84e160e2656695a883ce54a2d630e502b49c7797 |
07-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add hook for constant pool section selection for darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54449 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
|
| 93cacf131d64dccdfb04b215ca8a8909447f80cd |
07-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Select section for constant pool entries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54448 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
argetAsmInfo.h
|
| d829e6fdee7a26f97433d7946e22acd774a3e8fd |
07-Aug-2008 |
Matthijs Kooijman <matthijs@stdin.nl> |
Remove trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54447 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 6ac8df7f611b5b129af7192ad931862fc8169aae |
05-Aug-2008 |
Owen Anderson <resistor@mac.com> |
This option doesn't need to be a target option. It can be in SDISel instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54336 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| bd3ba461eb5578a81ba09ff7bd7eb271d1130196 |
05-Aug-2008 |
Owen Anderson <resistor@mac.com> |
- Fix SelectionDAG to generate correct CFGs.
- Add a basic machine-level dead block eliminator.
These two have to go together, since many other parts of the code generator are unable to handle the unreachable blocks otherwise created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54333 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 7232464bdaae5e6e48986a1e3b9a95fac7aa7bdf |
31-Jul-2008 |
Dale Johannesen <dalej@apple.com> |
Add a flag to disable jump table generation (all
switches use the binary search algorithm) for
environments that don't support it. PPC64 JIT
is such an environment; turn the flag on for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54248 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 09809801749d6ad3bcb79f6a53e8361c70b54b49 |
22-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Tie small stuff to non-small by default on ELF platforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53919 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 62d590cc8e8ce10351fa20b8cde77f511b8bdb74 |
22-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Basic support for small sections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53907 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 18f6ed9c29583283219a0c7e575b0a3d335b84d5 |
19-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use generic ELFTargetAsmInfo and DarwinTargetAsmInfo for X86 code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53788 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
LFTargetAsmInfo.h
|
| 745e864eab681bc24ada2032b31d3b411c123763 |
19-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add TargetAsmInfo stuff for all darwin-based targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53787 91177308-0d34-0410-b5e6-96231b3b80d8
arwinTargetAsmInfo.h
|
| debe34bd8df7c6bb3d85f836374a1c7763576a63 |
19-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add TargetAsmInfo for all ELF-based targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53786 91177308-0d34-0410-b5e6-96231b3b80d8
LFTargetAsmInfo.h
|
| 61e804f22bde414b2e8a8da22daf575a7e8ad816 |
16-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Clarify the comments here, to make slightly more clear the
difference in purpose of TargetInstrInfo and TargetInstrDesc,
which isn't immediately obvious from the name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53683 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8e819aea34bfd291149c956c673e97f06ba22a1d |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Silence a warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53326 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 4b4d100ad0a12e6787930dc499ece1b3063c7e88 |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Drop enum and use constants for SectionFlags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53325 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 0d44ba82b433d586f37e5f83f97fb1fddba35587 |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
First sketch of special section objects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53320 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 93911d239ba4b9f2929617255f95a8e3c8994c83 |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53317 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 7e7fc82cf3adfab1af673ebef4a671238f9c9bbb |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Another bunch of hacks for named sections support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53315 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| b20015b621aa4b0c30ffa75ef8917841183a22af |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add hacky way to distinguish named and named sections. This will be generalized in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53311 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 01b0e24c25857cb452b21b32ec243c6bf9220a5b |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Handle ELF mergeable sections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53306 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 265c5259ab98b5a4f9f25fbe9f2e470d0933cb38 |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide general hook for section name calculation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53304 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 6d8294209287eb36951f8445abe1129e015cd312 |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Print entity size for mergeable sections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53303 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 6e405f3f77c4f633a5f3de78d9276efbf3206fed |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move flag decoding stuff into special hook
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53297 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 29b03f737500ea32f4f0ac8378549984f0fb8860 |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Properly handle linkonce stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53296 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| c0f41db19ca8700f49d8db115030398a90e0bd4e |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide skeletone code for calculation of section, where global should be emitted into
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53295 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 555507896038323b5d8396279ed7a8cf46c4710e |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make hooks virtual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53293 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 0c602469f4e99a5775aebce16045f7c2598471e4 |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add default section name resolution routine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53292 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 8cc948d2288da5c89f1de5208f49bb95c1813c21 |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Constify
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53291 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| beb9d409006abd85ab7a9c1632fdb1d6ad9e6cdd |
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add code for default section falgs computation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53290 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 126d90770bdb17e6925b2fe26de99aa079b7b9b3 |
04-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Rather than having a different custom legalization
hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes. No change if the
new LegalizeTypes infrastructure is not turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53137 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ececf99c07febbcaeec73822519f0d36d3ee50c4 |
04-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Linux also does not require exception handling
moves in order to get correct debug info. Since
I can't imagine how any target could possibly
be any different, I've just stripped out the
option: now all the world's like Darwin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53134 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| f660c171c838793b87b7e58e91609cecf256378d |
03-Jul-2008 |
Owen Anderson <resistor@mac.com> |
Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53058 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| aa8f8889a861aadc061aec71fb7ed7f628848a2d |
02-Jul-2008 |
Bill Wendling <isanbard@gmail.com> |
Darwin doesn't need exception handling information for the "move" info when
debug information is being output, because it's leet!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52994 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 6547e406cf934346db7a206b61bcf09635afff0d |
02-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Avoid creating expensive comment string if it's not going to be printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52992 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 2dad0250f683ac5b28a8984ce5be00d299f3c35e |
01-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Prune a few dependencies on MachineFunction.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52976 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 605041e5a81fbb18769b0613dcd14e0cff32b5ee |
01-Jul-2008 |
Owen Anderson <resistor@mac.com> |
Make the subregister hashtable output more readable by wrapping the lines,
and mark it const along with the associated changes to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52966 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 57ce0319b7eb4418aac910d9a094e57d983a64d2 |
01-Jul-2008 |
Owen Anderson <resistor@mac.com> |
Implement suggestions from Chris:
- Use a more accurate heuristic for the size of the hashtable.
- Use bitwise and instead of modulo since the size is a power of two.
- Use new[] instead of malloc().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52951 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| f4f9c4f1cf4d497c63e40e6c7ef545c8c716a5ce |
01-Jul-2008 |
Owen Anderson <resistor@mac.com> |
Replace the dynamically computed std::set lookup method for subregisters with a hashtable-based
version that is computed by tblgen at the time LLVM is compiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52945 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 4406604047423576e36657c7ede266ca42e79642 |
01-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 87060f55f21a1076be83306f2efb97887d3d7654 |
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Update comments to new-style syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52925 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9665c2ae79ce7163d86e70ec2cc4eba818b80b06 |
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Reorder the fields in TargetLowering to require less padding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52919 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3d3c3e0cfade01e3cccdb9f1f2bddf5c8c17aa48 |
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Change bools to 1-bit bitfields to shrink ArgListEntry slightly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52918 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a44b674a42b6ca57128c4eb5a358298ed3bb1406 |
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Replace some std::vectors that showed up in heap profiling with
SmallVectors. Change the signature of TargetLowering::LowerArguments
to avoid returning a vector by value, and update the two targets
which still use this directly, Sparc and IA64, accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52917 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2036835346ddf983d66b49505bd52db1d3f8b49d |
30-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate TargetRegisterDesc::ImmSubRegs. It's no longer in use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52892 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 28a2b54580b28be10c536def7f49b5599adf3631 |
28-Jun-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Start refactoring of asmprinters: provide a TAI hook, which will select a 'section kind' for a global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52868 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 1360b7d8f8d1969026870d18c582b4e3a7cff8b8 |
27-Jun-2008 |
Owen Anderson <resistor@mac.com> |
Cache subregister relationships in a set in TargetRegisterInfo to allow faster lookups.
This speeds up LiveVariables from 0.6279s to 0.6165s on kimwitu++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52818 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| b5dae003252d8e650a32bfdf33cba5aed8e41e40 |
26-Jun-2008 |
Dale Johannesen <dalej@apple.com> |
Fixes the last x86-64 test failure in compat.exp:
<16 x float> is 64-byte aligned (for some reason),
which gets us into the stack realignment code. The
computation changing FP-relative offsets to SP-relative
was broken, assiging a spill temp to a location
also used for parameter passing. This
fixes it by rounding up the stack frame to a multiple
of the largest alignment (I concluded it wasn't fixable
without doing this, but I'm not very sure.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52750 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| bc52cada0933f353d30da7b49af9a641bdb2c57d |
25-Jun-2008 |
Chris Lattner <sabre@nondot.org> |
Switch the PPC backend and target-independent JIT to use the libsystem
InvalidateInstructionCache method instead of calling through
a hook on the JIT. This is a host feature, not a target feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52734 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 210539ebc466521e41e69b119649d59cc721b006 |
17-Jun-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide generic hooks for icache invalidation. Add PPC implementation.
Patch by Gary Benson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52418 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 58dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6 |
16-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| d4b9c17fb705c2f58ceef4f37d789ddb56783584 |
13-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Disable some DAG combiner optimizations that may be
wrong for volatile loads and stores. In fact this
is almost all of them! There are three types of
problems: (1) it is wrong to change the width of
a volatile memory access. These may be used to
do memory mapped i/o, in which case a load can have
an effect even if the result is not used. Consider
loading an i32 but only using the lower 8 bits. It
is wrong to change this into a load of an i8, because
you are no longer tickling the other three bytes. It
is also unwise to make a load/store wider. For
example, changing an i16 load into an i32 load is
wrong no matter how aligned things are, since the
fact of loading an additional 2 bytes can have
i/o side-effects. (2) it is wrong to change the
number of volatile load/stores: they may be counted
by the hardware. (3) it is wrong to change a volatile
load/store that requires one memory access into one
that requires several. For example on x86-32, you
can store a double in one processor operation, but to
store an i64 requires two (two i32 stores). In a
multi-threaded program you may want to bitcast an i64
to a double and store as a double because that will
occur atomically, and be indivisible to other threads.
So it would be wrong to convert the store-of-double
into a store of an i64, because this will become two
i32 stores - no longer atomic. My policy here is
to say that the number of processor operations for
an illegal operation is undefined. So it is alright
to change a store of an i64 (requires at least two
stores; but could be validly lowered to memcpy for
example) into a store of double (one processor op).
In short, if the new store is legal and has the same
size then I say that the transform is ok. It would
also be possible to say that transforms are always
ok if before they were illegal, whether after they
are illegal or not, but that's more awkward to do
and I doubt it buys us anything much.
However this exposed an interesting thing - on x86-32
a store of i64 is considered legal! That is because
operations are marked legal by default, regardless of
whether the type is legal or not. In some ways this
is clever: before type legalization this means that
operations on illegal types are considered legal;
after type legalization there are no illegal types
so now operations are only legal if they really are.
But I consider this to be too cunning for mere mortals.
Better to do things explicitly by testing AfterLegalize.
So I have changed things so that operations with illegal
types are considered illegal - indeed they can never
map to a machine operation. However this means that
the DAG combiner is more conservative because before
it was "accidentally" performing transforms where the
type was illegal because the operation was nonetheless
marked legal. So in a few such places I added a check
on AfterLegalize, which I suppose was actually just
forgotten before. This causes the DAG combiner to do
slightly more than it used to, which resulted in the X86
backend blowing up because it got a slightly surprising
node it wasn't expecting, so I tweaked it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52254 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4c54067f67a13999c301a484fda215b9a15a7281 |
12-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
If queried as to whether an operation is legal
for a particular MVT, return false if the type
is illegal rather than barfing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52229 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8e4eb09b1e3571965f49edcdfb56b1375b1b7551 |
08-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Remove comparison methods for MVT. The main cause
of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits. Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52098 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetRegisterInfo.h
|
| bd44c2e383723ef738f37a22ece912d163c66096 |
03-Jun-2008 |
Dale Johannesen <dalej@apple.com> |
Expand documentation of StringConstantPrefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51911 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 428ac54894f80ba4848d5f13576643f289412e6f |
03-Jun-2008 |
Dale Johannesen <dalej@apple.com> |
Add StringConstantPrefix to control what the
assembler names of string constants look like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51909 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 652f7ea955bb433d6b7a4d33685dca9485fd7b8b |
31-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 51775.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51795 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| babf11f249c7c6399c66f2567d4e7efa9c37a9c3 |
30-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Patches for building llvm on Solaris x86. Contributed by Nathan Keynes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51775 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| 1baa88e3de8947b02d9ef4caa73e5860f048ec6e |
29-May-2008 |
Dan Gohman <gohman@apple.com> |
Prune and tidy #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51697 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
argetMachine.h
|
| 8370d38adee63b3a4d87bfe81be4aacc55fe7cda |
29-May-2008 |
Bill Wendling <isanbard@gmail.com> |
Add a flag to indicate that an instruction is as cheap (or cheaper) than a move
instruction to execute. This can be used for transformations (like two-address
conversion) to remat an instruction instead of generating a "move"
instruction. The idea is to decrease the live ranges and register pressure and
all that jazz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51660 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| 13d57320bd212483463d4f8992d5787b29eda5df |
19-May-2008 |
Bill Wendling <isanbard@gmail.com> |
Remove warnings about unused parameters and shadowed variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51266 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 0ef8de30fa8dd317c8b45711fe144d39e51ecfa4 |
16-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix typos and comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51165 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f0df03134e698ea84e9cc1c28a853f83c02560d5 |
15-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51140 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9bfa03c6fd8e02b738e0077fd1af7b18eeeeb4c1 |
13-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51008 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9f8fea3531f8f8d04d1e183ff570be37d41d13f5 |
12-May-2008 |
Bill Wendling <isanbard@gmail.com> |
Constify the machine instruction passed into the
"is{Trivially,Really}ReMaterializable" methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51001 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| f86f211ec2fef2231f4ac4e8e4f4c0d4cf0f58f5 |
12-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Forgot this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50993 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c6c6a3e2b3ffa580cb84d75a2c60a961977e40d1 |
09-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Make OpActionsCapacity multiple of 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50917 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 671fa97a4b8c560150104329b517efbf2609297c |
07-May-2008 |
Duncan Sands <baldrick@free.fr> |
Output correct exception handling and frame info
on x86-64 linux. This causes no regressions on
32 bit linux and 32 bit ppc. More tests pass
on 64 bit ppc with no regressions. I didn't
turn on eh on 64 bit linux because the intrinsics
needed to compile the eh runtime aren't done
yet. But if you turn it on and link with the
mainline runtime then eh seems to work fine
on x86-64 linux with this patch. Thanks to
Dale for testing. The main point of the patch
is that if you output that some object is
encoded using 4 bytes you had better not output
8 bytes for it: the patch makes everything
consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50825 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 63307c335aa08b0d6a75f81d64d79af7e90eb78b |
05-May-2008 |
Mon P Wang <wangmp@apple.com> |
Added addition atomic instrinsics and, or, xor, min, and max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 34cd4a484e532cc463fd5a4bf59b88d13c5467c1 |
05-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix more -Wshorten-64-to-32 warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50659 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| a779a9899a5e23bd5198973f4709d66cb4bc2e64 |
05-May-2008 |
Dan Gohman <gohman@apple.com> |
Add AsmPrinter support for emitting a directive to declare that
the code being generated does not require an executable stack.
Also, add target-specific code to make use of this on Linux
on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50634 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 30e62c098b5841259f8026df1c5c45c7c1182a38 |
30-Apr-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 5a09690446a36f94f990db7d18d9b9ac8587888a |
27-Apr-2008 |
Chris Lattner <sabre@nondot.org> |
Implement a signficant optimization for inline asm:
When choosing between constraints with multiple options,
like "ir", test to see if we can use the 'i' constraint and
go with that if possible. This produces more optimal ASM in
all cases (sparing a register and an instruction to load it),
and fixes inline asm like this:
void test () {
asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14));
}
Previously we would dump "42" into a memory location (which
is ok for the 'm' constraint) which would cause a problem
because the 'c' modifier is not valid on memory operands.
Isn't it great how inline asm turns 'missed optimization'
into 'compile failed'??
Incidentally, this was the todo in
PowerPC/2007-04-24-InlineAsm-I-Modifier.ll
Please do NOT pull this into Tak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50315 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4376fea6631d41fff3f2a7c6186faed9eff59619 |
27-Apr-2008 |
Chris Lattner <sabre@nondot.org> |
Move a bunch of inline asm code out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50313 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 5e764233f398b6929b67701672a5e78fec20ce2e |
27-Apr-2008 |
Chris Lattner <sabre@nondot.org> |
A few inline asm cleanups:
- Make targetlowering.h fit in 80 cols.
- Make LowerAsmOperandForConstraint const.
- Make lowerXConstraint -> LowerXConstraint
- Make LowerXConstraint return a const char* instead of taking a string byref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50312 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 769b481e9f57b9fa2acf6c5fe0a94877520fcec3 |
23-Apr-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add facility for pre-RA passes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50165 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 45709ae09b252a18efd342bbd56574a12437c81c |
23-Apr-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make stack alignment options global for all targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50157 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 51cc3c13eac78da242f0518fc42580e48dd5304f |
16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function
the stub will resolve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49814 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 52e724ad7e679ee590f4bd763d55280586a8f1bc |
16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8102703d708e5d399926c6ba71ffa49bbd31fc8a |
15-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Sort sub-registers and super-registers lists according to super-sub register relations. e.g. X86::RAX sub-register list is EAX, AX, AL, AH (order of last two are not guaranteed).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49714 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 29e4bdbf27c5f03b12dd2bc41d9ccb0d5f3dfdf4 |
14-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49666 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3541af73b6b8a083cf2d7784438d60e8bcce3883 |
14-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Reverse sense of unwind-tables option. This means
stack tracebacks on Darwin x86-64 won't work by default;
nevertheless, everybody but me thinks this is a good idea.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49663 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| ec1f1a8bd2db222548ec74458c6053124b3fc367 |
14-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Clean up some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49661 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 707e0184233f27e0e9f9aee0309f2daab8cfe7f8 |
12-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetSubtarget.h
|
| 7d8143f0ef35fccc98a624525b4517eb790e2d14 |
09-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Make isVectorClearMaskLegal's operand list const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49446 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 920c6828ee2a31b324e2b0a9d16e01574955485d |
09-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix some minor errors in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49445 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| 4e1b79459fcf72216cdc42a59953e172c60e15ca |
08-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Implement new llc flag -disable-required-unwind-tables.
Corresponds to -fno-unwind-tables (usually default in gcc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49361 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| ca1267c02b025cc719190b05f9e1a5d174a9caf7 |
31-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetRegisterInfo.h
|
| d27c991cebe48fdf82b5d9eec6c2a1a244f82622 |
30-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Fix "Control reaches the end of non-void function" warnings,
patch by David Chisnall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48963 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d9ffd4cb92c95806b05df2d9f9e2be5c27cfe7fd |
27-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Fix a bug in Darwin EH: FDE->CIE pointer must
be relocatable. Describe why .set is needed better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48848 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| cfbb2f074da2842e42956d3b4c21e91b37f36f06 |
25-Mar-2008 |
Dan Gohman <gohman@apple.com> |
A quick nm audit turned up several fixed tables and objects that were
marked read-write. Use const so that they can be allocated in a
read-only segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48800 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetInstrItineraries.h
|
| 55c666a867f6c47ada58b3a620be285de719fb8e |
25-Mar-2008 |
Devang Patel <dpatel@apple.com> |
Add optimize-for-size knob.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48793 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| c9298235251b014e86a7368d92b589d093acb64a |
16-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 20ccded7dec5b90e58f649f4fb95b166a642b8cb |
15-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove isImplicitDef TargetInstrDesc flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| da47e6e0d003c873da960361549e57ee4617c301 |
15-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 6634e26aa11b0e2eabde8b3b463bb943364f8d9d |
13-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| bfae83139dcb4fffd50b939e1b1224b0126f04d4 |
11-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Use PassManagerBase instead of FunctionPassManager for functions
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48256 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
argetMachine.h
|
| 676dd7c80b6f91178452535ac45ca58feb23cc42 |
11-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48218 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 5b8f82e35b51bf007de07a7ca9347d804084ddf8 |
10-Mar-2008 |
Scott Michel <scottm@aero.org> |
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6fd599fa6916bd9438dbea7994cf2437bdf4ab8c |
05-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add a target lowering hook to control whether it's worthwhile to compress fp constant.
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47931 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8213f9cf94c740d078b444ecb125b9a581350837 |
29-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use enumeration for preffered EH dwarf encoding reason
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47770 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 28d08fdb9f6572cafd5aae95c7caffa3cd136d8e |
28-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Interface of getByValTypeAlignment differed between
generic & x86 versions; change generic to follow x86
and improve comments. Add PPC version (not right
for non-Darwin.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47734 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| fb8075d03f5c87bd57dcc9c5f2304f6b13c55aad |
28-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47703 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetLowering.h
|
| cee750fb1e25a75fd4ddae04fd0c6d8ac18fbaa9 |
28-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Preparation step for some cleanup/generalization in EH information emission:
provide TAI hook for selection of EH data emission format. Currently unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47699 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 7b8d4a9eef4eb02e561227b50c9d119cea4e8860 |
27-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt.
Change several cases in SimplifyDemandedMask that don't ever do any
simplifying to reuse the logic in ComputeMaskedBits instead of
duplicating it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47648 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e6d088acc90e422451e098555d383d4d65b6ce6b |
26-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Rename PrintableName to Name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47629 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 74ab84c31ef64538a1b56e1f282e49303412ad17 |
26-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
would have been a Godsend here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 5c80760fdf71659c5bdf45cd85d173df454dfb41 |
26-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Refactor inline asm constraint matching code out of SDIsel into TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47587 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 181eb737b28628adc4376b973610a02039385026 |
24-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Some platforms use the same name for 32-bit and 64-bit registers (like
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47534 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegisterInfo.h
|
| 8ec57d70051f70509e5db3345cd8d4f6cf9e5eb8 |
22-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove an invalid assertion now that there are implicit virtual register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47493 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| 08e78b18b8ef2c939ee95469662c98e23846d860 |
22-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Pass alignment on ByVal parameters, from FE, all
the way through. It is now used for codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47484 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ab0b949e0e9de452f3b052b11634ab761e008b23 |
21-Feb-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47430 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ae9f3a3b7c915f725aef5a7250e88eaeddda03c6 |
20-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak build with gcc 4.3: provide missed includes and silence most annoying warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47367 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
argetJITInfo.h
|
| f20db159541bf27f5d2fdf8d4ba1c8b270b936df |
15-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Added CommuteChangesDestination(). This returns true if commuting the specified
machine instr will change its definition register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47166 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 00fee65fd21f9615d1a604b8b7d42cd16a3f6b47 |
14-Feb-2008 |
Duncan Sands <baldrick@free.fr> |
In TargetLowering::LowerCallTo, don't assert that
the return value is zero-extended if it isn't
sign-extended. It may also be any-extended.
Also, if a floating point value was returned
in a larger floating point type, pass 1 as the
second operand to FP_ROUND, which tells it
that all the precision is in the original type.
I think this is right but I could be wrong.
Finally, when doing libcalls, set isZExt on
a parameter if it is "unsigned". Currently
isSExt is set when signed, and nothing is
set otherwise. This should be right for all
calls to standard library routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47122 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3 |
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| fd29e0eb060ea8b4d490860329234d2ae5f5952e |
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 04feb51886805046e8b1af10b7d21bc1ef85f457 |
11-Feb-2008 |
Duncan Sands <baldrick@free.fr> |
Add arbitrary integer support to getRegisterType and
getNumRegisters. This is needed for calling functions
with apint parameters or return values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46956 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0753fc1850a1ca4d17acca854d830d67737fd623 |
11-Feb-2008 |
Duncan Sands <baldrick@free.fr> |
Add a isBigEndian method to complement isLittleEndian.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46954 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetMachine.h
argetRegisterInfo.h
|
| 5fd79d0560570fed977788a86fa038b898564dfa |
08-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| a844bdeab31ef04221e7ef59a8467893584cc14d |
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b8033e821d9ccad10ba8770c4561600a3e9ce6cc |
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46655 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 72bebb9205c1628601b052d25555aabe6e15e6f4 |
31-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
MRegisterInfo::getLocation() is a really bad idea. Its function is to calculate the offset from frame pointer to a stack slot and then storing the delta in a MachineLocation object. The name is bad (it implies a getter), and MRegisterInfo doesn't need to know about MachineLocation.
Replace getLocation() with getFrameIndexOffset() which returns the delta from frame pointer to stack slot. Dwarf writer can then use the information for whatever it wants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46597 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| ff9b373e8f5006c629af81e2619778b4c4f5249e |
30-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d102593b425da27fa96359300ff0e3d547d0ac8d |
29-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
Use getPreferredAlignmentLog or getPreferredAlignment
to get the alignment of global variables, rather than
using hand-made versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46495 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| ba2a0b960ea4c73d0f81557f63ae2ea126e08905 |
29-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Handle 'X' constraint in asm's better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46485 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a095db13bf1f29ef75098ba71ff21851ec81ff46 |
25-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
Add more assertions to catch accesses outside of
arrays. Also, as a convenience, don't barf, just
return false, if someone calls isTruncStoreLegal
or isLoadXLegal with an extended type for the in
memory type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46352 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 29286502628867b31872ead2f2527592480f0970 |
24-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Let each target decide byval alignment. For X86, it's 4-byte unless the aggregare contains SSE vector(s). For x86-64, it's max of 8 or alignment of the type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46286 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 561e8c80f58b71414270105c6794dc18a5d68d79 |
18-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove magic numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46162 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ddf89566a93081cb230bb9406a72ab2d3eada4a7 |
17-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
This commit changes:
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4af349445222fa2a66b6248217ecd18eb6930646 |
16-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Fix and enable EH for x86-64 Darwin. Adds
ShortenEHDataFor64Bits as a not-very-accurate
abstraction to cover all the changes in DwarfWriter.
Some cosmetic changes to Darwin assembly code for
gcc testsuite compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46029 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| a22edc82cab86be4cb8876da1e6e78f82bb47a3e |
11-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Simplify the side effect stuff a bit more and make licm/sinking
both work right according to the new flags.
This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad.
It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags. Now the clients
can decide everything they need.
I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45843 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
argetInstrInfo.h
|
| 038129dd58acbb2cd6e80bee05649903897df967 |
10-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Emit unused EH frames for weak definitions on Darwin,
because assembler/linker can't cope with weak absolutes.
PR 1880.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45811 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 9c4428b217eca38e06c7bc01c8a6e1b248df326f |
10-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix PR1845 and rdar://5676945. Generic vectors smaller
than hardware supported type will be scalarized, so we
can infer their alignment from that info.
We now codegen pr1845 into:
_boolVectorSelect:
lbz r2, 0(r3)
stb r2, -16(r1)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45796 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| dcc8b4f5d3f62ae84aae100638085dedeee91588 |
08-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
add a mayLoad property for machine instructions, a correlary to mayStore.
This is currently not set by anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45748 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
|
| d3f99e2bbf5e62261c8948127aacfe9a7d3b2456 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
split TargetInstrDesc out into its own header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45696 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrDesc.h
argetInstrInfo.h
|
| 749c6f6b5ed301c84aac562e414486549d7b98eb |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetMachine.h
|
| 682b8aed0779ac0c9a6a13d79ccc1cff3e9730cf |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove a dead method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45694 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 0ff23966feb90618bec4d085095ffbc28426e691 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename all the M_* flags to be namespace qualified enums, and switch
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45692 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| e32d765f99f7ee0b8f50e419a2e1beb41003c99f |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
add more and significantly better comments to the rest of the machineinstr
flags that can be set. Add predicates for the ones lacking it, and switch
some clients over to using the predicates instead of Flags directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45690 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 13cea0bcefa892b6b73c39fd4d30d8bb42392e1f |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
add some mroe comments, add a isImplicitDef() method, add
isConditionalBranch() and isUnconditionalBranch() methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45688 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8f707e15fbd09ca948b86419bcb0c92470827ac9 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename hasVariableOperands() -> isVariadic(). Add some comments.
Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45687 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 4764189298b17432f79f01f4b707fc0a0ba33a3c |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Move M_* flags down in the file. Move SchedClass up in the
TargetInstrDescriptor class and shrink to 16-bits, saving a
word in TargetInstrDescriptor. Add some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45686 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 349c4952009525b27383e2120a6b3c998f39bd09 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| cc8cd0cbf12c12916d4b38ef0de5be5501c8270e |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove MachineOpCode typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| ba6da5d5b72618c836ebc3a7613583a16bc8ceac |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove some uses of MachineOpCode, move getSchedClass
into TargetInstrDescriptor from TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45678 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8ca5c67c6e95fdcf5ddb2f06586873c843dd0cde |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Add predicates methods to TargetOperandInfo, and switch all clients
over to using them, instead of diddling Flags directly. Change the
various flags from const variables to enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45677 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 69244300b8a0112efb44b6273ecea4ca6264b8cf |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 43dbe05279b753aabda571d9c83eaeb36987001a |
07-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetInstrInfo.h
|
| 834f1ce0312e3d00d836f9560cb63182c2c4570f |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 2e48a70b35635165703838fc8d3796b664207aa1 |
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isStore -> mayStore to more accurately reflect what it captures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8ed9c1a6d92083102867d0886dc0b6ed0fb05461 |
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
describe isStore and simplify the implementation of hasUnmodelledSideEffects.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45651 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 2a3e08b5961353fa3faeadf81f481ae9f5463427 |
05-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
X86 JIT PIC jumptable support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45616 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| d94b6a16fec7d5021e3922b0e34f9ddb268d54b1 |
05-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more functionality from MRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45603 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetInstrInfo.h
|
| be8c03fc66b75fa775e1f47d62a1b0d803fced1c |
04-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
X86 PIC JIT support fixes: encoding bugs, add lazy pointer stubs support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45575 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| f6372aa1cc568df19da7c5023e83c75aa9404a07 |
01-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetInstrInfo.h
|
| 641055225092833197efe8e5bce01d50bcf1daae |
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 |
31-Dec-2007 |
Owen Anderson <resistor@mac.com> |
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetInstrInfo.h
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 7ed47a13356daed2a34cd2209a31f92552e3bdd8 |
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Don't attribute in file headers anymore. See llvmdev for the
discussion of this change. Boy are my fingers tired. ;-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45411 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
ubtargetFeature.h
argetAsmInfo.h
argetData.h
argetELFWriterInfo.h
argetFrameInfo.h
argetInstrInfo.h
argetInstrItineraries.h
argetJITInfo.h
argetLowering.h
argetMachOWriterInfo.h
argetMachine.h
argetMachineRegistry.h
argetOptions.h
argetSubtarget.h
|
| b16f55f3c82fe72e2ca73f1071db5daaa2124e51 |
22-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Tell TargetLoweringOpt whether it is running before
or after legalize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45321 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4be2f7fe57896142ffd81432eab4dc31d21d689b |
18-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
s/hasSideEffects/hasUnmodelledSideEffects/g
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45133 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 882d2914871de826bb0c564c7db8a942f3c44a96 |
17-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
Add "hasSideEffects" method to MachineInstrInfo class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45126 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 7d9e97c2ac6f47473b2cb34971c53db30e5e9c27 |
17-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
As per feedback, revised comments to (hopefully) make the different side effect
flags clearer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45120 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 28174c5aa256cd001ad9bb8ad898af7561aa6c31 |
14-Dec-2007 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45032 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 6b1da9c39f0731d15cb743441bea6d4089efd9f8 |
14-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
Add flags to indicate that there are "never" side effects or that there "may be"
side effects for machine instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45022 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 6e141fd04897e5eb4925bb6351297170ebd8a756 |
13-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 67f1c493d105fdfb8ffa980ff82ff7d9e3fafefc |
13-Dec-2007 |
Duncan Sands <baldrick@free.fr> |
Remove host endianness info from TargetData and
put it in a new header System/Host.h instead.
Instead of getting the endianness from configure,
calculate it directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44959 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 8d2ed33f6f16850a7062d1fb5ab66fd025f301e8 |
12-Dec-2007 |
Dan Gohman <gohman@apple.com> |
Remove a forward-declaration for a non-existant class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44955 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8245aab33021f31888c7436af9fb1fe2360be791 |
12-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
Bit masks conflicted. Needed to bump them by one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44903 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 57d7d3f2d76d8d042faa95d82374b0c24cfce35f |
11-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Move TargetData::hostIsLittleEndian out of line, which means we
don't have to #include config.h in it. #including config.h breaks
other projects that have their own autoconf stuff and try to #include
the llvm headers. One obscure example is llvm-gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44825 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 1eff70451fbb079c1d5b8f45ff8c8a2b8f74d7ba |
10-Dec-2007 |
Duncan Sands <baldrick@free.fr> |
Fix PR1836: in the interpreter, read and write apints
using the minimum possible number of bytes. For little
endian targets run on little endian machines, apints are
stored in memory from LSB to MSB as before. For big endian
targets on big endian machines they are stored from MSB to
LSB which wasn't always the case before (if the target and
host endianness doesn't match values are stored according
to the host's endianness). Doing this requires knowing the
endianness of the host, which is determined when configuring -
thanks go to Anton for this. Only having access to little
endian machines I was unable to properly test the big endian
part, which is also the most complicated...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44796 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 041b3f835682588cb63df7e609d726369dd6b7d3 |
09-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
Reverting 44702. It wasn't correct to rename them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44727 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 320c630c1b55e17fa00249d499f974cb1a4238f8 |
08-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
Renaming:
isTriviallyReMaterializable -> hasNoSideEffects
isReallyTriviallyReMaterializable -> isTriviallyReMaterializable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44702 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| d64b5c82b97ad1b74eb9fd2f23257a7899b0c307 |
05-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| aee4af68ae2016afc5b4ec0c430e539c5810a766 |
02-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove redundant foldMemoryOperand variants and other code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44517 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| e62f97c094dba44e4c259d20135167fa91912eea |
01-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44479 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 27a6c7380fa4dfc8e1837a8dd67967d063b26544 |
24-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Several changes:
1) Change the interface to TargetLowering::ExpandOperationResult to
take and return entire NODES that need a result expanded, not just
the value. This allows us to handle things like READCYCLECOUNTER,
which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
ExpandOperationResult. This makes the result simpler and fully
general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
allowing them to work with LegalizeDAGTypes.
LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44300 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 526e39a02b73dd094348d63bbaf63bad5a3d7222 |
21-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
File missing from previous patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44259 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 50cdabcfd52e88381ade61450d98a1c757195bef |
19-Nov-2007 |
Dan Gohman <gohman@apple.com> |
Remove meaningless qualifiers from return types, avoiding compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44240 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| b97aec663b1591e71c9ddee6dbb327d1b827eda5 |
13-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 20ab29068d8a8ec31f26f022634f1e0bc4b1da56 |
12-Nov-2007 |
Owen Anderson <resistor@mac.com> |
Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| cc41586b9d79532172b37e1f44a9077da4b73fc9 |
09-Nov-2007 |
Evan Cheng <evan.cheng@apple.com> |
Much improved pic jumptable codegen:
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43924 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a1dc96edd28340bc6e1971835bf09610cc7ecdb3 |
07-Nov-2007 |
Hartmut Kaiser <hartmut.kaiser@gmail.com> |
Fixed compilation errors on VC++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43836 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f1ba1cad387dc52f3c2c5afc665edf9caad00992 |
06-Nov-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
Thanks for the suggestions Bill :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43742 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetSubtarget.h
|
| ca0ed744852a7d9625572fbb793f65e81225a3e8 |
05-Nov-2007 |
Duncan Sands <baldrick@free.fr> |
Eliminate the remaining uses of getTypeSize. This
should only effect x86 when using long double. Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment). This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43688 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 3cb3650a278e37aa6378127c51e407d2823139b4 |
04-Nov-2007 |
Duncan Sands <baldrick@free.fr> |
Change uses of getTypeSize to getABITypeSize, getTypeStoreSize
or getTypeSizeInBits as appropriate in ScalarReplAggregates.
The right change to make was not always obvious, so it would
be good to have an sroa guru review this. While there I noticed
some bugs, and fixed them: (1) arrays of x86 long double have
holes due to alignment padding, but this wasn't being spotted
by HasStructPadding (renamed to HasPadding). The same goes
for arrays of oddly sized ints. Vectors also suffer from this,
in fact the problem for vectors is much worse because basic
vector assumptions seem to be broken by vectors of type with
alignment padding. I didn't try to fix any of these vector
problems. (2) The code for extracting smaller integers from
larger ones (in the "int union" case) was wrong on big-endian
machines for integers with size not a multiple of 8, like i1.
Probably this is impossible to hit via llvm-gcc, but I fixed
it anyway while there and added a testcase. I also got rid of
some trailing whitespace and changed a function name which
had an obvious typo in it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43672 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 514ab348fddcdffa8367685dc608b2f8d5de986d |
01-Nov-2007 |
Duncan Sands <baldrick@free.fr> |
Executive summary: getTypeSize -> getTypeStoreSize / getABITypeSize.
The meaning of getTypeSize was not clear - clarifying it is important
now that we have x86 long double and arbitrary precision integers.
The issue with long double is that it requires 80 bits, and this is
not a multiple of its alignment. This gives a primitive type for
which getTypeSize differed from getABITypeSize. For arbitrary precision
integers it is even worse: there is the minimum number of bits needed to
hold the type (eg: 36 for an i36), the maximum number of bits that will
be overwriten when storing the type (40 bits for i36) and the ABI size
(i.e. the storage size rounded up to a multiple of the alignment; 64 bits
for i36).
This patch removes getTypeSize (not really - it is still there but
deprecated to allow for a gradual transition). Instead there is:
(1) getTypeSizeInBits - a number of bits that suffices to hold all
values of the type. For a primitive type, this is the minimum number
of bits. For an i36 this is 36 bits. For x86 long double it is 80.
This corresponds to gcc's TYPE_PRECISION.
(2) getTypeStoreSizeInBits - the maximum number of bits that is
written when storing the type (or read when reading it). For an
i36 this is 40 bits, for an x86 long double it is 80 bits. This
is the size alias analysis is interested in (getTypeStoreSize
returns the number of bytes). There doesn't seem to be anything
corresponding to this in gcc.
(3) getABITypeSizeInBits - this is getTypeStoreSizeInBits rounded
up to a multiple of the alignment. For an i36 this is 64, for an
x86 long double this is 96 or 128 depending on the OS. This is the
spacing between consecutive elements when you form an array out of
this type (getABITypeSize returns the number of bytes). This is
TYPE_SIZE in gcc.
Since successive elements in a SequentialType (arrays, pointers
and vectors) need to be aligned, the spacing between them will be
given by getABITypeSize. This means that the size of an array
is the length times the getABITypeSize. It also means that GEP
computations need to use getABITypeSize when computing offsets.
Furthermore, if an alloca allocates several elements at once then
these too need to be aligned, so the size of the alloca has to be
the number of elements multiplied by getABITypeSize. Logically
speaking this doesn't have to be the case when allocating just
one element, but it is simpler to also use getABITypeSize in this
case. So alloca's and mallocs should use getABITypeSize. Finally,
since gcc's only notion of size is that given by getABITypeSize, if
you want to output assembler etc the same as gcc then getABITypeSize
is the size you want.
Since a store will overwrite no more than getTypeStoreSize bytes,
and a read will read no more than that many bytes, this is the
notion of size appropriate for alias analysis calculations.
In this patch I have corrected all type size uses except some of
those in ScalarReplAggregates, lib/Codegen, lib/Target (the hard
cases). I will get around to auditing these too at some point,
but I could do with some help.
Finally, I made one change which I think wise but others might
consider pointless and suboptimal: in an unpacked struct the
amount of space allocated for a field is now given by the ABI
size rather than getTypeStoreSize. I did this because every
other place that reserves memory for a type (eg: alloca) now
uses getABITypeSize, and I didn't want to make an exception
for unpacked structs, i.e. I did it to make things more uniform.
This only effects structs containing long doubles and arbitrary
precision integers. If someone wants to pack these types more
tightly they can always use a packed struct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43620 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 3c3ddb3a856e44c603cb8cf8f52ff9c0f06ff14a |
29-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Enable more fold (sext (load x)) -> (sext (truncate (sextload x)))
transformation. Previously, it's restricted by ensuring the number of load uses
is one. Now the restriction is loosened up by allowing setcc uses to be
"extended" (e.g. setcc x, c, eq -> setcc sext(x), sext(c), eq).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43465 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2bd122c4d934a70e031dc0ca5171719bac66c2c9 |
26-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Loosen up iv reuse to allow reuse of the same stride but a larger type when truncating from the larger type to smaller type is free.
e.g.
Turns this loop:
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
movw %dx, %si
LBB1_2: # bb
movl L_X$non_lazy_ptr, %edi
movw %si, (%edi)
movl L_Y$non_lazy_ptr, %edi
movw %dx, (%edi)
addw $4, %dx
incw %si
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
into
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
LBB1_2: # bb
movl L_X$non_lazy_ptr, %esi
movw %cx, (%esi)
movl L_Y$non_lazy_ptr, %esi
movw %dx, (%esi)
addw $4, %dx
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43375 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e11fb343817d4bfa536cbf1b0ba979e1a4e16381 |
23-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
isSubRegOf() is a dup of isSubRegister.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43249 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 66f716354527c5ab4687a89a1605915e5128a106 |
19-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Local spiller optimization:
Turn a store folding instruction into a load folding instruction. e.g.
xorl %edi, %eax
movl %eax, -32(%ebp)
movl -36(%ebp), %eax
orl %eax, -32(%ebp)
=>
xorl %edi, %eax
orl -36(%ebp), %eax
mov %eax, -32(%ebp)
This enables the unfolding optimization for a subsequent instruction which will
also eliminate the newly introduced store instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43192 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 1c4d492b944768ded5356587779045cc346409d7 |
19-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
rename ExpandOperation to ExpandOperationResult, as suggested
by Duncan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43177 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f58dac31690f37c8f93328f8470298e1fe7862cc |
19-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
add a new target hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43165 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f0a0cddbcda344a90b7217b744c78dccec71851c |
19-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 58184e6878fdab651bc7c9a59dab2687ca82ede2 |
18-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 9bb4ea03be6fbf2fadf4727e6fad95782cbbf25b |
18-Oct-2007 |
Gordon Henriksen <gordonhenriksen@mac.com> |
Missing 'public' keyword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43121 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| 4b2b9402c5c369b94b35837470a170f1d0e47e1f |
17-Oct-2007 |
Gordon Henriksen <gordonhenriksen@mac.com> |
Switching TargetMachineRegistry to use the new generic Registry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43094 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| f411b83c8c6853c2a922b692e782566353153f08 |
17-Oct-2007 |
Duncan Sands <baldrick@free.fr> |
Return Expand from getOperationAction for all extended
types. This is needed for SIGN_EXTEND_INREG at least.
It is not clear if this is correct for other operations.
On the other hand, for the various load/store actions
it seems to correct to return the type action, as is
currently done.
Also, it seems that SelectionDAG::getValueType can be
called for extended value types; introduce a map for
holding these, since we don't really want to extend
the vector to be 2^32 pointers long!
Generalize DAGTypeLegalizer::PromoteResult_TRUNCATE
and DAGTypeLegalizer::PromoteResult_INT_EXTEND to handle
the various funky possibilities that apints introduce,
for example that you can promote to a type that needs
to be expanded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43071 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| af47b11b959713d70c45bee1922e468adfaeaff0 |
16-Oct-2007 |
Duncan Sands <baldrick@free.fr> |
Initial infrastructure for arbitrary precision integer
codegen support. This should have no effect on codegen
for other types. Debatable bits: (1) the use (abuse?)
of a set in SDNode::getValueTypeList; (2) the length of
getTypeToTransformTo, which maybe should be refactored
with a non-inline part for extended value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43030 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1622768794afca372e55732016dd9c11bd75a9a7 |
15-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
Fix 80 col violation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42976 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 106e8020bd1e36cffb749aa8358018b48839e336 |
13-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Change unfoldMemoryOperand(). User is now responsible for passing in the
register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42946 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 48abc5cf6ba6d53513034aa8c68b0a9abd748190 |
12-Oct-2007 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Corrected many typing errors. And removed 'nest' parameter handling
for fastcc from X86CallingConv.td. This means that nested functions
are not supported for calling convention 'fastcc'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42934 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetOptions.h
|
| c85e1716f0e45e4c18a9ef2fbe431a51ac3a4252 |
11-Oct-2007 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Added tail call optimization to the x86 back end. It can be
enabled by passing -tailcallopt to llc. The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
elf/pic enabled + callee is in module + callee has
visibility protected or hidden
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42870 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetOptions.h
|
| 1c08eba3fb44d59176ca1e3bfefce42e7f47d5ec |
10-Oct-2007 |
Bill Wendling <isanbard@gmail.com> |
Fix 80-column violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42823 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| cdf2b3b2f88d6f961b664e3f67a8ee37b46b0d27 |
08-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42747 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 66f0f640820b61cf9db814b6d187bae9faf7279c |
05-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added a few target hooks to generate load / store instructions from / to any
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 3b5b4cd1a50e3fe8748a8626cca3c643f5681f5a |
01-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Add getABITypeSize, getABITypeSizeInBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42488 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| e5f6204cd5d2306379bf8954e280ad35619a38b5 |
29-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Enabling new condition code modeling scheme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42459 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 82482944edd810c7a1803d6694d435adf341e611 |
28-Sep-2007 |
Dan Gohman <gohman@apple.com> |
TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets
other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42419 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| ff110265753c19daf0468ee1facf357460497b7e |
26-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from).
- X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42372 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 9efce638d307b2c71bd7f0258d47501661434c27 |
26-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| a3602685b34f4c9a1602fdc7fb120a7f51228736 |
25-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
New temporary option -new-cc-modeling-scheme to test the new cc modeling scheme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42283 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 72252732c8d31dc6af78e82ba9f9467d77152ecc |
24-Sep-2007 |
Dan Gohman <gohman@apple.com> |
Merge hasDotLoc and hasDotFile into hasDotLocAndDotFile since .loc and .file
aren't really usable without each other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42274 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| f1fc3a8fa6d4e81e30c08983d786c640acb2591c |
23-Sep-2007 |
Dale Johannesen <dalej@apple.com> |
Fix PR 1681. When X86 target uses +sse -sse2,
keep f32 in SSE registers and f64 in x87. This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42246 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a3ca3149f2b59c512c50aab330b5a0d8efddeffa |
19-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
between two registers in the specific class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42123 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| ffddf97e5dd1fc222cec049c30ca5d9018a741f8 |
13-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added getNumDefs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41901 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 4e319a30babef1175b514147aa18ee488311f1b2 |
11-Sep-2007 |
Bill Wendling <isanbard@gmail.com> |
Add accessor method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41854 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| ef4a661725716c60b49c40eed5225cac52f877e9 |
11-Sep-2007 |
Bill Wendling <isanbard@gmail.com> |
Add a bool to indicate if we should set the "indirect encoding" bit in the Dwarf
information for EH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41852 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| d60da495cd5c6bc119b3489e6b3147158735bb99 |
11-Sep-2007 |
Bill Wendling <isanbard@gmail.com> |
The personality function on Darwin needs a global stub. We then refer to
that global stub instead of doing the ".set" thingy we were doing before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41838 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 588af2fb99bf255c350fcfc582e475cf4840c606 |
07-Sep-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for having different alignment for objects on call frames.
The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41768 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 718cb665ca6ce2bc4d8e8479f46a45db91b49f86 |
07-Sep-2007 |
Owen Anderson <resistor@mac.com> |
Add lengthof and endof templates that hide a lot of sizeof computations.
Patch by Sterling Stein!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 35b35c5c320a71e4611fe2101452da685f8eeda0 |
30-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| f04afdbb48568ef09f11fd10ac03426101f2dbf8 |
30-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Change LegalFPImmediates to use APFloat.
Add APFloat interfaces to ConstantFP, SelectionDAG.
Fix integer bit in double->APFloat conversion.
Convert LegalizeDAG to use APFloat interface in
ConstantFPSDNode uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41587 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 81975f6dfd9d306d0ea7ce3ef22561c949de9af9 |
27-Aug-2007 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords and remove spurious trailing semicolons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41482 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
argetLowering.h
|
| 48884cd80b52be1528618f2e9b3425ac24e7b5ca |
25-Aug-2007 |
Chris Lattner <sabre@nondot.org> |
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
changing the interface to allow for future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41384 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 21485be444bd132941faf4e5653ac34b3ec74040 |
20-Aug-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Partial implementation of calling functions with byval arguments:
*) The needed information is propagated to the DAG
*) The X86-64 backend detects it and aborts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41179 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 276222a5ae189ed5c6a2afb248d4c8f0335585b4 |
12-Aug-2007 |
Reid Spencer <rspencer@reidspencer.com> |
Change casts from old style to new style. This helps document the details
better, gives the compiler a chance to validate the cast and reduces warnings
if the user turns on -Wold-style-cast option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41033 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 8b165731bcb9de313e3cc724e9f1b741d7fa4b05 |
10-Aug-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Move isSubRegOf into MRegisterInfo. Fix a missed move elimination in LowerSubregs and add more debugging output there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41005 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| ab081c7195ad0b2bc9a13fa718f2bbffe54ac61c |
09-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Update per review comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40965 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 5411a3937f4303f9c3fc50be92f985a4532d95e6 |
09-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
long double 9 of N. This finishes up the X86-32 bits
(constants are still not handled). Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40958 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 181b6c9cb5def44658d15848e34c5c45d973f065 |
05-Aug-2007 |
Reid Spencer <rspencer@reidspencer.com> |
Fix minor doxygen nits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40854 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| b5910820ce8608b75cb88e6c4efd2d1a5858159a |
02-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added TargetInstrDescriptor::numDefs - num of results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40709 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| c2bbfc18e9adbbdcf5b3375d8d25e2452f7df7f1 |
01-Aug-2007 |
Dan Gohman <gohman@apple.com> |
More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40673 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 06dd2a68e12a8c278faaf9cbf76ddf6d9e2d696d |
30-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Fix the comments for the 'fast' parameter in addPassesToEmitFile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40592 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| fb71d382471e82a9d064bb7cd0e7a7fee46e61f0 |
30-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Fix the comment for getClosestTargetForJIT to reflect the fact that
it does not have a Module parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40590 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| f452207d202618f92cbc04bcc6251ecae0eb6d61 |
30-Jul-2007 |
Dan Gohman <gohman@apple.com> |
More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40589 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 36397f50343639ce9a25996f2d790c656791ab92 |
27-Jul-2007 |
Duncan Sands <baldrick@free.fr> |
Support for trampolines, except for X86 codegen which is
still under discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1367fd09cb021bae61e7dd2ee208f76574c8e789 |
26-Jul-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Have register info provide the inverse mapping of register->superregisters. PR1350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40519 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 08d52071bae2f8cc2e9aa6a451118b83d043813b |
26-Jul-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8bd6035750f1b290832a3b1c90766d9b45ed8d6b |
20-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added -print-emitted-asm to print out JIT generated asm to cerr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40123 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 07a96765daedf180a7102d39fe56c499878312b7 |
16-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Fix comments about vectors to use the current wording.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39921 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 2365f51ed03afe6993bae962fdc2e5a956a64cd5 |
14-Jul-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Long live the exception handling!
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| ed80ef6089ef83bd1c79f1477d7a12a949474af5 |
10-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add OptionalDefOperand. Remove clobbersPred. Also add DefinesPredicate to be used by if-converter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38499 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 2c8c3e2e31e641085060edce0ddde3833ffa53da |
09-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38456 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| d8ebb3a0c2b42c5dedf96cfb7f2f3e87c91e1c23 |
06-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Remove redundant declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37946 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| b6f5b00c3bad3415d3f2ee1a6d5ee5a6f66a4540 |
29-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Add new TargetLowering code to provide the final register type that an
illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.
Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37781 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6595cb3000d7f5f8e9a76d556aa8609db91b7887 |
27-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Rename ("shrinkify") MVT::isExtendedValueType to MVT::isExtendedVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37758 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c33aa471300ceaa34870c6ca4973da916dbbfe3a |
26-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37741 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| c4f2fe06946b9037ce82eca309d9f2c631050cee |
26-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add immediate sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37738 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 4d2a0f5bd69f42e6313ae92a0470f8ef968e4c94 |
26-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Replace ?: with if statements, for clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37735 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 71d7794856cb559696935e3ad8215cdb1ae9886b |
26-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Simplify the expression for TargetLowering::isTypeLegal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37732 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d45eddd214061bf12ad1e6b86497a41725e61d75 |
26-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 7f32156bb9c017b71971c52fac892fa7b9b06dd2 |
25-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Generalize MVT::ValueType and associated functions to be able to represent
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37719 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ea859be53ca13a1547c4675549946b74dc3c6f41 |
22-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b9f10196961ebe5b5573a5705048a5a8a6b56bb3 |
21-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Rename TargetLowering::getNumElements and friends to
TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37687 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 82a87a01723c095176c6940bcc63d3a7c8007b4b |
19-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 4e6b1e1d999a224d932c466118aad577f27cdd56 |
19-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Replace CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37642 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 61a2598ebe007091e054325f568d1cc50c9ff3d2 |
15-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added CanBeDuplicated(). It returns true if an instruction can be safely duplicated (e.g. during ifcvt).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37605 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 318093b6f8d21ac8eab34573b0526984895fe941 |
15-Jun-2007 |
Dale Johannesen <dalej@apple.com> |
Do not treat FP_REG_KILL as terminator in branch analysis (X86).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37578 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| c101e95cb6aae1fd6a0727ba4b518a7894ae3089 |
14-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Add a target hook to allow loads from constant pools to be rematerialized, and an
implementation for x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37576 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| af67ea73184006b4f8a86ceb04fe318aad8b6558 |
14-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Eliminate some redundant newlines in asm output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37574 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| a321125e8b7e50d427d86b8053de2e6793b5df5b |
14-Jun-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Add support to tablegen for specifying subregister classes on a per register class basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37572 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8 |
08-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a utility routine to check for unpredicated terminator instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| f94ab6a6620d4a629f46fd764742db0331e6470f |
06-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a machine instruction flag indicating the instruction can clobber condition code / register(s) used to predicate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37464 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 59aefd15e59450c04fadb34f5054b34a8878ffb0 |
01-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Target specific ifcvt code duplication limit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37384 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 95ef406e0f2da0197f8b46849319c07e9bea1e55 |
30-May-2007 |
Dale Johannesen <dalej@apple.com> |
Make stable_sort in tail merging actually be stable (it never was, but didn't
matter until my last change). Reenable tail merging by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37354 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| f277ee4be7edabb759a7f78138b693d72d0c263f |
29-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add missing const qualifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37341 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| a8d53812093ef74786b8098f3d3f62bb6999b1eb |
25-May-2007 |
Devang Patel <dpatel@apple.com> |
Disable Tail Merging for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37329 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 4f85cd77046d76bd9091aa6caa06e767bd22f64c |
23-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a couple of target hooks for predication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37306 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| e6e435498c0e35d98644f868886d39c4665bb83a |
22-May-2007 |
Dale Johannesen <dalej@apple.com> |
name change requested by review of previous patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37289 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 81da02b553b86868637f27b89c6e919c31ed5b51 |
22-May-2007 |
Dale Johannesen <dalej@apple.com> |
Make tail merging the default, except on powerPC. There was no prior art
for a target-dependent default with a command-line override; this way
should be generally usable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37285 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| d46a8ea5d5383c16554a86105a43f63fa3786efb |
22-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37274 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b5cdaa257e167a08a8a54ea9249d847ccc415ce0 |
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37192 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| f48ae4630bdf5c58dfca8f4d82a1ee1a88c3a767 |
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37191 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d9e9efb253978ce4a3683085d1f75c5734143bf9 |
17-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove. Not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37139 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| d60483ef99a15630abba934001b1ff7d16a33b18 |
17-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add target hook to specify block size limit for if-conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37134 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetLowering.h
|
| 02c602b333ed2a1a13a17981f3c3f2f5463d5e5c |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
PredicateInstruction returns true if the operation was successful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 1bccb49082a8049d296dcdb2a741929437b6176f |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Rename M_PREDICATED to M_PREDICABLE; Move TargetInstrInfo::isPredicatable() to MachineInstr::isPredicable().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37115 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 6c1d2b90e31ea3337705372d1757727d6764686d |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37096 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 0402e170e8058cc5256e0c7b94ae37484253d73d |
16-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add TargetInstrInfo predication hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37091 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 5de723c1189c596a9c1b90ce4ee90c137f198ad4 |
15-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
All operands that made up of the predicate operands are maked M_PREDICATE_OPERAND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37062 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| ecd94c804a563f2a86572dcf1d2e81f397e19daa |
06-May-2007 |
Nick Lewycky <nicholas@mxc.ca> |
Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36873 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 2a07e2f4df8010bbb07591a097b5e55101ed4a96 |
05-May-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit sections/directives in the proper order. This fixes PR1376. Also,
some small cleanup was made.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36780 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 4222d806faae71ecc794cfdaa873817873c2f3d8 |
04-May-2007 |
Bill Wendling <isanbard@gmail.com> |
Add an "implies" field to features. This indicates that, if the current
feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36756 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 1997473cf72957d0e70322e2fe6fe2ab141c58a6 |
03-May-2007 |
Devang Patel <dpatel@apple.com> |
Drop 'const'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36662 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| aa4f1e164bb9a0fe438c262f40857ca639b56fad |
03-May-2007 |
Chris Lattner <sabre@nondot.org> |
Add a new option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36657 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 3e15bf33e024b9df9e89351a165acfdb1dde51ed |
02-May-2007 |
Devang Patel <dpatel@apple.com> |
Use 'static const char' instead of 'static const int'.
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 79dda2b0486dd90e2a1b1a1e4be74650a8258ce9 |
02-May-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix couple of bugs connected with eh info:
1. Correct output offsets on Linux
2. Fix "style" of personality function. It shouldn't be indirect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36633 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 794fd75c67a2cdc128d67342c6d88a504d186896 |
01-May-2007 |
Devang Patel <dpatel@apple.com> |
Do not use typeinfo to identify pass in pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 18b111bffe643b5ad52ae10a1d5728b0c1ac92f0 |
01-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add SPAdj parameter to account for call frame setup SP adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36623 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 7bf1c272ab27297a7bbab329de3f17ddb26e02a3 |
01-May-2007 |
Nate Begeman <natebegeman@mac.com> |
llvm bug #1350, parts 1, 2, and 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36618 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 14f1dd120fc13200697560680999c0efe7ecd714 |
01-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added hook hasReservedCallFrame(). It returns true if the call frame is
included as part of the stack frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36606 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 8650199fbb192c054f85647843b89e1182855718 |
29-Apr-2007 |
Dale Johannesen <dalej@apple.com> |
Make ARM-specific version of getInlineAsmLength
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36572 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 6f9896fcc81a1128b5f436d1763cc6213745adf1 |
29-Apr-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Implement protected visibility. This partly implements PR1363. Linker
should be taught to deal with protected symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36565 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 4c27344bfd45b1864c9996698d82635596ce8be9 |
28-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
add a default parameter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36529 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| edc1d159841fd279d58177bfd6ac4bc1f616d91a |
26-Apr-2007 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36485 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| b2f2e64c0790db11aea7eb52e2d056527204ee9a |
25-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Test if a register is sub- or super-register of another.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36433 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 50aadb96932a0f81ed69f73da6e7c8f8a453ee75 |
21-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add super-register set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36295 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| b3a0417cad8b625acc3033bd5e24afb9ffd0b084 |
20-Apr-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Implement "general dynamic", "initial exec" and "local exec" TLS models for
X86 32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| e3e31c22bf7ebed9e8e00ede4f4aa87ce2225528 |
20-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add sub-registers set accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36282 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| a92d62c15fa2bf84453489716323b0159912c55d |
20-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add sub-register sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36277 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| eff03db46d5d1df315cf2aa020ccd7f50ab3848e |
17-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Change getAllocatableSet() so it returns allocatable registers for a specific register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36215 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| bed2946a96ecb15b0b636fa74cb26ce61b1c648e |
16-Apr-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Removed tabs everywhere except autogenerated & external files. Add make
target for tabs checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2b95fd67da204c6f608cc280ea91230ff781d998 |
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
remove dead target hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35847 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b445d0cbb9b299ba8ec7be2494e35c501b6d3a93 |
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
remove some dead target hooks, subsumed by isLegalAddressingMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 050d541d081e39702ea61d6151167df755fb8067 |
09-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
add a default ctor for AddrMode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35832 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d2f340b746e54fca27b654fd6740973fdf6b85f1 |
31-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
switch TL::getValueType to use MVT::getValueType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35527 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1436bb657d22b01fd9a526ee7f9b2cb880c064a7 |
31-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
add one addressing mode description hook to rule them all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35520 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| caaf69107ece8bd9864fed4d64e2a84fa5f8cd4b |
28-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove isLegalAddressImmediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35406 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4234f57fa02b1f04a9f52a7b3c2aa22d32ac521c |
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| fa4bce2b76c8557cfd0794beef86efe5fb0087fa |
21-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
repair x86 performance, dejagnu problems from previous change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35245 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8e59e163db8cd3e7b4c96e438fbedf78bff06707 |
20-Mar-2007 |
Dale Johannesen <dalej@apple.com> |
do not share old induction variables when this would result in invalid
instructions (that would have to be split later)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35227 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| bf2c8b3c96f5c885095a10b0fcb29438f92d73c2 |
20-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added MRegisterInfo hook to re-materialize an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| d8197fd9d71786b48b2b0d735a37a43d5ed7984d |
19-Mar-2007 |
Duncan Sands <baldrick@free.fr> |
Fix obvious typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35164 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 5d5c93f659dd3f09375ea0fbe5d6c2df64791f73 |
19-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a TargetInstrDescriptor flag to mark an instruction as "re-materializable".
It means the instruction can be easily re-materialized at any point. e.g.
constant generation, load from constantpool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35158 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 14245a9d62d9a785a5d6590516380b300bab4957 |
16-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added isLegalAddressExpression hook to test if the given expression can be
folded into target addressing mode for the given type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35121 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2864eee7a322610a8dc5f01e450a5e1ca477f7e7 |
16-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
These forward declarations are not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35120 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| fb062ece96092e70a835c0d462613b07228d60a3 |
14-Mar-2007 |
Jeff Cohen <jeffc@jolt-lang.org> |
Fix for VS 2005 problem supplied by Morten Ofstad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35098 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 4603b402eb5929870026f60d11c068432d2c9b85 |
13-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
More flexible TargetLowering LSR hooks for testing whether an immediate is
a legal target address immediate or scale.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35071 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| be346c94760037842bb12c9c8434a23c70a00162 |
08-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add ReadOnlySection directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35015 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| d0b82b301d700217a716526f9329bb031e0d6578 |
07-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35008 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a6199c87c293d937b1e57549864345e64e6c6e8b |
07-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix DWARF debugging information on x86/Linux and (hopefully)
Mingw32/Cygwin targets. This fixes PR978
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35000 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 28b3c45109153bc50d3d9e97dccb25ffd043fa50 |
06-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Minor interface change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34967 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| fec910c3b9ba5790e5a627e1801fce25fbdddbaa |
28-Feb-2007 |
Nate Begeman <natebegeman@mac.com> |
More Mach-O writer improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34740 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachOWriterInfo.h
|
| 36230cdda48edf6c634f2dcf69f9d78ac5a17377 |
28-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Make requiresRegisterScavenging determination on a per MachineFunction basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34711 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 37f15a6d488d256d371f6c39ab83837bc9c0772d |
28-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
MRegisterInfo disowns RegScavenger. It's immutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34706 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 171eed533408a23de0b141af17475fd6b4da72e0 |
27-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Let MRegisterInfo owns RegScavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34689 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 5b7d5964c2b82607fcfafe7409957339753569ef |
23-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Temporay hook to enable register scavening for specific targets only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34513 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 2bc210d99f5a7322a1ae84775eba351d9ab6ea85 |
22-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Simplify lowering and selection of exception ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34491 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2ad9f17fee5d6395cd8db81668853e6dbf94060b |
22-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Simplify lowering and selection of exception ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34488 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 62819f31440fe1b1415473a89b8683b5b690d5fa |
21-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Support to provide exception and selector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| a15be8ce3aaaebc675f99302e2c5e1c564268322 |
21-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Add TAI field for exception table section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34477 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| f734ea21a37e27862ccf7570c2c64ad904568234 |
19-Feb-2007 |
Reid Spencer <rspencer@reidspencer.com> |
Implement support for non-standard integer bit widths of any size. The
rules alignment is to pick the alignment that corresponds to the smallest
specified alignment that is larger than the bit width of the type or the
largest specified integer alignment if none are larger than the bitwidth
of the type. For the byte size, the size returned is the next larger
multiple of the alignment for that type (using the above rule). This patch
also changes bit widths from "short" to "uint32_t" to ensure there are
enough bits to specify any bit width that LLVM can handle (currently 2^23);
16-bits isn't enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34431 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| b371f457b0ea4a652a9f526ba4375c80ae542252 |
19-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34428 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| a284cbf667e11660840dc7bae3ee9eeaa3c7cbd2 |
19-Feb-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1207:
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34399 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| efdcb839f20d09fd1e0455194b9a1df87d2d3a59 |
17-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added regsOverlap() to test if two registers overlap. Or in case they are
virtual registers, test if they the same.
- Added a virtual method to return target specific reserved registers, e.g. SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34375 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| affeb56480ab7cb2e2eed871fbf6701875934c04 |
17-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Do not dereference invalid ranges. Generalize targetdata alignment model.
This fixes the UnitTests/Vector/sumarray-dbl regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34358 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 1f43787bf056c0dda873ac2178f54009ad896fb6 |
15-Feb-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1195:
PACKED_ALIGN -> VECTOR_ALIGN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34330 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 61de82d8853a02fe39c47302432abb70a586704f |
15-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use BitVector instead of vector<bool> which can be extremely slow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34302 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| ac9dcb94dde5f166ee29372385c0e3b695227ab4 |
15-Feb-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1195:
Change use of "packed" term to "vector" in comments, strings, variable
names, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34300 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9d6565a5b1fbc4286d6ee638d8f47a3171a9ed7e |
15-Feb-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1195:
Rename PackedType -> VectorType, ConstantPacked -> ConstantVector, and
PackedTyID -> VectorTyID. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34293 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b7d61101b1a9e28541470e05af1321fea76f08e5 |
15-Feb-2007 |
Reid Spencer <rspencer@reidspencer.com> |
Fixed packed structure breakage from earlier TargetData patch; applied
Chris Lattner's code style suggestions.
Patch by Scott Michel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34292 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| d2b7cec527a0efa552628378ebca7a8ca63bb45d |
14-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Generalize TargetData strings, to support more interesting forms of data.
Patch by Scott Michel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34266 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 4e9f579028d06d92fa6d39a25c818a61d2384544 |
10-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
remove dead method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34164 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 9182e3f2054a98084f2d263bacbddd98d12258bd |
10-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
eliminate the std::vector from StructLayout, allocating the elements immediately
after the StructLayout object in memory. This marginally improves locality,
speeding up -load-vn -gcse by ~0.8%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34158 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| b0c39a3b4d1daa93d339493751976944b6422fd5 |
10-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
encapsulate the rest of the StructLayout members.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34157 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| b1919e2f08ecb37140af676fd2916f8d5ed7df3d |
10-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Privatize StructLayout::MemberOffsets, adding an accessor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34156 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| ddce8d21ea7088b9e6dd0f26e658a150614ca42a |
10-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Change TargetData::getIndexedOffset interface to not require indices
in a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34153 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| fa1eb27b76ab1e0f78574bf52a432c84a4c1a520 |
08-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34065 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d25f933c0ddc58bc19acc7a8ec5da3b0f5412a9a |
08-Feb-2007 |
Bill Wendling <isanbard@gmail.com> |
Added new method to finish up the addition of passes to emit files. This
allows us to split that method into two so that we can optionally call a
concrete function to add a writer. Removed moribund addObjectWriter()
method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34030 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 3da9981e167a1b8f6660d1dffbe033ba4f8dd218 |
03-Feb-2007 |
Bill Wendling <isanbard@gmail.com> |
Added GetTargetRelocation method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33815 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachOWriterInfo.h
|
| b82313fdc21e8190768addf0f16710b94f0e1441 |
01-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Support for non-landing pad exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33755 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| b25fe8267182662750dcb76a70a20f4b14a5568d |
01-Feb-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fixed uninitialized stuff inside LegalizeDAG. Fortunately, the only
affected part is codegen of "memove" inside x86 backend. This fixes
PR1144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33752 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 94c002a190cd2e3a52b1510bc997e53d63af0b3b |
01-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
rename DenseMap to IndexedMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33749 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| d385fd62cb43435b3ad70d789198d34bf148e579 |
31-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow the target to override the ISD::CondCode that's to be used to test the
result of the comparison libcall against zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33701 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| bcc5f36765e8111c13873a0c0dc874c92385d808 |
29-Jan-2007 |
Nate Begeman <natebegeman@mac.com> |
Finish off bug 680, allowing targets to custom lower frame and return
address nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33636 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1b340dc8e20dc1ce204ebdcc2ff11c3dd36888f1 |
29-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Flag to control exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33628 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 072200c36dd96b94e772029fd72edf9fa120c467 |
29-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Landing pad-less eh for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33622 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| b10308e440c80dd6ffb4b478f741ff7e5f30cb48 |
28-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33597 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 98b5795f6227fd31e6cd2852adf5a641ea1ce3be |
27-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Accessor for the TargetELFWriterInfo class object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33572 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 4f45222baa6ed803c836114f9681bd7a3204784d |
27-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
The TargetELFWriterInfo class holds target-specific information for the ELF writer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33570 91177308-0d34-0410-b5e6-96231b3b80d8
argetELFWriterInfo.h
|
| 1ee29257428960fede862fcfdbe80d5d007927e9 |
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Make LABEL a builtin opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 02a20291410a6814c657b69901a57103d4861a07 |
25-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added a MRegisterInfo hook that tells PEI the target is responsible for
rounding the stack frame to a multiple of stack alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33504 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 5e73d5bd2e98afda12fa69a7ea83050c69be0d34 |
24-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
by value so that clean up is less confusing (these vectors tend to be small.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33488 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 2b7218218faa02d9ece90f2ae6e009d7c55534df |
24-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Make ivars private and use getters. Have the MachOWriter return "Mach-O
Writer" for the pass name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33483 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachOWriterInfo.h
|
| de268f7dcf8a650afde162b84608ed434fb10613 |
24-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Renamed getTypeAlignmentShift() to getPreferredTypeAlignmentShift().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33482 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 8f5159e6b225356bd9c07c7040bab002b8707c0a |
24-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
A virtual method to return the TargetMachOWriterInfo object. This returns
a real value in derived classes, of course.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33477 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 841056a2ad6fce7786378a27aced46e37122259f |
24-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
New "TargetMachOWriterInfo" class. It holds target-specific information
that the MachOWriter needs in order to do its writing stuff 'n things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33475 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachOWriterInfo.h
|
| dc77540d9506dc151d79b94bae88bd841880ef37 |
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
hasFP() is now a virtual method of MRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 9b631a58ef25df2905cbe59fa618db79a3d535c5 |
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33450 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 7c2924367087caa738d1c6349d04a4645c6c26fa |
21-Jan-2007 |
Reid Spencer <rspencer@reidspencer.com> |
Implement a getTypeSizeInBits method. This helps in transforms that want
to ensure the bit size of a type is identical before proceeding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33413 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 1027a533d4f1806ff7d2f721504028201cffa7b5 |
21-Jan-2007 |
Owen Anderson <resistor@mac.com> |
TargetData assumes (and some regression tests depend on it) that the size of
an unspecified datatype in the datalayout is capped by the size of a pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33411 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 58092e35a3368e130438cbc793c8f9dce2e4fe0f |
20-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
Teach TargetData to handle 'preferred' alignment for each target, and use
these alignment amounts to align scalars when we can. Patch by Scott Michel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33409 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 393a8eea3c15de08eaf6953aa8a65a3961b76153 |
18-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
add new JumpTableSpecialLabelPrefix hook to asmprinter for jumptable emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33314 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| c099e49f5701cb497bf7328764e6abccfda6ec4d |
17-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
document that BSSSection can be null.
Add new ZeroFillDirective directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33301 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 292a007c946cce20badbe52dbae06d5758bfad42 |
17-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Document flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33300 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 5032e5a61381437174e035de2a7dd728978f7bd5 |
17-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
* Fix one more bug in PIC codegen: extra load is needed for *all*
non-statics.
* Introduce new option to output zero-initialized data to .bss section.
This can reduce size of binaries. Enable it by default for ELF &
Cygwin/Mingw targets. Probably, Darwin should be also added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33299 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetOptions.h
|
| e911615c4769d793588087b5321d303ecb9661c7 |
17-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Revert patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33298 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetObjInfo.h
|
| c49e1eb8cc5fc1effebf1863acd78889fad0aa32 |
17-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
make doxygen comment much better. Patch by B. Scott Michel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33294 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 3007f7a30e2202ea93de6f1e5f8c4a8914b43bd9 |
17-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
The TargetObjInfo object goes here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33288 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 34f03fff2d117068b4d627922484d2d79ed9c025 |
17-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
New "TargetObjInfo" class. This holds information that the object writers will
use to write things to the file. It's abstract so each target should implement
its own version for each writer type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33286 91177308-0d34-0410-b5e6-96231b3b80d8
argetObjInfo.h
|
| eb9a42c90bf7e21ad8544315a65f86b668cc0277 |
16-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Fix for PR1095:
LLVM would miscompile ASM dialects when compiling for PPC. Added dialects for
the X86 and PPC backends. It defaults to "0", the first variant of a compound
inline asm expression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33246 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 9784bc73c35ab4f6e79dd10804e7e1ed3b5bd3fa |
14-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
add a new HiddenDirective member for handling visibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33197 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| c254b1d666ab0788da3f69582813afe668963a24 |
13-Jan-2007 |
Reid Spencer <rspencer@reidspencer.com> |
Don't #include DerivedTypes.h in this header. Make adjustments to
compensate. Move a function out of line to TargetLowering.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33153 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 495600120e9d6c7599c599b7b16a9e8789c65aa5 |
12-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Move RTLIB::Libcall enum to a separate file.
- Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33148 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9f7f49caa46d00d455c8ae5152e4412dd5eed26d |
12-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Silence a bogus compiler warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33145 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a54b7cbd452b3adb2f51346140d996b29c2cdb30 |
12-Jan-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1064:
Implement the arbitrary bit-width integer feature. The feature allows
integers of any bitwidth (up to 64) to be defined instead of just 1, 8,
16, 32, and 64 bit integers.
This change does several things:
1. Introduces a new Derived Type, IntegerType, to represent the number of
bits in an integer. The Type classes SubclassData field is used to
store the number of bits. This allows 2^23 bits in an integer type.
2. Removes the five integer Type::TypeID values for the 1, 8, 16, 32 and
64-bit integers. These are replaced with just IntegerType which is not
a primitive any more.
3. Adjust the rest of LLVM to account for this change.
Note that while this incremental change lays the foundation for arbitrary
bit-width integers, LLVM has not yet been converted to actually deal with
them in any significant way. Most optimization passes, for example, will
still only deal with the byte-width integer types. Future increments
will rectify this situation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33113 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 56966225d1eed9f9a6951d2167bfbbec9628c8d6 |
12-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Store default libgcc routine names and allow them to be redefined by target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33105 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4fe16d607d11e29d742208894909733f5ad01f8f |
11-Jan-2007 |
Reid Spencer <rspencer@reidspencer.com> |
Rename BoolTy as Int1Ty. Patch by Sheng Zhou.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33076 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 257464a07272a74b772d03fca31617cd3a1826db |
06-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Remove isSetCCExpensive() etc. These are no longer used.
- Add isSelectExpensive() etc. It's used to tell codegen that select is expensive for a given target, avoid using it if possible. Currently it's only
used to expand FCOPYSIGN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32939 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0098b3e2b69e527ddcf2ebad7a3081898fa3b4f0 |
02-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix naming inconsistency: calleesave -> calleesaved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32821 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetFrameInfo.h
|
| ebdf389e2f0af7e90c7adf3f329e60a4e007ee70 |
02-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add virtual method spillCalleeSaveRegisters() and restoreCalleeSaveRegisters()
to MRegisterInfo. These allow the target to issue instructions to spill and
restore callee saved registers in case where individual stores / loads aren't
the correct / profitable choice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32820 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 2ba767f44ad8af9f941213e3dad017771e572db8 |
31-Dec-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR950:
Change integer type names for signless integer types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32777 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7f44f6a8d96922a13c80d852401df157e1486b6e |
21-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Grandchildren are covered by protect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32736 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| bf1118285c0f784b120a69b4a4207e15ef065ead |
21-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Changes from Nick Lewycky with a simplified PPCTargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32735 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 5c7e326585f3a543388ba871c3425f7664cd9143 |
17-Dec-2006 |
Bill Wendling <isanbard@gmail.com> |
Added an automatic cast to "std::ostream*" etc. from OStream. We then can
rework the hacks that had us passing OStream in. We pass in std::ostream*
instead, check for null, and then dispatch to the correct print() method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32636 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| f2f6a1baf78f3bdf375b258996abd567c20496bc |
15-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Silly assertion. Forgot variable_ops instructions can have arbitrary number of
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32592 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 975651ab98c16bbea05fa5357738056aa3c28818 |
13-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add getTypeToExpandTo() which recursively walks TransformToType to determine
the intrinsic type to expand to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32558 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6586adfc1a52fbafd0733b74cd73651e328ce019 |
13-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Update comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32532 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b9d89c9ffbfd68150d0e678df4ef00752c334713 |
13-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Update comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32531 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 3b1cf89edc760d6cca088ea59524a74373d6bb84 |
12-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Remove unneeded include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32489 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtarget.h
|
| 9a7dfa3fd465aa7cf275003dbb11234e34bb2d8c |
12-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Rollback changes to take a different tack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32488 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
argetSubtarget.h
|
| 55a7ec33d7cafa703a1b6e6410d7c26d5b7ded0b |
12-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Honor the command line specification for machine type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32483 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
argetSubtarget.h
|
| d27a258d2d7691db3731135a448b7654d260cc07 |
11-Dec-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32415 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c9ab2f39ceadefa4ac8c0c922c55a76c0d637a6e |
09-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added option -soft-float to generate SW fp library calls instead of fp instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32393 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| cc22a7a2adfea3fc318a6d8ca0c692a8e892105b |
08-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Move findTiedToSrcOperand to TargetInstrDescriptor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32366 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 3cc3816cd4dc92fbb0a2de93bdebb68dfcea31d5 |
08-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use MI's TargetInstrDescriptor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32352 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| bd7b67fd37166a129c1962981ea380e18077a4d6 |
01-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32095 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 6c14147d934bd644fc9d24a3b36f3c38799a3401 |
01-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Add getOperandConstraint() to TargetInstrDescriptor.
- convertToThreeAddress() change to allow single two-address MI to be converted
into one or more 3-address MIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32094 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8752ce61e1ba3973e0082085c1c3c9b8069ea2b7 |
01-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add weak reference directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32091 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 3f7927c84c1b8c449378eaaf67eb9c563eb78949 |
29-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add a hook to allow targets to hack on inline asms to lower them to llvm
when they want to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31997 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 3655de6873dfe68de050bb91a517a712246273f2 |
28-Nov-2006 |
Andrew Lenharth <andrewl@lenharth.org> |
Add per-target support for asm translation in the cbe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31972 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 33247d537ddce29e65bc324bf8d40a15d2d88c01 |
17-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add opcode to TargetInstrDescriptor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31802 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 5ff839fbabe8b1d26cf4db5c541eb5d7942c25d6 |
09-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add a mechanism to specify whether a target supports a particular indexed load / store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31597 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 144d8f09e139f691cafadbc17873943ba4c465f3 |
09-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31595 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d258efaf6eeb63792ba630edc50405fb559337fb |
09-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
getPostIndexedAddressParts change: passes in load/store instead of its loaded / stored VT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31584 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a1fd6504aaf62b87530e8230517957bad3facc96 |
09-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove M_2_ADDR_FLAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31583 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| a7bb6498fec20c9d0f7cfce4f7df7f6852ad1d57 |
07-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added target hook for post-indexed memory ops transformation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31499 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f6e8e6bace845cbbb6c1f6d859ffd8a3a154222b |
07-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Add a new operand flag to mark which operand is the first predicate operand
of an M_PREDICATED instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31482 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 1b1b737d7dc7b3330331cf65514719d719f88a43 |
06-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add a flag so that predicated instructions can be recognized by branch
folding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31479 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 1a854be35295fd1c9c4d0d0f8894e720e22b5e4f |
03-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31413 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 24d9cf025dff0852dfd9b53e764f6729bc8e67ac |
03-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added a target specific hook to check whether / how a node can be transformed
into a pair of base / offset nodes for pre-indexed load / store ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31407 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a74b4a3ddc0aadbcf6bf35754cf1c6d4b2d96e67 |
02-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
generalize this api
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31365 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e6ae14e1f413987f3de31a7cad1b20a7893f8cae |
02-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31364 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 981b5bd7080db6dbbac6931863d8a2e6d1fc5a0c |
02-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added getTiedToSrcOperand() to check for two-address'ness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31360 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| e2ba8975883874633a1035c245af3b948b940b25 |
01-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add operand constraints to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31333 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| dba1aeedd8179114a45be655b985455218d20806 |
31-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Change the prototype for TargetLowering::isOperandValidForConstraint
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31318 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6ac310d5e9185a07bc02eb22bf7791c847877b52 |
30-Oct-2006 |
Reid Spencer <rspencer@reidspencer.com> |
Don't mislead readers by claiming a variable is defaulted to false when
the default is actually true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31300 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 02b8511364a61b559369d8dc36e82a486f42fec3 |
30-Oct-2006 |
Reid Spencer <rspencer@reidspencer.com> |
Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4
generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31299 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| c24ff8ed12d01a1b1d2fac57876fc7580024ec49 |
28-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
add another target hook for branch folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31262 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8d8c5976ab4aadb6011d4604e3fbf81ba682b912 |
26-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added CStringSection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31202 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 5f90cbc56a9f4b651eed1e8208a209694c63b7ac |
24-Oct-2006 |
Devang Patel <dpatel@apple.com> |
TargetData is not subclassed. So no need to have virtual method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31173 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| f9c197e022521a83f8876890b4241fc23e63572c |
24-Oct-2006 |
Devang Patel <dpatel@apple.com> |
Move getPreferredAlignmentLog from AsmPrinter to TargetData
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31171 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 33644ba8d22a91b8fe0f0da3d73fc7cf38a46b06 |
24-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
update comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31165 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 24321d7e23a482cbd0b7502f43e9026f87a3684d |
24-Oct-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
fix assert comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31154 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| ae1dc403274d3a64bcee31f15e2d25e4b7178811 |
18-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
expose DWARF_LABEL opcode# so the branch folder can update debug info properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31024 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 72dc5852684bd56af68b3f344b295d9ff5c3a13f |
18-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
update comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31023 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8b2794aeff151be8cdbd44786c1d0f94f8f2e427 |
13-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d51c87f22f9b666204b27b301af771bc5badc142 |
13-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
it is easier to implement these when they are virtual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30944 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 5f1e4dbdf77de6887441af20857967a3d24c01ab |
13-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
allow branch reversal to fail
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30943 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b2cd26127973b97c3ed8d74a063e70a259369e44 |
13-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
replace the existing branch inspection/modification APIs with something more
useful and general.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30940 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 4c7b07a66f3d5c14339a6181fa12d060aeb9b18c |
13-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Expose method and ivars for measuring inline asm length properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30934 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 24446e253a17720f6462288255ab5ebd13b8491f |
09-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Merging ISD::LOAD and ISD::LOADX. Added LoadSDNode to represent load nodes.
Chain and address ptr remains as operands. SrcValue, extending mode, extending
VT (or rather loaded VT before extension) are now instance variables of
LoadSDNode.
Introduce load / store addressing modes to represent pre- and post-indexed
load and store. Also added an additional operand offset that is only used in
post-indexed mode (i.e. base ptr += offset after load/store).
Added alignment info (not yet used) and isVolatile fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30843 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 428e75eaef7ccbb027c53ff0f89e2e686db50e01 |
07-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for targets to declare that they use a GOT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30777 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 671d77bc8ea1ea50141ae87bce030110ac9c73f1 |
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
remove JumpTableTextSection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30746 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 1279b7c2a9849b499d5997d7efb5c0d6e902ca62 |
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
move getSectionForFunction to AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30734 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| f5b10ec509d7e27df12372e53adeda59051dfc30 |
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Give TargetAsmInfo a virtual dtor, add a new getSectionForFunction method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30732 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| c548428c5d7328592f4db6f6cd815af18b3152a3 |
04-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30714 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 02569d7355b03155b32c1c0d0e46f6aa957f4802 |
28-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Added a hook processFunctionBeforeCalleeSaveScn(). This is called by PEI just
before it determines which callee-save registers are to be spilled. This allows
the target to make changes such as forcing certain physical registers to be
spilled.
- Modified comments. It's important to note the order of registers in the array
returns by getCalleeSaveRegs() determines the order of callee save spill code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30635 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| cb05af852f1d346ac07b84c74a930a5cdbd6d427 |
26-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for targets that want to do something with the llvm.used list,
because they have an aggressive linker that does dead code stripping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30604 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 384299ef45840acf7c43125dc935237b333e339a |
26-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
order this properly to avoid warnings in TargetAsmInfo.cpp. Add a comment
in a format that matches every other ivars in this class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30603 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| beec30eaf301bd6882cd06800b5175b94f033f9d |
24-Sep-2006 |
Andrew Lenharth <andrewl@lenharth.org> |
Add support for other relocation bases to jump tables, as well as custom asm directives
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30593 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| fde1b3bb2f15b74c713d98a79fcddaff1ac00dd1 |
08-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
1. Remove condition on delete.
2. Protect and outline createTargetAsmInfo.
3. Misc. kruft.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30169 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| a0f3d17daac73c9c71aad497b298cbe82848f726 |
08-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
Make target asm info a property of the target machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30162 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
argetMachine.h
|
| ec0d9fe2b2dc87efb2dcb1a30f267c1e36adf5a5 |
06-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
Separate target specifc asm properties from asm printers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30127 91177308-0d34-0410-b5e6-96231b3b80d8
argetAsmInfo.h
|
| 2a0013f59fb3b23010c0509fab8bf509eb30fb36 |
04-Sep-2006 |
Duraid Madina <duraid@octopus.com.au> |
add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30095 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1911fd4f85aebcd4d7b8f27313c5a363eebf49cb |
04-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Completely rearchitect the interface between targets and the pass manager.
This pass:
1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
output, move all this to common code, and give targets hooks they can
implement.
3. Commonalize the target population stuff between file emission and JIT
emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
paves the way for "fast -O0" stuff in the CFE later, and now LLC could
lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
which is now orthogonal to the fact that JIT'ing is being done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30081 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
argetMachine.h
|
| 07ac914973ebb484dd7ed1ad143934e14ad56e26 |
03-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Eliminate target name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30071 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 3bca110dc35a930b28dd9e05105b52e9cd3c98ee |
24-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
update some comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29853 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 5ea64fd9eb0027ad20a66ea29211eef79d8842a0 |
18-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Constify some methods. Patch provided by Anton Vayvod, thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 6c8d90d65fa721d406c7a09a0045fa49254a9244 |
10-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Doxygenify some methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29592 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 1eaf0ac1dc470fb846c16c966d1ffff8213b33ef |
03-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
update comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29507 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| fb1fcf08c9caeac84d5b51a3a250283b2127fc6d |
03-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
remove some more dead sparcv9 support stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29506 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| f141cc46faf6f0525f0baa10b6a6c976301874a5 |
27-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Resolve BB references with relocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29351 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 55b5053b8e22cf165d1f0ce3aa9a04707e368a15 |
27-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Move synchronizeICache from TargetJITInfo into a static function in JITEmitter.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29334 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 35d86fef1f1fc5845366c7c36803a6a3334d8a2e |
26-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29307 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 55fc28076fa48723bd170e51638b3b5974ca0fa1 |
25-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Refactor the code that resolve basic block references to a TargetJITInfo
method.
- Added synchronizeICache() to TargetJITInfo. It is called after each block
of code is emitted to flush the icache. This ensures correct execution
on targets that have separate dcache and icache.
- Added PPC / Mac OS X specific code to do icache flushing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29276 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 60f09928a0d22d5927ff0a40fe9163cf1ba1014a |
21-Jul-2006 |
Jim Laskey <jlaskey@mac.com> |
Use an enumeration to eliminate data relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29249 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetInstrInfo.h
|
| 3b0c0148ed9ec752b240dbea767ad4a9f0a682ca |
19-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Make sub- and super- register classes const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29200 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 152ed053533b26194362994398c0ffad7e1c4109 |
06-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added option -code-model to set code model (only used in 64-bit) mode. Valid
values include small, kernel, medium, large, and default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29009 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 61496683b3c688032328119c83ea87df3093bc08 |
17-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Clean up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28851 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| c91dc678e937ca5b3e3d85e9c9f76ade7c957f29 |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Simplify the targetdata ctor by not passing in a "targetname" which is always
ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28829 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| acbc07aa2216f84967a1bcccaca1a425b141f77a |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Remove ctor with each piece specifyable (which causes overload ambiguities),
add a new init method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28828 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| f4432fac1425a590dd0e725ed3dd626cf37e1a37 |
15-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Avoid undesirable behavior when assert is not enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28793 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 8d3af5e7d082dbd029c3987ceadbdcf9e49af6d7 |
15-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Instructions with variable operands (variable_ops) can have a number required
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28791 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 232c910b8acd81cbf47fb18595ce557789c2217c |
12-Jun-2006 |
Andrew Lenharth <andrewl@lenharth.org> |
Start on my todo list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28752 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 19b7e0e0cabfa6dfc559c64e3d6ed053832c4047 |
24-May-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR786:
Minor tweaks in public headers and a few .cpp files so that LLVM can build
successfully with -pedantic and projects using LLVM with -pedantic don't
get warnings from LLVM. There's still more -pedantic warnings to fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28453 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 80235d508e5f7a9603ef43ba6625984173ff0323 |
23-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
-enable-unsafe-fp-math implies -enable-finite-only-fp-math
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28437 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 95942d76f4fdd1191febf1aa2b612fce6351ab3b |
23-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added option -enable-finite-only-fp-math. When on, the codegen can assume that
FP arithmetic arguments and results are never NaNs or +=Infs. This includes
ignoring parity flag (PF) when checking for FP equality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28432 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| bcd8a8264e35e147e23c219f0435c9277e24ec66 |
21-May-2006 |
Owen Anderson <resistor@mac.com> |
Make TargetData strings less redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28423 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 21d03f2de0087d60dbf575d95924404a97852879 |
18-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
lib/Target/Target.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28386 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 7e399c14abb27f9d1291442ee7f9251fa827f2e9 |
17-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Another typo. Pointed out by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28353 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 5beaacc189a5c6e6223a55c3ff121dccc4c44a56 |
17-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix a mis-leading comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28350 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6cacaee7249853a085b05fc6eec714803579c02c |
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
There is now a default impl of this method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28336 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| dae9cbe8d4fcd8f182a99403d67cae906bdb3175 |
16-May-2006 |
Andrew Lenharth <andrewl@lenharth.org> |
Move this code to a common place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28329 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6460becced5303637bb00d342f168710abde7134 |
15-May-2006 |
Chris Lattner <sabre@nondot.org> |
Improve comments, patch provided by Vladimir Prus!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28305 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| 2577c22131fbcf58cefdad63114c3e14a9d00c26 |
12-May-2006 |
Owen Anderson <resistor@mac.com> |
Add a method to generate a string representation from a TargetData.
This continues the work on PR 761.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28239 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 07000c6f01d8f57170f2d4c77a86d934bdc5c696 |
12-May-2006 |
Owen Anderson <resistor@mac.com> |
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28238 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 8f60c56a06c4bc2027c5d1a7ee7ad626ae274604 |
12-May-2006 |
Owen Anderson <resistor@mac.com> |
Add a new constructor to TargetData that builds a TargetData from its
string representation.
This is part of PR 761.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28234 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 13d41b9d721f98372b97d2ec119e6c91932ab0ae |
12-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add capability to scheduler to commute nodes for profit.
If a two-address code whose first operand has uses below, it should be commuted
when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28230 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| c3580cace271b0f7d35a25eb285a1cc0d644c30c |
11-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Also add super- register class info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28222 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 696736be8b80fe3946f73605b46359345afdf57a |
09-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added sub- register classes information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28196 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| a0d513ba753e0df43aa36d653502effddeadb34e |
06-May-2006 |
Chris Lattner <sabre@nondot.org> |
Add some new methods for computing sign bit information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28144 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ed5b016f0ecd232647b9ea9cb54bf2768d55d690 |
04-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix this to be a proper copy ctor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28111 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| a69571c7991813c93cba64e88eced6899ce93d81 |
03-May-2006 |
Owen Anderson <resistor@mac.com> |
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
This fixes PR 759.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28074 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
argetLowering.h
argetMachine.h
|
| f7fb31ea33c78f1bc46c23d9edbf9580b7756bbe |
20-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Remove a bunch of dead stuff, shrinkifying TargetInstrDescriptor significantly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27897 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 3dc38d26fb9fd0d65a4428a7f5820bbbb0c723dd |
20-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Remove some obsolete interfaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27896 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetSchedInfo.h
|
| c313c66a88a19f6cb59f8c349fe86eb69ee68b5f |
20-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added a virtual method isVectorClearMaskLegal to TLI. It is similar to
isShuffleMaskLegal, used to determine if it makes sense to turn a
"vector clear" (e.g. pand V, <0, -1, 0, -1> to a shuffle of the vector and
a zero vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27873 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b878151b1e50e820ef0a00aed12a200a1e0fef57 |
12-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Provide a default impl of LowerArguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27605 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 1069fbdd2fc637321ca69f501b8af4f321aeb9f7 |
11-Apr-2006 |
Jim Laskey <jlaskey@mac.com> |
Use existing information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27574 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 4188699f80c233a20b6ddc61570a8a8c1804cb85 |
07-Apr-2006 |
Jim Laskey <jlaskey@mac.com> |
Foundation for call frame information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27491 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| c45420ddd2db5200426fa4d8b9b4edaeffe01cc5 |
04-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Move isShuffleLegal from TLI to Legalize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27398 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e6bfffbae26a3593531d0f6b78ae2b8125244c38 |
04-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Allow targets to have fine grained control over which types various ops get
promoted to, if they desire.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27389 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 79227e2906656b2c92965f5dbebcd66a5774c87f |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Modify the TargetLowering::getPackedTypeBreakdown method to also return the
unpromoted element type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27273 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 00cc494595ea848438012eec6c89b174305070d7 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add a method useful for decimating vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27269 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4 |
28-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Expose base register for DwarfWriter. Refactor code accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27225 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| b470caad788ea838c6815588029db5eed8715154 |
24-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Tweak a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27066 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 98a6979b253740a33d9187c95cf9e9085e4c28da |
24-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Clean up some commentary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27064 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| f1d78e83356a412e525c30ac90dabf090a8cfc99 |
23-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Add support to locate local variables in frames (early version.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26994 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 475c010366da9788b5f87d6a453d5eed6053ef46 |
23-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Eliminate IntrinsicLowering from TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26973 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetMachineRegistry.h
|
| ef98691ca3a3b765b18b24ec9e01000e9e1b6bd6 |
23-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
remove always-null IntrinsicLowering argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26971 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| ca6e8eafd2dfb13b89875405c54613b9cea1ca2e |
22-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
64-bit vector shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26964 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| dc26e32ec7a10a7dea536b5953c75ff8e06b7f15 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add some helper methods
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26882 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 714554d70717c73e0542ca93df36fa78765f87af |
16-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added a way for TargetLowering to specify what values can be used as the
scale component of the target addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26802 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 30b37b5f29991874648d839d018aa2921b39355f |
14-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add LSR hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26740 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a84b1c7c4efdba050cbf308eb9ac4fd8392b69d9 |
14-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added getTargetLowering() - returns DAG lowering info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26739 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 1566d18fe2f469839fd91fdbfd65e1d239aa99e6 |
06-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
custom lowered nodes are legal too
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26561 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 65e9f3969bec427f14d41f0aaef12ed689ca85b5 |
06-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add a hook to insert a noop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26560 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 33143dce15c0dc4155ff4cf2e375a9a59c8a5d61 |
03-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Number of NodeTypes now exceeds 128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26503 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 00ffed0468ad406062b7c08c2ff46d79d2d1be4d |
01-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add interfaces for targets to provide target-specific dag combiner optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26442 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| bf57e1f456603b3f584ea42313bed89f630828fb |
01-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Missing a cast previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26434 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 5ee3e141277599df41488b965327d5c62b904860 |
24-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Add C_Memory operand type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26344 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4c1aa866578f7a358407a22fe55b454f52a24325 |
22-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Added option -relocation-model to set relocation model. Valid values include static, pic,
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetOptions.h
|
| 410354fe0c052141dadeca939395743f8dd58e38 |
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Make the LLVM headers "-ansi -pedantic -Wno-long-long" clean.
Patch by Martin Partel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26313 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetLowering.h
|
| 1efa40f6a4b561cf8f80fe018684236010645cd0 |
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
split register class handling from explicit physreg handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 16d597a20d405d8cb13f89f15b8c1fed20428808 |
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
expose the set of values types holdable in a regclass to clients
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26307 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| aba3b13fb3e00b16725860e46a484c88136569f6 |
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Pass in a value type to getRegForInlineAsmConstraint, allowing targets to
select different sets of registers depending on the type requested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26304 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c9fdea915aaeb1343c3e9825886ce18efdb91994 |
18-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Move PICEnabled declaration here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26271 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 70804d3e148a52a44ba6748e59149b3a9b90070b |
17-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Fix a nit sabre noticed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26262 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 368e18d56a87308045d341e85584597bfe7426e9 |
16-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a03a5dc7ce876dac4b3b91bae14216de4233bacd |
14-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26174 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| eac707f7022c011c61154568b136290703b74316 |
07-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
getConstraintType should be virtual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26041 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c991cf58aa36b369c296b8ad3087f405939bc530 |
04-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Add some methods for inline asm support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25950 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| de99629e2ae8cd7cc731328d2ad6ed6b8e759f2c |
03-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Add a framework for eliminating instructions that produces undemanded bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25945 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| af9fa2bd0c1ee25f3adda96b3e5d7129fbab393a |
02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,
a far more logical place. Other methods should also be moved if anyone
is interested. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25912 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetInstrInfo.h
|
| 679836360a94cb419e8d945b14483a3e47607638 |
02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
add a new isStoreToStackSlot method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25909 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| cb0b5556630aec89231e3e656ed4f1357cf1bb61 |
30-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Clear the OpAction field before setting it. This allows a target to set
an instruction operation action to Expand, then set it to Legal later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25812 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 553d8007ad29ab4ba7be261e91c38556dccdd95e |
30-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,
making isMaskedValueZeroForTargetNode simpler, and useable from other parts
of the compiler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25802 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 030dae5bcec6ba82ccfbf633354d1766ee70b084 |
30-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Pass the address of the main MaskedValueIsZero function to allow recursion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25797 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| e3bd778e4dbf6271ef522ba4f7b28499c3819b2a |
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Clean up the interface to ValueTypeActions, allowing Legalize to use a copy
of it more cleanly. Double the size of OpActions, allowing it to hold actions
for any VT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25782 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7e871b28a208b497f31ec7b162586f57e4d38d58 |
28-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
remove this method I just added, now is not the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25729 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4f16e70faad0840357998059f7f296e5f5e412be |
28-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
add a new callback
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25727 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 0aed7840ec8cc85f91b4aa6e69318bba0cbd1f03 |
28-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Implement Promote for VAARG, and allow it to be custom promoted for people
who don't want the default behavior (Alpha).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25726 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ee625573b5b39b91441fc6ea23f3ba415abdc71f |
27-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4ed88eb8229848cd6add06a1ec90e497e382306f |
27-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Add a common INLINEASM opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25667 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 9471c8a93b117d8ac01c4ef1cb9faa583e03dec0 |
26-Jan-2006 |
Jeff Cohen <jeffc@jolt-lang.org> |
Improve compatibility with VC2005, patch by Morten Ofstad!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25661 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| bc9ae377d9880a0257b9a5aaeac9b1691cc47398 |
26-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Add a method for inline asm support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25656 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| acc398c195a697795bff3245943d104eb19192b9 |
25-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
First part of bug 680:
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25606 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d854b62afa9a9c3ee8c968199af0d94ed215e19e |
25-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add a enum to specify target scheduling preference: SchedulingForLatency or
SchedulingForRegPressure. Added corresponding methods to set / get the value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25598 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 2790383f7387f0770e08f36ccefc9b621d88f98b |
14-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Add a new InvalidateStructLayoutInfo method and some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25303 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| d90ef9ef2b24047f46973a43390a3191fc1fee63 |
13-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Provide an interface for Targets to specify their stack pointer register
for llvm.stacksave/restore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25275 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 9337de86516832daf991e75d8a6f7ae2493b6225 |
22-Dec-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Oh oh... Unix is case sensitive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24928 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| f31a60cd71ea4dd0577cc1a21df8b7d49bf18c8c |
22-Dec-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Make it compile with VC++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24927 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| c85b33f264f978a4276775873da935d0a906f19d |
22-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Added TargetLowering::isMaskedValueZeroForTargetNode() declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24923 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7226158d7e3986e55b58214a749aa4eabb3fb6d5 |
20-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Added a hook to print out names of target specific DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24877 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6510b22cec7de4f0acc9965ec24c3668a6a8a87e |
01-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 6a648614e88586e85a36ceb5c1d3b84e4f55b458 |
29-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Add the majority of the vector machien value types we expect to support,
and make a few changes to the legalization machinery to support more than
16 types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24511 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 395cba8d41a170e86d16d37ec4c31f6e441b82f6 |
17-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Teach the type lowering code about turning packed types into vector types.
Next step: generating vector dag nodes, and legalizing them into scalar
code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24404 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| df2e425f2a3b64eb17be927539cd39cb1f1c5f77 |
08-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Add a new option to indicate we want the code generator to emit code quickly,
not spending tons of time microoptimizing it. This is useful for an -O0
style of build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24235 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| be07f72ca27035a93269987ae06cdd19f655744b |
04-Nov-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
<cassert> no longer required to make VC++ happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24177 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 09540387058a23f2d559ad5f89bba0763b427ea7 |
04-Nov-2005 |
Duraid Madina <duraid@octopus.com.au> |
change NULL to 0, unbreaks the ppc target when building on ia64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24176 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 7f39c14f52262a154285df9180f5edcdabe2d7df |
03-Nov-2005 |
Jim Laskey <jlaskey@mac.com> |
1. Remove ranges from itinerary data.
2. Tidy up the subtarget emittined code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24172 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 55d1728ec80c7f39d0bb2a68a1bd38b268496ef7 |
02-Nov-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Keep VC++ happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24148 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 6cee630070b1a7183ed56a8404e812629f5ca538 |
01-Nov-2005 |
Jim Laskey <jlaskey@mac.com> |
Allow itineraries to be passed through the Target Machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24139 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
argetInstrItineraries.h
argetMachine.h
|
| 15517be4bfc7ec7e60ecb25dc0bb46de27d3de37 |
27-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Structures used to hold scheduling information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24049 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrItineraries.h
|
| 34bd5d5d876212611d8b66a18f4c8604b342c6eb |
25-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Preparation of supporting scheduling info. Need to find info based on selected
CPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23974 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 3e8d596ded8255ec66bdf962cc53db4971414cd8 |
23-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Move static functions to .cpp file, reduce #includes, pass strings by
const&.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23890 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 405e3ecb563f21e7b4ee30f0de57821f3eb91219 |
21-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Invert the TargetLowering flag that controls divide by consant expansion.
Add a new flag to TargetLowering indicating if the target has really cheap
signed division by powers of two, make ppc use it. This will probably go
away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23853 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d32d4a93f6aa524116e7043a1d4059febab0de9b |
20-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Enable targets to say that integer divide is expensive, which will trigger
an upcoming optimization in the DAG Combiner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23834 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 4a95945fa5aa431110f50092f4a45d24772a553b |
19-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Add the ability to lower return instructions to TargetLowering. This
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23802 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a385bf7b6dc9b71024aa4c7bb7026bab3c7ebe91 |
03-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Fix case of path
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23605 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 9390368970d14361a2ab8c2886e10cc51e42fd1a |
03-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
This member can be const too
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23600 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 4c225baa3eeabca9b0e1ee71ee9f11f2193a0195 |
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Expose the actual valuetype of each register class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23583 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 0f21fd5204a2627c613340269e2e39e2c8cca659 |
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Rename MRegisterDesc -> TargetRegisterDesc for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23564 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 2f02ed9a1f952e534807fae3c51de92ca0eacfd3 |
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
trim down the target info structs now that we have a preferred spill register class for each callee save register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23560 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 2f9dbe8ee6ebe8ec2d72d66dcbd6018918eab018 |
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
expose a new virtual method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23555 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 294f41d5fc713350f060656e562c34ddf1cbe1c6 |
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Change these methods to take RC's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23535 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 5e93fbe68c8f0b08cf79fd3ec4d58e74aa760e15 |
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Add a new flag for targets where setjmp/longjmp saves/restores the signal mask,
and _setjmp/_longjmp should be used instead (for llvm.setjmp/llvm.longjmp).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23479 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7d3041e060adfd1f4054f45581bb01a4b9920f56 |
17-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
add a new callback
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23373 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 839615a510c582ddcdb09a8e2934f30775daa032 |
02-Sep-2005 |
Jim Laskey <jlaskey@mac.com> |
Add help support for -mcpu and -mattr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23222 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 0271077eba5f62796f4c725baa8e7fc88bf97650 |
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Move a bunch of non-deprecated methods above the "deprecated line"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23216 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 7cd57f4c452c39ee595de19633787ec37933eb34 |
02-Sep-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Fix VC++ build errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23210 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| b1e1180ca0b32f37aa74d7ad703eeaf91e66c8fa |
01-Sep-2005 |
Jim Laskey <jlaskey@mac.com> |
1. Use SubtargetFeatures in llc/lli.
2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23192 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| b3302db18a779527a4b1cd7a2024543ade7e83c6 |
01-Sep-2005 |
Jim Laskey <jlaskey@mac.com> |
This new class provides support for platform specific "features". The intent
is to manage processor specific attributes from the command line. See examples
of use in llc/lli and PowerPCTargetSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23191 91177308-0d34-0410-b5e6-96231b3b80d8
ubtargetFeature.h
|
| 0f9beca707b98ecfc7af252c5827958f7ede4c74 |
27-Aug-2005 |
Reid Spencer <rspencer@reidspencer.com> |
Change the names of member variables per Chris' instructions, and document
them more clearly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23118 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 050967c4d1b97dea9afbe4a27d9e601af63f918f |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add some forward defs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23100 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8fae46675dbd636f68fde437263d7e6fb03c482a |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
spell this right!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23097 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| a8fbee6f09f06ae224d855e07093c5e70b3fb694 |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add a hook
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23096 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 09321dcf5a3d8acb89dfcad2191c630a54938458 |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add a new instruction flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23093 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| de6a4bc058b10a63d7989b85a2ea239362babbe7 |
24-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
rename hasNativeSupportFor* -> is(Operation|Type)Legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23011 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| ae72f4a642192abab5a2d10592200a94fcba61de |
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add a new field to TargetInstrDescriptor for tracking information about
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22908 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 73bfa7152481620d60bf63d5397dfe35bbc9c098 |
19-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove the X86 and PowerPC Simple instruction selectors; their time has
passed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22886 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 5ab83632066071413841af43bc5d1edcced18076 |
05-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Since getSubtarget() always provides a const Subtarget, dont' require the user
to pass it in. Also, since it always returns a non-null pointer, make it
return a reference instead for easier use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22686 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 9eb59ec548b861d6ede05b4e6dc22aabf645e665 |
27-Jul-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Eliminate tabs and trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22520 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
argetMachine.h
|
| 6a6b2dbd3a6786c6ef3d79a0b685291631245d32 |
22-Jul-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
allow constants to be relocated like GV (necessary for alpha, as constants are relocated with globals, not with .text), and allow targets to have a GOT managed for them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22496 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| a0f5bf306c0e66ca5fc519fd3b0cb732d37d4a5e |
19-Jul-2005 |
Reid Spencer <rspencer@reidspencer.com> |
For: memory operations -> stores
This is the first incremental patch to implement this feature. It adds no
functionality to LLVM but setup up the information needed from targets in
order to implement the optimization correctly. Each target needs to specify
the maximum number of store operations for conversion of the llvm.memset,
llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations.
The limit needs to be chosen at the threshold of performance for such an
optimization (generally smallish). The target also needs to specify whether
the target can support unaligned stores for multi-byte store operations.
This helps ensure the optimization doesn't generate code that will trap on
an alignment errors.
More patches to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22468 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 8d2623d49a7b53f2bb25f2b61c14aecb91e19154 |
12-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Clean up and add comments to the newly implemented subtarget code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22396 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 0e219eb9b8a2f6cb1128066584b06c6bd1b51238 |
12-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Clean up the TargetSubtarget class a bit, removing an unnecessary argument
to the constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22392 91177308-0d34-0410-b5e6-96231b3b80d8
argetSubtarget.h
|
| fb5792f416089d8d8d0c6ee62c1f41a55d2cf75d |
12-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement Subtarget support
Implement the X86 Subtarget.
This consolidates the checks for target triple, and setting options based
on target triple into one place. This allows us to convert the asm printer
and isel over from being littered with "forDarwin", "forCygwin", etc. into
just having the appropriate flags for each subtarget feature controlling
the code for that feature.
This patch also implements indirect external and weak references in the
X86 pattern isel, for darwin. Next up is to convert over the asm printers
to use this new interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22389 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetSubtarget.h
|
| e64e72b794cfa385372436b3c88460aeee0acbf6 |
05-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
Make several cleanups to Andrews varargs change:
1. Pass Value*'s into lowering methods so that the proper pointers can be
added to load/stores from the valist
2. Intrinsics that return void should only return a token chain, not a token
chain/retval pair.
3. Rename LowerVAArgNext -> LowerVAArg, because VANext is long gone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22338 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 33f80a87230f61b85f62cbc956b6f521b6e2063c |
25-Jun-2005 |
Chris Lattner <sabre@nondot.org> |
add some new file types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22286 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 11f14c8be0946a8fb95189156ff1d64a01ff7da3 |
25-Jun-2005 |
Chris Lattner <sabre@nondot.org> |
refactor these interfaces a bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22281 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| f5428213853bae45247fe6da711ff20954d73dbd |
18-Jun-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
header file changes for varargs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22253 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 771c5c18193f800b7e8a29c0c897831cc056cf08 |
17-Jun-2005 |
Tanya Lattner <tonic@nondot.org> |
Added ModuloSchedSB as a friend class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22237 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| bc83996b31795173b9dd550bd9fbf55d08335901 |
14-May-2005 |
Chris Lattner <sabre@nondot.org> |
Pass the dag into LowerOperation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22005 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| adf6a965a321372c640845407195594835921eb4 |
13-May-2005 |
Chris Lattner <sabre@nondot.org> |
Add an isTailCall flag to LowerCallTo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21958 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| b15a8f5f8c986b1761993792bb5654a2b7abbbfa |
12-May-2005 |
Chris Lattner <sabre@nondot.org> |
LowerCallTo now takes the cc to use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21901 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 39d7f8f3383552868b3ea2f3fa8cabca78decfbd |
12-May-2005 |
Chris Lattner <sabre@nondot.org> |
Add a little hook
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21883 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 34f74a6162f1e493a9773e83a684cf31fa4838de |
30-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Expose an option allowing unsafe math optimizations. Patch contributed by
Morten Ofstad!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21630 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| a1aad3b0eda2a516f663cb5f9f8c4c9bbb6ef224 |
25-Apr-2005 |
Reid Spencer <rspencer@reidspencer.com> |
Shut GCC 4.0 up about classes that have virtual functions but a non-virtual
destructor. Just add the do-nothing virtual destructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21524 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 446b5a9dd9b249e5910489dbfcf86fda502627ef |
24-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
* The aesthetic police is on patrol!!...
* ... but it wasn't so busy as to not smell the roses and doxygenify comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21487 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 3fa94bffcba19f60c8a3f0503a6b1ed3abb1b5c7 |
24-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Add a helper method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21486 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 00876a2808f1a8061f7e0852c7949fc5074ecb04 |
22-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
Convert tabs to spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21438 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetFrameInfo.h
argetInstrInfo.h
argetSchedInfo.h
|
| 34695381d626485a560594f162701088079589df |
21-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21412 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetData.h
argetFrameInfo.h
argetInstrInfo.h
argetJITInfo.h
argetLowering.h
argetMachine.h
argetMachineRegistry.h
argetOptions.h
argetSchedInfo.h
|
| f8b02949e3d13e9b7cd38e029fcbf3e799366aa7 |
16-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Make pattern isel default for ppc
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
0 == off
1 == on
2 == target default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21309 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| 7b5987d56e194cea0364433a838abc2d6844e047 |
07-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Allow targets which produce setcc results in non-MVT::i1 registers to describe
what the contents of the top bits of these registers are, in the common cases
of targets that sign and zero extend the results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21145 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 5ebc3dbc1c11c4c626c7aca9d545dc624c08bd1a |
26-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Change LowerCallTo to take a boolean isVarArg argument. This is needed
by the PowerPC backend, and probably others in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20843 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 977df767228a1754d17c8624c33138325e5dbf1b |
13-Mar-2005 |
Chris Lattner <sabre@nondot.org> |
add a helper method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20578 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| d7e2fe40e42dffa04a770191c3414446d5e8c30a |
19-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Add a new method, described in the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19683 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 6147a7aa17b40f457f073689481fed2ff9ef4819 |
19-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Move all data members to the end of the class.
Add a hook to find out how the target handles shift amounts that are out of
range. Either they are undefined (the default), they mask the shift amount
to the size of the register (X86, Alpha, etc), or they extend the shift (PPC).
This defaults to undefined, which is conservatively correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19676 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 6ae76fcc060e1943c54bb9b07bd3b5cdb3c793bc |
17-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Add comments
Add fields to hold the result type of setcc operations and shift amounts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19618 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 7e5ee4097940d9e3b49b858ffbb3e52b0953fde0 |
16-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Revamp supported ops. Instead of just being supported or not, we now keep
track of how to deal with it, and provide the target with a hook that they
can use to legalize arbitrary operations in arbitrary ways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19609 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 638559aaa3a30cef596fae20292295cb0a329df1 |
16-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Improve compatiblity with HPUX on Itanium, patch by Duraid Madina
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19586 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| bb97d81cc873e2c0914f2ece43832723cc936d24 |
16-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Move some information out of LegalizeDAG into the generic Target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19581 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 45554a61f2814e1d445e272076fd7187e74a25c0 |
15-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Add a new target-independent code generator flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19567 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptions.h
|
| f19ae7df65fd50ff459347c240a738895cc71867 |
09-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Add interfaces to lower varargs and return/frame address intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19406 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| d4b1c9a938f77b31be88e2ac68b20a035c397275 |
08-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Make LowerCallTo more generic and useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19373 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 75c2d0a351cecb222af1da8734a8c1a32f9177a3 |
07-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
First draft of a new Target interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19323 91177308-0d34-0410-b5e6-96231b3b80d8
argetLowering.h
|
| 15f63ad2e59998f0bf1a3a23547582074391f650 |
02-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Add some bits that can be set on instructions. Renumber existing bits so
they are dense. Add a virtual method that targets can choose to implement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19242 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b0f72a17d9a852d5fd2e67f36636d8536cd60cc5 |
21-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix a warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18083 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| f3ae06ee1f257ff847200d51ed795bba2399e9a2 |
21-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Add new methods that a target should implement
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18060 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 9da3c56efd98cd9bf55104ca7d484728470eda6a |
20-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Allow targets to implement relocation support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18032 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 1fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721 |
27-Oct-2004 |
Chris Lattner <sabre@nondot.org> |
Convert 'struct' to 'class' in various places to adhere to the coding standards
and work better with VC++. Patch contributed by Morten Ofstad!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17281 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
argetFrameInfo.h
argetInstrInfo.h
argetSchedInfo.h
|
| 0aafc3289c3043abd5e8f2efdd8b9fc3e830d97f |
27-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Move destructor out of line to avoid vtable emission in every file that includes the header. Thanks to sabre.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17278 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 4c3480169ba413a86463a3ca8791f23816a8acc2 |
27-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix the build by eliminating some more dead code. That'll learn me not to listen to Reid
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17275 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 7853b38fd009a4b968c8dce983e226f99eedc77a |
27-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Remove dead data member in MRegisterInfo class. Thanks sabre!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17274 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 01808b36c33f9f2e245014bf917599138d8a5acc |
26-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Remove method getRegClass from MRegisterInfo, as it is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17243 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 7cf820191c0318a3ac75754eb9974a8b844809f6 |
25-Oct-2004 |
Chris Lattner <sabre@nondot.org> |
Remove a dead class. Thanks to Morten Ofstad for pointing this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17222 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| 49db6fe193168239be2f5aa8b4201614b739e840 |
28-Sep-2004 |
Chris Lattner <sabre@nondot.org> |
Be consistent with our naming
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16552 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| dcc4a6f705bacb66b98c58bb3b8c738d3e6df37b |
28-Sep-2004 |
Chris Lattner <sabre@nondot.org> |
Capture information about whether the target instructions have delay slots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16550 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 148d2065e4eb60357014a39c8e0d66c908679ffd |
28-Sep-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Use class instead of struct for defining classes. This unbreaks the
build on windows. Patch contributed by Paolo Invernizzi!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16531 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
|
| 551ccae044b0ff658fe629dd67edd5ffe75d10e8 |
02-Sep-2004 |
Reid Spencer <rspencer@reidspencer.com> |
Changes For Bug 352
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16137 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
argetInstrInfo.h
argetMachineRegistry.h
argetSchedInfo.h
|
| c3d479a40f5cc1efe6a6ece0cd43533a24971f12 |
29-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Update doxygen comment now that getSpillSize is supposed to return value in bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16101 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8 |
27-Aug-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Add getAllocatableSet() function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16059 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| d6640951c2425fd2fded86b380bbe5491c7940cd |
18-Aug-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
M_DUMMY_PHI_FLAG is no longer used to distinguish V9::PHI. Get rid of it and
its TargetInstrInfo accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15907 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b406d84dd8f8faee31d891ab9af298c672f98256 |
18-Aug-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
M_PSEUDO_FLAG is no longer used. Get rid of it and its accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15902 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| cdab78f036f7deef6fc9c15a45f9c1adf91c63ad |
17-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Add punctuation, add a new method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15886 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 303603f75876c1cb407002f0a3a110fe4c202b31 |
16-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Flags and TSFlags were (thankfully) never used, so remove them. But wait,
not so fast, add some fields for spill slot size and alignment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15803 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| f02b37da6f956dc9120a0da6ffa643b2753beb41 |
16-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Add new TargetRegisterClass::contains method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15783 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| da34645b2bd24e31e9df404e3ec1d5ac05ef412e |
16-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Implement a long overdue FIXME, by changing these methods to return void.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15778 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| ed6655920fe65a0e627b0de198793104663ee11e |
15-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Eliminate the RegisterClass argument, since it can easily be derived from
the regno
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15773 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 8c9b4de5744ea6c4ce8b79e8a55130df268761cd |
15-Aug-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Make this compile on gc 3.4.1 (static_cast to non-const type was not
allowed).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15766 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 5de0f7aa14f15f463cedf6391bc4823e79d342b5 |
15-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Elminiate MachineFunction& argument from eliminateFrameIndex
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15736 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 09431e187f9abd45af08461df728204ee9731fd7 |
12-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Allow targets to specify particular stack slots that certain physregs must
be spilled into.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15702 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 28690ea28515f60550ea4256a98b9e1b2caef563 |
12-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Remove dead methods
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15698 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 484577a870562ea16886f582650afcf38026b4cb |
12-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Remove dead methods
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15691 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 80b90cd1914ced00a58ed9ac4b9dce06e573c8eb |
11-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add new constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15632 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 93ad2cf91092c4ff45ace5b87b97179202e3de06 |
04-Aug-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
getResultPos() is dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15484 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 5714f44fdf1260d98722d902e11f8f9b9ed9bcc2 |
01-Aug-2004 |
Tanya Lattner <tonic@nondot.org> |
Adding friend MSSchedule for ModuloScheduling pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15407 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| c2df129da9828406d97f708989b5151ed04dec6b |
01-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Fix warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15406 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| e4d32f6cf96566f8d37e50212e4f67330150ee20 |
31-Jul-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Change signature to take two basic blocks: the target and the one
where the goto will be appended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15361 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 0cad9f53b15b7308e977864d681f710646e7d376 |
31-Jul-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Doxygenify some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15360 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 096f58b09adb03b5b060e12b327cff57329909f7 |
31-Jul-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Remove const from iterators passed by value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15359 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 905f7af59cb85ea71b6c011f1e79f24f8db16efc |
31-Jul-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Add declarations for insertGoto and reverseBranchCondition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15358 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 2441d6a895c1aad171bfbdc84cd6e246171b101d |
31-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Add new M_BARRIER_FLAG flag, and isBarrier() method to TargetInstrInfo
opCode -> Opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15353 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| b2f30a3792c84790fcf7f20bf581b963bb0a25d3 |
28-Jul-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
TargetInstrInfo::hasOperandInterlock() is always true, because it is
never overridden by any target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15308 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| de0ceb58bac96a6df133a04cf92bb220a16e12fd |
27-Jul-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
ConstantTypeMustBeLoaded has been incorporated into SparcV9PreSelection, its
only user.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15294 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 1b4aeb5cec6b6732d0833bac388c20de04fab961 |
27-Jul-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
As it happens, none of these TargetInstrInfo methods which are only
used in the SparcV9 backend really have anything to do with
TargetInstrInfo, so we're converting them into regular old global
functions and moving their declarations to SparcV9InstrSelectionSupport.h.
(They're mostly used as helper functions for SparcV9InstrSelection.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15277 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 1c2b1294d3f992aaee5262e62380ce2e730e6aa3 |
27-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15257 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| 8a1478b6d7aeaed8363316d2e0b90d9f53525c29 |
27-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Fix out of date comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15256 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| e3fa53ee4df41925c90ad6cc6a4f132284a1ae66 |
23-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Add a BoolAlignment field to TargetData, default is 1 byte
* Fix spacing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15119 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
argetMachine.h
|
| 2845ece825f302f9d841e8a743539ffd3f7edff8 |
11-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Add a new listener class for things that want to be informed about new
targets that are loaded
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14758 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| 635ffcdf58f9bdc35c4ad4969fb35dc3659cf384 |
11-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Delete the allocate*TargetMachine functions. Move options to a header file
that makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14754 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
argetOptions.h
|
| cbc74123d8ee5413fd87356e30037ed70201dac0 |
11-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Add a new TargetNameParser class, which is useful for parsing options.
Add two methods which are useful for autoselecting targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14748 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| 9f27ede92d42fde91cd118ab3a2146b59801a06a |
11-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
First cut at TargetMachineRegistry and RegisterTarget classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14742 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineRegistry.h
|
| a51e273a764b2a3e8fe856c3bd47b09f9446f380 |
11-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Add two new "virtual static" methods to the TargetMachine class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14741 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 992dce13ece1748aef8a6fdeef0f4e271165258c |
01-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Doxygenify comments
* Tabs-to-spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14549 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 66d6ee4247aa17b3019eb42f07b3842250b6f990 |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Spell out `NoFramePointerElim' for readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14299 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| b41dabd8ad06fd7780f5158af54c887a79515d07 |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Make a single `NoFPElim' switch available to all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14296 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| 694ffc0850c08df6332071c2bc535efff4136b81 |
16-Jun-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
I'm afraid this doesn't exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14193 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| 6e404b897b5a63368d424235d111bc134f6cd4e2 |
11-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix grammar: 's is for possessive only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14155 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| c07c0df634d31849ac659234e4718b57ddacb882 |
08-Jun-2004 |
Chris Lattner <sabre@nondot.org> |
Add documentation to the TargetFrameInfo class, contributed by Vladimir Prus
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14060 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 4f02562ec18e4690d46ecbfdaf967806ad072bdd |
04-Jun-2004 |
Chris Lattner <sabre@nondot.org> |
Fix a nasty bug that caused areAliases to always return false.
Bug fix courtesy of Anshu Dasgupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14011 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 498231bc601013da055fb8786d091b743c20006a |
03-Jun-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Collapse together the abstract superclass TargetRegInfo and SparcV9RegInfo, its
only concrete implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13977 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 36c2a0593509da714bea6457dd1b00a7417ce342 |
02-Jun-2004 |
Chris Lattner <sabre@nondot.org> |
Delete the V9 specific findOptimalStorageSize method, inlining it into all callers.
Substantially clean up all target implementations by having the OPTIONAL get*Info
methods return a pointer instead of a reference. This allows us to have default
implementations!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13950 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| e5abfd2c053058c322a5ef0213e8a0155fb9c05e |
08-May-2004 |
Tanya Lattner <tonic@nondot.org> |
Changed CPUResource to allow access to max num users for a resource.
Also added ModuloScheduling as a friend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13426 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| d11297f2ee2d6a366d129b7c10e60339ea4aa87f |
30-Apr-2004 |
Tanya Lattner <tonic@nondot.org> |
Sorry, now friend class name should be right!!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13294 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| c9bdf09192d3901608d73b16621d4b2e5f954944 |
30-Apr-2004 |
Tanya Lattner <tonic@nondot.org> |
Fixed friend class name for ModuloScheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13293 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| 32c182a0a880bfffa8b319abd9b6a1dd8f43835a |
30-Apr-2004 |
Tanya Lattner <tonic@nondot.org> |
Fixed friend class name for ModuloSched
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13292 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| 0e1c48b20995f4c6c304688ff2d06f26528baf1a |
30-Apr-2004 |
Tanya Lattner <tonic@nondot.org> |
Removing MachineResource class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13291 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| a7e405c95da37e0743a6d299bb777727a0186ae2 |
23-Apr-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Merged this file into the SparcV9 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13128 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 325297142c93ac162fcf9a3d78faeb1f49763914 |
14-Apr-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Add a copy constructor for TargetData.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12948 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| a1a7148c4de22a2cedc76b97ef80569b36698342 |
14-Mar-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Another API change to MRegisterInfo::foldMemoryOperand. Instead of a
MachineBasicBlock::iterator take a MachineInstr*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12392 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 39354c99a158685d8bc91b0836c283e936a29cb2 |
14-Mar-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Change MRegisterInfo::foldMemoryOperand to return the folded
instruction to make the API more flexible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12386 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 242e94ab268a6f614e0820540bda846a4b3306a9 |
12-Mar-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Move function implementations to a .cpp file, avoid #including <cstdlib> here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12296 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 323819e4e1e3573072e7dbd82b0ebd75b5df0648 |
04-Mar-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
make -print-machineinstrs work for both SparcV9 and X86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12122 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| 2bed9ecc4b5d74e61c997eb2d3877e0ab6257979 |
03-Mar-2004 |
Chris Lattner <sabre@nondot.org> |
Add a new constructor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12087 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 05b15fb075307d55a61694ebcb19bbc9b13aa9f8 |
01-Mar-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
TargetCacheInfo has been removed; its only uses were to propagate a constant
(16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's
dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in
the interest of not breaking things any more than they already are, I'm going
to leave the constant alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12043 91177308-0d34-0410-b5e6-96231b3b80d8
argetCacheInfo.h
argetMachine.h
|
| 6ac5300fbcebdc9a62a4e399c63997ab9b670c61 |
29-Feb-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Remove dead member variables of SparcV9SchedInfo and TargetSchedInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11994 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| bceb68807fdb86c794bc8d8f8aef0940f12c2ceb |
29-Feb-2004 |
Chris Lattner <sabre@nondot.org> |
Eliminate the distinction between "real" and "unreal" instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11986 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 450b6d29988fa01e828e5b7917a47726a4dd46ec |
29-Feb-2004 |
Chris Lattner <sabre@nondot.org> |
Scrap a huge layer of cruft out of this interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11980 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 3da51173349e2ec6d26228d4d2f59c91fccc39b0 |
28-Feb-2004 |
Chris Lattner <sabre@nondot.org> |
Add hook for V8 target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11961 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| 71e353ed3530a5da48c3dd3257c410f6c4ce2e3e |
26-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Uncomment assertions that register# != 0 on calls to
MRegisterInfo::is{Physical,Virtual}Register. Apply appropriate fixes
to relevant files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11882 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| c81493711574375bae500e7c702ca64fc0351e38 |
26-Feb-2004 |
Chris Lattner <sabre@nondot.org> |
Make TargetData no longer use annotations!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11874 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 4c50715e9e6ab41208b1bdb6b9c4145c357ab765 |
26-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Temporarily comment out asserts as they break things. I will uncomment
them when all the problem areas are fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11855 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 332d5d0a685bc31c2499b7cab8056a1fbcc52fa3 |
25-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Duh, forgot to close the parenthesis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11843 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 338ce3d64efed7abe7bf462a8477831dc9812685 |
25-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Add assert to isPhysicalRegister and isVirtualRegister to fail when
passed the special 'register' 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11842 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 4d0d864be3d9a698c4edfe36961a22126f041298 |
25-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Add DenseMap template and actually use it for for mapping virtual regs
to objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11840 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 150666fd82f96a8615e63d3797e2d00f3edcb3e0 |
25-Feb-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Great renaming part II: Sparc --> SparcV9 (also includes command-line options and Makefiles)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11827 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| 04319bb2bda50d2ae7cc284cb1c4e742b44a466b |
19-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
This is needed by assignment verification in linear-scan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11618 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 8026a6982e72f51cc231489fecfe19fbb973eb87 |
17-Feb-2004 |
Chris Lattner <sabre@nondot.org> |
Simplify and document the new interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11524 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| b499866c05cac0e97a22c5e1f477c89096be836b |
17-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Add API to check and fold memory operands into instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11519 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 8604e7572132e8728a1e20d53965bc4ab6986818 |
14-Feb-2004 |
Chris Lattner <sabre@nondot.org> |
The prologue/epilogue related method calls have no reason to return a value,
make them return void.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11447 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 8ff9a8639a526ec4c7bb86588c6154645bcdfbca |
14-Feb-2004 |
Chris Lattner <sabre@nondot.org> |
Make sure to provide a prototype for the cbackend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11419 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| be766c72464116a445a02b542a450c4274bab5d0 |
13-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Remove getAllocatedRegNum(). Use getReg() instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11393 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| ab8672c8bb83e722b856eac67863542ea7e0cbb2 |
12-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Add parent pointer to MachineInstr that points to owning
MachineBasicBlock. Also change opcode to a short and numImplicitRefs
to an unsigned char so that overall MachineInstr's size stays the
same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11357 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 024126ee23e6e4430a77025b61d0e713180f03d3 |
12-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Change interface so that we can add to the end of a basic block
without getting an assertion from ilist that we are dereferencing
ilist<T>::end().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11345 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| c0b9dc5be79f009d260edb5cd5e1d8346587aaa2 |
12-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Change MachineBasicBlock's vector of MachineInstr pointers into an
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| e28adaa633393d5beea7f8e97951cbe1e3cd1646 |
11-Feb-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Fix typos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11333 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 2d62c896a56d344fac4600918699d1a6208538d6 |
02-Feb-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Add prototype for llvm::allocatePowerPCTargetMachine().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11072 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| 93aa52a8a96c036454be9318bb1c78c9bfb5f390 |
01-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Add MRegisterInfo::getNumRegs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11058 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| bd490d919bd36d2ab956031b524a55dd8519eb64 |
31-Jan-2004 |
Chris Lattner <sabre@nondot.org> |
Add two static methods to avoid having client code explicitly compare against
FirstVirtualRegister
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11031 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 61eec1573a0a51b464da8cb3e4e081cf02475fbe |
21-Jan-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
If you call abort(), #include <cstdlib>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10941 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| f70e0c216c074bd2ae2b08178f5512849545db4e |
28-Dec-2003 |
Chris Lattner <sabre@nondot.org> |
Clean up a lot of the code I added yesterday by exposing the IntrinsicLowering
implementation from the TargetMachine directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10636 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 5e30002af70ef09a42cac155d9196f7f0f3b1695 |
28-Dec-2003 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Add TargetInstrInfo::isMoveInstr() to support coalescing in register
allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10633 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| cd824d7678785379a4a11fd7e3099cc44b37db41 |
28-Dec-2003 |
Chris Lattner <sabre@nondot.org> |
We may now pass IntrinsicLowering implementations into these methods
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10630 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| b0404c7a6c30fe347194b6c323bb283fcf708d49 |
22-Dec-2003 |
Chris Lattner <sabre@nondot.org> |
Doxygenize methods, add new getIntPtrType method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10578 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 1e60a9165dc4d6ce5650dacc026f2942696af920 |
20-Dec-2003 |
Chris Lattner <sabre@nondot.org> |
Rip JIT specific stuff out of TargetMachine, as per PR176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10542 91177308-0d34-0410-b5e6-96231b3b80d8
argetJITInfo.h
argetMachine.h
|
| 459ccab0021c9688c9a9be384758d0ce9cb5d79f |
12-Dec-2003 |
Chris Lattner <sabre@nondot.org> |
Add new getJITStubForFunction method, which may optionally be implemented by
targets for better performance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10429 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| d0fde30ce850b78371fd1386338350591f9ff494 |
11-Nov-2003 |
Brian Gaeke <gaeke@uiuc.edu> |
Put all LLVM code into the llvm namespace, as per bug 109.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetCacheInfo.h
argetData.h
argetFrameInfo.h
argetInstrInfo.h
argetMachine.h
argetMachineImpls.h
argetRegInfo.h
argetSchedInfo.h
|
| 80f0b57b5d101f5b52d803c570dc74cca47e53f9 |
05-Nov-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
Since this function returns an int, let's actually return something.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9734 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 4dad76cea0a85f62e016636b5b59d0bc4a7411dc |
05-Nov-2003 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Update documentation since it was misleading: make it clear that a
negative instruction count is returned if instructions are removed
from a basic block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9705 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| e668dab5b339df01920b8bff890a70455b7dd27a |
04-Nov-2003 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Change all machine basic block modifier functions in MRegisterInfo to
return the number of instructions added to/removed from the basic block
passed as their first argument.
Note: This is only needed because we use a std::vector instead of an
ilist to keep MachineBasicBlock instructions. Inserting an instruction
to a MachineBasicBlock invalidates all iterators to the basic
block. The return value can be used to update an index to the machine
basic block instruction vector and circumvent the iterator elimination
problem but this is really not needed if we move to a better
representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9704 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 6fbcc26f1460eaee4e0eb8b426fc1ff0c7af11be |
20-Oct-2003 |
John Criswell <criswell@uiuc.edu> |
Added LLVM copyright header (for lack of a better term).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9304 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetCacheInfo.h
argetData.h
argetFrameInfo.h
argetInstrInfo.h
argetMachine.h
argetMachineImpls.h
argetRegInfo.h
argetSchedInfo.h
|
| a42649e3dd4c8be2d45451429a41f2b13dbeeb78 |
20-Oct-2003 |
Brian Gaeke <gaeke@uiuc.edu> |
Make replaceMachineCodeForFunction return void.
Make it assert by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9287 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 5358bc39c11868390fd444a04149d6964f8fdc62 |
17-Oct-2003 |
Brian Gaeke <gaeke@uiuc.edu> |
Add stub version of replaceMachineCodeForFunction. It will live here until
we have a better place for it to go.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9197 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 48486893f46d2e12e926682a3ecb908716bc66c4 |
30-Sep-2003 |
Chris Lattner <sabre@nondot.org> |
Standardize header file comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8782 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
argetMachine.h
argetRegInfo.h
argetSchedInfo.h
|
| 4f98928d580d6f6c5fa2547ec06c0546b33285bd |
01-Sep-2003 |
Chris Lattner <sabre@nondot.org> |
Remove dead file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8313 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptInfo.h
|
| c5dc89059621783d8b765bdacdb0e209fe1280ca |
01-Sep-2003 |
Chris Lattner <sabre@nondot.org> |
No longer require an OptInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8310 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| e3ac7565a05145e736771ef55b625a64633a23ec |
24-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
Targets should configure themselves based on the module, not some wierd flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8131 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| ef6a6a69ff1e1b709d0acb315b9f6c926c67a778 |
22-Aug-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
The word `dependent' has no `a'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8030 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 5560c9d49ccae132cabf1155f18aa0480dce3eda |
18-Aug-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
Spell `necessary' correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7944 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 960ff04a09407ba6e4bd5ccee880990b8fc41686 |
15-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
Remove extraneous #include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7881 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 8844a0ba898a3a1db7f5fd91ecf6a5402e3d51a0 |
13-Aug-2003 |
Brian Gaeke <gaeke@uiuc.edu> |
addPassesToJITCompile and addPassesToEmitMachineCode now take a
FunctionPassManager, to support function-at-a-time compilation and
emission of code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7821 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 9ca5a2a33e98b0a93dc335a00f4d63aeb9a192b8 |
03-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
The NOOP instruction is no longer needed. Instead, use the
TargetInstrInfo::isNOPinstr method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7530 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 92988ecdb6ca641ba39d1d1f8cbc57a89b63bbad |
30-Jul-2003 |
Chris Lattner <sabre@nondot.org> |
Code generation passes don't need access to raw LLVM types, this method is unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7412 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 588668d4681bf928e09534c373b1bcf86757f899 |
29-Jul-2003 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Unify all constant evaluations that depend on register size
in TargetInstrInfo::ConvertConstantToIntType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7398 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| ceb7d2f4f8bb220990b9392f4dcf1eff7fd5690c |
29-Jul-2003 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Moved insertCallerSavingCode() to PhyRegAlloc and
moved isRegVolatile and modifiedByCall here: they are all
machine independent. Remove all uses of PhyRegAlloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7387 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 5d7407cbef2a441801e6d6a3a9f0c98793fd72e1 |
29-Jul-2003 |
Chris Lattner <sabre@nondot.org> |
Move value type enums to CodeGen/ValueTypes.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7376 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 523eb3f768b8c1252e231acd77d0ee758f5ddcd0 |
25-Jul-2003 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Change the way unused regs. are marked and found to consider regType
info (since multiple reg types may share the same reg class).
Remove machine-specific regalloc. methods that are no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7328 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| be67780f31958b05ad3c510ca3a973d327517e86 |
25-Jul-2003 |
Chris Lattner <sabre@nondot.org> |
#include <cassert> as necessary...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7315 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetInstrInfo.h
argetRegInfo.h
|
| 6da69e75ec594afe6758d923ff011b59c2e82dee |
20-Jul-2003 |
Anand Shukla <ashukla@cs.uiuc.edu> |
Added special consideration for instrumentation strategy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7208 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| bc0e998c497446f5448425b3cbd7f8f19a458764 |
14-Jul-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
The word `separate' only has one `e'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7173 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 7a73b80b9052136c8cd2234eb3433a07df7cf38e |
30-Jun-2003 |
John Criswell <criswell@uiuc.edu> |
Merged in autoconf branch. This provides configuration via the autoconf
system.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7014 91177308-0d34-0410-b5e6-96231b3b80d8
argetCacheInfo.h
argetInstrInfo.h
argetRegInfo.h
|
| d7908f679eeadc108e09e2aca5faba0b5410ea4a |
27-Jun-2003 |
Brian Gaeke <gaeke@uiuc.edu> |
Nice tasty llc fixes. These should fix LLC for x86 for everything in
SingleSource except oopack and Oscar. (Sorry, Oscar.)
include/llvm/Target/TargetInstrInfo.h: Remove virtual print method. Add
accessors for ImplicitUses/Defs.
lib/Target/TargetInstrInfo.cpp: Remove virtual print method. If you
really wanted this, just use MI->print(O, TM); instead...
lib/Target/X86:
FloatingPoint.cpp: ...like this.
X86InstrInfo.h: Remove virtual print method. Define the PrintImplUses
target-specific flag bit.
X86InstrInfo.def: Add the PrintImplUses flag to all the instructions
which implicitly use CL, because the assembler needs to see the CL in
order to generate the right instruction.
Printer.cpp: Ditch fnIndex at Chris's request. Now we use CurrentFnName
to name constants in the constant pool for each function instead. This
avoids keeping state between runOnMachineFunction() invocations, which
is a no-no. Having MangledGlobals be global is a bogon I'd like to get
rid of too, but making it a static member of Printer causes link errors
(why???).
Make NumberForBB into a member of Printer instead of a global, too.
Make printOp and printMemReference into methods of Printer.
X86InstrInfo::print is now Printer::printMachineInstruction, because
TargetInstrInfo::print is history. (Because of this, we have to qualify
the names of some TargetInstrInfo methods we call.)
Print out the ImplicitUses field of any instruction we print that has
the PrintImplUses bit set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6924 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 3889a2cb05c36f30050941679d5fd55d45e6a3ed |
22-Jun-2003 |
Chris Lattner <sabre@nondot.org> |
Remove a ton of extraneous #includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6842 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetSchedInfo.h
|
| be583b914d8156b99d3da264d5adca37fee8dbc9 |
11-Jun-2003 |
John Criswell <criswell@uiuc.edu> |
Included assert.h so that the code compiles under newer versions of GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6682 91177308-0d34-0410-b5e6-96231b3b80d8
argetCacheInfo.h
argetInstrInfo.h
argetRegInfo.h
argetSchedInfo.h
|
| 17035c0edf5463fd9edb8496502f4c5a0dc1d7ab |
03-Jun-2003 |
Chris Lattner <sabre@nondot.org> |
Remove noncopyableV base classes, as they were confusing the doxygen documentation,
making it harder to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6575 91177308-0d34-0410-b5e6-96231b3b80d8
argetCacheInfo.h
argetMachine.h
argetOptInfo.h
argetRegInfo.h
|
| 3fd7bf425789c798ec13ed3c9fdfcde26926f3d7 |
31-May-2003 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Made a single common InvalidRegNum = -1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6473 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| e5841daa7901154a018a93f863347e2e77f64abe |
29-May-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
Fixed misspelling and broke a line that was wrapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6391 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 504905fd4b5334c8763fa4b9c61e618fa68d4b8b |
27-May-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
Allow allocation of a Sparc TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6364 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| bfebd79dd11a04974ea71f79a160c31fc45a91af |
27-May-2003 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
(1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6343 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 28fc440bc630b50f17d911eb9adab7038a771836 |
25-May-2003 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Make case of GetNumOfInt/FloatArgRegs functions to be use lower case
like all the other functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6326 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 12745c55e1d5a6e76d41684f1b507ea7c6b888ac |
24-May-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
Reword to remove reference to how things worked in the past.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6323 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 00b05bd703b0d50133aecf4ce9f48e96d14504b3 |
24-May-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
NOP instructions are pseudo-instructions. We should not have them explicitly in
our representation, since they are usually special cases of already-existing
instructions.
This abstracts away methods that let a pass create and verify a NOP instruction,
without relying on a `NOP' enum to be in existence in the target's instruction
info descriptor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6319 91177308-0d34-0410-b5e6-96231b3b80d8
argetInstrInfo.h
|
| 10daaa141661d96843f3d8ece0e5a4c2da4b6e87 |
26-Apr-2003 |
Chris Lattner <sabre@nondot.org> |
Remove two fields from TargetData which are target specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5963 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
argetMachine.h
|
| 322bc2b5aa02dc9be24cf1f81c69e67f246aa52b |
25-Apr-2003 |
Chris Lattner <sabre@nondot.org> |
Fix method name type-o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5933 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| d6cbe339afebd5c16afec9b810ce46ffd3102791 |
25-Apr-2003 |
Chris Lattner <sabre@nondot.org> |
Default ctor doesn't provide name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5921 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 4bc8e640b8338566f59bea3532e818eb9e2685b2 |
24-Apr-2003 |
Chris Lattner <sabre@nondot.org> |
Add new targetdata ctor to create a targetdata appropriate to the module
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5902 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 4bd8b244701feda01adf713eac0a16342c12021e |
07-Apr-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
Must use std::pair instead of just 'pair'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5767 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| 681220dc3c80b2485cac895a18e63a028eb0fed0 |
07-Apr-2003 |
Guochun Shi <gshi1@uiuc.edu> |
added a function and a member to the TargetSchedInfo class
which is used by Modulo Scheduling pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5766 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| 0a166155e71910515b79d482e69ac52deb47db06 |
15-Jan-2003 |
Chris Lattner <sabre@nondot.org> |
Simplify the interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5313 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 3501feab811c86c9659248a4875fc31a3165f84d |
14-Jan-2003 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstrInfo -> TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
argetRegInfo.h
argetSchedInfo.h
|
| cb09cc268b510e99d40b3518c5a390369ae3ffd5 |
14-Jan-2003 |
Chris Lattner <sabre@nondot.org> |
Move annotation to support library
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5268 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 2584ba5867c06e676519d5c7cccbcd59eb7641bc |
13-Jan-2003 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstrInfo -> TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5214 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 075b4a066db31f48e0f6daec34b1ff463523cd3f |
13-Jan-2003 |
Chris Lattner <sabre@nondot.org> |
* Start renaming MachineInstrInfo -> TargetInstrInfo
* Add new M_TERMINATOR_FLAG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5213 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 09d4fd57de5ffa254808cc8ae71cd72ab2433911 |
13-Jan-2003 |
Chris Lattner <sabre@nondot.org> |
Add new getName method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5212 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| d0f166a4868c957041fa0ca0a35adde97aa10c91 |
29-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
More renamings of Target/Machine*Info to Target/Target*Info
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5204 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetRegInfo.h
argetSchedInfo.h
|
| f27eeea54fb0176986f76731c499176345047dff |
29-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Rename MachineOptInfo to TargetoptInfo
Rename MachineCacheInfo to TargetCacheInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5203 91177308-0d34-0410-b5e6-96231b3b80d8
argetCacheInfo.h
argetMachine.h
argetOptInfo.h
|
| 5b927c790ed3baa9b555057c9c0904fc34990ba8 |
28-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
* doxygenize comment
* rename MachineFrameInfo to TargetFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5170 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 5fa01b9c7a33ecd0e006427ae2a44170cf60422d |
28-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Sparc specific methods default to abort rather than being pure virtual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5169 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| fd529d2e4aed9a455d539962248fda8583d6ba8e |
28-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Expose some very simple information about the frame, rather than in-depth
target specific information. Rename MachineFrameInfo to TargetFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5168 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| f9b332b59d1c008268551572557dca6ab6028a4d |
28-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
* Keep track of register alignment as well as register size
* Add comments
* Add a new allocation_order iterator for register classes which targets may
use to control the register order and available registers based on properties
of the function being compiled.
* Remove access to FP and SP registers
* Add new callframe setup opcode support
* Eliminate moveImm2Reg method
* Revamp frame offset handling and prolog/epilog code generation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5167 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 8c5d47da98e98ca70bbdba0d7eb9149c52ff29ba |
25-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Simplify spill interface methods
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5142 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 13a6e1e5a1483db8f88d38dd7dcd48b9ca8e945a |
25-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Add comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5141 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 434c86dd3f03dff344793e9faf1a66d164bf21b6 |
24-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Allow the target machines to specify endianness and pointer size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5128 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
argetMachineImpls.h
|
| 8797caac84c3012416e933c9c05ad34d75bf4029 |
17-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Simplify interface to remove virtual function references
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5100 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 00032bf6cc236b1fb534f74b1ac288f611a86804 |
16-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Add support for register alias set description
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5080 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 70535c608d88ce25fb992dba3b6d3d0176153a09 |
15-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Export well known instruction opcodes usable by target independant passes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5063 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 198ab640bbb0b8e1cdda518b7f8b348764e4402c |
15-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Simplify interfaces used by regalloc to insert code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5052 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 0f24e33b73542bd7b280550aec6cff32d808e724 |
15-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Simplify TargetRegisterClass a bit, also eliminating virtual function call
overhead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5049 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| aa8dad5561f148d4706612549808d024f5bc43cb |
15-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
* Rename const_regclass_begin/end to just regclass_begin/end
* Regclass iterators need an extra level of pointerness to work right
* Pull inverse mapping code out of target description files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5046 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 2b46e8ecccfe8a6adc861158a21b67fb9e786885 |
13-Dec-2002 |
Misha Brukman <brukman+llvm@gmail.com> |
Added moveReg2Reg() and moveImm2Reg() to accomodate moving data around due to
PHI nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5001 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 9ada014ec09579a7dd3833f779a1de82bd71bce1 |
13-Dec-2002 |
Misha Brukman <brukman+llvm@gmail.com> |
Define the 2-address flag used by X86 instructions (add,sub,and,or,xor) that
need to be declared as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4975 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 9da4d263b98ab50aa707ef3edbe2f02a6e3337f3 |
05-Dec-2002 |
Misha Brukman <brukman+llvm@gmail.com> |
Added prototypes for emitting prologue and epilogue for function code
generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4927 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| a361c8417b9c2381a097a6dfdbfb7ac0d8379a69 |
04-Dec-2002 |
Misha Brukman <brukman+llvm@gmail.com> |
storeReg2RegOffset() and loadRegOffset2Reg() now take the iterator by value
instead of by reference, since they return the modified iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4914 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 0af0d5bd3e38dfcf29aec3e9982e3097a6e491d9 |
04-Dec-2002 |
Misha Brukman <brukman+llvm@gmail.com> |
Moved buildReg2RegClassMap() into from X86RegisterInfo to MRegisterInfo, since
it is target-independent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4911 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 08053e46be0c7f2024b3df7bfad822f71ac94de3 |
04-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Expose target data through a method for uniformity
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4901 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 44662a783b8dbef0292c8337a52fce665b3b9f4c |
04-Dec-2002 |
Misha Brukman <brukman+llvm@gmail.com> |
RegisterInfo now supports handing out caller- and callee-save registers, as
well as building a map from a physical register to its register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4896 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| f6d12fbd9cc0355978a739f5ab213eff85b75a19 |
03-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Add entries to track information about implicit uses and definitions of
the instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4875 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| b7a2d2256fede467c7f50444eb3cddadcd7d34c9 |
02-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
The hopefully final version of addPassesToEmitMachineCode which does not
have any question about ownership
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4863 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| dc095240c9016a7957a1976f6b1c0266b648f9d0 |
02-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Add comment about ownership semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4859 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 9f729a30b2e0648209f864da9da8aaa6a4be5e38 |
02-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Add stub to emit machine code for JIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4856 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| f6a132c7a0226979aacf9d34b953452df9f140b3 |
22-Nov-2002 |
Misha Brukman <brukman+llvm@gmail.com> |
Added virtual functions for storing and retrieving values from the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4824 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
|
| 282ec57c4cdd4574103922487b6f1563b5034fb4 |
20-Nov-2002 |
Misha Brukman <brukman+llvm@gmail.com> |
MRegisterInfo.h - Added prototypes for functions we need to map a register to
an appropriate TargetRegisterClass, also adds TargetRegisterClass definition.
TargetMachine.h - speling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4781 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterInfo.h
argetMachine.h
|
| fe30dd3f2390c26fe1f83868cd57a1e6b27d3075 |
18-Nov-2002 |
Chris Lattner <sabre@nondot.org> |
Make sure that print gets a targetmachine
CVS: ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4735 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 9bca50d6ddb8b53659a8db1dfa91a8b239178fe9 |
17-Nov-2002 |
Chris Lattner <sabre@nondot.org> |
Add machine independant printer interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4729 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 75e961ae6b2e2801160e560057ad97ece4443986 |
30-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
* Add new "Target Specific Flags" field to instruction descriptor
* Rename iclass to Flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4439 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 478df7a7ae3c9aaa753948712d894fade36a8195 |
30-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Add new optional getRegisterInfo to TargetMachine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4436 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 272ba1d0ad1ffcdeb19eea416ecedba220802bb6 |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Eliminate virtual methods that are sparc specific
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4419 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| c56406c236478f718a2257c2b660561ebc855f16 |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
* Privatize the TargetName
* Move optSizeForSubWordData to TargetData
* Remove unused fields
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4417 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
argetMachine.h
|
| 6334205cb5c626d2b35e42dd4c710b857bf0a126 |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Allow TargetMachine to refuse static code gen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4415 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| a74db854a3dc9b6fe8e0d5837e35e47d744b7d8f |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Rename Sparc.h to TargetMachineImpls.h. Add hook for X86 target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4412 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachineImpls.h
|
| 5c1b5244b956a28667bc2a9e7a84fa39697ba715 |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Add hook for JIT compiler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4411 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 5f9a61a598228ac8698188d46a70695a528fc2d6 |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Move to TargetMachineImpls.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4405 91177308-0d34-0410-b5e6-96231b3b80d8
parc.h
|
| c1f49e4b358e1822ea00dbe74e6d659acb971f35 |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Merge to MachineInstrInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4402 91177308-0d34-0410-b5e6-96231b3b80d8
InstructionInfo.h
|
| f1757c414cbf7d1b7a11cc8287fd26c2ce13fb41 |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Move TargetInstrDescriptors extern to the one .cpp file that refers to it:
MachineInstr.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4392 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 4683f9bfb4dc2f5557e8a7a229912e7f2ed366ca |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Rename opCodeString to Name, add new getName() method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4388 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| e30eeaaf72b461aebf3dfcdd7c119eea76458561 |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstrInfo::getDescriptor to MachineInstrInfo::get
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4387 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| d020801aeaacbee4dc139bb08f81e44bc53b872e |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
MachineInstrInfo doesn't need a TargetMachine member
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4371 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| de0e87bb83a575d414bcdabfab8839669df181c5 |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Minor cleanups, remove noncopyable so dot doesn't cluster unrelated stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4365 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| 2cc214c06cbb94f95928636981c9805d6300cff1 |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Strip a bunch of #includes from the file, move some virtual functions to
.cpp file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4364 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 534124d0e35165b7cb38d5fffb5ea2ac4638252b |
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Inline some code from the cpp file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4363 91177308-0d34-0410-b5e6-96231b3b80d8
argetCacheInfo.h
|
| 9a8e4121aa4121100fb562134c098aeb38f70b37 |
28-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Remove all traces of the "Opcode Mask" field in the MachineInstr class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4359 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| c7e65fb7d850d010a141420d7b1d8ddad484d3b3 |
28-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
* s/unsigned int/unsigned
* Make MachineInstrDescriptor only keep a const char * instead of a string
for the opcode name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4335 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| c188b733babbcdb0ff51613d0bb133e0496963b6 |
28-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Make scheduling class variables be 'unsigned' instead of 'int'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4334 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
argetSchedInfo.h
|
| 67e4132caa08f15973d7e64e7dc04fe81994011e |
28-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Remvoe a bunch of unneeded forward decls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4326 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 4a63b72df95b5c0d4af064cef19377f811ba6060 |
28-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Don't #include <Support/*>, #include "Support/*"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4325 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
argetSchedInfo.h
|
| ebb1af16bea8f163cbb74c55ae41885c396f72cb |
28-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
* Doxygenify comments
* Move addPassesToEmitAssembly back to Sparc.cpp because it really is
sparc specific
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4306 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| fce1143bcfa73f61845002fa50473d1a01384202 |
28-Oct-2002 |
Misha Brukman <brukman+llvm@gmail.com> |
Changed `MachineCodeForMethod' to `MachineFunction'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4301 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetFrameInfo.h
argetInstrInfo.h
|
| 3d7771a387d9476cfb25451ab95b72ce7b3e2532 |
26-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Initial checkin of target support for X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4287 91177308-0d34-0410-b5e6-96231b3b80d8
InstructionInfo.h
RegisterInfo.h
|
| 502374a58fcd1c28065170a8c4a210be002ff190 |
25-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
* Remove unneccesary #includes
* Fix typeo in the (unused) MachineInstrInfo::isArith method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4275 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 85131c8277891c91f24fd6411449298ce4b1b648 |
15-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
- Add an endianness field to the TargetData datastructure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4174 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 5aefcad35bc81e3de4031b1f779c9a9520790cd7 |
13-Oct-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Use vectors instead of hash_maps for issueGaps and conflictLists.
These hash lookups were a major sink of time because they happen so often!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4136 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| 9d0168d2d54008729632f676475ce710448cf8a8 |
29-Sep-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Minor change to interface for Create{Zero,Sign}ExtensionsInstructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3979 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 106604ea6dff253fb00c762264186201b7ccfef4 |
28-Sep-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Simplified code that handles call args and rets, so it no longer
needs the RegClass list to be passed in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3964 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 2da7afb963dd9760e6feb9ab87ebca963d2b964e |
26-Sep-2002 |
Chris Lattner <sabre@nondot.org> |
Convert TargetData to be an ImmutablePass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3928 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 2d237858523b56ea5ea0f6efdbd40d7e7c52e771 |
24-Sep-2002 |
Chris Lattner <sabre@nondot.org> |
There are no implicit gep forms of load and store anymore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3901 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| d55697cf136150b697b9bbddce9088e87a1be963 |
20-Sep-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Added class MachineOptInfo as interface to target-specific
routines supporting machine code optimization.
Also added method MachineInstrInfo::getNOPOpCode().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3845 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
argetMachine.h
|
| 2542d9a18304d60576158e635f6123f60bbd80ba |
20-Sep-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Interface to target-specific routines that support machine code optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3844 91177308-0d34-0410-b5e6-96231b3b80d8
argetOptInfo.h
|
| 214bf5417562777a16a687cb095fa59d0be65285 |
16-Sep-2002 |
Chris Lattner <sabre@nondot.org> |
Fix compile problem on linux. Noone should ever #include <inttypes.h>
directly. Instead, include Support/DataTypes.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3766 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| aa500f3f4307cf24f4775fa2c28870ff0a45bcaf |
16-Sep-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Add method adjustAlignment so that stack slot alignments can be computed
in a target-dependent manner (because of the dang OFFSET in Sparc v9).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3745 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 4900116ab0c17252bdca2e66b87d8b6da1839b54 |
16-Sep-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Add methods to query about the representation of LLVM quantities (e.g.,
constants). Useful for target-dependent LLVM transformations like
Preselection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3743 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| ebc7511e8688f2ec23915570377dd4aaf167560e |
16-Sep-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
*** empty log message ***
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3741 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 68f716190baa08675793adba428605797eb658a4 |
05-Sep-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Add new function MachineInstrInfo::CreateZeroExtensionInstructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3582 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 6ef33693213356eb1afe04046b7af343616fafa7 |
12-Aug-2002 |
Chris Lattner <sabre@nondot.org> |
Return const char * const instead of std::string from get register name method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3294 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 035dfbe7f2d109008d2d62d9f2a67efb477a7ab6 |
09-Aug-2002 |
Chris Lattner <sabre@nondot.org> |
* Removed extraneous #includes
* Fixed file headers to be consistent with the rest of LLVM
* Other minor fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3278 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 39d69009d015a5177303c9d8865143531e099314 |
25-Jul-2002 |
Chris Lattner <sabre@nondot.org> |
*** empty log message ***
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3067 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| cb6289a73d8caaad87da1b26f03b9b63b7b712cc |
24-Jul-2002 |
Chris Lattner <sabre@nondot.org> |
*** empty log message ***
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3058 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| 09ff1126dab045d68be7d9e8ae7ad0601002a718 |
24-Jul-2002 |
Chris Lattner <sabre@nondot.org> |
*** empty log message ***
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3056 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
argetSchedInfo.h
|
| 24787fa2ed43dc58813b14ac18fbc402a7315062 |
11-Jul-2002 |
Anand Shukla <ashukla@cs.uiuc.edu> |
added std:: to vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2874 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 9d22cd45359f0d200e374d75f7a8935235da2ef6 |
10-Jul-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Put caller-saving code *before* argument copying code!
(This file has a minor change required for this fix.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2854 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| bba2485c709adecd65526fbcfea77f2344d29d69 |
10-Jul-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Minor change in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2853 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 5023bd4a64e6a6926c5a158bbe9957136e554f10 |
09-Jul-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
cpMem<->Reg functions now support CC registers (int and FP) correctly.
A scratch register has to be provided when needed to do the copy.
Also, cpMem<->Reg functions now return a vector of machine instructions.
Added several get{Class,Type} functions.
Suggest/Color methods may modify the MachineInstr (and always did),
so don't make that argument const!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2824 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 4a9f9337511441af0624e754ad9b2b1262ee584d |
25-Jun-2002 |
Anand Shukla <ashukla@cs.uiuc.edu> |
changes to make it compatible with 64bit gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2786 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 85c5465e072b3bbebb1f5e112fb2db46f7fba148 |
23-May-2002 |
Chris Lattner <sabre@nondot.org> |
Convert RegClass::IsColorUsedArr from a dynamically allocated array to
a vector. This makes asserting on array bounds easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2731 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 14e3c4448677595697f300a7de4b185f1398b4bb |
19-May-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Added parameter IntRegSize for standard general-purpose register size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2652 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| c864fde15c68fe56d2af48ddeaddfd4e13006f4a |
19-May-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
New function CreateSignExtensionInstructions.
Methods now take MachineCodeForInstruction& as an argument and record
temporary values in it directly, instead of return the temps.
Really simplifies callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2651 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| febfae46a7137d7b4f89a518ea09f94665c247e3 |
19-May-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Many functions that returned a single MachineInstr now take a
vector of MachineInstr* to return multiple ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2650 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| f66723fc4b8bfebc17c8efa0753701d1c2840d5c |
19-May-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Add integer register size field.
Make all sizes and offsets uint64_t instead of uint.
Fixed GetIndexedOffset to handle mixed array and struct indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2641 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| b6dcbfc6d1d18e9b3a5dcd0df5f00f7ac3d0100f |
28-Apr-2002 |
Chris Lattner <sabre@nondot.org> |
Use forward decl instead of #include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2380 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| a8ac3fca6f31ece5f9675434f1ddace6cd912c09 |
25-Apr-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Added functions to compute the offset of a given incoming or outgoing
argument. These are no longer allocated as they are discovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2320 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| dbc3b00df5bee8d082b9a74e2d21aac4f9671b1d |
09-Apr-2002 |
Chris Lattner <sabre@nondot.org> |
Free memory when done with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2198 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| d0bac697929bc75aea432316fd8c588f67751869 |
31-Mar-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Add method getCallInstIndirectAddrVal() to add call interference
for this value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2072 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| e7506a366e8bd56c97d10beb68e4db953aebaeca |
23-Mar-2002 |
Chris Lattner <sabre@nondot.org> |
Rename Method to Function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1957 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
argetRegInfo.h
|
| 851597c3b34a03b700f48d284fb9b186ccf9ef91 |
18-Mar-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Added machine-independent value for INVALID_MACHINE_OPCODE.
Just cosmetic changes otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1898 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 80347ecb148534169086c719c8228e4e03bdce96 |
18-Mar-2002 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Add function getRegClassIDOfType.
getRegClassIDOfValue is now just a wrapper around this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1897 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| bc53c04789ba11e241ef9793fc3cae5b2902725b |
04-Feb-2002 |
Chris Lattner <sabre@nondot.org> |
* Minor cleanups
* Reduce number of #includes
* Delete blank lines at end of files
* Remove blatently misleading qualifiers (how do you have an inlined pure virtual function?)
* Remove unnecesary & ignored qualifiers (const int argument vs int argument)
* Remove LARGE chunks of "inline" code out to .cpp file
* s/unsigned int/unsigned/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1673 91177308-0d34-0410-b5e6-96231b3b80d8
argetCacheInfo.h
argetRegInfo.h
argetSchedInfo.h
|
| ccca2ed8543d2ec08782eb2237242d59b7b8f7b3 |
04-Feb-2002 |
Chris Lattner <sabre@nondot.org> |
Revamp compilation to be pass based instead of being monolithic so that
backend's can customize compilation as much as they want
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1661 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 88e2fbc4bbe63ca5f208a4e9c7f47ff6711923e8 |
03-Feb-2002 |
Chris Lattner <sabre@nondot.org> |
Add methods to TargetMachine to:
* Output assembly code a method at a time instead of building it all up then emitting it as a whole module
* Release memory contained in various annotations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1641 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 871b1939b52553a6bb1d51d326b0b1356de03353 |
03-Feb-2002 |
Chris Lattner <sabre@nondot.org> |
* Trim #includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1640 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| f3aaadf48277acddc3f6fdc4cc8d18b13d313595 |
03-Feb-2002 |
Chris Lattner <sabre@nondot.org> |
Remove #include
move typedefs here
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1639 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 9aab9ec321e2774bb4daab6355d89ab1aef0556a |
03-Feb-2002 |
Chris Lattner <sabre@nondot.org> |
Remove extranous #include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1638 91177308-0d34-0410-b5e6-96231b3b80d8
argetCacheInfo.h
|
| 7012bcd61b249c87f027d97747f51a1c86cc96d0 |
21-Jan-2002 |
Chris Lattner <sabre@nondot.org> |
Fix for problem that caused both HUGE and INVALID latencies to be negative
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1513 91177308-0d34-0410-b5e6-96231b3b80d8
argetSchedInfo.h
|
| 697954c15da58bd8b186dbafdedd8b06db770201 |
20-Jan-2002 |
Chris Lattner <sabre@nondot.org> |
Changes to build successfully with GCC 3.02
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1503 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetCacheInfo.h
argetData.h
argetInstrInfo.h
argetMachine.h
argetRegInfo.h
argetSchedInfo.h
|
| 6011e2eeadcf84bbfd14365f412c7df049a522b0 |
07-Jan-2002 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
Added more comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1495 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| c1a29f10a6f0bc3d219db9594ed8d3ec20efd8a4 |
07-Jan-2002 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
MachineRegInfo: Added a method to get the size of a register pushed on to stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1492 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
argetRegInfo.h
|
| dd08e32deb39311824248be56be3bf3fbe64f39d |
15-Dec-2001 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
getIndexedOffset() shd take vector of Values, not of Constants!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1484 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| e9bb2df410f7a22decad9a883f7139d5857c1520 |
03-Dec-2001 |
Chris Lattner <sabre@nondot.org> |
Rename ConstPoolVal -> Constant
Rename ConstPool* -> Constant*
Rename ConstPoolVals.h -> ConstantVals.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1407 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetData.h
argetInstrInfo.h
|
| cee8f9ae67104576b2028125b56e9ba4856a1d66 |
27-Nov-2001 |
Chris Lattner <sabre@nondot.org> |
Create a new #include "Support/..." directory structure to move things
from "llvm/Support/..." that are not llvm dependant.
Move files and fix #includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1400 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
argetMachine.h
argetRegInfo.h
|
| 360e17eaf1a2abda82b02235dc57d26d8f83c937 |
27-Nov-2001 |
Chris Lattner <sabre@nondot.org> |
Move DataTypes.h from llvm/Support to just Support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1399 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetCacheInfo.h
argetInstrInfo.h
|
| 4c5fe2d3ed4043c34f3305c081297ba4ca26ddc2 |
14-Nov-2001 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Add function returning which operand holds immediate constant
for a given opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1307 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| b9f550ddfbaf963a0aced2df8cd40c71021fd3e5 |
14-Nov-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
added isPseudoInstr()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1302 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 8486cdd3f9850eb08fceea05deb6a0315e962574 |
12-Nov-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
Changed for adding Phi Elimination code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1266 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 984adc25c981155040f3a7e3801d2292e18880b1 |
10-Nov-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
Made isPhi const
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1251 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 40abd3fab81a8e81ebde3d54825b1d71b2db50ac |
09-Nov-2001 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Cache parameters for target machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1222 91177308-0d34-0410-b5e6-96231b3b80d8
argetCacheInfo.h
|
| 4938d4528f80dd015c58dec9d6d72bc27bf26bbd |
09-Nov-2001 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Added class MachineCacheInfo.
Also added function to convert float to int by copying via memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1221 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
argetMachine.h
|
| 9b19894da9d9bdd101ba90c51c9fd99d91a04314 |
08-Nov-2001 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Add handle to object MachineFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1202 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 1c84e2a7d35e5e4094db958a8f982420a4b1243b |
08-Nov-2001 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Include handle to TargetMachine in each Machine...Info class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1201 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
argetSchedInfo.h
|
| 44508e333cc1d36e699aa330d84312d1c8fc655a |
08-Nov-2001 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Add method CreateCodeToCopyIntToFloat.
Include handle to TargetMachine in each Machine...Info object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1200 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| 7cffcaaa48656fa6f90b041cc5f056304addef32 |
08-Nov-2001 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Machine-independent interface to target's stack frame layout parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1190 91177308-0d34-0410-b5e6-96231b3b80d8
argetFrameInfo.h
|
| 0d3ea0268f44f8fd4ddf7a15f3624b384b0691db |
03-Nov-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
Moved InsertCallerSaveInstr to the SparcRegInfo.cpp and made machine independent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1107 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
argetRegInfo.h
|
| 78d63ee3136b74c7ee3eae1e7362d3b642fabf0c |
28-Oct-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
Moved callerSaving code to machine specific classes since we have to handle
%ccr reg differently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@991 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| b3b6f5338c246ad1b209047cf9422fbf08fb1ddc |
21-Oct-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
Added support for both call/jmpl instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@930 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 5684c4e2b41f1d6ddf70b116a84f438040f66297 |
18-Oct-2001 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Added virtual function to generate an instruction sequence to
load a constant into a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@862 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetInstrInfo.h
|
| c4d4b76efbe57025525edf75d6b91cec363d2fc4 |
16-Oct-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
Added support for caller saving
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@847 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| f125525e3b020b15c541a17d21f78d23756149dd |
15-Oct-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
--changed Sugesting colors for method calls/return values etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@829 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| ec0a95f4e4d35df64518a7bdf4d394cf35b83914 |
15-Oct-2001 |
Chris Lattner <sabre@nondot.org> |
Be const correct
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@826 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 2f004fdf185320b80748a23fd28ce1625494f793 |
13-Oct-2001 |
Chris Lattner <sabre@nondot.org> |
Fix filename in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@751 91177308-0d34-0410-b5e6-96231b3b80d8
argetData.h
|
| 06faeee041dc2f24f2fd657ecc1bb5647d64fd40 |
01-Oct-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
added suggesting color suppor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@672 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| 8a28124a5fb7153460909c079e2413f439253e80 |
19-Sep-2001 |
Chris Lattner <sabre@nondot.org> |
Add emitAssembly Method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@639 91177308-0d34-0410-b5e6-96231b3b80d8
argetMachine.h
|
| 80acc6cf43af185f406cbe29b3ba902a3528717f |
19-Sep-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
*** empty log message ***
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@634 91177308-0d34-0410-b5e6-96231b3b80d8
argetRegInfo.h
|
| e6cbbfeeadd0266f06da3a04e16c14258325a806 |
18-Sep-2001 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Renamed files to match the primary classes they provide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@620 91177308-0d34-0410-b5e6-96231b3b80d8
ata.h
nstInfo.h
achine.h
egInfo.h
chedInfo.h
|
| a578a6d054e8219c730840700d8d5fd29f15a962 |
18-Sep-2001 |
Vikram S. Adve <vadve@cs.uiuc.edu> |
Make class TargetMachine the common interface to all target-dependent
information, including instr, sched, and reg information.
Rename files to match the primary classes they provide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@602 91177308-0d34-0410-b5e6-96231b3b80d8
achineInstrInfo.h
argetData.h
argetInstrInfo.h
argetMachine.h
argetRegInfo.h
argetSchedInfo.h
|
| c5258a421024bcaa93d5f7bab872df97f60ee4a5 |
15-Sep-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
added reg alloc support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@588 91177308-0d34-0410-b5e6-96231b3b80d8
achine.h
|
| 94d86e9677c863a10741b888177085fe2d48d50c |
14-Sep-2001 |
Ruchira Sasanka <sasanka@students.uiuc.edu> |
*** empty log message ***
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@579 91177308-0d34-0410-b5e6-96231b3b80d8
egInfo.h
|
| 46cbff625eb9593cf9ddac415c39311a54aa27fa |
14-Sep-2001 |
Chris Lattner <sabre@nondot.org> |
Chris seems fond of #include <vector>. Fix these. Also convert use list in
Value to a vector instead of a list.
Move SchedGraph.h & SchedPriorities.h into lib/CodeGen/InstrScheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@572 91177308-0d34-0410-b5e6-96231b3b80d8
ata.h
egInfo.h
|
| 7c94f9dc96358bb010127160d05149373a058924 |
14-Sep-2001 |
Chris Lattner <sabre@nondot.org> |
Minor reformatting, & protection fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@570 91177308-0d34-0410-b5e6-96231b3b80d8
nstInfo.h
achine.h
|
| 5f3c2e566f946db6c95234e7c1de73bef8f8afe0 |
14-Sep-2001 |
Chris Lattner <sabre@nondot.org> |
Split Register specific stuff out from TargetMachine.h to RegInfo.h
Get rid of unneccesary #includes from TargetMachine.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@568 91177308-0d34-0410-b5e6-96231b3b80d8
nstInfo.h
achine.h
egInfo.h
chedInfo.h
|
| e5bc8b06533ba0f50403158a63f99a0c83da0493 |
14-Sep-2001 |
Chris Lattner <sabre@nondot.org> |
Split Target/Machine.h into three files:
* Machine.h
* InstInfo.h
* SchedInfo.h
TODO: Split out reg info stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@567 91177308-0d34-0410-b5e6-96231b3b80d8
nstInfo.h
achine.h
chedInfo.h
|
| b26bcc5087029ffe8037ed9036ff74430c6054cf |
14-Sep-2001 |
Chris Lattner <sabre@nondot.org> |
Make a new llvm/Target #include directory.
Move files from lib/CodeGen/TargetMachine to lib/Target
Move TargetData.h and TargetMachine.h to Target/{Data.h|Machine.h}
Prepare to split TargetMachine.h into several smaller files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@566 91177308-0d34-0410-b5e6-96231b3b80d8
ata.h
achine.h
parc.h
argetMachineImpls.h
|