| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
smParser/PPCAsmParser.cpp
CTargetDesc/PPCMCCodeEmitter.cpp
CTargetDesc/PPCMCExpr.cpp
CTargetDesc/PPCMCExpr.h
PC.td
PCAsmPrinter.cpp
PCFastISel.cpp
PCFrameLowering.cpp
PCFrameLowering.h
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrFormats.td
PCInstrInfo.cpp
PCInstrInfo.h
PCInstrInfo.td
PCJITInfo.cpp
PCJITInfo.h
PCRegisterInfo.cpp
PCSelectionDAGInfo.cpp
PCSelectionDAGInfo.h
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
smParser/LLVMBuild.txt
smParser/PPCAsmParser.cpp
isassembler/LLVMBuild.txt
isassembler/PPCDisassembler.cpp
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCMCAsmInfo.cpp
CTargetDesc/PPCMCAsmInfo.h
CTargetDesc/PPCMCCodeEmitter.cpp
CTargetDesc/PPCMCExpr.cpp
CTargetDesc/PPCMCExpr.h
CTargetDesc/PPCMCTargetDesc.cpp
CTargetDesc/PPCMachObjectWriter.cpp
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCTRLoops.cpp
PCCodeEmitter.cpp
PCFastISel.cpp
PCFrameLowering.cpp
PCFrameLowering.h
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
PCInstrInfo.cpp
PCInstrInfo.h
PCInstrInfo.td
PCInstrVSX.td
PCJITInfo.cpp
PCJITInfo.h
PCMCInstLower.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
PCRegisterInfo.td
PCSelectionDAGInfo.cpp
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
PCTargetMachine.h
PCTargetTransformInfo.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
smParser/CMakeLists.txt
smParser/PPCAsmParser.cpp
MakeLists.txt
isassembler/CMakeLists.txt
isassembler/LLVMBuild.txt
isassembler/Makefile
isassembler/PPCDisassembler.cpp
nstPrinter/CMakeLists.txt
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
LVMBuild.txt
CTargetDesc/CMakeLists.txt
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCMCAsmInfo.cpp
CTargetDesc/PPCMCAsmInfo.h
CTargetDesc/PPCMCCodeEmitter.cpp
CTargetDesc/PPCMCExpr.cpp
CTargetDesc/PPCMCExpr.h
CTargetDesc/PPCMCTargetDesc.cpp
CTargetDesc/PPCMCTargetDesc.h
CTargetDesc/PPCPredicates.cpp
CTargetDesc/PPCPredicates.h
akefile
PC.h
PC.td
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCTRLoops.cpp
PCCallingConv.td
PCCodeEmitter.cpp
PCFastISel.cpp
PCFrameLowering.cpp
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrFormats.td
PCInstrInfo.cpp
PCInstrInfo.h
PCInstrInfo.td
PCInstrVSX.td
PCJITInfo.cpp
PCMCInstLower.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
PCRegisterInfo.td
PCSchedule.td
PCSchedule440.td
PCScheduleA2.td
PCScheduleE500mc.td
PCScheduleE5500.td
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
PCScheduleP7.td
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
PCTargetObjectFile.cpp
PCTargetObjectFile.h
PCTargetStreamer.h
PCTargetTransformInfo.cpp
argetInfo/CMakeLists.txt
argetInfo/LLVMBuild.txt
|
| 593c23caad07bd8b4d042db897b7d9fed7b4f213 |
12-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r-197100:
------------------------------------------------------------------------
r197100 | hfinkel | 2013-12-11 16:23:29 -0800 (Wed, 11 Dec 2013) | 1 line
Remove unused multiclass from PPCInstrInfo.td
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197131 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 02d8bf1f24c25a0db1f43789958c28975903ccb7 |
12-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r197100:
------------------------------------------------------------------------
r197100 | hfinkel | 2013-12-11 16:23:29 -0800 (Wed, 11 Dec 2013) | 1 line
Remove unused multiclass from PPCInstrInfo.td
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197130 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| b29de8ba0044548f0259b5eca180e07bdba992bc |
12-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r197089:
------------------------------------------------------------------------
r197089 | hfinkel | 2013-12-11 15:12:25 -0800 (Wed, 11 Dec 2013) | 6 lines
Fix the PPC subsumes-predicate check
For one predicate to subsume another, they must both check the same condition
register. Failure to check this prerequisite was causing miscompiles.
Fixes PR18003.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197126 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| ade90c9f1d01f3401a5db183a33b5a6380476a35 |
21-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195272:
------------------------------------------------------------------------
r195272 | hfinkel | 2013-11-20 12:54:55 -0800 (Wed, 20 Nov 2013) | 4 lines
PPC popcnt[dw] do not have record forms
The instruction definitions incorrectly specified that popcntd and popcntw have
record forms; they do not. This mistake was causing invalid code generation.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195320 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 354362524a72b3fa43a6c09380b7ae3b2380cbba |
19-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
PCInstrInfo.cpp
PCInstrInfo.h
PCTargetStreamer.h
|
| b21ab43cfc3fa0dacf5c95f04e58b6d804b59a16 |
18-Nov-2013 |
Alexey Samsonov <samsonov@google.com> |
Revert r194865 and r194874.
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
PCInstrInfo.cpp
PCInstrInfo.h
PCTargetStreamer.h
|
| 5a364c5561ec04e33a6f5d52c14f1bac6f247ea0 |
15-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
PCInstrInfo.cpp
PCInstrInfo.h
PCTargetStreamer.h
|
| cc7052343e5e955d4e2f48885c06360f9003390a |
15-Nov-2013 |
Bob Wilson <bob.wilson@apple.com> |
Avoid illegal integer promotion in fastisel
Stop folding constant adds into GEP when the type size doesn't match.
Otherwise, the adds' operands are effectively being promoted, changing the
conditions of an overflow. Results are different when:
sext(a) + sext(b) != sext(a + b)
Problem originally found on x86-64, but also fixed issues with ARM and PPC,
which used similar code.
<rdar://problem/15292280>
Patch by Duncan Exon Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194840 91177308-0d34-0410-b5e6-96231b3b80d8
PCFastISel.cpp
|
| f14beced2b3120f5f65d29e4553e478f3012345e |
11-Nov-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC option for full register names in asm
On non-Darwin PPC systems, we currently strip off the register name prefix
prior to instruction printing. So instead of something like this:
mr r3, r4
we print this:
mr 3, 4
The first form is the default on Darwin, and is understood by binutils, but not
yet understood by our integrated assembler. Once our integrated-as understands
full register names as well, this temporary option will be replaced by tying
this functionality to the verbose-asm option. The numeric-only form is
compatible with legacy assemblers and tools, and is also gcc's default on most
PPC systems. On the other hand, it is harder to read, and there are some
analysis tools that expect full register names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194384 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
|
| 565ebfff158d8afc4e09612f7e3cd14d05939cf9 |
31-Oct-2013 |
Rui Ueyama <ruiu@google.com> |
Use StringRef::startswith_lower. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193796 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
|
| ffc7dca885151ed42642c2d6733e8db75d276621 |
29-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a helper getSymbol to AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193627 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCMCInstLower.cpp
|
| 985ce242a74adf6519609782acbdce2d5464fc22 |
16-Oct-2013 |
Eric Christopher <echristo@gmail.com> |
Add support for the VSX target attribute. No functional change
as we don't actually use it to emit any code yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192837 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCSubtarget.h
|
| 06957f43f6051901590b318c10b1a0a5c7f898d4 |
16-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCAsmInfoELF class and factor some code into it.
We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192760 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
CTargetDesc/PPCMCAsmInfo.h
|
| 320296a4cfe414ce59f406b8a5ce15272f563103 |
08-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCTargetStreamer interface.
This patch fixes an old FIXME by creating a MCTargetStreamer interface
and moving the target specific functions for ARM, Mips and PPC to it.
The ARM streamer is still declared in a common place because it is
used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are
completely hidden in the corresponding Target directories.
I will send an email to llvmdev with instructions on how to use this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
PCAsmPrinter.cpp
PCTargetStreamer.h
|
| ef8c4ca252f1289ca8d0a1e6cfd96ca17fe3c5a8 |
07-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove getEHExceptionRegister and getEHHandlerRegister.
They haven't been used for a long time. Patch by MathOnNapkins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192099 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| daf6b948b98b886f5f0fba130e91e01c9ca7c2f2 |
26-Sep-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Fix PR17354: Generate nop after local calls for PIC code.
When generating code for shared libraries, even local calls may be
intercepted, so we need a nop after the call for the linker to fix up the
TOC. Test case adapted from the one provided in PR17354.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191440 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 9637da60835a60f8ccd8289d04c60b2dcd4b9b5a |
26-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
PPC: Allow partial fills in writeNopData()
When asked to pad an irregular number of bytes, we should fill with
zeros. This is consistent with the behavior specified in the AIX
Assembler Language Reference as well as other LLVM and binutils
assemblers.
N.B. There is a small deviation from binutils' PPC assembler:
when handling pads which are greater than 4 bytes but not mod 4,
binutils will not emit any NOP sequences at all and only use zeros.
This may or may not be a bug but there is no excellent rationale as to
why that behavior is important to emulate. If that behavior is needed,
we can change writeNopData() to behave in the same way.
This fixes PR17352.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191426 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| dd5cebdd74aaaefcf50eb1ea44bee8b02ab65a2e |
26-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
PPC: Do not introduce ISD nodes for fctid and fctiw
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191421 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 11c2b15c0a8282cfdc1c74968ebaba92f1fdae34 |
26-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
PPC: Add support for fctid and fctiw
Encodings were checked against the Power ISA documents and double
checked against binutils.
This fixes PR17350.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191419 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 3f22cc1df64a6dd6a3ecc5e7e261f15af083f806 |
25-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
MC: Add support for treating $ as a reference to the PC
The binutils assembler supports a mode called DOLLAR_DOT which treats
the dollar sign token as a reference to the current program counter if
the dollar sign doesn't precede a constant or identifier.
This commit adds a new MCAsmInfo flag stating whether or not a given
target supports this interpretation of the dollar sign token; by
default, this flag is not enabled.
Further, enable this flag for PPC. The system assembler for AIX and
binutils both support using the dollar sign in this manner.
This fixes PR17353.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191368 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
|
| 8ba3f9c9008223136207295b48b53c8aefffa178 |
25-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
MC: Remove vestigial PCSymbol field from AsmInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191362 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
|
| 3e84ad28d4d3ceee25771b1e30315c20b7608c39 |
22-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
ISelDAG: spot chain cycles involving MachineNodes
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.
Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.
This should fix PR15840.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 50019d8f7e1af96b85098ba501acbb9845682e4a |
22-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Correct the pre-increment load latencies in the PPC A2 itinerary
Pre-increment loads are microcoded on the A2, and the address increment occurs
only after the load completes. As a result, the latency of the GPR address
update is an additional 2 cycles on top of the load latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191156 91177308-0d34-0410-b5e6-96231b3b80d8
PCScheduleA2.td
|
| 3789209b79ba8097cc489630c005898365134f65 |
17-Sep-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Add a FIXME.
Documenting a design choice to generate only medium model sequences for TLS
addresses at this time. Small and large code models could be supported if
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190883 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 5bd1dfa2b5deab10a1a7a5a4ba117c28d878595d |
17-Sep-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Fix problems with large code model (PR17169).
Large code model on PPC64 requires creating and referencing TOC entries when
using the addis/ld form of addressing. This was not being done in all cases.
The changes in this patch to PPCAsmPrinter::EmitInstruction() fix this. Two
test cases are also modified to reflect this requirement.
Fast-isel was not creating correct code for loading floating-point constants
using large code model. This also requires the addis/ld form of addressing.
Previously we were using the addis/lfd shortcut which is only applicable to
medium code model. One test case is modified to reflect this requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190882 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCFastISel.cpp
|
| 5c616f91a5136295bf83850bc3610bd28756e58e |
16-Sep-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Fix PR17155 - Ignore COPY_TO_REGCLASS during emit.
Fast-isel generates a COPY_TO_REGCLASS for widening f32 to f64, which
is a nop on PPC64. This is needed to keep the register class system
happy, but on the fast-isel path it is not removed before emit as it
is for DAG select. Ignore this op when emitting instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190795 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCCodeEmitter.cpp
|
| fabfb5d5880354983c89c6f475312dd359e5bb03 |
16-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Don't restrict lvsl generation to after type legalization
This is a re-commit of r190764, with an extra check to make sure that we're not
performing the transformation on illegal types (a small test case has been
added for this as well).
Original commit message:
The PPC backend uses a target-specific DAG combine to turn unaligned Altivec
loads into a permutation-based sequence when possible. Unfortunately, the
target-specific DAG combine is not always called on all loads of interest
(sometimes the routines in DAGCombine call CombineTo such that the new node and
users are not added to the worklist); allowing the combine to trigger early
(before type legalization) mitigates this problem. Because the autovectorizers
only create legal vector types, I don't expect a lot of cases where this
optimization is enabled by type legalization in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190771 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 19b59e66afa8d19c35444e0a739b467d368725d3 |
15-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Revert r190764: PPC: Don't restrict lvsl generation to after type legalization
This is causing test-suite failures.
Original commit message:
The PPC backend uses a target-specific DAG combine to turn unaligned Altivec
loads into a permutation-based sequence when possible. Unfortunately, the
target-specific DAG combine is not always called on all loads of interest
(sometimes the routines in DAGCombine call CombineTo such that the new node and
users are not added to the worklist); allowing the combine to trigger early
(before type legalization) mitigates this problem. Because the autovectorizers
only create legal vector types, I don't expect a lot of cases where this
optimization is enabled by type legalization in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190765 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 55532adc687a87574fd79822c876b10db95cd9ee |
15-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Don't restrict lvsl generation to after type legalization
The PPC backend uses a target-specific DAG combine to turn unaligned Altivec
loads into a permutation-based sequence when possible. Unfortunately, the
target-specific DAG combine is not always called on all loads of interest
(sometimes the routines in DAGCombine call CombineTo such that the new node and
users are not added to the worklist); allowing the combine to trigger early
(before type legalization) mitigates this problem. Because the autovectorizers
only create legal vector types, I don't expect a lot of cases where this
optimization is enabled by type legalization in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190764 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 98bae99266d8e527e7399c717a79c6dc9a073331 |
13-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add missing break statement in PPCISelLowering
As it turns out, not a problem in practice, but it should be there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190720 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a2c982129ed93f4bcb9738e0749a0b08e51a8b83 |
13-Sep-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Remove an unused variable, fixing -Werror build with latest Clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190640 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6671cd4db079eb993f9bd340e0c33d61f0f27d81 |
13-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix PPC ABI for ByVal structs with vector members
When a structure is passed by value, and that structure contains a vector
member, according to the PPC ABI, the structure will receive enhanced alignment
(so that the vector within the structure will always be aligned).
This should resolve PR16641.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190636 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 4a1535c0383254741bcddd3500081782aad11864 |
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Make the PPC fast-math sqrt expansion safe at 0
In fast-math mode sqrt(x) is calculated using the fast expansion of the
reciprocal of the reciprocal sqrt expansion. The reciprocal and reciprocal
sqrt expansions use the associated estimate instructions along with some Newton
iterations. Unfortunately, as a result, sqrt(0) was being calculated as NaN,
which is not correct. Now we explicitly return a result of zero if the input is
zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190624 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ba7183bc5284a0e4254ad12b78e2ea61e291dd88 |
12-Sep-2013 |
Roman Divacky <rdivacky@freebsd.org> |
Implement asm support for a few PowerPC bookIII that are needed for assembling
FreeBSD kernel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190618 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PCInstrFormats.td
PCInstrInfo.td
PCSchedule.td
|
| c0b12dfd0a83081c1ebbb55a89c7a2c1f98f1842 |
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Mark PPC MFTB and DST (and friends) as deprecated
Use the new instruction deprecation feature to mark mftb (now replaced with
mfspr) and dst (along with the other Altivec cache control instructions) as
deprecated when targeting cores supporting at least ISA v2.03.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190605 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PC.td
PCInstrAltivec.td
PCInstrInfo.td
PCSubtarget.cpp
PCSubtarget.h
|
| 715d98d657491b3fb8ea0e14643e9801b2f9628c |
12-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.
The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
ComplexDeprecationPredicate<"MCR">
would mean you would have to define the following function:
bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info)
Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.
The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
|
| 411dea0e7206ccc8018261831225d898d069ff1d |
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Enable aggressive anti-dependency breaking
Aggressive anti-dependency breaking is enabled by default for all PPC cores.
This provides a general speedup on the P7 and other platforms (among other
factors, the instruction group formation for the non-embedded PPC cores is done
during post-RA scheduling). In order to do this safely, the incompatibility
between uses of the MFOCRF instruction and anti-dependency breaking are
resolved by marking MFOCRF with hasExtraSrcRegAllocReq. As noted in the removed
FIXME, the problem was that MFOCRF's output is sensitive to the identify of the
source register, and always paired with a shift to undo this effect. Because
anti-dependency breaking is unaware of this hidden dependency of the shift
amount on the source register of the MFOCRF instruction, changing that register
must be inhibited.
Two test cases were adjusted: The SjLj test was made more insensitive to
register choices and scheduling; the saveCR test disabled anti-dependency
breaking because part of what it is testing is proper register reuse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190587 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
PCSubtarget.cpp
|
| d24ba9ff6e7ffc64c0597171b1980cc4e9556eb0 |
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Greatly simplify the PPC A2 scheduling itinerary
As Andy pointed out to me a long time ago, there are no structural hazards in
the later pipeline stages of the A2, and so modeling them is useless. Also,
modeling the top pre-dispatch stages is deceiving because, when multiple
hardware threads are active, those resources are shared among the threads. The
bypass definitions were mostly wrong, and so those have been removed. The
resulting itinerary is much simpler, and more accurate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190562 91177308-0d34-0410-b5e6-96231b3b80d8
PCScheduleA2.td
PCScheduleE500mc.td
PCScheduleE5500.td
|
| b7fbc5baad87eb5cc143193e66139824993883d3 |
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Enable MI scheduling (and CodeGen AA) by default for embedded PPC cores
For embedded PPC cores (especially the A2 core), using the MI scheduler with AA
is far superior to the other scheduling options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190558 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCSubtarget.cpp
PCSubtarget.h
|
| a5d756ca39c8566a0995a3f748812befe9021ef0 |
11-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement TTI getUnrollingPreferences for PowerPC
The PowerPC A2 core greatly benefits from aggressive concatenation unrolling;
use the new getUnrollingPreferences to enable this by default when targeting
the PPC A2 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190549 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetTransformInfo.cpp
|
| c3cee57f7d20f69a84fd88464ed8cf050e63c7ad |
09-Sep-2013 |
Bill Wendling <isanbard@gmail.com> |
Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.
Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.
<rdar://problem/13623355>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCMCTargetDesc.h
|
| 5510728d28bb1ee04abc32da3d21b7df12948053 |
01-Sep-2013 |
Charles Davis <cdavis5x@gmail.com> |
Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189728 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCMachObjectWriter.cpp
|
| cda04f9a0a7ef0755ca36db404239346c0edb24c |
31-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Fast-isel cleanup patch.
Here are a few miscellaneous things to tidy up the PPC64 fast-isel
implementation. I corrected a couple of commentary lapses, and added
documentation of future opportunities. I also implemented
TargetMaterializeAlloca, which I somehow forgot when I split up the
original huge patch.
Finally, I decided to delete SelectCmp. I hadn't previously hooked it
in to TargetSelectInstruction(), and when I did I realized it wasn't
serving any useful purpose. This is only useful for compares that
don't feed a branch in the same block, and to handle that we would
have to have logic to interpret i1 as a condition register. This
could probably be done, but would require Unseemly Hackery, and
honestly does not seem worth the hassle.
This ends the current patch series.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189715 91177308-0d34-0410-b5e6-96231b3b80d8
PCFastISel.cpp
|
| 9d2238cb0f6f67ed6883a0e9f98a835c523724da |
31-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Add integer truncation support to fast-isel.
This is the last substantive patch I'm planning for fast-isel in the
near future, adding fast selection of integer truncates. There are
certainly more things that can be improved (many of which are called
out in FIXMEs), but for now we are catching most of the important
cases.
I'll document some of the remaining work in a cleanup patch shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189706 91177308-0d34-0410-b5e6-96231b3b80d8
PCFastISel.cpp
|
| 9056dd45a4402cf6266b61f219aa56651633b2c1 |
31-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Correct partially defined variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189705 91177308-0d34-0410-b5e6-96231b3b80d8
PCFastISel.cpp
|
| 11addd2a2f584571ffcfd51711972b27aef0133f |
31-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Call support for fast-isel.
This patch adds fast-isel support for calls (but not intrinsic calls
or varargs calls). It also removes a badly-formed assert. There are
some new tests just for calls, and also for folding loads into
arguments on calls to avoid extra extends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189701 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCFastISel.cpp
PCISelLowering.cpp
|
| 9bc94276e796d644cb425a7c7d38cc44dbf4e9c1 |
30-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Add handling for conversions to fast-isel.
Yet another chunk of fast-isel code. This one handles various
conversions involving floating-point. (It also includes some
miscellaneous handling throughout the back end for LWA_32 and LWAX_32
that should have been part of the load-store patch.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189677 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
PCAsmPrinter.cpp
PCFastISel.cpp
PCRegisterInfo.cpp
|
| e206efd39bcc00600d816b67b041820b35d023fe |
30-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Handle selection of compare instructions in fast-isel.
Mostly trivial patch adding support for compares. The meat of the
work was added with the branch support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189639 91177308-0d34-0410-b5e6-96231b3b80d8
PCFastISel.cpp
|
| 40433e5df94f05ba93df7e96f7eb3f861915152a |
30-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Remove bogus debug statement. Sheesh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189638 91177308-0d34-0410-b5e6-96231b3b80d8
PCFastISel.cpp
|
| 7248968fa529726b44d41bd25403d50c74db4bc4 |
30-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Add loads, stores, and related things to fast-isel.
This is the next big chunk of fast-isel code. The primary purpose is
to implement selection of loads and stores, but there is a lot of
drag-along to support this. The common code to analyze addresses for
both loads and stores is substantial. It's also necessary to add the
materialization code for global values.
Related to load-store processing is the code to fold loads into
integer extends, since otherwise we generate lots of redundant
instructions. We also need to add some overrides to some FastEmit
routines to ensure we don't assign GPR 0 to a virtual register when
this would change the meaning of an instruction.
I added handling selection of a few binary arithmetic instructions, to
enable committing some test cases I wrote a while back.
Finally, ap couple of miscellaneous changes:
* I cleaned up some poor style from a previous patch in
PPCISelLowering.cpp, pointed out by David Blaikie.
* I enlarged the Addr.Offset field to avoid sign problems with 32-bit
offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189636 91177308-0d34-0410-b5e6-96231b3b80d8
PCFastISel.cpp
PCISelLowering.cpp
PCInstr64Bit.td
|
| ead2d5a4be3012699252e015ce774733590bf9b0 |
28-Aug-2013 |
Alexey Samsonov <samsonov@google.com> |
Fix use of uninitialized value added in r189400 (found by MemorySanitizer)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189456 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCExpr.cpp
|
| 66b7139b1be1ddce410d97499d5831231c6be267 |
27-Aug-2013 |
Joerg Sonnenberger <joerg@bec.de> |
Given target assembler parsers a chance to handle variant expressions
first. Use this to turn the PPC modifiers into PPC specific expressions,
allowing them to work on constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189400 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
CTargetDesc/PPCMCExpr.cpp
|
| f69a29b23a116a3520f185054290c445abf9aa62 |
27-Aug-2013 |
Charles Davis <cdavis5x@gmail.com> |
Revert "Fix the build broken by r189315." and "Move everything depending on Object/MachOFormat.h over to Support/MachO.h."
This reverts commits r189319 and r189315. r189315 broke some tests on what I
believe are big-endian platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189321 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCMachObjectWriter.cpp
|
| 9c3dd1b0d1e96ef408b68da3b06c6ebd6c943601 |
27-Aug-2013 |
Charles Davis <cdavis5x@gmail.com> |
Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189315 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCMachObjectWriter.cpp
|
| 7c42ede04579373a2d3e124b4417d89430d541f3 |
26-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Dummy code to silence warning from 4189266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189272 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 055d20742642a7392d5931b61f2ea09c60c204dd |
26-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] More fast-isel chunks (returns and integer extends)
Incremental improvement to fast-isel for PPC64. This allows us to
select on ret, sext, and zext. Filling in sext/zext improves some of
the existing logic in handling compare-immediates that needed extends.
A simplified return convention for fast-isel is also added to the
PPC64 calling conventions. All call/return processing for DAG
selection is handled with custom code, so there isn't an existing CC
to rely on here. The include of PPCGenCallingConv.inc causes compiler
warnings due to the 32-bit calling conventions that are not used, so
the dummy function "usePPC32CCs()" is added here to silence those.
Test cases for the return and extend logic are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189266 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCFastISel.cpp
PCInstr64Bit.td
|
| 3fad2bcd25d5f46d98ea7e41c6654833f197b960 |
26-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Add fast-isel branch and compare selection.
First chunk of actual fast-isel selection code. This handles direct
and indirect branches, as well as feeding compares for direct
branches. PPCFastISel::PPCEmitIntExt() is just roughed in and will be
expanded in a future patch. This also corrects a problem with
selection for constant pool entries in JIT mode or with small code
model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189202 91177308-0d34-0410-b5e6-96231b3b80d8
PCFastISel.cpp
|
| 6af35e95765e2d577919714dfbdac3ebf84cac78 |
20-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] More refactoring prior to real PPC emitPrologue/Epilogue changes.
(Patch committed on behalf of Mark Minich, whose log entry follows.)
This is a continuation of the refactorings performed in svn rev 188573
(see that rev's comments for more detail).
This is my stage 2 refactoring: I combined the emitPrologue() &
emitEpilogue() PPC32 & PPC64 code into a single flow, simplifying a
lot of the code since in essence the PPC32 & PPC64 code generation
logic is the same, only the instruction forms are different (in most
cases). This simplification is necessary because my functional changes
(yet to come) add significant complexity, and without the
simplification of my stage 2 refactoring, the overall complexity of
both emitPrologue() & emitEpilogue() would have become almost
intractable for most mortal programmers (like me).
This submission was intended to be a pure refactoring (no functional
changes whatsoever). However, in the process of combining the PPC32 &
PPC64 flows, I spotted a difference that I believe is a bug (see svn
rev 186478 line 863, or svn rev 188573 line 888): This line appears to
be restoring the BP with the original FP content, not the original BP
content. When I merged the 32-bit and 64-bit code, I used the
corresponding code from the 64-bit flow, which I believe uses the
correct offset (BPOffset) for this operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188741 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 66d1fa6f4b443ac9f8bcea5d1f71a73ada733a42 |
20-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a llvm.copysign intrinsic
This adds a llvm.copysign intrinsic; We already have Libfunc recognition for
copysign (which is turned into the FCOPYSIGN SDAG node). In order to
autovectorize calls to copysign in the loop vectorizer, we need a corresponding
intrinsic as well.
In addition to the expected changes to the language reference, the loop
vectorizer, BasicTTI, and the SDAG builder (the intrinsic is transformed into
an FCOPYSIGN node, just like the function call), this also adds FCOPYSIGN to a
few lists in LegalizeVector{Ops,Types} so that vector copysigns can be
expanded.
In TargetLoweringBase::initActions, I've made the default action for FCOPYSIGN
be Expand for vector types. This seems correct for all in-tree targets, and I
think is the right thing to do because, previously, there was no way to generate
vector-values FCOPYSIGN nodes (and most targets don't specify an action for
vector-typed FCOPYSIGN).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188728 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 30cbccb029b01738202bd04341b1cbf68a7814c9 |
20-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Don't form PPC CTR-based loops around a copysignl call
copysign/copysignf never become function calls (because the SDAG expansion code
does not lower to the corresponding function call, but rather directly
implements the associated logic), but copysignl almost always is lowered into a
call to the requested libm functon (and, thus, might clobber CTR).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188727 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 953a78084b85ea88cd2b208153a72df70e27133f |
19-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC fcpsgn instruction
Modern PPC cores support a floating-point copysign instruction, and we can use
this to lower the FCOPYSIGN node (which is created from calls to the libm
copysign function). A couple of extra patterns are necessary because the
operand types of FCOPYSIGN need not agree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188653 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCISelLowering.cpp
PCInstrInfo.td
PCSubtarget.cpp
PCSubtarget.h
|
| 9bb6c81683393363ed1ff8c66397f2d944c0966b |
16-Aug-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Preparatory refactoring for making prologue and epilogue
safe on PPC32 SVR4 ABI
[Patch and following text by Mark Minich; committing on his behalf.]
There are FIXME's in PowerPC/PPCFrameLowering.cpp, method
PPCFrameLowering::emitPrologue() related to "negative offsets of R1"
on PPC32 SVR4. They're true, but the real issue is that on PPC32 SVR4
(and any ABI without a Red Zone), no spills may be made until after
the stackframe is claimed, which also includes the LR spill which is
at a positive offset. The same problem exists in emitEpilogue(),
though there's no FIXME for it. I intend to fix this issue, making
LLVM-compiled code finally safe for use on SVR4/EABI/e500 32-bit
platforms (including in particular, OS-free embedded systems & kernel
code, where interrupts may share the same stack as user code).
In preparation for making these changes, to make the diffs for the
functional changes less cluttered, I am providing the non-functional
refactorings in two stages:
Stage 1 does some minor fluffy refactorings to pull multiple method
calls up into a single bool, creating named bools for repeated uses of
obscure logic, moving some code up earlier because either stage 2 or
my final version will require it earlier, and rewording/adding some
comments. My stage 1 changes can be characterized as primarily fluffy
cleanup, the purpose of which may be unclear until the stage 2 or
final changes are made.
My stage 2 refactorings combine the separate PPC32 & PPC64 logic,
which is currently performed by largely duplicate code, into a single
flow, with the differences handled by a group of constants initialized
early in the methods.
This submission is for my stage 1 changes. There should be no
functional changes whatsoever; this is a pure refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188573 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 5a0910b34959fa8e0b5a49908f51a15bc3a48069 |
15-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
Replace getValueType().getSimpleVT() with getSimpleValueType(). Also remove one weird cast from MVT->EVT just to call getSimpleVT().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188441 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 341c1a50adeadd848b2e73e9184d81331ee1cb92 |
14-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Actually fix PPC64 64-bit GPR inline asm constraint matching
This is a follow-up to r187693, correcting that code to request the correct
register class. The previous version, with the wrong register class, was not
really correcting the constraints, but rather was removing them. Coincidentally,
this fixed the failing test case in r187693, but obviously created other
problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188407 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| d76adee1b214fe1f5a26b8ffaec3e461beda6c88 |
08-Aug-2013 |
David Fang <fang@csl.cornell.edu> |
cast fix to appease buildbot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188014 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMachObjectWriter.cpp
|
| d4f9d05fde4b2cfd202a5852ec1ec3e960ef53ed |
08-Aug-2013 |
David Fang <fang@csl.cornell.edu> |
initial draft of PPCMachObjectWriter.cpp
this records relocation entries in the mach-o object file
for PIC code generation.
tested on powerpc-darwin8, validated against darwin otool -rvV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188004 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/CMakeLists.txt
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCMCTargetDesc.h
CTargetDesc/PPCMachObjectWriter.cpp
|
| 05a4d2642b415e3332651733015b656bc3c7b9bc |
08-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Map frin to round() not nearbyint() and rint()
Making use of the recently-added ISD::FROUND, which allows for custom lowering
of round(), the PPC backend will now map frin to round(). Previously, we had
been using frin to lower nearbyint() (and rint() via some custom lowering to
handle the extra fenv flags requirements), but only in fast-math mode because
frin does not tie-to-even. Several users had complained about this behavior,
and this new mapping of frin to round is certainly more appropriate (and does
not require fast-math mode).
In effect, this reverts r178362 (and part of r178337, replacing the nearbyint
mapping with the round mapping).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187960 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| 41418d17cced656f91038b2482bc9d173b4974b0 |
08-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add ISD::FROUND for libm round()
All libm floating-point rounding functions, except for round(), had their own
ISD nodes. Recent PowerPC cores have an instruction for round(), and so here I'm
adding ISD::FROUND so that round() can be custom lowered as well.
For the most part, this is straightforward. I've added an intrinsic
and a matching ISD node just like those for nearbyint() and friends. The
SelectionDAG pattern I've named frnd (because ISD::FP_ROUND has already claimed
fround).
This will be used by the PowerPC backend in a follow-up commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187926 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 0e910d2cb5feac287c2a3050c1945a3c4a3d2dd5 |
06-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC64 mulli pattern
The PPC backend had been missing a pattern to generate mulli for 64-bit
multiples. We had been generating it only for 32-bit multiplies. Unfortunately,
generating li + mulld unnecessarily increases register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187807 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 8e1d64666f493e4994b26a390bec1290a5d94b96 |
06-Aug-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187780 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| af00feb1a6af78fbb07c4deca6e9e30a49cdcd15 |
04-Aug-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
PPCAsmParser: Stop leaking names.
Store them in a place that gets cleaned up properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187700 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
|
| 5cad12d12a823d258fc60e3975ffa142d0e190ef |
03-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix PPC64 64-bit GPR inline asm constraint matching
Internally, the PowerPC backend names the 32-bit GPRs R[0-9]+, and names the
64-bit parent GPRs X[0-9]+. When matching inline assembly constraints with
explicit register names, on PPC64 when an i64 MVT has been requested, we need
to follow gcc's convention of using r[0-9]+ to refer to the 64-bit (parent)
registers.
At some point, we'll probably want to arrange things so that the generic code
in TargetLowering uses the AsmName fields declared in *RegisterInfo.td in order
to match these inline asm register constraints. If we do that, this change can
be reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187693 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 61fc8d670f1e991804c2ab753e567981e60962cb |
01-Aug-2013 |
Bill Wendling <isanbard@gmail.com> |
Use function attributes to indicate that we don't want to realign the stack.
Function attributes are the future! So just query whether we want to realign the
stack directly from the function instead of through a random target options
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187618 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 646cd7933b16b78443b06ce9ba2362e6695cb526 |
30-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Skeletal FastISel support for 64-bit PowerPC ELF.
This is the first of many upcoming patches for PowerPC fast
instruction selection support. This patch implements the minimum
necessary for a functional (but extremely limited) FastISel pass. It
allows the table-generated portions of the selector to be created and
used, but in most cases selection will fall back to the DAG selector.
None of the block terminator instructions are implemented yet, and
most interesting instructions require some special handling.
Therefore there aren't any new test cases with this patch. There will
be quite a few tests coming with future patches.
This patch adds the make/CMake support for the new code (including
tablegen -gen-fast-isel) and creates the FastISel object for PPC64 ELF
only. It instantiates the necessary virtual functions
(TargetSelectInstruction, TargetMaterializeConstant,
TargetMaterializeAlloca, tryToFoldLoadIntoMI, and FastLowerArguments),
but of these, only TargetMaterializeConstant contains any useful
implementation. This is present since the table-generated code
requires the ability to materialize integer constants for some
instructions.
This patch has been tested by building and running the
projects/test-suite code with -O0. All tests passed with the
exception of a couple of long-running tests that time out using -O0
code generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187399 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
akefile
PCFastISel.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| f5b9110ce1e0d5bc6f96b1e74d110f0cc576324a |
28-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Add comment explaining preprocessor directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187320 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| eec21735b36ec7f79e6f925b192430bd39e8cd29 |
28-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Revert 187318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187319 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 8faa99081d9ad07234b95f86d02b4204bc561668 |
28-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Remove unnecessary preprocessor checking.
The tests !defined(__ppc__) && !defined(__powerpc__) are not needed
or helpful when verifying that code is being compiled for a 64-bit
target. The simpler test provided by this revision is sufficient to
tell if the target is 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187318 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 496cf2308acf4bb719a015517f27dff10db7de49 |
27-Jul-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert "[PowerPC] Improve consistency in use of __ppc__, __powerpc__, etc."
This reverts commit r187248. It broke many bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187254 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| d063a326b2567c3ca759f069e7680979036b9d5e |
26-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Improve consistency in use of __ppc__, __powerpc__, etc.
Both GCC and LLVM will implicitly define __ppc__ and __powerpc__ for
all PowerPC targets, whether 32- or 64-bit. They will both implicitly
define __ppc64__ and __powerpc64__ for 64-bit PowerPC targets, and not
for 32-bit targets. We cannot be sure that all other possible
compilers used to compile Clang/LLVM define both __ppc__ and
__powerpc__, for example, so it is best to check for both when relying
on either inside the Clang/LLVM code base.
This patch makes sure we always check for both variants. In addition,
it fixes one unnecessary check in lib/Target/PowerPC/PPCJITInfo.cpp.
(At least one of __ppc__ and __powerpc__ should always be defined when
compiling for a PowerPC target, no matter which compiler is used, so
testing for them is unnecessary.)
There are some places in the compiler that check for other variants,
like __POWERPC__ and _POWER, and I have left those in place. There is
no need to add them elsewhere. This seems to be in Apple-specific
code, and I won't take a chance on breaking it.
There is no intended change in behavior; thus, no test cases are
added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187248 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| f38cc38fa647d4e72c053c39bbe0cdec1342535f |
26-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Support powerpc64le as a syntax-checking target.
This patch provides basic support for powerpc64le as an LLVM target.
However, use of this target will not actually generate little-endian
code. Instead, use of the target will cause the correct little-endian
built-in defines to be generated, so that code that tests for
__LITTLE_ENDIAN__, for example, will be correctly parsed for
syntax-only testing. Code generation will otherwise be the same as
powerpc64 (big-endian), for now.
The patch leaves open the possibility of creating a little-endian
PowerPC64 back end, but there is no immediate intent to create such a
thing.
The LLVM portions of this patch simply add ppc64le coverage everywhere
that ppc64 coverage currently exists. There is nothing of any import
worth testing until such time as little-endian code generation is
implemented. In the corresponding Clang patch, there is a new test
case variant to ensure that correct built-in defines for little-endian
code are generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187179 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCMCTargetDesc.cpp
CTargetDesc/PPCMCTargetDesc.h
PC.td
PCAsmPrinter.cpp
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
argetInfo/PowerPCTargetInfo.cpp
|
| 6ebf55d811bab50e7f42ee8cec60c125f6fe0cd2 |
25-Jul-2013 |
Roman Divacky <rdivacky@freebsd.org> |
PPC32 va_list is an actual structure so va_copy needs to copy the whole
structure not just a pointer. This implements that and thus fixes va_copy
on PPC32. Fixes #15286. Both bug and patch by Florian Zeitz!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187158 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| ef540b194f8ae1ff994ccdcb10dcc36f60e419c2 |
24-Jul-2013 |
David Fang <fang@csl.cornell.edu> |
allow tests to run on powerpc-darwin8 again, checking for __ppc__
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187027 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| f63ef914b67593e4b20a0b85e889380c20b41f55 |
24-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Split generated asm mnemonic matching table into a separate table for each asm variant.
This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187026 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
|
| aad2a72c285a48e34d89ba69d24eb624f2b09b0e |
18-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Support dynamic allocas with large alignment
Support for dynamic stack alignments in the PPC backend has been unfinished, in
part because it depends on dynamic stack realignment (which I only just
recently implemented fully). Now we can also support dynamic allocas with
higher than the default target stack alignment (16 bytes).
In order to round-up the requested size to the maximum requested alignment, we
need an additional register to hold the rounded-up size. We're already using one
scavenged register to hold the previous stack-pointer value (which needs to be
stored with the signal-safe stdux update), and so when we have dynamic allocas
and a large alignment, we allocate two emergency spill slots for the scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186562 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCRegisterInfo.cpp
|
| 0541722de4beb2e53058dbf4ed1ebf0d96ddd6cb |
18-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Add base-pointer support to builtin setjmp/longjmp
First, this changes the base-pointer implementation to remove an unnecessary
complication (and one that is incompatible with how builtin SjLj is
implemented): instead of using r31 as the base pointer when it is not needed as
a frame pointer, now the base pointer will always be r30 when needed.
Second, we introduce another pseudo register, BP, which is used just like the FP
pseudo register to refer to the base register before we know for certain what
register it will be.
Third, we now save BP into the jmp_buf, and restore r30 from that slot in
longjmp. If the function that called setjmp did not use a base pointer, then
r30 will be overwritten by the setjmp-calling-function's restore code. FP
restoration (which is restored into r31) works the same way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186545 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCFrameLowering.h
PCISelLowering.cpp
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| 8d7435e9b1319c6e748a06c0b41a4c3de82ec750 |
17-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Add CTR-register clobber to builtin setjmp
Because the builtin longjmp implementation uses a CTR-based indirect jump, when
the control flow arrives at the builtin setjmp call, the CTR register has
necessarily been clobbered. Correspondingly, this adds CTR to the list of
implicit definitions of the builtin setjmp pseudo instruction.
We don't need to add CTR to the implicit definitions of builtin longjmp
because, even though it does clobber the CTR register, the control flow cannot
return to inside the loop unless there is also a builtin setjmp call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186488 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753d |
17-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Implement base pointer and stack realignment
This builds on some frame-lowering code that has existed since 2005 (r24224)
but was disabled in 2008 (r48188) because it needed base pointer support to
function correctly. This implementation follows the strategy suggested by Dale
Johannesen in r48188 where the following comment was added:
This does not currently work, because the delta between old and new stack
pointers is added to offsets that reference incoming parameters after the
prolog is generated, and the code that does that doesn't handle a variable
delta. You don't want to do that anyway; a better approach is to reserve
another register that retains to the incoming stack pointer, and reference
parameters relative to that.
And now we do exactly that. If we don't need a frame pointer, then we use r31
as a base pointer. If we do need a frame pointer, then we use r30 as a base
pointer. The base pointer retains the value of the stack pointer before it was
decremented in the prologue. We then use the base pointer to resolve all
negative frame indicies. The basic scheme follows that for base pointers in the
X86 backend.
We use a base pointer when we need to dynamically realign the incoming stack
pointer. This currently applies only to static objects (dynamic allocas with
large alignments, and base-pointer support in SjLj lowering will come in future
commits).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186478 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCFrameLowering.h
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 649c7fc4747b508d72031bce111902fe53932cca |
16-Jul-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCJITInfo.cpp: Tweak r186252 with s/__ppc/__powerpc/ to work on powerpc-linux Fedora 12.
g++ (GCC) 4.4.4 20100630 (Red Hat 4.4.4-10)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186396 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| a44c37f880c8ca84b7388dd52fb2708495697a18 |
16-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Refactoring to support subtarget feature changing
This change mirrors the changes that were made to the X86 and ARM targets to
support subtarget feature changing. As indicated in r182899, the mechanism is
still undergoing revision, and so as with the X86 and ARM targets, there is no
test case yet (there is no effective functionality change).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186357 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
|
| ae4f3f6820c28a4ba4fab538f5ff4724cbe82d50 |
15-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix register subclass handling in PPCInstrInfo::insertSelect
PPCInstrInfo::insertSelect and PPCInstrInfo::canInsertSelect were computing the
common subclass of the true and false inputs, and then selecting either the
32-bit or the 64-bit isel variant based on the result of calling
PPC::GPRCRegClass.hasSubClassEq(RC) and PPC::G8RCRegClass.hasSubClassEq(RC)
(where RC is the common subclass). Unfortunately, this is not quite right: if
we have something like this:
%vreg8<def> = SELECT_CC_I8 %vreg4<kill>, %vreg7<kill>, %vreg6<kill>, 76;
G8RC_and_G8RC_NOX0:%vreg8 CRRC:%vreg4 G8RC_NOX0:%vreg7,%vreg6
then the common subclass of G8RC_and_G8RC_NOX0 and G8RC_NOX0 is G8RC_NOX0, and
G8RC_NOX0 is not a subclass of G8RC (because it also contains the ZERO8
pseudo-register). As a result, we also need to check the common subclass
against GPRC_NOR0 and G8RC_NOX0 explicitly.
This had not been a problem for clients of insertSelect that called
canInsertSelect first (because it had a compensating mistake), but insertSelect
is also used by the PPC pseudo-instruction expander, and this error was causing
a problem in that context.
This problem was found by csmith.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186343 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| b9df53a40b22c74ce3f3a7b4a7c0676a38cf5e73 |
15-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use llvm::array_lengthof to replace sizeof(array)/sizeof(array[0]).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186301 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| a0ec3f9b7b826b9b40b80199923b664bad808cce |
14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCISelLowering.cpp
PCMachineFunctionInfo.h
|
| 0a14e7123269ffc84b26d87676ddce1afc335f02 |
13-Jul-2013 |
Joerg Sonnenberger <joerg@bec.de> |
Reduce large list of macros to the primary platform macros. Distingiush
between ELF (Linux, FreeBSD, NetBSD) and OSX as platform for the
assembler dialect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186252 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| e2ff00e117ba9b758b298e671f65c0b002f8a52d |
11-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Add some missing V_SET0 patterns
We had patterns to match v4i32 immAllZerosV -> V_SET0, but not patterns for
v8i16 (which occurs in the test case) or v16i8. The same was true for
V_SETALLONES (so I added the associated patterns for those as well).
Another bug found by llvm-stress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186108 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 53c86db25b5b4e163c68dc91c8ce1bc8180e6ff3 |
11-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPCDAGToDAGISel::isRunOfOnes should return false on zero
This fixes a bug (found by csmith) at -O0 where we attempt to create a RLWIMI
with an out-of-range operand. Most uses of the isRunOfOnes function are guarded
by a condition that the value is not zero. This was not true in two places, and
in both places a zero input would result in an out-of-rage MB value (= 32).
To fix this, isRunOfOnes returns false on a zero input (and I've remove one
now-redundant guard).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186101 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| e355d850d6b3f595ce58a7b612502b57ca7f3271 |
10-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Add a better comment about the i64 FI fixup
In discussing this change with Bill Schmidt, it was decided that the original
comment about negative FIs was incorrect. We'll still exclude them for now, but
now with a more-accurate explanation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186005 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 7c2d8f7b5ea1d0abaed1176f87ea2509e65e82be |
09-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Better fix for PR16556.
A more complete example of the bug in PR16556 was recently provided,
showing that the previous fix was not sufficient. The previous fix is
reverted herein.
The real problem is that ReplaceNodeResults() uses LowerFP_TO_INT as
custom lowering for FP_TO_SINT during type legalization, without
checking whether the input type is handled by that routine.
LowerFP_TO_INT requires the input to be f32 or f64, so we fail when
the input is ppcf128.
I'm leaving the test case from the initial fix (r185821) in place, and
adding the new test as another crash-only check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185959 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e54885af9b54bfc7436a928a48d3db1ef88a2a70 |
09-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185956 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 7a34599db017a5486cf7cd11eb124984acec8286 |
09-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Revert r185476 and fix up TLS variant kinds
In the commit message to r185476 I wrote:
>The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
>correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
>This causes some confusion with the asm parser, since VK_PPC_TLSGD
>is output as @tlsgd, which is then read back in as VK_TLSGD.
>
>To avoid this confusion, this patch removes the PowerPC-specific
>modifiers and uses the generic modifiers throughout. (The only
>drawback is that the generic modifiers are printed in upper case
>while the usual convention on PowerPC is to use lower-case modifiers.
>But this is just a cosmetic issue.)
This was unfortunately incorrect, there is is fact another,
serious drawback to using the default VK_TLSLD/VK_TLSGD
variant kinds: using these causes ELFObjectWriter::RelocNeedsGOT
to return true, which in turn causes the ELFObjectWriter to emit
an undefined reference to _GLOBAL_OFFSET_TABLE_.
This is a problem on powerpc64, because it uses the TOC instead
of the GOT, and the linker does not provide _GLOBAL_OFFSET_TABLE_,
so the symbol remains undefined. This means shared libraries
using TLS built with the integrated assembler are currently
broken.
While the whole RelocNeedsGOT / _GLOBAL_OFFSET_TABLE_ situation
probably ought to be properly fixed at some point, for now I'm
simply reverting the r185476 commit. Now this in turn exposes
the breakage of handling @tlsgd/@tlsld in the asm parser that
this check-in was originally intended to fix.
To avoid this regression, I'm also adding a different fix for
this problem: while common code now parses @tlsgd as VK_TLSGD,
a special hack in the asm parser translates this code to the
platform-specific VK_PPC_TLSGD that the back-end now expects.
While this is not really pretty, it's self-contained and
shouldn't hurt anything else for now. One the underlying
problem is fixed, this hack can be reverted again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185945 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
CTargetDesc/PPCELFObjectWriter.cpp
PCAsmPrinter.cpp
|
| b2713e018e1c99bb9a65d2d2e63dc7e3e2222c57 |
09-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support ".machine any"
The PowerPC assembler is supposed to provide a directive .machine
that allows switching the supported CPU instruction set on the fly.
Since we do not yet check CPU feature sets at all and always accept
any available instruction, this is not really useful at this point.
However, it makes sense to accept (and ignore) ".machine any" to
avoid spuriously rejecting existing assembler files that use this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185924 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
|
| ff16df71f50231c79c379a146dc55b4d6867cbd9 |
09-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support .llong and fix .word
This adds support for the .llong PowerPC-specifc assembler directive.
In doing so, I notices that .word is currently incorrect: it is
supposed to define a 2-byte data element, not a 4-byte one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185911 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
|
| fa55969acb64da32acf6305064c9f6e3c237b74e |
09-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Allocate RS spill slot for unaligned i64 load/store
This fixes another bug found by llvm-stress!
If we happen to be doing an i64 load or store into a stack slot that has less
than a 4-byte alignment, then the frame-index elimination may need to use an
indexed load or store instruction (because the offset may not be a multiple of
4, a requirement of the STD/LD instructions). The extra register needed to hold
the offset comes from the register scavenger, and it is possible that the
scavenger will need to use an emergency spill slot. As a result, we need to
make sure that a spill slot is allocated when doing an i64 load/store into a
less-than-4-byte-aligned stack slot.
Because test cases for things like this tend to be fairly fragile, I've
concatenated a few small bugpoint-reduced test cases together to form the
regression test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185907 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a68f58ab2bec6a024afae498e4082ddd8b01f178 |
08-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Always use "assembler dialect" 1
A setting in MCAsmInfo defines the "assembler dialect" to use. This is used
by common code to choose between alternatives in a multi-alternative GNU
inline asm statement like the following:
__asm__ ("{sfe|subfe} %0,%1,%2" : "=r" (out) : "r" (in1), "r" (in2));
The meaning of these dialects is platform specific, and GCC defines those
for PowerPC to use dialect 0 for old-style (POWER) mnemonics and 1 for
new-style (PowerPC) mnemonics, like in the example above.
To be compatible with inline asm used with GCC, LLVM ought to do the same.
Specifically, this means we should always use assembler dialect 1 since
old-style mnemonics really aren't supported on any current platform.
However, the current LLVM back-end uses:
AssemblerDialect = 1; // New-Style mnemonics.
in PPCMCAsmInfoDarwin, and
AssemblerDialect = 0; // Old-Style mnemonics.
in PPCLinuxMCAsmInfo.
The Linux setting really isn't correct, we should be using new-style
mnemonics everywhere. This is changed by this commit.
Unfortunately, the setting of this variable is overloaded in the back-end
to decide whether or not we are on a Darwin target. This is done in
PPCInstPrinter (the "SyntaxVariant" is initialized from the MCAsmInfo
AssemblerDialect setting), and also in PPCMCExpr. Setting AssemblerDialect
to 1 for both Darwin and Linux no longer allows us to make this distinction.
Instead, this patch uses the MCSubtargetInfo passed to createPPCMCInstPrinter
to distinguish Darwin targets, and ignores the SyntaxVariant parameter.
As to PPCMCExpr, this patch adds an explicit isDarwin argument that needs
to be passed in by the caller when creating a target MCExpr. (To do so
this patch implicitly also reverts commit 184441.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185858 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
nstPrinter/PPCInstPrinter.h
CTargetDesc/PPCMCAsmInfo.cpp
CTargetDesc/PPCMCExpr.cpp
CTargetDesc/PPCMCExpr.h
CTargetDesc/PPCMCTargetDesc.cpp
PC.h
PCAsmPrinter.cpp
PCMCInstLower.cpp
|
| 947d447ee0ac927cc308e5e53062e0edb71e7d8e |
08-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Mark vector CC action for SETO and SETONE as Expand
Another bug found by llvm-stress! This fixes hitting
llvm_unreachable("Invalid integer vector compare condition");
at the end of getVCmpInst in PPCISelDAGToDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185855 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ad3b34d1bc4eaa92a95c56fe32fd18a6f36f62f4 |
08-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Mark vector FREM as Expand by default
Another bug found by llvm-stress! This fixes crashing with:
LLVM ERROR: Cannot select: v4f32 = frem ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185840 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 19d2b78978905cfde0a0d7190c8480219fb2d1c6 |
08-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support time base instructions
This adds support for the old-style time base instructions;
while new programs are supposed to use mfspr, the mftb instructions
are still supported and in use by existing assembler files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185829 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 9e5bbeab1f6f79375c24bfab87c28f5f4c5afea1 |
08-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support basic compare mnemonics
This adds support for the basic mnemoics (with the L operand) for the
fixed-point compare instructions. These are defined as aliases for the
already existing CMPW/CMPD patterns, depending on the value of L.
This requires use of InstAlias patterns with immediate literal operands.
To make this work, we need two further changes:
- define a RegisterPrefix, because otherwise literals 0 and 1 would
be parsed as literal register names
- provide a PPCAsmParser::validateTargetOperandClass routine to
recognize immediate literals (like ARM does)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185826 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PC.td
PCInstrInfo.td
|
| 12ae7fd2da24e53c795c0cc17d06c91a0f09fb3d |
08-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Fix PR16556 (handle undef ppcf128 in LowerFP_TO_INT).
PPCTargetLowering::LowerFP_TO_INT() expects its source operand to be
either an f32 or f64, but this is not checked. A long double
(ppcf128) operand will normally be custom-lowered to a conversion to
f64 in this context. However, this isn't the case for an UNDEF node.
This patch recognizes a ppcf128 as a legal source operand for
FP_TO_INT only if it's an undef, in which case it creates an undef of
the target type.
At some point we might want to do a wholesale custom lowering of
ISD::UNDEF when the type is ppcf128, but it's not really clear that's
a great idea, and probably more work than it's worth for a situation
that only arises in the case of a programming error. At this point I
think simple is best.
The test case comes from PR16556, and is a crash-test only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185821 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 457571ed6977f78ca8d30b993fa7e86e2d7ad8d5 |
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add some special @got@tprel fixup cases
When a target@got@tprel or target@got@tprel@l symbol variant is used in
a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail,
since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO
relocation types do not exist.
However, since such symbol variants resolve to GOT offsets which are
always 4-aligned, we can simply instead use the _DS variants of the
relocation types, which *do* exist.
The same applies for the @got@dtprel variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185700 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| 23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df |
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related
assembler code:
add 3, 4, symbol@tls
The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant. This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS. This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.
As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCFixupKinds.h
CTargetDesc/PPCMCCodeEmitter.cpp
PC.h
PCISelLowering.cpp
PCInstr64Bit.td
PCMCInstLower.cpp
|
| 972befb3f281f0f9ce08d7cf27b4e879327676b0 |
04-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Implement writeNopData
This implements a proper PPCAsmBackend::writeNopData routine
that actually writes PowerPC nop instructions.
This fixes the last remaining difference in object file output
(text section) between the integrated assembler and GNU as
that I've seen anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185662 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| 3c99602ca87f604080e367838180c3d63f6931f3 |
04-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add all trap mnemonics
This adds support for all basic and extended variants
of the trap instructions to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185638 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 5606fcae50951e9d9aef7def18531b5fd017971b |
04-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add asm parser support for CR expressions
This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PCInstrInfo.td
|
| f349a6e9e6ee0b589c403e0c5785266da121d05c |
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6227d5c690504c7ada5780c00a635b282c46e275 |
04-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| c93822901aef17aaf8bb1303f27b47025fd1d582 |
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 62204220e1dc2dc21256adf765728ae257b33eac |
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1666c6a8c38a2bb2535fe667023b3f0537e03eb1 |
03-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] FreeBSD does not require f128 in its data layout string.
Long double is 64 bits on FreeBSD PPC, so the f128 entry is superfluous.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185583 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 51f558c9aed3bf74c2e8f3ff3bf365c94637ecdf |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support lmw/stmw in the asm parser
This adds support for the load/store multiple instructions,
currently used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185564 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 33efedc0481c4b0d9866ff526eb1161372b5919f |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.
Current code however always emits mtcrf. This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible. It does create
inefficient code with the integrated assembler, however.
To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything. Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.
As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCCodeEmitter.cpp
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCFrameLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 965b20e39c7fd73846e9b6ed55ba90e032ae3b1b |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Always use mfocrf if available
When accessing just a single CR register, it is always preferable to
use mfocrf instead of mfcr, if the former is available on the CPU.
Current code makes that distinction in many, but not all places
where a single CR register value is retrieved. One missing
location is PPCRegisterInfo::lowerCRSpilling.
To fix this and make this simpler in the future, this patch changes
the bulk of the back-end to always assume mfocrf is available and
simply generate it when needed.
On machines that actually do not support mfocrf, the instruction
is replaced by mfcr at the very end, in EmitInstruction.
This has the additional benefit that we no longer need the
MFCRpseud hack, since before EmitInstruction we always have
a MFOCRF instruction pattern, which already models data flow
as required.
The patch also adds the MFOCRF8 version of the instruction,
which was missing so far.
Except for the PPCRegisterInfo::lowerCRSpilling case, no change
in generated code intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185556 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCCodeEmitter.cpp
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.cpp
|
| f6b67dc7f8ed87443dc03856e789f42ba72ecaa8 |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Remove dead code from PPCDAGToDAGISel::SelectSETCC
The subroutine getCRIdxForSetCC has a parameter "Other" and comment:
If this returns with Other != -1, then the returned comparison
is an or of two simpler comparisons.
However for at least the last five years this routine has never
returned a value of Other != -1; these cases are now handled
differently to begin with.
This patch removes the parameter and the code in SelectSETCC that
attempted to handle the Other != -1 case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185541 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| bf8eb3d55cc0fe37d0ef140c2492214083a48dcb |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Make specialized AltiVec patterns isCodeGenOnly
A couple of AltiVec patterns are just specialized forms of the
generic instruction pattern, and should therefore be marked
isCodeGenOnly to avoid confusing the asm parser:
VCFSX_0, VCTUXS_0, VCFUX_0, VCTSXS_0, and V_SETALLONES.
Noticed by inspection of the generated PPCGenAsmMatcher.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185533 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 44175d9715268bfb7c2cb10ebf14474f4a411464 |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support mtspr/mfspr in the asm parser
This adds support for the generic forms of mtspr/mfspr
for the asm parser. The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 25b9bbae69befa03cc48d4be73b741eff8e523bc |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] PR16512 - Support TLS call sequences in the asm parser
This patch now adds support for recognizing TLS call sequences in
the asm parser. This needs a new pattern BL8_TLS, which is like
BL8_NOP_TLS except without nop. That pattern is used for the
asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185478 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PCInstr64Bit.td
|
| a17a7e1868076a4430cfa16694bcb42884130928 |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Rework TLS call operand processing
As part of the global-dynamic and local-dynamic TLS sequences, we need
to use a special form of the call instruction:
bl __tls_get_addr(sym@tlsld)
bl __tls_get_addr(sym@tlsgd)
which generates two fixups. The current implementation of this causes
problems with recognizing this form in the asm parser. To fix this,
this patch reworks operand processing for this special form by using
a single operand to hold both __tls_get_addr and sym@tlsld and defining
a print method to output the above form, and an encoding method to
generate the two fixups.
As a side simplification, the patch replaces the two instruction
patterns BL8_NOP_TLSGD and BL8_NOP_TLSLD by a single BL8_NOP_TLS,
since the patterns already operate in an identical fashion (whether
we have a local-dynamic or global-dynamic symbol is already encoded
in the symbol modifier).
No change in code generation intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185477 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
CTargetDesc/PPCMCCodeEmitter.cpp
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCInstr64Bit.td
|
| 58fc1f52ce070003acbdfedc85d52ba999a2bd11 |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD
The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
This causes some confusion with the asm parser, since VK_PPC_TLSGD
is output as @tlsgd, which is then read back in as VK_TLSGD.
To avoid this confusion, this patch removes the PowerPC-specific
modifiers and uses the generic modifiers throughout. (The only
drawback is that the generic modifiers are printed in upper case
while the usual convention on PowerPC is to use lower-case modifiers.
But this is just a cosmetic issue.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185476 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
PCAsmPrinter.cpp
|
| b843060ecfa29efb5f896350f6530fa81184e420 |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support TLS variables in debug info
This adds an implementation of getDebugThreadLocalSymbol for
(64-bit) PowerPC. This needs to return a generic MCExpr
since on ppc64, we need to add a bias of 0x8000 to the
value returned by the R_PPC64_DTPREL64 relocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185461 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetObjectFile.cpp
PCTargetObjectFile.h
|
| a3863ea2dacafc925a8272ebf9884fc64bef686c |
02-Jul-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove address spaces from MC.
This is dead code since PIC16 was removed in 2010. The result was an odd mix,
where some parts would carefully pass it along and others would assert it was
zero (most of the object streamer for example).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185436 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 75dd57a8f0407be32551cf695e63a106dd051a27 |
02-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling
There are a couple of (small) related changes here:
1. The printed name of the VRSAVE register has been changed from VRsave to
vrsave in order to match the name accepted by GNU binutils.
2. Support for parsing vrsave has been added to the asm parser (it seems that
there was no test case specifically covering this code, so I've added one).
3. The list of Altivec registers, which was common to all calling conventions,
has been separated out. This allows us to define the base CSR lists, and then
lists for each ABI with Altivec included. This allows SjLj, for example, to
work correctly on non-Altivec targets without using unnatural definitions of
the NoRegs CSR list.
4. VRSAVE is now always reserved on non-Darwin targets and all Altivec
registers are reserved when Altivec is disabled.
With these changes, it is now possible to compile a function containing
__builtin_unwind_init() on Linux/PPC64 with debugging information. This did not
work previously because GNU binutils assumes that all .cfi_offset offsets will
be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned
offset). This is not true for the vrsave register, however, because this
register is used only on Darwin, GCC does not bother printing a .cfi_offset
entry for it (even though there is a slot in the stack frame for it as
specified by the ABI). This change allows us to do the same: we will also not
print .cfi_offset directives for vrsave.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PCCallingConv.td
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| 228e0afcfd0d5f167a95c6ddbec2c6a4a90b6d2b |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add support for TLS data relocations
This adds support for TLS data relocations and modifiers:
.quad target@dtpmod
.quad target@tprel
.quad target@dtprel
Currently exploited by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185394 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| 1307d8300f6fe97059998480c42b44faefbc9b99 |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support all condition register logical instructions
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| c38c1d135cb9d617254c396c22949baca024dd35 |
01-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Index: test/CodeGen/PowerPC/reloc-align.ll
===================================================================
--- test/CodeGen/PowerPC/reloc-align.ll (revision 0)
+++ test/CodeGen/PowerPC/reloc-align.ll (revision 0)
@@ -0,0 +1,34 @@
+; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s
+
+; This test verifies that the peephole optimization of address accesses
+; does not produce a load or store with a relocation that can't be
+; satisfied for a given instruction encoding. Reduced from a test supplied
+; by Hal Finkel.
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.S1 = type { [8 x i8] }
+
+@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1
+
+; Function Attrs: nounwind readonly
+define signext i32 @main() #0 {
+entry:
+ %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*))
+; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l
+ ret i32 %call
+}
+
+; Function Attrs: nounwind readonly
+define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 {
+entry:
+ %0 = bitcast %struct.S1* %p_91 to i64*
+ %bf.load = load i64* %0, align 1
+ %bf.shl = shl i64 %bf.load, 26
+ %bf.ashr = ashr i64 %bf.shl, 54
+ %bf.cast = trunc i64 %bf.ashr to i32
+ ret i32 %bf.cast
+}
+
+attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
Index: lib/Target/PowerPC/PPCAsmPrinter.cpp
===================================================================
--- lib/Target/PowerPC/PPCAsmPrinter.cpp (revision 185327)
+++ lib/Target/PowerPC/PPCAsmPrinter.cpp (working copy)
@@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI
OutStreamer.EmitRawText(StringRef("\tmsync"));
return;
}
+ break;
+ case PPC::LD:
+ case PPC::STD:
+ case PPC::LWA: {
+ // Verify alignment is legal, so we don't create relocations
+ // that can't be supported.
+ // FIXME: This test is currently disabled for Darwin. The test
+ // suite shows a handful of test cases that fail this check for
+ // Darwin. Those need to be investigated before this sanity test
+ // can be enabled for those subtargets.
+ if (!Subtarget.isDarwin()) {
+ unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
+ const MachineOperand &MO = MI->getOperand(OpNum);
+ if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4)
+ llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
+ }
+ // Now process the instruction normally.
+ break;
}
+ }
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
OutStreamer.EmitInstruction(TmpInst);
Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp (revision 185327)
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp (working copy)
@@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() {
if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
SDLoc dl(GA);
const GlobalValue *GV = GA->getGlobal();
+ // We can't perform this optimization for data whose alignment
+ // is insufficient for the instruction encoding.
+ if (GV->getAlignment() < 4 &&
+ (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
+ StorageOpcode == PPC::LWA)) {
+ DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
+ continue;
+ }
ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
} else if (ConstantPoolSDNode *CP =
dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185380 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
|
| 3bd2b92267df204c5633329611cc7ae3e1c11834 |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Also add "msync" alias
This adds an alias for "msync" (which is used on Book E
systems instead of "sync").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185375 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| b5f7b0f9780cd1bc6f948b194adfc57176d41711 |
01-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
Don't form PPC CTR loops for over-sized exit counts
Although you can't generate this from C on PPC64, if you have a loop using a
64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had
been cauing the PPCCTRLoops pass to assert.
Thanks to Joerg Sonnenberger for providing a test case!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185361 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 222e781d92541017c3a9c5dd40cb52e334cdb86f |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix @got references to local symbols
A @got reference must always result in a relocation, so that
the linker has a chance to set up the GOT entry, even if the
symbol happens to be local.
Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces
a relocation to be emitted for GOT references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185353 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| 62c1baf8b58a40d37f56a5431214e6514e42970f |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add "wait" instruction
This adds the "wait" instruction and its extended mnemonics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185350 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| c0a6b981de8efd2c68125edb94bf9ffb933df727 |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support "eieio" instruction
This adds support for the "eieio" instruction to
the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185349 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| af679a22923d2b61e3bfb6721bd562b99546bfad |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add variants of "sync" instruction
This adds support for the "sync $L" instruction with operand,
and provides aliases for "lwsync" and "ptesync".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185344 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 6a636a813f33b46b3271ec8517ee1936a0c92c9f |
29-Jun-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Ignore spill/restore requests for VRSAVE (except on Darwin)
This fixes PR16418, which reports that a function calling
__builtin_unwind_init() asserts. The cause is that this generates a
spill/restore for VRSAVE, and we support that only on Darwin (because VRSAVE is
only really used on Darwin).
The test case checks only that we don't crash. We can add correctness checks
once someone verifies what behavior the function is supposed to have.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185235 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 2c77a625b79908f6e1238890caae630d28c48bee |
28-Jun-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix a PPC rlwimi instruction-selection bug
Under certain (evidently rare) circumstances, this code used to convert OR(a,
AND(x, y)) into OR(a, x). This was incorrect.
While there, I've added a comment to the code immediately above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185201 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 8950dd127ad4cccd9dadf616b5057cf130f24ade |
26-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Accept 17-bit signed immediates for addis
The assembler currently strictly verifies that immediates for
s16imm operands are in range (-32768 ... 32767). This matches
the behaviour of the GNU assembler, with one exception: gas
allows, as a special case, operands in an extended range
(-65536 .. 65535) for the addis instruction only (and its
extended mnemonic lis).
The main reason for this seems to be to allow using unsigned
16-bit operands for lis, e.g. like lis %r1, 0xfedc.
Since this has been supported by gas for a long time, and
assembler source code seen "in the wild" actually exploits
this feature, this patch adds equivalent support to LLVM
for compatibility reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184946 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 0b8594268feb1c804370541c7853e658caee0ae5 |
26-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support symbolic u16imm operands
Currently, all instructions taking s16imm operands support symbolic
operands. However, for u16imm operands, we only support actual
immediate integers. This causes the assembler to reject code like
ori %r5, %r5, symbol@l
This patch changes the u16imm operand definition to likewise
accept symbolic operands. In fact, s16imm and u16imm can
share the same encoding routine, now renamed to getImm16Encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184944 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
CTargetDesc/PPCMCCodeEmitter.cpp
PCCodeEmitter.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 5de735a962a255676cf3a9bc255579d465670633 |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @got modifier
Add VK_... values and relocation types necessary to support
the @got family of modifiers. Used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184860 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| 1bc147c0910bb02398730c79e0d0310ffbbd2868 |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add extended rotate/shift mnemonics
This adds all missing extended rotate/shift mnemonics to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184834 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PCInstrInfo.td
|
| 816c06f7fa73e8150e260a11d897be2f52d4f2b8 |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add rldcr/rldic instructions
This adds pattern for the rldcr and rldic instructions (the last instruction
from the rotate/shift family that were missing). They are currently used
only by the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184833 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 9c52f81e1787dc9666e510f5b7a0ea75b697cd0b |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add extended subtract mnemonics
This adds support for the extended subtract mnemonics to the asm parser:
subi
subis
subic
subic.
sub
sub.
subc
subc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184832 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PCInstrInfo.td
|
| 746f7cafb2d1362de62024a6e62664c3eb3999d2 |
25-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCAsmParser.cpp: Quote "@l/@ha" in comments. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184809 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
|
| 96fb3a25cb0007f06d22d28c0b9c3503798324f6 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support some miscellaneous mnemonics in the asm parser
This adds support for the following extended mnemonics:
xnop
mr.
not
not.
la
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184767 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PCInstrInfo.td
|
| cf1a3b16c00cef30207e6b83d046ad38752dfefb |
24-Jun-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
PPC: Remove default case from fully covered switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184758 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
|
| 2e8bd8950345b0857130dd0f4068222a79c103f2 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add predicted forms of branches
This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
For these, I've added new PPC::Predicate codes corresponding
to the BO values for predicted branch forms, and updated insn
printing to print them correctly. I've also added new aliases
for the asm parser matching the new forms.
- bt/bf
I've added new aliases matching to gBC etc.
- bd(n)z variants
I've added new instruction patterns for the predicted forms.
In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184754 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
nstPrinter/PPCInstPrinter.cpp
CTargetDesc/PPCPredicates.cpp
CTargetDesc/PPCPredicates.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 48473a8de50d6047432a3619e4781788ba004c93 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add t/f branch mnemonics to asm parser
This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the
asm parser, resolving to the generic conditional patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184725 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| e5a30f0ca22cc1ba97478e9fadcdef02d341004e |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support generic conditional branches in asm parser
This adds instruction patterns to cover the generic forms of
the conditional branch instructions. This allows the assembler
to support the generic mnemonics.
The compiler will still generate the various specific forms
of the instruction that were already supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184722 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 9679c47a07386cbf3547a0927609c7ee080b2aab |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support absolute branches
There is currently only limited support for the "absolute" variants
of branch instructions. This patch adds support for the absolute
variants of all branches that are currently otherwise supported.
This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.
While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.
No change in code generation intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184721 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCFixupKinds.h
CTargetDesc/PPCMCCodeEmitter.cpp
PCCodeEmitter.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 9068d5310cfafdd201f77b0434dc7eebb7f51a45 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support bd(n)zl and bd(n)zlrl
This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184720 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 813942a0cf8e0605002c5fa364372a8a61634cc4 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support b(cond)l in the asm parser
This patch adds support for the conditional variants of bl.
The pattern is currently used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184719 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 7e66f5c1b4a166d823e0452d1a1bc0f822d04201 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support blrl and variants in the asm parser
This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184718 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 84569698f01bcb49afe5b6140bf0d61cf4f3cf5a |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support R_PPC_REL16 family of relocations
The GNU assembler supports (as extension to the ABI) use of PC-relative
relocations in half16 fields, which allows writing code like:
li 1, base-.
This patch adds support for those relocation types in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184552 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| cab0a1933875935c717136d251e2af9749533ba8 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support various tls-related modifiers
The current code base only supports the minimum set of tls-related
relocations and @modifiers that are necessary to support compiler-
generated code. This patch extends this to the full set defined
in the ABI (and supported by the GNU assembler) for the benefit
of the assembler parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184551 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| f7c1ee79fe90353fcd3f545f9d45a01a837bbf4b |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @higher et.al. modifiers
This adds support for the @higher, @highera, @highest, and @highesta
modifers, including some missing relocation types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184550 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCMCExpr.cpp
CTargetDesc/PPCMCExpr.h
|
| f8f87dcfceadd1b842d130303a7091ad7d7d67d0 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @toc@h modifier
This adds the relocation type and other necessary infrastructure
to use the @toc@h modifier in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184549 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| d2849572463da994c685b3bd7a60d5a7566c01e3 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @h modifier
This adds necessary infrastructure to support the @h modifier.
Note that all required relocation types were already present
(and unused).
This patch provides support for using @h in the assembler;
it would also be possible to now use this feature in code
generated by the compiler, but this is not done yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184548 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCMCExpr.cpp
CTargetDesc/PPCMCExpr.h
|
| 92cfa61c50d01307d658753f8d47f4e8555a6fa9 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Rename some more VK_PPC_ enums
This renames more VK_PPC_ enums, to make them more closely reflect
the @modifier string they represent. This also prepares for adding
a bunch of new VK_PPC_ enums in upcoming patches.
For consistency, some MO_ flags related to VK_PPC_ enums are
likewise renamed.
No change in behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184547 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCMCExpr.cpp
CTargetDesc/PPCMCExpr.h
PC.h
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCMCInstLower.cpp
|
| 846565924a6f2932efc75c249b29c3619e587bbb |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Clean up VK_PPC_TOC... names
This is another minor cleanup; to bring enum names in line
with the corresponding @modifier names, this renames:
VK_PPC_TOC -> VK_PPC_TOCBASE
VK_PPC_TOC_ENTRY -> VK_PPC_TOC16
No code change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184491 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
PCAsmPrinter.cpp
|
| 769accfb4d71caff9152309eaa5e704e065b5846 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Minor cleanup in PPCELFObjectWriter::getRelocTypeInner
This just re-sorts the big switch statement in
PPCELFObjectWriter::getRelocTypeInner to follow
the (numerical) order of the reloc types, and
fixes a couple of whitespace issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184485 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| ea18f0cc4d3595ed55b53faf08ead1fc3d5abfa3 |
20-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Remove unused parameter
The isDarwin parameter to the llvm::LowerPPCMachineInstrToMCInst
routine is now no longer needed; remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184441 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCMCInstLower.cpp
|
| 06eb45c358c0872c8f9a82f601d89d0a7329d38d |
20-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add missing build dependency
This (hopefully) fixes build failures resulting from r184436;
the PowerPC asm parser now depends on PowerPC target expresssions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184439 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/LLVMBuild.txt
|
| 027e94479c9e69eb3c3c5536fa9990d0b96e9510 |
20-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Optimize @ha/@l constructs
This patch adds support for having the assembler optimize fixups
to constructs like "symbol@ha" or "symbol@l" if "symbol" can be
resolved at assembler time.
This optimization is already present in the PPCMCExpr.cpp code
for handling PPC_HA16/PPC_LO16 target expressions. However,
those target expression were used only on Darwin targets.
This patch changes target expression code so that they are
usable also with the GNU assembler (using the @ha / @l syntax
instead of the ha16() / lo16() syntax), and changes the
MCInst lowering code to generate those target expressions
where appropriate.
It also changes the asm parser to generate HA16/LO16 target
expressions when parsing assembler source that uses the
@ha / @l modifiers. The effect is that now the above-
mentioned optimization automatically becomes available
for those situations too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184436 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
CTargetDesc/PPCMCExpr.cpp
CTargetDesc/PPCMCExpr.h
PCMCInstLower.cpp
|
| 0db5379fe643cbe738b4831e337251819cc5dc5d |
20-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| ea44281d5da5096de50ce1cb358ff0c6f20e1a2a |
19-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184349 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 99cb622041a0839c7dfcf0263c5102a305a0fdb5 |
18-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Use pointers to the MCAsmInfo and MCRegInfo.
Someone may want to do something crazy, like replace these objects if they
change or something.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCCodeEmitter.cpp
PCFrameLowering.cpp
|
| 0187e7a9ba5c50b4559e0c2e0afceb6d5cd32190 |
16-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstrInfo.cpp
PCInstrInfo.h
PCRegisterInfo.cpp
|
| 7e17024400941889b6fe1b178e5374f75c34d9ab |
12-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
Revert r183854 (PPC: Fix switch warnings from r183841)
Now that the PRED_BAD has been removed, this is failing the Clang
-Werror build due to -Wcovered-switch-default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183863 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
CTargetDesc/PPCPredicates.cpp
|
| 628953385396cfa4f59b6ccb56ee3b10d6b5f865 |
12-Jun-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Remove PRED_BAD from PPC::Predicate enumeration.
I'm taking David Blaikie's suggestion to use an
Optional<PPC::Predicate> return value instead. That's the right
solution for this problem. Thanks for pointing out that possibility!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183858 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCPredicates.h
|
| dab366bf25ef00a37e5d9306c6dcbbb7c1d3e19a |
12-Jun-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Fix switch warnings from r183841.
Introducing PRED_BAD caused some unexpected warnings that are now
suppressed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183854 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
CTargetDesc/PPCPredicates.cpp
|
| d3f7766f2363862b9c8586d2f78bc413223240d3 |
12-Jun-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
[PowerPC] Expose some calling convention functions in PPCISelLowering.h.
This is a preparatory patch for fast-isel support. The instruction
selector will need to access some functions in PPCGenCallingConv.inc,
which in turn requires several helper functions to be defined. These
are currently defined near the only use of PCCGenCallingConv.inc,
inside PPCISelLowering.cpp. This patch moves the declaration of the
functions into the associated header file to provide the needed
visibility.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183844 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| f69ead465110efd53cc838191080bc0f2d71c345 |
12-Jun-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Add artificial PRED_BAD to PPC::Predicate enumeration.
Allows returning a PPC::Predicate from a function with a no-predicate
value possible. Preparatory patch for fast-isel on PPC64 ELF. No
behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183841 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCPredicates.h
|
| c1f4a4b2640dfc871bacacef53a95f1c96a9fe48 |
12-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[MC/DWARF] Support .debug_frame / .debug_line code alignment factors
I've been comparing the object file output of LLVM's integrated
assembler against the external assembler on PowerPC, and one
area where differences still remain are in DWARF sections.
In particular, the GNU assembler generates .debug_frame and
.debug_line sections using a code alignment factor of 4, since
all PowerPC instructions have size 4 and must be aligned to a
multiple of 4. However, current MC code hard-codes a code
alignment factor of 1.
This patch changes this by adding a "minimum instruction alignment"
data element to MCAsmInfo and using this as code alignment factor.
This requires passing a MCContext into MCDwarfLineAddr::Encode
and MCDwarfLineAddr::EncodeAdvanceLoc. Note that one caller,
MCDwarfLineAddr::Write, didn't actually have that information
available. However, it turns out that this routine is in fact
never used in the whole code base, so the patch simply removes
it. If it turns out to be needed again at a later time, it
could be re-added with an updated interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183834 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
|
| 278916500a2d7c735e3ed6b0f57cd757815b9867 |
10-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support extended sc mnemonic
A plain "sc" without argument is supposed to be treated like "sc 0"
by the assembler. This patch adds a corresponding alias.
Problem reported by Joerg Sonnenberger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183687 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 7c6f90d486911076da01ec0f37af4760fdd7041f |
10-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support branch mnemonics with implied CR0
The extended branch mnemonics are supposed to use an implied CR0
if there is no explicit condition register specified. This patch
adds extra variants of the mnemonics to this effect.
Problem reported by Joerg Sonnenberger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183686 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| b838f9fe619382b212f6055ad94a74ff36db9219 |
10-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use multiclass to generate extended branch mnemonics
This patch removes some redundancy by generating the extended branch
mnemonics via a multiclass.
No change in behaviour expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183685 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 40be73bed71a69853720a7f0609cb1f2f77dc3bd |
08-Jun-2013 |
Hal Finkel <hfinkel@anl.gov> |
Disallow i64 div/rem in PPC32 counter loops
On PPC32, [su]div,rem on i64 types are transformed into runtime library
function calls. As a result, they are not allowed in counter-based loops (the
counter-loops verification pass caught this error; this change fixes PR16169).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183581 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 041399aad5a3d93c2dc9d2b70cb9b87d4a987ece |
07-Jun-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fold variable that's only used in assert into the assert.
Avoids unused variable warnings in Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183512 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 80ada583f3b40ffb201e54cd57c42f9518039c9e |
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 23ed37a6b76e79272194fb46597f7280661b828f |
01-Jun-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
Make SubRegIndex size mandatory, following r183020.
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2 |
30-May-2013 |
Andrew Trick <atrick@apple.com> |
Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 119da2eb20fffce88fa659d761ef5cea43f09ab6 |
27-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Add a isConsecutiveLS utility function
isConsecutiveLS is a slightly more general form of
SelectionDAG::isConsecutiveLoad. Aside from also handling stores, it also does
not assume equality of the chain operands is necessary. In the case of the PPC
backend, this chain condition is checked in a more general way by the
surrounding code.
Mostly, this part of the refactoring in preparation for supporting optimized
unaligned stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182723 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1907cad7c822f07894a1189886fa7577f109045a |
26-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Prefer to duplicate PPC Altivec loads when expanding unaligned loads
When expanding unaligned Altivec loads, we use the decremented offset trick to
prevent page faults. Unfortunately, if we have a sequence of consecutive
unaligned loads, this leads to suboptimal code generation because the 'extra'
load from the first unaligned load can be combined with the base load from the
second (but only if the decremented offset trick is not used for the first).
Search up and down the chain, through loads and token factors, looking for
consecutive loads, and if one is found, don't use the offset reduction trick.
These duplicate loads are later combined to yield the desired sequence (in the
future, we might want a more-powerful chain search, but that will require some
changes to allow the combiner routines to access the AA object).
This should complete the initial implementation of the optimized unaligned
Altivec load expansion. There is some refactoring that should be done, but
that will happen when the unaligned store expansion is added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182719 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 5a0e60425f4f942afb7e901b401a130da48a4d21 |
25-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Combine duplicate (offset) lvsl Altivec intrinsics
The lvsl permutation control instruction is a function only of the alignment of
the pointer operand (relative to the 16-byte natural alignment of Altivec
vectors). As a result, multiple lvsl intrinsics where the operands differ by a
multiple of 16 can be combined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182708 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| 80d10ded8cd4f34b87d82b03d6f63328ea337b26 |
25-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Initial support for permutation-based unaligned Altivec loads
Altivec only directly supports aligned loads, but the loads have a strange
property: If given an unaligned address, they truncate the address to the next
lower aligned address, and load from there. This property, along with an extra
load and some special-purpose permutation-control instructions that generate
the appropriate permutations from the original unaligned address, allow
efficient lowering of aligned loads. This code uses the trick explained in the
Apple Velocity Engine optimization overview document to prevent the needed
extra load from possibly causing a page fault if the original address happens
to be aligned.
As noted in the FIXMEs, there are several additional optimizations that can be
performed to reduce the cost of these loads even more. These will be
implemented in future commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182691 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c6af2432c802d241c8fffbe0371c023e6c58844e |
25-May-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PCISelDAGToDAG.cpp
|
| 586f6d009a37d4d38be0badaaa60d7cdb647b442 |
24-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Remove symbolLo/symbolHi instruction operand types
Now that there is no longer any distinction between symbolLo
and symbolHi operands in either printing, encoding, or parsing,
the operand types can be removed in favor of simply using
s16imm.
This completes the patch series to decouple lo/hi operand part
processing from the particular instruction whose operand it is.
No change in code generation expected from this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182618 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| edaa58ee66699b99841ee5dfdd485aedbae3bf90 |
24-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Clean up generation of ha16() / lo16() markers
When targeting the Darwin assembler, we need to generate markers ha16() and
lo16() to designate the high and low parts of a (symbolic) immediate. This
is necessary not just for plain symbols, but also for certain symbolic
expression, typically along the lines of ha16(A - B). The latter doesn't
work when simply using VariantKind flags on the symbol reference.
This is why the current back-end uses hacks (explicitly called out as such
via multiple FIXMEs) in the symbolLo/symbolHi print methods.
This patch uses target-defined MCExpr codes to represent the Darwin
ha16/lo16 constructs, following along the lines of the equivalent solution
used by the ARM back end to handle their :upper16: / :lower16: markers.
This allows us to get rid of special handling both in the symbolLo/symbolHi
print method and in the common code MCExpr::print routine. Instead, the
ha16 / lo16 markers are printed simply in a custom print routine for the
target MCExpr types. (As a result, the symbolLo/symbolHi print methods
can now replaced by a single printS16ImmOperand routine that also handles
symbolic operands.)
The patch also provides a EvaluateAsRelocatableImpl routine to handle
ha16/lo16 constructs. This is not actually used at the moment by any
in-tree code, but is provided as it makes merging into David Fang's
out-of-tree Mach-O object writer simpler.
Since there is no longer any need to treat VK_PPC_GAS_HA16 and
VK_PPC_DARWIN_HA16 differently, they are merged into a single
VK_PPC_ADDR16_HA (and likewise for the _LO16 types).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182616 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
CTargetDesc/CMakeLists.txt
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCMCExpr.cpp
CTargetDesc/PPCMCExpr.h
PCAsmPrinter.cpp
PCInstr64Bit.td
PCInstrInfo.td
PCMCInstLower.cpp
|
| 5cd01f74b11dc3e1c08c3ddea067af8203079b87 |
22-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Change some PowerPC PatLeaf definitions to ImmLeaf for fast-isel.
Using PatLeaf rather than ImmLeaf when defining immediate predicates
prevents simple patterns using those predicates from being recognized
for fast instruction selection. This patch replaces the immSExt16
PatLeaf predicate with two ImmLeaf predicates, imm32SExt16 and
imm64SExt16, allowing a few more patterns to be recognized (ADDI,
ADDIC, MULLI, ADDI8, and ADDIC8). Using the new predicates does not
help for LI, LI8, SUBFIC, and SUBFIC8 because these are rejected for
other reasons, but I see no reason to retain the PatLeaf predicate.
No functional change intended, and thus no test cases yet. This is
preliminary work for enabling fast-isel support for PowerPC. When
that support is ready, we'll be able to test this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182510 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 75e9ee8b7fc2b7c91239f4b9b8d77087fd8ea4e4 |
21-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix PPC branch selection for counter-based branches
Although I had added some support for the BDZ/BDNZ branches into the selector
(in r158204), I had not correctly adjusted the condition at the top of the
loop. As a result, these branches were still essentially unsupported.
This fixes PR16086. Unfortunately, any test case would be very large (because
it would need to force the loop backedge to exceed the range of the 16-bit
immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182385 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 4e6b24ffcfafbc0c5eda1bb89163ccd56f394fdf |
20-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Rename LoopSimplify.h to LoopUtils.h
As discussed, LoopUtils.h is a better name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182314 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 08f92c98ac1cdb43ec35653536c89964401d936c |
20-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove copied preheader insertion logic from PPCCTRLoops
Now that the preheader insertion logic in LoopSimplify is externally exposed,
use it, and remove the copy-and-pasted version.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182300 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 85c08b059ce4248ee739e756cf717a9b429e2ec2 |
20-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Rename PPC MTCTRse to MTCTRloop
As the pairing of this instruction form with the bdnz/bdz branches is now
enforced by the verification pass, make it clear from the name that these
are used only for counter-based loops.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182296 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| e50c8c1f81a38f0ecebafa5dc60a163814a9713a |
20-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a PPCCTRLoops verification pass
When asserts are enabled, this adds a verification pass for PPC counter-loop
formation. Unfortunately, without sacrificing code quality, there is no better
way of forming counter-based loops except at the (late) IR level. This means
that we need to recognize, at the IR level, anything which might turn into a
function call (or indirect branch). Because this is currently a finite set of
things, and because SelectionDAG lowering is basic-block local, this can be
done. Nevertheless, it is fragile, and failure results in a miscompile. This
verification pass checks that all (reachable) counter-based branches are
dominated by a loop mtctr instruction, and that no instructions in between
clobber the counter register. If these conditions are not satisfied, then an
ICE will be triggered.
In short, this is to help us sleep better at night.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182295 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCCTRLoops.cpp
PCTargetMachine.cpp
|
| bf0bc3b2a2e11ff7e79b881ca82324fe17919a97 |
18-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Check InlineAsm clobbers in PPCCTRLoops
We don't need to reject all inline asm as using the counter register (most does
not). Only those that explicitly clobber the counter register need to prevent
the transformation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182191 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 4456a8ec76bba1148f64bb2707e18b980eda291e |
17-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix hi/lo encoding in old-style code emitter
This patch implements the equivalent change to r182091/r182092
in the old-style code emitter. Instead of having two separate
16-bit immediate encoding routines depending on the instruction,
this patch introduces a single encoder that checks the machine
operand flags to decide whether the low or high half of a
symbol address is required.
Since now both encoders make no further distinction between
"symbolLo" and "symbolHi", the .td operand can now use a
single getS16ImmEncoding method.
Tested by running the old-style JIT tests on 32-bit Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182097 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCCodeEmitter.cpp
PCCodeEmitter.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| e152eac63efa836cbb109d79e4307516fa16f1a6 |
17-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Merge/rename PPC fixup types
Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly
the same everywhere, it no longer makes sense to have two fixup types.
This patch merges them both into a single type fixup_ppc_half16,
and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency.
(The half16 and half16ds names are taken from the description of
relocation types in the PowerPC ABI.)
No change in code generation expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182092 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCFixupKinds.h
CTargetDesc/PPCMCCodeEmitter.cpp
|
| c299ad32c8e59ceea05ede15e1c59ac787d17feb |
17-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix processing of ha16/lo16 fixups
The current PowerPC MC back end distinguishes between fixup_ppc_ha16
and fixup_ppc_lo16, which are determined by the instruction the fixup
applies to, and uses this distinction to decide whether a fixup ought
to resolve to the high or the low part of a symbol address.
This isn't quite correct, however. It is valid -if unusual- assembler
to use, e.g.
li 1, symbol@ha
or
lis 1, symbol@l
Whether the high or the low part of the address is used depends solely
on the @ suffix, not on the instruction.
In addition, both
li 1, symbol
and
lis 1, symbol
are valid, assuming the symbol address fits into 16 bits; again, both
will then refer to the actual symbol value (so li will load the value
itself, while lis will load the value shifted by 16).
To fix this, two places need to be adapted. If the fixup cannot be
resolved at assembler time, a relocation needs to be emitted via
PPCELFObjectWriter::getRelocType. This routine already looks at
the VK_ type to determine the relocation. The only problem is that
will reject any _LO modifier in a ha16 fixup and vice versa. This
is simply incorrect; any of those modifiers ought to be accepted
for either fixup type.
If the fixup *can* be resolved at assembler time, adjustFixupValue
currently selects the high bits of the symbol value if the fixup
type is ha16. Again, this is incorrect; see the above example
lis 1, symbol
Now, in theory we'd have to respect a VK_ modifier here. However,
in fact common code never even attempts to resolve symbol references
using any nontrivial VK_ modifier at assembler time; it will always
fall back to emitting a reloc and letting the linker handle it.
If this ever changes, presumably there'd have to be a target callback
to resolve VK_ modifiers. We'd then have to handle @ha etc. there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
|
| 6b67ffd68bb2e555b1b512a809f3c82c68f3debe |
16-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove addFrameMove.
Now that we have good testing, remove addFrameMove and create cfi
instructions directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182052 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| c482454e3cc2a33a2cf2d1cf0881c7c5e2641c80 |
16-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Create an new preheader in PPCCTRLoops to avoid counter register clobbers
Some IR-level instructions (such as FP <-> i64 conversions) are not chained
w.r.t. the mtctr intrinsic and yet may become function calls that clobber the
counter register. At the selection-DAG level, these might be reordered with the
mtctr intrinsic causing miscompiles. To avoid this situation, if an existing
preheader has instructions that might use the counter register, create a new
preheader for the mtctr intrinsic. This extra block will be remerged with the
old preheader at the MI level, but will prevent unwanted reordering at the
selection-DAG level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182045 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 347a5079e18278803bc05b197d325b8580e95610 |
16-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use true offset value in "memrix" machine operands
This is the second part of the change to always return "true"
offset values from getPreIndexedAddressParts, tackling the
case of "memrix" type operands.
This is about instructions like LD/STD that only have a 14-bit
field to encode immediate offsets, which are implicitly extended
by two zero bits by the machine, so that in effect we can access
16-bit offsets as long as they are a multiple of 4.
The PowerPC back end currently handles such instructions by
carrying the 14-bit value (as it will get encoded into the
actual machine instructions) in the machine operand fields
for such instructions. This means that those values are
in fact not the true offset, but rather the offset divided
by 4 (and then truncated to an unsigned 14-bit value).
Like in the case fixed in r182012, this makes common code
operations on such offset values not work as expected.
Furthermore, there doesn't really appear to be any strong
reason why we should encode machine operands this way.
This patch therefore changes the encoding of "memrix" type
machine operands to simply contain the "true" offset value
as a signed immediate value, while enforcing the rules that
it must fit in a 16-bit signed value and must also be a
multiple of 4.
This change must be made simultaneously in all places that
access machine operands of this type. However, just about
all those changes make the code simpler; in many cases we
can now just share the same code for memri and memrix
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182032 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
CTargetDesc/PPCMCCodeEmitter.cpp
PCCodeEmitter.cpp
PCFrameLowering.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 2a5e8c328eb0d957f00190c0c6189a4f1fef1117 |
16-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC32 cannot form counter loops around i64 FP conversions
On PPC32, i64 FP conversions are implemented using runtime calls (which clobber
the counter register). These must be excluded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182023 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| f0ef882828bd9ba13cefce9869bde8be5e854956 |
16-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Report true displacement value from getPreIndexedAddressParts
DAGCombiner::CombineToPreIndexedLoadStore calls a target routine to
decompose a memory address into a base/offset pair. It expects the
offset (if constant) to be the true displacement value in order to
perform optional additional optimizations; in particular, to convert
other uses of the original pointer into uses of the new base pointer
after pre-increment.
The PowerPC implementation of getPreIndexedAddressParts, however,
simply calls SelectAddressRegImm, which returns a TargetConstant.
This value is appropriate for encoding into the instruction, but
it is not always usable as true displacement value:
- Its type is always MVT::i32, even on 64-bit, where addresses
ought to be i64 ... this causes the optimization to simply
always fail on 64-bit due to this line in DAGCombiner:
// FIXME: In some cases, we can be smarter about this.
if (Op1.getValueType() != Offset.getValueType()) {
- Its value is truncated to an unsigned 16-bit value if negative.
This causes the above opimization to generate wrong code.
This patch fixes both problems by simply returning the true
displacement value (in its original type). This doesn't
affect any other user of the displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182012 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ec7f4231cb7c26d5f52375617a9a73a1e79f3857 |
16-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Removed dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181975 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| f1e7ea43aa3b511ea9750c7a1f721d1c683e31b2 |
16-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
undef setjmp in PPCCTRLoops
Trying to unbreak the VS build by copying some undef code from
Utils/LowerInvoke.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181938 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| b1fd3cd78f8acd21dbf514b75fef991827c343b6 |
15-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement PPC counter loops as a late IR-level pass
The old PPCCTRLoops pass, like the Hexagon pass version from which it was
derived, could only handle some simple loops in canonical form. We cannot
directly adapt the new Hexagon hardware loops pass, however, because the
Hexagon pass contains a fundamental assumption that non-constant-trip-count
loops will contain a guard, and this is not always true (the result being that
incorrect negative counts can be generated). With this commit, we replace the
pass with a late IR-level pass which makes use of SE to calculate the
backedge-taken counts and safely generate the loop-count expressions (including
any necessary max() parts). This IR level pass inserts custom intrinsics that
are lowered into the desired decrement-and-branch instructions.
The most fragile part of this new implementation is that interfering uses of
the counter register must be detected on the IR level (and, on PPC, this also
includes any indirect branches in addition to function calls). Also, to make
all of this work, we need a variant of the mtctr instruction that is marked
as having side effects. Without this, machine-code level CSE, DCE, etc.
illegally transform the resulting code. Hopefully, this can be improved
in the future.
This new pass is smaller than the original (and much smaller than the new
Hexagon hardware loops pass), and can handle many additional cases correctly.
In addition, the preheader-creation code has been copied from LoopSimplify, and
after we decide on where it belongs, this code will be refactored so that it
can be explicitly shared (making this implementation even smaller).
The new test-case files ctrloop-{le,lt,ne}.ll have been adapted from tests for
the new Hexagon pass. There are a few classes of loops that this pass does not
transform (noted by FIXMEs in the files), but these deficiencies can be
addressed within the SE infrastructure (thus helping many other passes as well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181927 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCCTRLoops.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.cpp
PCTargetMachine.cpp
|
| 4ef61f2ad4ff509ee05c7051d359009511f81226 |
15-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Cleanup relocation sorting for ELF.
We want the order to be deterministic on all platforms. NAKAMURA Takumi
fixed that in r181864. This patch is just two small cleanups:
* Move the function to the cpp file. It is only passed to array_pod_sort.
* Remove the ppc implementation which is now redundant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181910 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| 9d86f9cc3ab4db75b388c2761bf3dd205f84a6d8 |
15-May-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCISelLowering.h: Escape \@ in comments. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181907 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
|
| 8108a80677a3ab5aff132aea5d340c0beb1ebef7 |
15-May-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181906 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
|
| 9122396a4dea52cf917062782fc2f39c7dc698bb |
15-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Remove need for adjustFixupOffst hack
Now that applyFixup understands differently-sized fixups, we can define
fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte
fixups, applied at an offset of 2 relative to the start of the
instruction text.
This has the benefit that if we actually need to generate a real
relocation record, its address will come out correctly automatically,
without having to fiddle with the offset in adjustFixupOffset.
Tested on both 64-bit and 32-bit PowerPC, using external and
integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181894 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCMCCodeEmitter.cpp
|
| b1cf8de85af10ff3d4ded6431be1cebd6133fd54 |
15-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Correctly handle fixups of other than 4 byte size
The PPCAsmBackend::applyFixup routine handles the case where a
fixup can be resolved within the same object file. However,
this routine is currently hard-coded to assume the size of
any fixup is always exactly 4 bytes.
This is sort-of correct for fixups on instruction text; even
though it only works because several of what really would be
2-byte fixups are presented as 4-byte fixups instead (requiring
another hack in PPCELFObjectWriter::adjustFixupOffset to clean
it up).
However, this assumption breaks down completely for fixups
on data, which legitimately can be of any size (1, 2, 4, or 8).
This patch makes applyFixup aware of fixups of varying sizes,
introducing a new helper routine getFixupKindNumBytes (along
the lines of what the ARM back end does). Note that in order
to handle fixups of size 8, we also need to fix the return type
of adjustFixupValue to uint64_t to avoid truncation.
Tested on both 64-bit and 32-bit PowerPC, using external and
integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181891 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| 5bbdb190412a55436b808cfa59820b1e6cf08db0 |
14-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Implement the PowerPC system call (sc) instruction.
Instruction added at request of Roman Divacky. Tested via asm-parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181821 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrFormats.td
PCInstrInfo.td
|
| ded53bf4dd499f213334400fa870d0c7896d1d0d |
14-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
PPC32: Fix stack collision between FP and CR save areas.
The changes to CR spill handling missed a case for 32-bit PowerPC.
The code in PPCFrameLowering::processFunctionBeforeFrameFinalized()
checks whether CR spill has occurred using a flag in the function
info. This flag is only set by storeRegToStackSlot and
loadRegFromStackSlot. spillCalleeSavedRegisters does not call
storeRegToStackSlot, but instead produces MI directly. Thus we don't
see the CR is spilled when assigning frame offsets, and the CR spill
ends up colliding with some other location (generally the FP slot).
This patch sets the flag in spillCalleeSavedRegisters for PPC32 so
that the CR spill is properly detected and gets its own slot in the
stack frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181800 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 59b078fc56e64b9b2d13521670648034cd870c0f |
13-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix goofy commentary in PPCTargetObjectFile.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181725 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetObjectFile.cpp
|
| 240b9b6078cdf8048945107b4ff7d517729dab96 |
13-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.
This fixes warning messages observed in the oggenc application test in
projects/test-suite. Special handling is needed for the 64-bit
PowerPC SVR4 ABI when a constant is initialized with a pointer to a
function in a shared library. Because a function address is
implemented as the address of a function descriptor, the use of copy
relocations can lead to problems with initialization. GNU ld
therefore replaces copy relocations with dynamic relocations to be
resolved by the dynamic linker. This means the constant cannot reside
in the read-only data section, but instead belongs in .data.rel.ro,
which is designed for constants containing dynamic relocations.
The implementation creates a class PPC64LinuxTargetObjectFile
inheriting from TargetLoweringObjectFileELF, which behaves like its
parent except to place constants of this sort into .data.rel.ro.
The test case is reduced from the oggenc application.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181723 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PCISelLowering.cpp
PCTargetObjectFile.cpp
PCTargetObjectFile.h
|
| 4a971705bc6030dc2e4338b3cd5cffa2e0f88b7b |
13-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the MachineMove class.
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
PCTargetMachine.cpp
|
| d84ccfaf50c7843f31ffc74a8a8e33f779453d6e |
11-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Change getFrameMoves to return a const reference.
To add a frame now there is a dedicated addFrameMove which also takes
care of constructing the move itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 6e53180db120b30f600ac31611a9dd47ef7f4921 |
10-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
|
| fd94f0ab358ea12cf2b17c9628207b3fd11d40b4 |
08-May-2013 |
Roman Divacky <rdivacky@freebsd.org> |
Remove unused isLegalAddressImmediate() method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181452 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| a3967b6844f4be588c724ada3692e734bba65cf1 |
08-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix regression in generating @ha/@l relocs
The patch I committed as revision 167864 introduced a regression that
causes LLVM to no longer generate appropriate relocs for @ha/@l symbol
references (but fail an assertion instead).
This is fixed here by re-enabling support for the VK_PPC_GAS_HA16/
VK_PPC_GAS_LO16 variant kinds (and their Darwin variants) in
PPCELFObjectWriter.cpp.
Tested by running projects/test-suite in -m32 mode with the integrated
assembler forced on. A standalone test case will be committed shortly
as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181450 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| a7f2ce85e5bd8d2826537f50ac510ef9fbe83792 |
08-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix handling of anonymous aggregate parameters for powerpc*-apple-darwin8.
This fixes bug 15821 similarly to the powerpc64-linux fix for bug 14779.
Patch by David Fang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181449 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b45eb9fd275f857788cabb15ef8aabf0ff5907cc |
08-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPCInstrInfo::optimizeCompareInstr should not optimize FP compares
The floating-point record forms on PPC don't set the condition register bits
based on a comparison with zero (like the integer record forms do), but rather
based on the exception status bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181423 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 8a88cadaedcfa3bb020df1d100d67cecaf638f35 |
07-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPCInstrInfo::optimizeCompareInstr
Implement suggestions by Bill Schmidt in post-commit review. No functionality
change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181338 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 7d55b6bb1a4a5220ef973cf7b68ae508859a9b71 |
06-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix memory corruption in AsmParser
As pointed out by Evgeniy Stepanov, assigning a std::string temporary
to a StringRef is not a good idea. Rework MatchRegisterName to avoid
using the .lower routine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181192 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
|
| fcdfd5a7ffa2557753038fcbf421dd518e3fda98 |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Avoid using '$' in generated assembler code
PowerPC assemblers are supposed to support a stand-alone '$' symbol
as an alternative of '.' to refer to the current PC. This does not
work in the LLVM assembler parser yet.
To avoid bootstrap failures when using the LLVM assembler as system
assembler, this patch modifies the assembler source code generated
by LLVM to avoid using '$' (and simply use '.' instead).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181054 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
|
| 8e4ba8f7b19615907e5874b3aa661d52c21fff74 |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add some Book II instructions to AsmParser
This patch adds a couple of Book II instructions (isync, icbi) to the
PowerPC assembler parser. These are needed when bootstrapping clang
with the integrated assembler forced on, because they are used in
inline asm statements in the code base.
The test case adds the full list of Book II storage control instructions,
including associated extended mnemonics. Again, those that are not yet
supported as marked as FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181052 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 16adfdb2e666f46e058b603a8a7aa75758819fd5 |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support extended mnemonics in AsmParser
This patch adds infrastructure to support extended mnemonics in the
PowerPC assembler parser. It adds support specifically for those
extended mnemonics that LLVM will itself generate.
The test case lists *all* extended mnemonics according to the
PowerPC ISA v2.06 Book I, but marks those not yet supported
as FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181051 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/PPCAsmParser.cpp
PCInstrInfo.td
|
| 5e220753ff81ac5cbee874e7c00c76c7fbe0d20a |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add assembler parser
This adds assembler parser support to the PowerPC back end.
The parser will run for any powerpc-*-* and powerpc64-*-* triples,
but was tested only on 64-bit Linux. The supported syntax is
intended to be compatible with the GNU assembler.
The parser does not yet support all PowerPC instructions, but
it does support anything that is generated by LLVM itself.
There is no support for testing restricted instruction sets yet,
i.e. the parser will always accept any instructions it knows,
no matter what feature flags are given.
Instruction operands will be checked for validity and errors
generated. (Error handling in general could still be improved.)
The patch adds a number of test cases to verify instruction
and operand encodings. The tests currently cover all instructions
from the following PowerPC ISA v2.06 Book I facilities:
Branch, Fixed-point, Floating-Point, and Vector.
Note that a number of these instructions are not yet supported
by the back end; they are marked with FIXME.
A number of follow-on check-ins will add extra features. When
they are all included, LLVM passes all tests (including bootstrap)
when using clang -cc1as as the system assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/CMakeLists.txt
smParser/LLVMBuild.txt
smParser/Makefile
smParser/PPCAsmParser.cpp
MakeLists.txt
LVMBuild.txt
akefile
PC.td
PCInstr64Bit.td
PCInstrInfo.td
|
| 5b0ce3570c03919f71cab6ef8ed2312d2b707ca2 |
27-Apr-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make all darwin ppc stubs local.
This fixes pr15763.
Patch by David Fang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180657 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCInstLower.cpp
|
| a3acc2b6cf093571812e7e55d936cf188c695e23 |
26-Apr-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Use RegisterOperand instead of RegisterClass operands
In the default PowerPC assembler syntax, registers are specified simply
by number, so they cannot be distinguished from immediate values (without
looking at the opcode). This means that the default operand matching logic
for the asm parser does not work, and we need to specify custom matchers.
Since those can only be specified with RegisterOperand classes and not
directly on the RegisterClass, all instructions patterns used by the asm
parser need to use a RegisterOperand (instead of a RegisterClass) for
all their register operands.
This patch adds one RegisterOperand for each RegisterClass, using the
same name as the class, just in lower case, and updates all instruction
patterns to use RegisterOperand instead of RegisterClass operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180611 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrInfo.td
|
| 069a4a958323e9912a3c0ce4e5dffd0eec1fc618 |
26-Apr-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Fix encoding of vsubcuw and vsum4sbs instructions
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong sub-opcodes).
Tests will be added together with the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180608 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 0c0a1be9c565bd8908e2cf2ffccd356b3a3d7c2a |
26-Apr-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Fix encoding of stfsu and stfdu instructions
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong sub-opcodes). Note that apparently
the compiler currently never generates pre-inc instructions
for floating point types for some reason ...
Tests will be added together with the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180607 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 1adc97c901e1c42d4f31981a3604d607581c31c3 |
26-Apr-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Fix encoding of rldimi and rldcl instructions
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong operand name in rldimi, wrong form
and sub-opcode for rldcl).
Tests will be added together with the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180606 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.td
|
| 8ade90930863acf94fbb2ccd91acefcf114c1f3e |
26-Apr-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Support PC-relative fixup_ppc_brcond14.
When testing the asm parser, I ran into an error when using a conditional
branch to an external symbol (this doesn't occur in compiler-generated
code) due to missing support in PPCELFObjectWriter::getRelocTypeInner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180605 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| fa799112ddd69cebc6bacb9e24feb1298c9cdfb5 |
23-Apr-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Change commentary for PowerPC Boolean vector contents.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180131 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ed5707baf9be36c0d06c278f589b6c55db8b96c0 |
23-Apr-2013 |
Owen Anderson <resistor@mac.com> |
DAGCombine should not aggressively fold SEXT(VSETCC(...)) into a wider VSETCC without first checking the target's vector boolean contents.
This exposed an issue with PowerPC AltiVec where it appears it was setting the wrong vector boolean contents. The included change
fixes the PowerPC tests, and was OK'd by Hal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180129 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6265d5c91a18b2fb6499eb581c488315880c044d |
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| abe64dc6f7363c7e6170568e382fb06d81d62f51 |
20-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Move PPC getSwappedPredicate for reuse
The getSwappedPredicate function can be used in other places (such as in
improvements to the PPCCTRLoops pass). Instead of trapping it as a static
function in PPCInstrInfo, move it into PPCPredicates with other
predicate-related things.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179926 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCPredicates.cpp
CTargetDesc/PPCPredicates.h
PCInstrInfo.cpp
|
| 2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2 |
20-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
ArrayRefize getMachineNode(). No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 87c1e42be7dadaea7c3e00fb7ccbd77633cea37f |
20-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix PPC optimizeCompareInstr swapped-sub argument handling
When matching a compare with a subtract where the arguments of the compare are
swapped w.r.t. the arguments of the subtract, we need to negate the predicates
(or CR bit indices) of the users. This, however, is not the same as inverting
the predicate (negating LT -> GT, but inverting LT -> GE, for example). The ARM
backend seems to do this correctly, but when I adapted the code for the PPC
backend, I introduced an error in this logic.
Comparison optimization is now enabled again by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179899 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 4029c3feed5c9a5b0793e3da140ecaabef19e3fe |
19-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Disable PPC comparison optimization by default
This seems to cause a stage-2 LLVM compile failure (by crashing TableGen); do
I'm disabling this for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179807 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 860c08cad5b7c1359123bb2b0e74df4b6e48a15c |
19-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement optimizeCompareInstr for PPC
Many PPC instructions have a so-called 'record form' which stores to a specific
condition register the result of comparing the result of the instruction with
zero (always as a signed comparison). For integer operations on PPC64, this is
always a 64-bit comparison.
This implementation is derived from the implementation in the ARM backend;
there are some differences because PPC condition registers are allocatable
virtual registers (although the record forms always use a specific one), and we
look for a matching subtraction instruction after the compare (but before the
first use) in addition to before it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179802 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| df39be6cb4eb44011db3d3e86f8fe463f81ce127 |
17-Apr-2013 |
Peter Collingbourne <peter@pcc.me.uk> |
Add support for subsections to the ELF assembler. Fixes PR8717.
Differential Revision: http://llvm-reviews.chandlerc.com/D598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179725 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 1fb54cfb0a013c8ab664a6e754b34a125fe85254 |
17-Apr-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Mark some more patterns as isCodeGenOnly.
A couple of recently introduced conditional branch patterns
also need to be marked as isCodeGenOnly since they cannot
be handled by the asm parser.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179690 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 00e86ad167e2d151d819ae7b691dadf9e1d9418c |
15-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Mark all PPC comparison instructions as not having side effects
Now that the CR spilling issues have been resolved, we can remove the
unmodeled-side-effect attributes from the comparison instructions (and also
mark them as isCompare). By allowing these, by default, to have unmodeled side
effects, we were hiding problems with CR spilling; but everything seems much
happier now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179502 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36 |
15-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix PPC64 CR spill location for callee-saved registers
This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition
registers, the spill location is specified relative to the stack pointer (SP +
8). However, this is not relative to the SP after the new stack frame is
established, but instead relative to the caller's stack pointer (it is stored
into the linkage area of the parent's stack frame).
So, like with the link register, we don't directly spill the CRs with other
callee-saved registers, but just mark them to be spilled during prologue
generation.
In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179500 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCMachineFunctionInfo.h
|
| 63496f66c5b528a48f8da7714ee3f635f8aadd18 |
14-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Mark all PPC CR registers to be spilled as live-in and tag MFCR appropriately
Leaving MFCR has having unmodeled side effects is not enough to prevent
unwanted instruction reordering post-RA. We could probably apply a stronger
barrier attribute, but there is a better way: Add all (not just the first) CR
to be spilled as live-in to the entry block, and add all CRs to the MFCR
instruction as implicitly killed.
Unfortunately, I don't have a small test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179465 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| b99c995825a49f0da5af40ee1b61269deb8994b5 |
13-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Spill and restore PPC CR registers using the FP when we have one
For functions that need to spill CRs, and have dynamic stack allocations, the
value of the SP during the restore is not what it was during the save, and so
we need to use the FP in these cases (as for all of the other spills and
restores, but the CR restore has a special code path because its reserved slot,
like the link register, is specified directly relative to the adjusted SP).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179457 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 598574695b70627213ea7bc224ee87ccfef44031 |
12-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Remove (broken) nested implicit definition lists
TableGen will not combine nested list 'let' bindings into a single list, and
instead uses only the inner scope. As a result, several instruction definitions
were missing implicit register defs that were in outer scopes. This de-nests
these scopes and makes all instructions have only one let binding which sets
implicit register definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179392 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 81b2fd5819af2d06011d5a2b031e41527d478ba4 |
12-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a comment about the PPC Interpretation64Bit bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179391 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 171a8adf3168aee2f739f91c1800e9025892c7b5 |
12-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC instruction record forms and associated query functions
This is prep. work for the implementation of optimizeCompare. Many PPC
instructions have 'record' forms (in almost all cases, this means that the RC
bit is set) that cause the result of the instruction to be compared with zero,
and the result of that comparison saved in a predefined condition register. In
order to add the record forms of the instructions without too much
copy-and-paste, the relevant functions have been refactored into multiclasses
which define both the record and normal forms.
Also, two TableGen-generated mapping functions have been added which allow
querying the instruction code for the record form given the normal form (and
vice versa).
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179356 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.cpp
PCInstrInfo.td
|
| 4b040294816e49413c739825d801042bc76171a7 |
11-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Make PPCInstrInfo::isPredicated always return false
Because of how predication in implemented on PPC (only for branches), I think
that this is the right thing to do. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179252 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| da47e17a6f58bb4dae22d3e79c69fcb1d254ba44 |
10-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Don't predicate a diamond with two counter decrements
I've not seen this happen in practice, and probably can't until we start
allowing decrement-counter-based conditional branches to be double predicated,
but just in case, don't allow predication of a diamond in which both sides have
ctr-defining branches. Even though the branching behavior of these can be
predicated, the counter-decrementing behavior cannot be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179199 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 4e3172867d0c1acfda9d2cc88dfad23634e649eb |
10-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPCInstrInfo::DefinesPredicate
Implement suggestions made by Bill Schmidt in post-commit review. Thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179162 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 90dd7fd167b6d09e4a7f37e35dcbfdc492546a79 |
10-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Prep for if conversion of bctr[l]
This adds in-principle support for if-converting the bctr[l] instructions.
These instructions are used for indirect branching. It seems, however, that the
current if converter will never actually predicate these. To do so, it would
need the ability to hoist a few setup insts. out of the conditionally-executed
block. For example, code like this:
void foo(int a, int (*bar)()) { if (a != 0) bar(); }
becomes:
...
beq 0, .LBB0_2
std 2, 40(1)
mr 12, 4
ld 3, 0(4)
ld 11, 16(4)
ld 2, 8(4)
mtctr 3
bctrl
ld 2, 40(1)
.LBB0_2:
...
and it would be safe to do all of this unconditionally with a predicated
beqctrl instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179156 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.cpp
PCInstrInfo.td
|
| 7eb0d8148e1210d9e31ab471477de47b53bab117 |
10-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Allow PPC B and BLR to be if-converted into some predicated forms
This enables us to form predicated branches (which are the same conditional
branches we had before) and also a larger set of predicated returns (including
instructions like bdnzlr which is a conditional return and loop-counter
decrement all in one).
At the moment, if conversion does not capture all possible opportunities. A
simple example is provided in early-ret2.ll, where if conversion forms one
predicated return, and then the PPCEarlyReturn pass picks up the other one. So,
at least for now, we'll keep both mechanisms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179134 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.cpp
PCInstrInfo.h
PCInstrInfo.td
PCTargetMachine.cpp
|
| 13049aef8ad86795e94006dea0e097a8add85665 |
09-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPCEarlyReturn
Some general cleanup and only scan the end of a BB for branches (once we're
done with the terminators and debug values, then there should not be any other
branches). These address post-commit review suggestions by Bill Schmidt.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179112 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| f6f8198d85f278ff03aaf32c9db6ae0b3826395c |
09-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use virtual base registers on PPC
On PowerPC, non-vector loads and stores have r+i forms; however, in functions
with large stack frames these were not being used to access slots far from the
stack pointer because such slots were out of range for the signed 16-bit
immediate offset field. This increases register pressure because we need a
separate register for each offset (when the r+r form is used). By enabling
virtual base registers, we can deal with large stack frames without unduly
increasing register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179105 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 5ee67e8e76dfcaffa5e776ef3d5eeb80807a627b |
08-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Generate PPC early conditional returns
PowerPC has a conditional branch to the link register (return) instruction: BCLR.
This should be used any time when we'd otherwise have a conditional branch to a
return. This adds a small pass, PPCEarlyReturn, which runs just prior to the
branch selection pass (and, importantly, after block placement) to generate
these conditional returns when possible. It will also eliminate unconditional
branches to returns (these happen rarely; most of the time these have already
been tail duplicated by the time PPCEarlyReturn is invoked). This is a nice
optimization for small functions that do not maintain a stack frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179026 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCInstrFormats.td
PCInstrInfo.cpp
PCInstrInfo.td
PCTargetMachine.cpp
EADME.txt
|
| 59889f7f496f549965764820a0150c4068c02f5b |
08-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup and improve PPC fsel generation
First, we should not cheat: fsel-based lowering of select_cc is a
finite-math-only optimization (the ISA manual, section F.3 of v2.06, makes
this clear, as does a note in our own README).
This also adds fsel-based lowering of EQ and NE condition codes. As it turned
out, fsel generation was covered by a grand total of zero regression test
cases. I've added some test cases to cover the existing behavior (which is now
finite-math only), as well as the new EQ cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179000 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 946a811ef12188f4a129f4f98759fc9f7ba33d61 |
07-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC rotate instructions don't have unmodeled side effcts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178982 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| f0e3ca012bc7dd6b95c091a7f5f147794983cf97 |
07-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Most PPC M[TF]CR instructions do not have side effects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178978 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 3aea7cb7b2c54071fc273a0c3a97850bd14de5ac |
07-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC pre-increment load instructions do not have side effects
A few were missed in r178972.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178973 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| fa1d102a052e0375c954d9a35b3a687f81194f7a |
07-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC pre-increment load instructions do not have side effects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178972 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| aecbe2426825463c183a036da4bfae621e8ec080 |
07-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC MCRF instruction does not have side effects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178971 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| fa1cac2a1e37f9925543894b0a4ae5db080a862a |
07-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC FMR instruction does not have side effects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178970 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 839b9096538f790a2bb060547df24703807cb83b |
06-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement PPCInstrInfo::FoldImmediate
There are certain PPC instructions into which we can fold a zero immediate
operand. We can detect such cases by looking at the register class required
by the using operand (so long as it is not otherwise constrained).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178961 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
PCRegisterInfo.cpp
|
| 012ffd56059576d4a0ee523f673b3190b1f03311 |
06-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC ISEL is a select and never has side effects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178960 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| ff56d1a2011f239e114267c13302ea26db4f8046 |
06-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Enable early if conversion on PPC
On cores for which we know the misprediction penalty, and we have
the isel instruction, we can profitably perform early if conversion.
This enables us to replace some small branch sequences with selects
and avoid the potential stalls from mispredicting the branches.
Enabling this feature required implementing canInsertSelect and
insertSelect in PPCInstrInfo; isel code in PPCISelLowering was
refactored to use these functions as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178926 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.cpp
PCInstrInfo.h
PCTargetMachine.cpp
|
| de80951ae9bb86ab6b4183f0d482d426c02ab708 |
06-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Correct the PPC A2 misprediction penalty
The manual states that there is a minimum of 13 cycles from when the
mispredicted branch is issued to when the correct branch target is
issued.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178925 91177308-0d34-0410-b5e6-96231b3b80d8
PCScheduleA2.td
|
| 1abaf907b6aff6e468cb838fa40e0ec6cc5ece24 |
05-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a SchedMachineModel for the PPC G5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178850 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCScheduleG5.td
|
| 575e9229bd2053e6887ec4253f29b570d90d80c9 |
05-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a SchedMachineModel for the PPC A2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178848 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCScheduleA2.td
|
| 6bf4f676413b8f7d97aaff289997aab344180957 |
05-Apr-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
CostModel: Add parameter to instruction cost to further classify operand values
On certain architectures we can support efficient vectorized version of
instructions if the operand value is uniform (splat) or a constant scalar.
An example of this is a vector shift on x86.
We can efficiently support
for (i = 0 ; i < ; i += 4)
w[0:3] = v[0:3] << <2, 2, 2, 2>
but not
for (i = 0; i < ; i += 4)
w[0:3] = v[0:3] << x[0:3]
This patch adds a parameter to getArithmeticInstrCost to further qualify operand
values as uniform or uniform constant.
Targets can then choose to return a different cost for instructions with such
operand values.
A follow-up commit will test this feature on x86.
radar://13576547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178807 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetTransformInfo.cpp
|
| caeeb1865043d5410b5b0356694fb1228a18ec78 |
05-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Rename the current PPC BCL definition to BCLalways
BCL is normally a conditional branch-and-link instruction, but has
an unconditional form (which is used in the SjLj code, for example).
To make clear that this BCL instruction definition is specifically
the special unconditional form (which does not meaningfully take
a condition-register input), rename it to BCLalways.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178803 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelLowering.cpp
PCInstrInfo.td
|
| 7530a9f7d1e62b28e04d771158613c2954cc8d8c |
05-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Improve code generation for mixed-precision reciprocal sqrt
The DAGCombine logic that recognized a/sqrt(b) and transformed it into
a multiplication by the reciprocal sqrt did not handle cases where the
sqrt and the division were separated by an fpext or fptrunc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178801 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 63c32a7a9fd30f67bc623c818f434e742d43c085 |
03-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC reciprocal-estimate functionality
Incorporating review feedback from Bill Schmidt on r178617. No functionality
change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178672 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 110e323b619c64e63f8d7814f9ad9a455e6dbf59 |
03-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Enable FRES and FRSQRTE on the default PPC64 description
I discussed this with Bill Schmidt on IRC, and it was decided that this is a
safe and reasonable default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178659 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| 7d52a41e320b8b22a9dde2481df2e5157e950d79 |
03-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Add a FIXME regarding the non-working fma+fneg Altivec pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178658 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| d8f8f5847631aeff4714d42ae762c2c2266dcb23 |
03-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove some obsolete PowerPC/README entries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178657 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 6b9d52eefd3e7d57618c0b7e84f0297298a5a65f |
03-Apr-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
More direct types in PowerPC AltiVec intrinsics.
This patch follows up on work done by Bill Schmidt in r178277,
and replaces most of the remaining uses of VRRC in ISEL DAG patterns.
The resulting .inc files are identical except for comments, so
no change in code generation is expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178656 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| cd7a1558edd0bdae770c57b82b32291e54e014b2 |
03-Apr-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.
For this we need to use a libcall. Previously LLVM didn't implement
libcall support for frem, so I've added it in the usual
straightforward manner. A test case from the bug report is included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178639 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2d8f62017d6223444564f79fc8044cc35d9d5678 |
03-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove some unsupported-feature comments from PPC.td
These refer to the reciprocal estimate support recently committed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178618 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| 827307b95fa909e35a3ddef612f9f50ffcf0963a |
03-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use PPC reciprocal estimates with Newton iteration in fast-math mode
When unsafe FP math operations are enabled, we can use the fre[s] and
frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together
with some Newton iteration, in order to quickly generate floating-point
division and sqrt results. All of these instructions are separately optional,
and so each has its own feature flag (except for the Altivec instructions,
which are covered under the existing Altivec flag). Doing this is not only
faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these
computations to be pipelined with other computations in order to hide their
overall latency.
I've also added a couple of missing fnmsub patterns which turned out to be
missing (but are necessary for good code generation of the Newton iterations).
Altivec needs a similar fix, but that will probably be more complicated because
fneg is expanded for Altivec's v4f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178617 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
PCInstrInfo.td
PCSubtarget.cpp
PCSubtarget.h
|
| debf7d345aa297ebedf2d3b1db234feb44c71483 |
02-Apr-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR15630: Replace faulty stdcx. with stwcx.
When doing a partword atomic operation, a lwarx was being paired with
a stdcx. instead of a stwcx. when compiling for a 64-bit target. The
target has nothing to do with it in this case; we always need a stwcx.
Thanks to Kai Nacke for reporting the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178559 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2a401959b9d5d7824e4296683e2467e5aafe01b7 |
02-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix typo in PPCISelLowering
Thanks to Bill Schmidt for finding this in review of r178480.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178521 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a1646ceb9a5da080607e503c8bd36241aa465613 |
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix a bad assert in PPCTargetLowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178489 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 46479197843ecb651adc9417c49bbd1b00acfcb6 |
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add more PPC floating-point conversion instructions
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
PCSubtarget.cpp
PCSubtarget.h
|
| a1f4290ac94f34173e3561c717390de07dccc646 |
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use ImmToIdxMap.count in PPCRegisterInfo
Code improvement suggested by Jakob (in review of r178450). No functionality
change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178473 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 1fce88313e4d46fdd432b68f7c54fde972c0b526 |
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC popcntw instruction
The popcntw instruction is available whenever the popcntd instruction is
available, and performs a separate popcnt on the lower and upper 32-bits.
Ignoring the high-order count, this can be used for the 32-bit input case
(saving on the explicit zero extension otherwise required to use popcntd).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178470 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstr64Bit.td
|
| f170cc9b2eb98efee40ee22cff6bcf401c209b00 |
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Treat PPCISD::STFIWX like the memory opcode that it is
PPCISD::STFIWX is really a memory opcode, and so it should come after
FIRST_TARGET_MEMORY_OPCODE, and we should use DAG.getMemIntrinsicNode to create
nodes using it.
No functionality change intended (although there could be optimization benefits
from preserving the MMO information).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178468 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 4345e8040f14781d20fd5fa2f7ee3c75fa611fa1 |
31-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup ImmToIdxMap and noImmForm in PPCRegisterInfo
ImmToIdxMap should be a DenseMap (not a std::map) because there
is no ordering requirement. Also, we don't need a separate list
of instructions for noImmForm in eliminateFrameIndex, because this
list is essentially the complement of the keys in ImmToIdxMap.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178450 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 8049ab15e4b638a07d6f230329945c2310eca27b |
31-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC lfiwax instruction
This instruction is available on modern PPC64 CPUs, and is now used
to improve the SINT_TO_FP lowering (by eliminating the need for the
separate sign extension instruction and decreasing the amount of
needed stack space).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178446 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
PCRegisterInfo.cpp
PCSubtarget.cpp
PCSubtarget.h
|
| 9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405 |
31-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC(64) i32 -> float/double conversion
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled
because it relied on broken EXTSW_32/STD_32 instruction definitions. The
original intent had been to enable these 64-bit instructions to be used on CPUs
that support them even in 32-bit mode. Unfortunately, this form of lying to
the infrastructure was buggy (as explained in the FIXME comment) and had
therefore been disabled.
This re-enables this functionality, using regular DAG nodes, but only when
compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead)
are removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 0882fd6c4f90f1cbaa4bb6f6ceec289428cca734 |
29-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement FRINT lowering on PPC using frin
Like nearbyint, rint can be implemented on PPC using the frin instruction. The
complication comes from the fact that rint needs to set the FE_INEXACT flag
when the result does not equal the input value (and frin does not do that). As
a result, we use a custom inserter which, after the rounding, compares the
rounded value with the original, and if they differ, explicitly sets the XX bit
in the FPSCR register (which corresponds to FE_INEXACT).
Once LLVM has better modeling of the floating-point environment we should be
able to (often) eliminate this extra complexity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178362 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| 74a4533a4290b7c6f1fe04a30ca13ec25c529e0a |
29-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f5d5c434606161fb017a34cb656fa4aa5a3e076b |
29-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC FP rounding instructions fri[mnpz]
These instructions are available on the P5x (and later) and on the A2. They
implement the standard floating-point rounding operations (floor, trunc, etc.).
One caveat: frin (round to nearest) does not implement "ties to even", and so
is only enabled in fast-math mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178337 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCISelLowering.cpp
PCInstrInfo.td
PCSubtarget.cpp
PCSubtarget.h
|
| 2544f221c5f4047d7bdf10ec911c86a1d8be4a29 |
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Only enable 64-bit bswap DAG combines for PPC64
Compiling in 32-bit mode on a P7 would assert after 64-bit DAG combines were
added for bswap with load/store. This is because these combines are really only
valid in 64-bit mode, regardless of the CPU (and this was not being checked).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178286 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b52980be0788a907c98fc08de090ad61aef86716 |
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix bad indentation in r178276
Thanks to Bill Schmidt for pointing this out!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178280 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 53774a821d21f954c1ba0eaa493d4142b68fbfcd |
28-Mar-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Use direct types in most PowerPC Altivec instructions and patterns.
This follows up Ulrich Weigand's work in PPCInstrInfo.td and
PPCInstr64Bit.td by doing the corresponding work for most of the
Altivec patterns. I have not been able to do anything for the
following classes of instructions:
(1) Vector logicals. These don't have corresponding intrinsics and
don't have a single obvious vector type. So far as I can tell I need
to leave these as VRRC. Affected instructions are: VAND, VANDC,
VNOR, VOR, VXOR, V_SET0.
(2) Instructions that make use of vector shuffle. The selection code
promotes all shuffles to v16i8, so any pattern that matches on a
shuffle is constrained. I haven't found any way to make the patterns
match on their natural types, so I plan to leave these as VRRC.
Affected instructions are: VMRG*, VSPLTB, VSPLTH, VSPLTW, VPKUHUM,
VPKUWUM.
No change in behavior is anticipated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178277 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| efdd4673d6e78f3d406c5d1f44316aef8a5a9a48 |
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC64 ldbrx/stdbrx instructions
These are 64-bit load/store with byte-swap, and available on the P7 and the A2.
Like the similar instructions for 16- and 32-bit words, these are matched in the
target DAG-combine phase against load/store-bswap pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178276 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
PCSubtarget.cpp
PCSubtarget.h
|
| c53ab4d77f4b3d2905cf9ad625c28ff6b1c04aff |
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC64 popcntd instruction
PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and
tell TTI about it so that popcount-loop recognition will know about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178233 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCISelLowering.cpp
PCInstr64Bit.td
PCSubtarget.cpp
PCSubtarget.h
PCTargetTransformInfo.cpp
|
| d957f957eee12cf26a7160e6015f0a7c2629904f |
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC CR-spill kill flags and 32- vs. 64-bit instructions
There were a few places where kill flags were not being set correctly, and
where 32-bit instruction variants were being used with 64-bit registers. After
r178180, this code was being triggered causing llc to assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178220 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCRegisterInfo.cpp
|
| d01efc737aad480eaaa1316b05b7165ce7c04c96 |
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix typo in PPCInstr64Bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178219 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| f25f93b685a6cb91d8370ae5dc1436a863a670d2 |
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Resynchronize isLoadFromStackSlot with LoadRegFromStackSlot (and stores) in PPCInstrInfo
These functions should have the same list of load/store instructions. Now that
all load/store forms have been normalized (to single instructions or pseudos)
they can be resynchronized.
Found by inspection, although hopefully this will improve optimization. I've
also added some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178180 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| e915047fed99221afb8c540d8a7e81038a6483f1 |
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix typo (common to both X86 and PPC)
Thanks to Bill Schmidt for pointing this out during code review!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178170 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| fc8058696820332cfd3d382f6534edc96420a0b1 |
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove more dead LR-as-GPR PPC code
I had removed similar code a few days ago, but somehow missed this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178169 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| e77918c355610ef2c68c3b666b3a3dd0085e1766 |
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove "gpr0 allocation" from the PPC README TODO list
As Chris pointed out, post r178123, this is now done!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178165 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 32e12df253de7993f5a9bb89668d98ec0454f623 |
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Print PPC ZERO as 0 (not r0) even on Darwin
It seems that the Darwin PPC assembler requires r0 to be written as 0 when it
means 0 (at least in lwarx/stwcx.). Fixes PR15605.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178142 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 240b7f3324da70937d4fe6d0bd7278ae82849114 |
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Allocate r0 on PPC
The R0 register can now be allocated because instructions
that cannot use R0 as a GPR have been appropriately marked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178123 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 6375e1b87b089093fecdb09f609251e91d1c2c4f |
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use the PPC no-r0 class on the TOC LD pseudos
The register parameter in these instructions becomes the base register in an
r+i ld instruction (and, thus, cannot be r0).
This is not yet testable because we don't yet allocate r0 (and even then any
test would be very fragile).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178121 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| ab42ec258627376e49f84141dd7be455b1e4ab3d |
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Apply the no-r0 register class to the PPC SELECT_CC_I[4|8] pseudos
Either operand of these pseudo instructions can be transformed into the first
operand of an isel instruction (and this operand cannot be r0).
This is not yet testable because we don't yet allocate r0 (and even when we do,
any test would be very fragile).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178119 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 56d926ac14406ef87d34fbf77632c26d8e789818 |
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructions
Like the addi/addis instructions themselves, these pseudo instructions also
cannot have r0 as their register parameter (because it will be interpreted as
the value 0).
This is not yet testable because we don't yet allocate r0 (and even when we do,
any regression test would be very fragile because it would depend on the
register allocator heuristics).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178118 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 37ef805818e32531c2c3a454fee33f06f363f9c2 |
27-Mar-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Remove the link register from the GPR classes on PowerPC.
Some implementation detail in the forgotten past required the link
register to be placed in the GPRC and G8RC register classes. This is
just wrong on the face of it, and causes several extra intersection
register classes to be generated. I found this was having evil
effects on instruction scheduling, by causing the wrong register class
to be consulted for register pressure decisions.
No code generation changes are expected, other than some minor changes
in instruction order. Seven tests in the test bucket required minor
tweaks to adjust to the new normal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178114 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| b7e11e400dabced046e7ec53a66926716563bb36 |
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Don't spill PPC VRSAVE on non-Darwin (even in SjLj)
As Bill Schmidt pointed out to me, only on Darwin do we need to spill/restore
VRSAVE in the SjLj code. For non-Darwin, don't spill/restore VRSAVE (and I've
added some asserts to make sure that we're not).
As it turns out, we're not currently handling the Darwin case correctly (I've
added a FIXME in the test case). I've tried adding various implied register
definitions/uses to force the spill without success, so I'll need to address
this later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178096 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 1a0034c74a0a8562199f9e6a00feb0a80619b886 |
26-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Restore real bit lengths on PPC register numbers
As suggested by Bill Schmidt (in reviewing r178067), use the real register
number bit lengths (which is self-documenting, and prevents using illegal
numbers), and set only the relevant bits in HWEncoding (which defaults to 0).
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178077 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| aa6047d23d8ed55abd8545f5cbe82cd13cbd756a |
26-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Use HWEncoding and TRI->getEncodingValue
As pointed out by Jakob, we don't need to maintain a separate
register-numbering table. Instead we should let TableGen generate the table for
us from the information (already present) in PPCRegisterInfo.td.
TRI->getEncodingValue is now used to access register-encoding values.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178067 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
CTargetDesc/PPCBaseInfo.h
CTargetDesc/PPCMCCodeEmitter.cpp
PC.h
PCCodeEmitter.cpp
PCFrameLowering.cpp
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| 01f99d29c3010f2891e5edb78182216214017063 |
26-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use multiple virtual registers in PPC CR spilling
Now that the register scavenger can support multiple spill slots, and PEI can
use virtual-register-based scavenging for multiple simultaneous registers, we
can use a virtual register for the transfer register in the CR spilling code.
This should eliminate the last place (outside of the prologue/epilogue) where
we depend on the unconditional availability of the r0 register. We will soon be
able to allocate it (in a somewhat restricted sense) as a GPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178060 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCRegisterInfo.cpp
|
| 3b196f20fbd24b2c178a51e2473437655dc7066a |
26-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Update PPCRegisterInfo's use of virtual registers to be SSA
PPC's use of PEI's virtual-register-based scavenging functionality had
redefined the virtual registers (it was non-SSA). Now that PEI supports
dealing with instructions with multiple virtual registers, this can be
cleanup up to use multiple virtual registers and keep SSA form.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178059 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| d6f5a581ab968a2618b0c5a8472ea2ab37797916 |
26-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove default case from fully covered switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178025 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCPredicates.cpp
|
| 3d386421e0d8756a4665d00fcfa66a99990f0f91 |
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Mark patterns as isCodeGenOnly.
There remain a number of patterns that cannot (and should not)
be handled by the asm parser, in particular all the Pseudo patterns.
This commit marks those patterns as isCodeGenOnly.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178008 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrFormats.td
PCInstrInfo.td
|
| 65e90c036472380bba160c349412f37128608e1c |
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Simplify handling of fixups.
MCTargetDesc/PPCMCCodeEmitter.cpp current has code like:
if (isSVR4ABI() && is64BitMode())
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_toc16));
else
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_lo16));
This is a problem for the asm parser, since it requires knowledge of
the ABI / 64-bit mode to be set up. However, more fundamentally,
at this point we shouldn't make such distinctions anyway; in an assembler
file, it always ought to be possible to e.g. generate TOC relocations even
when the main ABI is one that doesn't use TOC.
Fortunately, this is actually completely unnecessary; that code was added
to decide whether to generate TOC relocations, but that information is in
fact already encoded in the VariantKind of the underlying symbol.
This commit therefore merges those fixup types into one, and then decides
which relocation to use based on the VariantKind.
No changes in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178007 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCFixupKinds.h
CTargetDesc/PPCMCCodeEmitter.cpp
|
| 7d35d3f432cb59d3d1c0884af3023de9b5cb10b1 |
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Simplify FADD in round-to-zero mode.
As part of the the sequence generated to implement long double -> int
conversions, we need to perform an FADD in round-to-zero mode. This is
problematical since the FPSCR is not at all modeled at the SelectionDAG
level, and thus there is a risk of getting floating point instructions
generated out of sequence with the instructions to modify FPSCR.
The current code handles this by somewhat "special" patterns that in part
have dummy operands, and/or duplicate existing instructions, making them
awkward to handle in the asm parser.
This commit changes this by leaving the "FADD in round-to-zero mode"
as an atomic operation on the SelectionDAG level, and only split it up into
real instructions at the MI level (via custom inserter). Since at *this*
level the FPSCR *is* modeled (via the "RM" hard register), much of the
"special" stuff can just go away, and the resulting patterns can be used by
the asm parser.
No significant change in generated code expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178006 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrFormats.td
PCInstrInfo.td
|
| d67768db809d6b1cfe6f7c484b3719a6103286ea |
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Remove LDrs pattern.
The LDrs pattern is a duplicate of LD, except that it accepts memory
addresses where the displacement is a symbolLo64. An operand type
"memrs" is defined for just that purpose.
However, this wouldn't be necessary if the default "memrix" operand
type were to simply accept 64-bit symbolic addresses directly.
The only problem with that is that it uses "symbolLo", which is
hardcoded to 32-bit.
To fix this, this commit changes "memri" and "memrix" to use new
operand types for the memory displacement, which allow iPTR
instead of i32. This will also make address parsing easier to
implment in the asm parser.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178005 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 2b0850b8305380244ec98e1b1c89aaf57adf3b09 |
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Remove ADDIL patterns.
The ADDI/ADDI8 patterns are currently duplicated into ADDIL/ADDI8L,
which describe the same instruction, except that they accept a
symbolLo[64] operand instead of a s16imm[64] operand.
This duplication confuses the asm parser, and it actually not really
needed, since symbolLo[64] already accepts immediate operands anyway.
So this commit removes the duplicate patterns.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178004 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| a01c7dbaabae7cf569410bedd71361b75f65875f |
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Use CCBITRC operand for ISEL patterns.
This commit changes the ISEL patterns to use a CCBITRC operand
instead of a "pred" operand. This matches the actual instruction
text more directly, and simplifies use of ISEL with the asm parser.
In addition, this change allows some simplification of handling
the "pred" operand, as this is now only used by BCC.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178003 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.td
|
| 3b2552933642c19ce5e8836d82c26c562910e239 |
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Simplify BLR pattern.
The BLR pattern cannot be recognized by the asm parser in its current form.
This complexity is due to an apparent attempt to enable conditional BLR
variants. However, none of those can ever be generated by current code;
the pattern is only ever created using the default "pred" operand.
To simplify the pattern and allow it to be recognized by the parser,
this commit removes those attempts at conditional BLR support.
When we later come back to actually add real conditional BLR, this
should probably be done via a fully generic conditional branch pattern.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178002 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
CTargetDesc/PPCPredicates.h
PCInstrInfo.td
|
| e8680da874631c0531872c83d6643e05bbefebd1 |
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Move some 64-bit branch patterns.
In PPCInstr64Bit.td, some branch patterns appear in a different sequence
than the corresponding 32-bit patterns in PPCInstrInfo.td.
To simplify future changes that affect both files, this commit moves
those patterns to rearrange them into a similar sequence.
No effect on generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178001 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 5b390e4cd8838bad351364e65d20c292fae6bf23 |
25-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Use direct types in PowerPC instruction patterns.
This commit updates the PowerPC back-end (PPCInstrInfo.td and
PPCInstr64Bit.td) to use types instead of register classes in
instruction patterns, along the lines of Jakob Stoklund Olesen's
changes in r177835 for Sparc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177890 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 1492a4e5185d963cb79786311b882153fce6718a |
25-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Use direct types in PowerPC Pat patterns.
This commit updates the PowerPC back-end (PPCInstrInfo.td and
PPCInstr64Bit.td) to use types instead of register classes in
Pat patterns, along the lines of Jakob Stoklund Olesen's
changes in r177829 for Sparc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177889 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 526d6c451bf7cbffdb6976f551c42607680c1e3a |
23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC ZERO register needs a register number of 0.
In order for the new ZERO register to be used with MC, etc. we need to specify
its register number (0).
Thanks to Kai for reporting the problem!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177833 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCBaseInfo.h
|
| 3f2c047f32c9b488d9c49bb2dc87b979530dab3f |
23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Note in PPCFunctionInfo VRSAVE spills
In preparation for using the new register scavenger capability for providing
more than one register simultaneously, specifically note functions that have
spilled VRSAVE (currently, this can happen only in functions that use the
setjmp intrinsic). As with CR spilling, such functions will need to provide two
emergency spill slots to the scavenger.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177832 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCInstrInfo.cpp
PCInstrInfo.h
PCMachineFunctionInfo.h
|
| 7d35f74a5d5fafc66eafd945273153bf060a8bf4 |
23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
MCize the bcl instruction in PPCAsmPrinter
I recently added a BCL instruction definition as part of implementing SjLj
support. This can also be used to MCize bcl emission in the asm printer.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177830 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 02327fefd8a4b7d9f4dc90e066ba70b1d6253c27 |
23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup some unused reg. scavenger parameters in PPCRegisterInfo
These spilling functions will eventually make use of the register scavenger,
however, they'll do so by taking advantage of PEI's virtual-register-based
delayed scavenging mechanism. As a result, these function parameters will not
be used, and can be removed.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177827 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 7257fda1b3b047f6fd46df8a9999580fcfafbfae |
23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove dead PPC LR spilling code
The LR register is unconditionally reserved, and its spilling and restoration
is handled by the prologue/epilogue code. As a result, it is never explicitly
spilled by the register allocator.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177823 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| dc3beb90178fc316f63790812b22201884eaa017 |
23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Allow the register scavenger to spill multiple registers
This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.
To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.
In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 86765fbe170198e7bb40fd8499d1354f4c786f60 |
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Remove ABI-duplicated call instruction patterns.
We currently have a duplicated set of call instruction patterns depending
on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the
different ABIs will result in different instruction sequences, the actual
instructions themselves ought to be independent of the ABI. And in fact it
turns out that the only nontrivial difference between the two sets of
patterns is that in the PPC64 Linux ABI, the instruction used for indirect
calls is marked to take X11 as extra input register (which is indeed used
only with that ABI to hold an incoming environment pointer for nested
functions). However, this does not need to be hard-coded at the .td
pattern level; instead, the C++ code expanding calls can simply add that
use, just like it adds uses for argument registers anyway.
No change in generated code expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177735 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCCodeEmitter.cpp
PCAsmPrinter.cpp
PCHazardRecognizers.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.cpp
PCInstrInfo.td
|
| 89ec847ec79f422527dce0d5321be5526c84bb71 |
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Rename memrr ptrreg and offreg components.
Currently, the sub-operand of a memrr address that corresponds to what
hardware considers the base register is called "offreg", while the
sub-operand that corresponds to the offset is called "ptrreg".
To avoid confusion, this patch simply swaps the named of those two
sub-operands and updates all uses. No functional change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177734 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 881a7154b9f9b85f6a8515e282cacdfc9df156cf |
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix swapped BasePtr and Offset in pre-inc memory addresses.
PPCTargetLowering::getPreIndexedAddressParts currently provides
the base part of a memory address in the offset result, and the
offset part in the base result. That swap is then undone again
when an MI instruction is generated (in PPCDAGToDAGISel::Select
for loads, and using .md Pat patterns for stores).
This patch reverts this double swap, to make common code and
back-end be in sync as to which part of the address is base
and which is offset.
To avoid performance regressions in certain cases, target code
now checks whether the choice of base register would be rejected
for pre-inc accesses by common code, and attempts to swap base
and offset again in such cases. (Overall, this means that now
pre-ice accesses are generated *more* frequently than before.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177733 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 0301e79a1af665422f205fd367cdbd8e6164f324 |
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Tighten iaddroff ComplexPattern.
The iaddroff ComplexPattern is supposed to recognize displacement
expressions that have been processed by a SelectAddressRegImm,
which means it needs to accept TargetConstant and TargetGlobalAddress
nodes. Currently, it erroneously also accepts some other nodes,
in particular Constant and PPCISD::Lo.
While this problem is currently latent, it would cause wrong-code
bugs with a follow-on patch I'm about to commit, so this patch
tightens the ComplexPattern. The equivalent change is made in
PPCDAGToDAGISel::Select, where pre-inc load patterns are handled
(as opposed to store patterns, the loads are handled in C++ code
without making use of the .td ComplexPattern).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177732 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| cff0faa16a7d03951fba0aa279a2c8441c5718f8 |
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Remove the xaddroff ComplexPattern.
The xaddroff pattern is currently (mistakenly) used to recognize
the *base* register in pre-inc store patterns. This patch replaces
those uses by ptr_rc_nor0 (as is elsewhere done to match the base
register of an address), and removes the now unused ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177731 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 7697370adff8983e2a3de493362f0d8c9f9b0e17 |
22-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register class
As Jakob pointed out in his review of r177423, having a shared ZERO
register between the 32- and 64-bit register classes causes this
odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended,
this adds a ZERO8 register which differentiates the 32- and 64-bit
zeros.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177683 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| 3ea1b064a0b9c3d161b0f77a9e957970f98907ab |
22-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix a register-class comparison bug in PPCCTRLoops
Thanks to Jakob for isolating the underlying problem from the
test case in r177423. The original commit had introduced
asymmetric copy operations, but these turned out to be a work-around
to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177679 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
PCInstr64Bit.td
PCInstrInfo.cpp
|
| 7ee74a663a3b4d4ee6b55d23362f347ed1d390c2 |
21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement builtin_{setjmp/longjmp} on PPC
This implements SJLJ lowering on PPC, making the Clang functions
__builtin_{setjmp/longjmp} functional on PPC platforms. The implementation
strategy is similar to that on X86, with the exception that a branch-and-link
variant is used to get the right jump address. Credit goes to Bill Schmidt for
suggesting the use of the unconditional bcl form (instead of the regular bl
instruction) to limit return-address-cache pollution.
Benchmarking the speed at -O3 of:
static jmp_buf env_sigill;
void foo() {
__builtin_longjmp(env_sigill,1);
}
main() {
...
for (int i = 0; i < c; ++i) {
if (__builtin_setjmp(env_sigill)) {
goto done;
} else {
foo();
}
done:;
}
...
}
vs. the same code using the libc setjmp/longjmp functions on a P7 shows that
this builtin implementation is ~4x faster with Altivec enabled and ~7.25x
faster with Altivec disabled. This comparison is somewhat unfair because the
libc version must also save/restore the VSX registers which we don't yet
support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177666 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 10f7f2a222d0e83dc0c33ad506a7686190c2f7a2 |
21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add support for spilling VRSAVE on PPC
Although there is only one Altivec VRSAVE register, it is a member of
a register class, and we need the ability to spill it. Because this
register is normally callee-preserved and handled by special code this
has never before been necessary. However, this capability will be required by
a forthcoming commit adding SjLj support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177654 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6 |
21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Correct PPC FRAMEADDR lowering using a pseudo-register
The old code used to lower FRAMEADDR tried to replicate the logic in the real
frame-lowering code that determines whether or not the frame pointer (r31) will
be used. When it seemed as through the frame pointer would not be used, the
stack pointer (r1) was used instead. Unfortunately, because the stack size is
not yet known, this does not work. Instead, this change introduces new
always-reserved pseudo-registers (FP and FP8) that are replaced during prologue
insertion with the real frame-pointer register (either r1 or r31).
It is important that this intrinsic always return a valid frame address because
it is used by Clang to store the frame address as part of code generation for
__builtin_setjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177653 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCFrameLowering.h
PCISelLowering.cpp
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| dff4d1522a3a14df3c40c33421e24f59633da67b |
19-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Add missing mayLoad flag to LHAUX8 and LWAUX.
All pre-increment load patterns need to set the mayLoad flag (since
they don't provide a DAG pattern).
This was missing for LHAUX8 and LWAUX, which is added by this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177431 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 8353d1e0e5fd23bb9b6c11acda8157d728d89223 |
19-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Rewrite LHAU8 pattern to use standard memory operand.
As opposed to to pre-increment store patterns, the pre-increment
load patterns were already using standard memory operands, with
the sole exception of LHAU8.
As there's no real reason why LHAU8 should be different here,
this patch simply rewrites the pattern to also use a memri
operand, just like all the other patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177430 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 5882e3d82831710a7ea1fe8de4813350d4eecf05 |
19-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Rewrite pre-increment store patterns to use standard memory operands.
Currently, pre-increment store patterns are written to use two separate
operands to represent address base and displacement:
stwu $rS, $ptroff($ptrreg)
This causes problems when implementing the assembler parser, so this
commit changes the patterns to use standard (complex) memory operands
like in all other memory access instruction patterns:
stwu $rS, $dst
To still match those instructions against the appropriate pre_store
SelectionDAG nodes, the patch uses the new feature that allows a Pat
to match multiple DAG operands against a single (complex) instruction
operand.
Approved by Hal Finkel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177429 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 880d82e3dbf8ae6c2babf5943d524bbe25015eba |
19-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix sub-operand size mismatch in tocentry operands.
The tocentry operand class refers to 64-bit values (it is only used in 64-bit,
where iPTR is a 64-bit type), but its sole suboperand is designated as 32-bit
type. This causes a mismatch to be detected at compile-time with the TableGen
patch I'll check in shortly.
To fix this, this commit changes the suboperand to a 64-bit type as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177427 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| a548afc98fd4c61a8dfdd550ba57c37f2cfe3ed9 |
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| ec2e968b7a60a4b48bbb315f8dd6e96e51c31691 |
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC64 unaligned i64 load/store
Remove an accidentally-added instruction definition and add a comment in the
test case. This is in response to a post-commit review by Bill Schmidt.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177404 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 54e57f8cb79bdc23ed8289cf2a558fa7c9602972 |
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Don't reserve R31 on PPC64 unless the frame pointer is needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177379 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 9f2518cdc6321d8cfb16973654df2996bad8ad78 |
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix a sign-extension bug in PPCCTRLoops
Don't sign extend the immediate value from the OR instruction in
an LIS/OR pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177361 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 08a215c2869a89b977754334943681a56f5fc460 |
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix PPC unaligned 64-bit loads and stores
PPC64 supports unaligned loads and stores of 64-bit values, but
in order to use the r+i forms, the offset must be a multiple of 4.
Unfortunately, this cannot always be determined by examining the
immediate itself because it might be available only via a TOC entry.
In order to get around this issue, we additionally predicate the
selection of the r+i form on the alignment of the load or store
(forcing it to be at least 4 in order to select the r+i form).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177338 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| e39b107c468affd0aafa719edce67717cbb4bbec |
18-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix 80-col. violations in PPCCTRLoops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177296 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 9887ec31e630ede8541dee1d90c44a1efb63c417 |
18-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix large count and negative constant count handling in PPCCTRLoops
This commit fixes an assert that would occur on loops with large constant counts
(like looping for ((uint32_t) -1) iterations on PPC64). The existing code did
not handle counts that it computed to be negative (asserting instead), but
these can be created with valid inputs.
This bug was discovered by bugpoint while I was attempting to isolate a
completely different problem.
Also, in writing test cases for the negative-count problem, I discovered that
the ori/lsi handling was broken (there was a typo which caused the logic that
was supposed to detect these pairs and extract the iteration count to always
fail). This has now also been corrected (and is covered by one of the new test
cases).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177295 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 1448d06156728712f47e5a71fac8e8edc0aba73b |
18-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup initial-value constants in PPCCTRLoops
Because the initial-value constants had not been added to the list
of instructions considered for DCE the resulting code had redundant
constant-materialization instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177294 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 53856be683113838cc112331adca3717d4a520cc |
17-Mar-2013 |
Sylvestre Ledru <sylvestre@debian.org> |
To avoid symbol clash, undefine PPC here. PPC may be predefined on some hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177234 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCFixupKinds.h
CTargetDesc/PPCMCTargetDesc.h
CTargetDesc/PPCPredicates.h
|
| 324972904353594ad4a0cdfc79370f85e9fb9c8f |
17-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Improve PPC VR (Altivec) register spilling
This change cleans up two issues with Altivec register spilling:
1. The spilling code was inefficient (using two instructions, and add and a
load, when just one would do)
2. The code assumed that r0 would always be available (true for now, but this
will change)
The new code handles VR spilling just like GPR spills but forced into r+r mode.
As a result, when any VR spills are present, we must now always allocate the
register-scavenger spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCInstrInfo.cpp
PCInstrInfo.h
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
|
| ce638c8248355452cb7892c9c27807a92176a7b2 |
16-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Remove PPC avoidWriteAfterWrite callback
As a follow-up to r158719, remove PPCRegisterInfo::avoidWriteAfterWrite.
Jakob pointed out in response to r158719 that this callback is currently unused
and so this has no effect (and the speedups that I thought that I had observed
as a result of implementing this function must have been noise).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177228 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 2d37f7b979a24930c444f9783173a90a6e548118 |
15-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Enable unaligned memory access on PPC for scalar types
Unaligned access is supported on PPC for non-vector types, and is generally
more efficient than manually expanding the loads and stores.
A few of the existing test cases were using expanded unaligned loads and stores
to test other features (like load/store with update), and for these test cases,
unaligned access remains disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177160 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 044f841267139c25240d93d5bf6b862d473cefd5 |
15-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Protect PPC Altivec patterns with a predicate
In preparation for the addition of other SIMD ISA extensions (such as QPX) we
need to make sure that all Altivec patterns are properly predicated on having
Altivec support.
No functionality change intended (one test case needed to be updated b/c it
assumed that Altivec intrinsics would be supported without enabling Altivec
support).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177152 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 0cfb42adb5072fb19a01dba3ea58a33fd5927947 |
15-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Allocate the RS spill slot for any PPC function with spills and a large stack frame
For spills into a large stack frame, the FI-elimination code uses the register
scavenger to obtain a free GPR for use with an r+r-addressed load or store.
When there are no available GPRs, the scavenger gets one by using its spill
slot. Previously, we were not always allocating that spill slot and the RS
would assert when the spill slot was needed.
I don't currently have a small test that triggered the assert, but I've
created a small regression test that verifies that the spill slot is now
added when the stack frame is sufficiently large.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCFrameLowering.h
PCInstrInfo.cpp
PCMachineFunctionInfo.h
|
| 3080d23fde4981835d8a7faf46c152441fadb11f |
14-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Provide the register scavenger to processFunctionBeforeFrameFinalized
Add the current PEI register scavenger as a parameter to the
processFunctionBeforeFrameFinalized callback.
This change is necessary in order to allow the PowerPC target code to
set the register scavenger frame index after the save-area offset
adjustments performed by processFunctionBeforeFrameFinalized. Only
after these adjustments have been made is it possible to estimate
the size of the stack frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCFrameLowering.h
|
| 1c6c61a6089fb2bef47de5ee9a5f4acc34047600 |
14-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use frame-index scavenging for PPC register spilling
Make requiresFrameIndexScavenging return true, and create virtual registers in
the spilling code instead of using the register scavenger directly. This makes
the target-level code simpler, and importantly, delays the scavenging until
after callee-saved register processing (which will be important for later
changes).
Also cleans up trackLivenessAfterRegAlloc (makes it inline in the header with
the other related functions). This makes it clear that it always returns true.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177107 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 100a94bc93dcf9af99eba169599ce950faf0df7e |
14-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Not all PPC functions with a frame pointer need a RS spill slot
We used to add a spill slot for the register scavenger whenever the function
has a frame pointer. This is unnecessarily conservative: We may need the spill
slot for dynamic stack allocations, and functions with dynamic stack
allocations always have a FP, but we might also have a FP for other reasons
(such as the user explicitly disabling frame-pointer elimination), and we don't
necessarily need a spill slot for those functions.
The structsinregs test needed adjustment because it disables FP elimination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177106 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 6bc99603c0f4fdd15d734851a4343b768f4725a4 |
14-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a comment about overlapping PPC frame offsets
I don't think that it is otherwise clear how the overlapping offsets
are processed into distinct spill slots. Comment that this is done
in processFunctionBeforeFrameFinalized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177094 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.h
|
| 4d53e7798c94143a22a9871261b8443592b929d5 |
12-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Don't reserve R2 on Darwin/PPC
Now that only the register-scavenger version of the CR spilling code remains,
we no longer need the Darwin R2 hack. Darwin can use R0 as a spare register in
any case where the System V ABI uses it (R0 is special architecturally, and so
is reserved under all common ABIs).
A few test cases needed to be updated to reflect the register-allocation changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176868 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 7285e8d98c9a44b7efe792462188cfe713dd9641 |
12-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC should always use the register scavenger for CR spilling
This removes the -disable-ppc[32|64]-regscavenger options; the code
that uses the register scavenger has been working well (and has been the default)
for some time, and we don't need options to enable the old (broken) CR spilling code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176865 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 3853f74aba301ef08b699bac2fa8e53230714a58 |
07-Mar-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
ArrayRefize some code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176648 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a6b20ced765b67a85d9219d0c8547fc9c133e14f |
01-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
but TLI.getShiftAmountTy() so far only return scalar type. As a
result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
return target-specificed scalar type or the same vector type as the
1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
|
| 65396823305326bcb379e88a95ded318e1da875c |
26-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR15332 (patch by Florian Zeitz).
There's no need to generate a stack frame for PPC32 SVR4 when there are
no local variables assigned to the stack, i.e., when no red zone is needed.
(PPC64 supports a red zone, but PPC32 does not.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176124 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| fc7695a653323071ec141aee994e4188592ad1f5 |
25-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix missing relocation for TLS addressing peephole optimization.
Report and fix due to Kai Nacke. Testcase update by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176029 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| 4edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4 |
24-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR14364.
This removes a const_cast hack from PPCRegisterInfo::hasReservedSpillSlot().
The proper place to save the frame index for the CR spill slot is in the
PPCFunctionInfo object, not the PPCRegisterInfo object.
No new test cases, as this just reimplements existing function. Existing
tests such as test/CodeGen/PowerPC/crsave.ll are sufficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175998 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 700ed80d3da5e98e05ceb90e9bfb66058581a6db |
21-Feb-2013 |
Eli Bendersky <eliben@google.com> |
Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.
There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.
The refactoring was OK'd by Anton Korobeynikov on llvmdev.
Note: this touches the target interfaces, so out-of-tree targets may
be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCFrameLowering.h
PCISelLowering.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 399eafb580f824d6df2d7392e1bc3e25ecb39f32 |
21-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Trivial cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175771 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 53b0b0e75480121e4e01a7a76e17909e92b1762a |
21-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Large code model support for PowerPC.
Large code model is identical to medium code model except that the
addis/addi sequence for "local" accesses is never used. All accesses
use the addis/ld sequence.
The coding changes are straightforward; most of the patch is taken up
with creating variants of the medium model tests for large model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175767 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 0514595b9b20c9d807a3e31ba6bc270fb6c3f9e7 |
21-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Code review cleanup for r175697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175739 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 421021157eda12453b4fea7ea853d8c472bd8532 |
21-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
PPCDAGToDAGISel::PostprocessISelDAG()
This patch implements the PPCDAGToDAGISel::PostprocessISelDAG virtual
method to perform post-selection peephole optimizations on the DAG
representation.
One optimization is implemented here: folds to clean up complex
addressing expressions for thread-local storage and medium code
model. It will also be useful for large code model sequences when
those are added later. I originally thought about doing this on the
MI representation prior to register assignment, but it's difficult to
do effective global dead code elimination at that point. DCE is
trivial on the DAG representation.
A typical example of a candidate code sequence in assembly:
addis 3, 2, globalvar@toc@ha
addi 3, 3, globalvar@toc@l
lwz 5, 0(3)
When the final instruction is a load or store with an immediate offset
of zero, the offset from the add-immediate can replace the zero,
provided the relocation information is carried along:
addis 3, 2, globalvar@toc@ha
lwz 5, globalvar@toc@l(3)
Since the addi can in general have multiple uses, we need to only
delete the instruction when the last use is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175697 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 06ab2c828a5605abec36eb0d6749940fa6eb7391 |
21-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Relocation enablement for PPC DAG postprocessing pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175693 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
PC.h
PCInstrInfo.td
PCMCInstLower.cpp
|
| 3450f800aa65c91f0496816ba6061a422a74c1fe |
20-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| abc402886e407e21d845cccc15723cffd6e2dc20 |
20-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Additional fixes for bug 15155.
This handles the cases where the 6-bit splat element is odd, converting
to a three-instruction sequence to add or subtract two splats. With this
fix, the XFAIL in test/CodeGen/PowerPC/vec_constants.ll is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175663 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| 49deebb5ebcde502fa7908362a5c000e7adbb359 |
20-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix bug 14779 for passing anonymous aggregates [patch by Kai Nacke].
The PPC backend doesn't handle these correctly. This patch uses logic
similar to that in the X86 and ARM backends to track these arguments
properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175635 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b34c79e4bbe5accbb54d0291e8bef5d2bfef32e4 |
20-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR15155: lost vadd/vsplat optimization.
During lowering of a BUILD_VECTOR, we look for opportunities to use a
vector splat. When the splatted value fits in 5 signed bits, a single
splat does the job. When it doesn't fit in 5 bits but does fit in 6,
and is an even value, we can splat on half the value and add the result
to itself.
This last optimization hasn't been working recently because of improved
constant folding. To circumvent this, create a pseudo VADD_SPLAT that
can be expanded during instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175632 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| 59d580c8d664448f01ea5652ea51b90e0b7e84f6 |
20-Feb-2013 |
Jakub Staszak <kubastaszak@gmail.com> |
Add missing #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175583 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCInstLower.cpp
|
| a79cbb12324db93236e06cc820f0e36ea1f7e4c4 |
17-Feb-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make the visibility of LLVMPPCCompilationCallback work with GCC.
GCC warns about the attribute being ignored if it occurs after void*.
There seems to be some kind of incompatibility between clang and gcc here, but
I can't fathom who's right.
void* LLVM_LIBRARY_VISIBILITY foo(); // clang: hidden, gcc: default
LLVM_LIBRARY_VISIBILITY void *bar(); // clang: hidden, gcc: hidden
void LLVM_LIBRARY_VISIBILITY qux(); // clang: hidden, gcc: hidden
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175394 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 8a8a2dcae054a7b4dfea360b9b88e6be53fda40f |
15-Feb-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Give these callbacks hidden visibility. It is better to not export them more
than we need to and some ELF linkers complain about directly accessing symbols
with default visibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175268 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 9fa05f98e0e8410bc8c5e4000e0d47880f8b37c4 |
15-Feb-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't make assumptions about the mangling of static functions in extern "C"
blocks. We still don't have consensus if we should try to change clang or
the standard, but llvm should work with compilers that implement the current
standard and mangle those functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175267 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| bf7ac42663e087b2effc6b9428eddab3b2475073 |
14-Feb-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert r175120 and r175121. Clang is producing the expected asm names again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175133 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 382a5530ec0682d8dd17f7d9212f52ace38460ed |
14-Feb-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't asume that a static function in an extern "C" block will not be mangled.
Since functions with internal linkage don't have language linkage, it is valid
to overload them:
extern "C" {
static int foo();
static int foo(int);
}
So we mangle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175120 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 96848dfc465c8c7f156a562c246803ebefcf21cf |
13-Feb-2013 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
Add registration for PPC-specific passes to allow the IR to be dumped
via -print-after-all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175058 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCTRLoops.cpp
PCISelDAGToDAG.cpp
|
| 0f58dbae4ab2397dc310e19d171a4bc60fc6c9a7 |
08-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Refine fix to bug 15041.
Thanks to help from Nadav and Hal, I have a more reasonable (and even
correct!) approach. This specifically penalizes the insertelement
and extractelement operations for the performance hit that will occur
on PowerPC processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174725 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetTransformInfo.cpp
|
| 8f7dc823bfda3efede14a3cf9c294a2da3ad8777 |
07-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Constrain PowerPC autovectorization to fix bug 15041.
Certain vector operations don't vectorize well with the current
PowerPC implementation. Element insert/extract performs poorly
without VSX support because Altivec requires going through memory.
SREM, UREM, and VSELECT all produce bad scalar code.
There's a lot of work to do for the cost model before
autovectorization will be tuned well, and this is not an attempt to
address the larger problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174660 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetTransformInfo.cpp
|
| 212af6af024ca358ed109c7b1c3a6b1fd30fd71b |
06-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
PPC calling convention cleanup.
Most of PPCCallingConv.td is used only by the 32-bit SVR4 ABI. Rename
things to clarify this. Also delete some code that's been commented out
for a long time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174526 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCISelLowering.cpp
|
| 6ab5061a2c01b68c6e47c55d4cfe29b3e3b29963 |
05-Feb-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move MRI liveouts to PowerPC return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174409 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0a9d1d31e9b3239b1dc38a67d31810c4bb405d0a |
05-Feb-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Avoid using MRI::liveout_iterator for computing VRSAVEs.
The liveout lists are about to be removed from MRI, this is the only
place they were used after register allocation.
Get the live out V registers directly from the return instructions
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174399 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 0d3731478e6242cceae7c006a071b8b17f7fd298 |
04-Feb-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Disable a couple more vector splat optimizations on PPC.
I didn't see those because the test case used "not grep". FileCheck the test and
XFAIL it, preserving the old optimization, so this can be fixed eventually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174330 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 4969310052f45b1e2e5d21735e38641a20be0e21 |
04-Feb-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
SelectionDAG: Teach FoldConstantArithmetic how to deal with vectors.
This required disabling a PowerPC optimization that did the following:
input:
x = BUILD_VECTOR <i32 16, i32 16, i32 16, i32 16>
lowered to:
tmp = BUILD_VECTOR <i32 8, i32 8, i32 8, i32 8>
x = ADD tmp, tmp
The add now gets folded immediately and we're back at the BUILD_VECTOR we
started from. I don't see a way to fix this currently so I left it disabled
for now.
Fix some trivially foldable X86 tests too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174325 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 87b1a453f08fd0d56a074d2d665f779232a6cac0 |
04-Feb-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCDarwinAsmPrinter::EmitStartOfAsmFile(): Add checking range in CPUDirectives[].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174298 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| b516e9b64850e0e1a50f680fd1443ac12e56557b |
04-Feb-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCDarwinAsmPrinter::EmitStartOfAsmFile(): Add possible elements in CPUDirectives[].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174297 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| dbc86b98f2acd459ab3270cd8500afd32eba7b09 |
02-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Add notes about future PowerPC features
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174232 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| cdc3b74cfb8a1fb3d053106cd8843a39fbb5e2e5 |
01-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
LLVM enablement for some older PowerPC CPUs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174230 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCSubtarget.h
|
| 108fb3202af6f500073cdbb7be32c25d7a273a2e |
31-Jan-2013 |
Chad Rosier <mcrosier@apple.com> |
[PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 9a79b320cb7f179118e69427bc684f2232a24bd9 |
31-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC QPX requires a 32-byte aligned stack
On systems which support the QPX vector instructions, the stack must be
32-byte aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173993 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.h
PCSubtarget.cpp
|
| f9cd7738a3966986dd50db56d8a74952b3016cc0 |
30-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
Initialize hasQPX in PPCSubtarget
This should have gone in with r173973.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173984 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 5bb16fdbb363abee2b9495116ff1a97568460cae |
30-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add definitions for the PPC a2q core marked as having QPX available
This is the first commit of a large series which will add support for the
QPX vector instruction set to the PowerPC backend. This instruction set is
used on the IBM Blue Gene/Q supercomputers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173973 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCSubtarget.h
|
| 8688a58c53b46d2dda9bf50dafd5195790a7ed58 |
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.
Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.
rdar://13087969
PR13204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| d3427d3f4094767884f3eafdef3d60c7f5038197 |
29-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add isBGQ method to PPCSubtarget
This function will be used in future commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173729 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 395210d15b323aa620059fe362e0f8e5eacc0b05 |
26-Jan-2013 |
Dmitri Gribenko <gribozavr@gmail.com> |
Remove unused variables, silences -Wunused-variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173526 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetTransformInfo.cpp
|
| a8b289b70d5ef416608bb71a874b8b4fe80158e1 |
26-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
Initial implementation of PPCTargetTransformInfo
This provides a place to add customized operation cost information and
control some other target-specific IR-level transformations.
The only non-trivial logic in this checkin assigns a higher cost to
unaligned loads and stores (covered by the included test case).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173520 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
PCTargetTransformInfo.cpp
|
| 5928deaf2021b8fd6defa7138e15dc455e492316 |
25-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
More cleanup of PPC register definitions.
Uses the new !add TableGen operator to do more cleanup of the
PPC register definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173446 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 78e10573710a2f2623dfd5a2cc66855814b7371f |
24-Jan-2013 |
Hal Finkel <hfinkel@anl.gov> |
Start cleanup of PPC register definitions using foreach loops.
No functionality change intended.
This captures the first two cases GPR32/64. For the others, we need
an addition operator (if we have one, I've not yet found it).
Based on a suggestion made by Tom Stellard in the AArch64 review!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173366 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| e807d1ea1e05fea895ba90dd4da8c91026ba1f29 |
23-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Fix powerpc test failure - forgot to initialize stack slot size for PPCLinuxMCAsmInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173275 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
|
| e752feee5228bfa33acee35ef9c606ce12f0f173 |
23-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Clean up assignment of CalleeSaveStackSlotSize: get rid of the default and explicitly set this in every target that needs to change it from the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173270 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
|
| 90230c84668269fbd53d163e398cd16486d5d414 |
19-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Sort all of the includes. Several files got checked in with mis-sorted
includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172891 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 8f4ee4b2a2d2aa682643ee16da86195c804686a6 |
17-Jan-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch fixes PR13626 by providing i128 support in the return
calling convention. 128-bit integers are now properly returned
in GPR3 and GPR4 on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172745 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
|
| 792b1233384da442e6c75cf580bd1927123a56f3 |
17-Jan-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch fixes the PPC calling convention to handle returns of
_Complex float and _Complex long double, by simply increasing the
number of floating point registers available for return values.
The test case verifies that the correct registers are loaded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172733 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
|
| a1db5de9e70dd8ffda57b1a4373915ea866b6f1d |
09-Jan-2013 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: EH adjustments
This patch adjust the r171506 to make all DWARF enconding pc-relative
for PPC64. It also adds the R_PPC64_REL32 relocation handling in MCJIT
(since the eh_frame will not generate PIC-relative relocation) and also
adds the emission of stubs created by the TTypeEncoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171979 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 68ca56285f9b6e82eb16ff8ea02a301f2c489fae |
09-Jan-2013 |
Eric Christopher <echristo@gmail.com> |
These functions have default arguments of 0 for the last arg. Use
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171933 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 251040bc18eedfa56d01fe92836e55cfd8c5d990 |
08-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Renamed MCInstFragment to MCRelaxableFragment and added some comments.
No change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171822 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| 5b7f9216c357f1cdf507f300f396b44cb982eb3f |
07-Jan-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch addresses bug 14678 by fixing two problems in medium code model
code generation. Variables addressed through a GlobalAlias were not being
handled, and variables with available_externally linkage were treated
incorrectly. The patch contains two new tests to verify the correct code
generation for these cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171778 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
|
| aeef83c6afa1e18d1cf9d359cc678ca0ad556175 |
07-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 7b449889e7886b263718b5103538970f287bc37e |
04-Jan-2013 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Fix eh_frame relocation for PIC
This patch fixes the PPC eh_frame definitions for the personality and
frame unwinding for PIC objects. It makes PIC build correctly creates
relative relocations in the '.rela.eh_frame' segments and thus avoiding
a text relocation that generates a DT_TEXTREL segments in link phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171506 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCCTRLoops.cpp
PCCodeEmitter.cpp
PCFrameLowering.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCJITInfo.cpp
PCRegisterInfo.cpp
PCSubtarget.cpp
PCTargetMachine.h
argetInfo/PowerPCTargetInfo.cpp
|
| 831737d329a727f53a1fb0572f7b7a8127208881 |
30-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the Function::getFnAttributes method in favor of using the AttributeSet
directly.
This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCISelLowering.cpp
PCRegisterInfo.cpp
|
| cd9ea5198660a80c9c28c6471b0983bb450ca8cb |
25-Dec-2012 |
Hal Finkel <hfinkel@anl.gov> |
Expand PPC64 atomic load and store
Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171072 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 399532b25a939d8c653fd453137bb8e01dc4b8fc |
20-Dec-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Undefine PPC harder.
This was causing a build failure while trying to build on ppc ubuntu 12.10 with
cmake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170668 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.h
CTargetDesc/PPCPredicates.h
|
| 91223a41ef0f5b469b1230919cba9012beb6f321 |
19-Dec-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
PowerPC: Expand VSELECT nodes.
There's probably a better expansion for those nodes than the default for
altivec, but this is better than crashing. VSELECTs occur in loop vectorizer
output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170551 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 034b94b17006f51722886b0f2283fb6fb19aca1f |
19-Dec-2012 |
Bill Wendling <isanbard@gmail.com> |
Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCISelLowering.cpp
PCRegisterInfo.cpp
|
| d3eb4f46f011f5880e09862559c17f03e38bef39 |
14-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch removes some nondeterminism from direct object file output
for TLS dynamic models on 64-bit PowerPC ELF. The default sort routine
for relocations only sorts on the r_offset field; but with TLS, there
can be two relocations with the same r_offset. For PowerPC, this patch
sorts secondarily on descending r_type, which matches the behavior
expected by the linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170237 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| b453e16855f347e300f1dc0cd0dfbdd65c27b0d2 |
14-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI. The ABI will be updated with the new code sequence.
Former sequence:
ld 9,x@got@tprel(2)
add 9,9,x@tls
New sequence:
addis 9,2,x@got@tprel@ha
ld 9,x@got@tprel@l(9)
add 9,9,x@tls
Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170209 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCMCCodeEmitter.cpp
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 1e18b861920ad2fd1a63e006cac61a4e274e5fdf |
13-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This is another cleanup patch for 64-bit PowerPC TLS processing. I had
some hackery in place that hid my poor use of TblGen, which I've now sorted
out and cleaned up. No change in observable behavior, so no new test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170149 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstr64Bit.td
|
| dfebc4cc4c267f797e823b781d73586cc6fc49c5 |
13-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This is just a clean-up patch that simplifies the initial-exec TLS logic by
avoiding use of machine operand flags. No change in observable behavior, so
no new test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170141 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCISelLowering.cpp
PCInstr64Bit.td
PCMCInstLower.cpp
|
| 349c2787cf9e174c8aa955bf8e3b09a405b2aece |
12-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements local-dynamic TLS model support for the 64-bit
PowerPC target. This is the last of the four models, so we now have
full TLS support.
This is mostly a straightforward extension of the general dynamic model.
I had to use an additional Chain operand to tie ADDIS_DTPREL_HA to the
register copy following ADDI_TLSLD_L; otherwise everything above the
ADDIS_DTPREL_HA appeared dead and was removed.
As before, there are new test cases to test the assembly generation, and
the relocations output during integrated assembly. The expected code
gen sequence can be read in test/CodeGen/PowerPC/tls-ld.ll.
There are a couple of things I think can be done more efficiently in the
overall TLS code, so there will likely be a clean-up patch forthcoming;
but for now I want to be sure the functionality is in place.
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170003 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCFixupKinds.h
CTargetDesc/PPCMCCodeEmitter.cpp
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 946a3a9f22c967d5432eaab5fa464b91343477cd |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?
This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 7d34267df63e23be1957f738de783c145febb7af |
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
- Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 57ac1f458a754f30cf500410b438fb260f9b8fe5 |
11-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCFixupKinds.h
CTargetDesc/PPCMCCodeEmitter.cpp
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| d7802bf0ddcac16ee910105922492aee86a53e1b |
04-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch introduces initial-exec model support for thread-local storage
on 64-bit PowerPC ELF.
The patch includes code to handle external assembly and MC output with the
integrated assembler. It intentionally does not support the "old" JIT.
For the initial-exec TLS model, the ABI requires the following to calculate
the address of external thread-local variable x:
Code sequence Relocation Symbol
ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x
add 9,9,x@tls R_PPC64_TLS x
The register 9 is arbitrary here. The linker will replace x@got@tprel
with the offset relative to the thread pointer to the generated GOT
entry for symbol x. It will replace x@tls with the thread-pointer
register (13).
The two test cases verify correct assembly output and relocation output
as just described.
PowerPC-specific selection node variants are added for the two
instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted
when an initial-exec global variable is encountered by
PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to
machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo
that uses the same LDrs support added for medium code model's LDtocL,
with a different relocation type.
The rest of the processing is straightforward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169281 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCFixupKinds.h
CTargetDesc/PPCMCCodeEmitter.cpp
PC.h
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
PCMCInstLower.cpp
|
| a1514e24cc24b050f53a12650e047799358833a1 |
04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.
Note that the script is now able to handle all of these headers without
manual edits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.h
PCISelLowering.h
PCJITInfo.h
PCSubtarget.h
PCTargetMachine.h
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCMCCodeEmitter.cpp
CTargetDesc/PPCMCTargetDesc.cpp
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCTRLoops.cpp
PCCodeEmitter.cpp
PCFrameLowering.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
PCJITInfo.cpp
PCMCInstLower.cpp
PCRegisterInfo.cpp
PCSubtarget.cpp
PCTargetMachine.cpp
|
| 375cbe414329ebade5b50cf3648611af58ae9de7 |
30-Nov-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
This patch fixes the Altivec addend construction for the fused multiply-add
instruction (vmaddfp) to conform with IEEE to ensure the sign of a zero
result when resulting product is -0.0.
The -0.0 vector addend to vmaddfp is generated by a creating a vector
with full bits sets and then shifting each elements by 31-bits to the
left, resulting in a vector of 0x80000000 (or -0.0 as float).
The 'buildvec_canonicalize.ll' was adjusted to reflect this change and
the 'vec_mul.ll' was complemented with the float vector multiplication
test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168998 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 781dfbd482c5177215ae7a43c9483e641eeb0d47 |
28-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix initial frame state on powerpc64.
The createPPCMCAsmInfo routine used PPC::R1 as the initial frame
pointer register, but on PPC64 the 32-bit R1 register does not
have a corresponding DWARF number, causing invalid CIE initial
frame state to be emitted. Fix by using PPC::X1 instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168799 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
|
| a9fa4fd9736f7d1066223f32fa54efbe86c0fceb |
28-Nov-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove all references to TargetInstrInfoImpl.
This class has been merged into its super-class TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| daa65f5e08e19b1fac5f476cef45223b1b4e5a8e |
28-Nov-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch makes medium code model the default for 64-bit PowerPC ELF.
When the CodeGenInfo is to be created for the PPC64 target machine,
a default code-model selection is converted to CodeModel::Medium
provided we are not targeting the Darwin OS. Defaults for Darwin
are unaffected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168747 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
|
| 34a9d4b3b9b7858b729a1af67afa721c048fe5e7 |
27-Nov-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer. Additionally,
only TOC entries are addressed via the TOC pointer.
With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset. Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed. Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.
Consider a load of an external 4-byte integer. With small code model, the
compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
With medium model, it instead generates:
addis 3, 2, .LC1@toc@ha
ld 3, .LC1@toc@l(3)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer. Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits. Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.
Consider next a load of a function-scope static integer. For small code
model, the compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc test_fn_static.si[TC],test_fn_static.si
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
For medium code model, the compiler generates:
addis 3, 2, test_fn_static.si@toc@ha
addi 3, 3, test_fn_static.si@toc@l
lwz 4, 0(3)
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.
Note that it would be more efficient for the compiler to generate:
addis 3, 2, test_fn_static.si@toc@ha
lwz 4, test_fn_static.si@toc@l(3)
The current patch does not perform this optimization yet. This will be
addressed as a peephole optimization in a later patch.
For the moment, the default code model for 64-bit PowerPC will remain the
small code model. We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior. Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.
I've tested the regression suite and the application/benchmark test suite in
two ways: Once with the patch as submitted here, and once with additional
logic to force medium code model as the default. The tests all compile
cleanly, with one exception. The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers. It just so happens
that small code model was incredibly lucky, in that temporary values in
floating-point registers held the expected values needed by the external
library routine that was called incorrectly. My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."
Here are a few comments on how the patch works, since the selection code
can be difficult to follow:
The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses. These are expanded by SelectCodeCommon(). The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL. These new node types correspond naturally to
the sequences described above.
The addis/ld sequence is generated for the following cases:
* Jump table addresses
* Function addresses
* External global variables
* Tentative definitions of global variables (common linkage)
The addis/addi sequence is generated for the following cases:
* Constant pool entries
* File-scope static global variables
* Function-scope static variables
Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.
The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to
a "real" PowerPC instruction. When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).
I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL. So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.
Note that for LDtocL, we generate a new form of LD called LDrs. This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.
The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.
The above assumes use of an external assembler. For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| ed9e442cf098663ce213cb16778b44be466b441f |
26-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Decouple MCInstBuilder from the streamer per Eli's request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168597 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 391271f3bbcec02e0da26d7c246bfabff5cb4ddf |
26-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add MCInstBuilder, a utility class to simplify MCInst creation similar to MachineInstrBuilder.
Simplify some repetitive code with it. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168587 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| d3022b894691017169ff0681c6bea18725330cd1 |
24-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
PPC: Reinstate the fatal error when trying to emit a macho file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168543 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| 915558e77559bf76c57031729d244d319fdce3e6 |
24-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
PPC: MCize most of the darwin PIC emission.
The last remaining bit is "bcl 20, 31, AnonSymbol", which I couldn't find the
instruction definition for. Only whitespace changes in assembly output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168541 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| e8ca482c9734a556f3b66d44ba27e23a1d00b1e0 |
24-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
PPC: Share applyFixup between ELF and Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168540 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| 8f2dce0cda89a18c65735a62b2059a6d22d9ffd8 |
24-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
PPC: Simplify code with Twines.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168539 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 48f63be3684213e16fb657e9bb8c37ae02788e90 |
16-Nov-2012 |
Joe Abbey <jabbey@arxan.com> |
Using const cast to alleviate a warning.
A PR is being filed to address some code issues here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168185 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| e95ed2b7afbe37f1831cb6d8d46d09ccb5cd6b7f |
15-Nov-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Lowering floor intrinsic for Altivec
This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and
llvm.nearbyint to Altivec instruction when using 4 single-precision
float vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168086 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrAltivec.td
|
| 44e394cf618e67b74b0ca566c0acefbc3ca16a58 |
15-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Make a bunch of floating point operations on vectors Expand so that instruction selection won't fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168028 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 490104720db9e1e0eb9cc27e88e2d7288ac27ff0 |
15-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1ab489a42d013151b21655a4c011dc15d6d75eab |
14-Nov-2012 |
Craig Topper <craig.topper@gmail.com> |
Set FFLOOR of vectors to expand to keep intruction selection from failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167922 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ba6086818d9c5070061f74ac9944666b4312c6f0 |
13-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Add (some) PowerPC TLS relocation types to ELF.h and
generate them from PPCELFObjectWriter::getRelocTypeInner
as appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167864 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
|
| 8f887369cbab012e39c3fc80b00ea399509aa24e |
13-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix wrong PowerPC instruction opcodes for:
- lwaux
- lhzux
- stbu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167863 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 4ff09818a945978920e9209a45db98fc6093101b |
13-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix wrong PowerPC instruction encodings due to
operand field name mismatches in:
- AForm_3 (fmul, fmuls)
- XFXForm_5 (mtcrf)
- XFLForm (mtfsf)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167862 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 18430436cad62d6215e1c07cba2059f6eecb7657 |
13-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix instruction encoding for "bd(n)z" on PowerPC,
by using a new instruction format BForm_1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167861 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.td
|
| bc40df3f22a026ffce616cbd69ddb28148b82aad |
13-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix instruction encoding for "isel" on PowerPC,
using a new instruction format AForm_4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167860 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.td
|
| 95d8afc5f2898b59240b0c0cd78d6f54140a91b8 |
12-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Make TOC order deterministic by using MapVector instead of DenseMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167737 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 86aef0a4f093700420c76f313e5668c39db110aa |
05-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
On PowerPC64, integer return values (as well as arguments) are supposed
to be extended to a full register. This is modeled in the IR by marking
the return value (or argument) with a signext or zeroext attribute.
However, while these attributes are respected for function arguments,
they are currently ignored for function return values by the PowerPC
back-end. This patch updates PPCCallingConv.td to ask for the promotion
to i64, and fixes LowerReturn and LowerCallResult to implement it.
The new test case verifies that both arguments and return values are
properly extended when passing them; and also that the optimizers
understand incoming argument and return values are in fact guaranteed
by the ABI to be extended.
The patch caused a spurious breakage in CodeGen/PowerPC/coalesce-ext.ll,
since the test case used a "ret" instruction to create a use of an i32
value at the end of the function (to set up data flow as required for
what the test is intended to test). Since there's now an implicit
promotion to i64, that data flow no longer works as expected. To fix
this, this patch now adds an extra "add" to ensure we have an appropriate
use of the i32 value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167396 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCISelLowering.cpp
|
| 827b7a070d349737f1d6ff63115e0cbb0c031f9c |
05-Nov-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for the PowerPC-specific inline asm Z constraint and y modifier.
The Z constraint specifies an r+r memory address, and the y modifier expands
to the "r, r" in the asm string. For this initial implementation, the base
register is forced to r0 (which has the special meaning of 0 for r+r addressing
on PowerPC) and the full address is taken in the second register. In the
future, this should be improved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167388 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelLowering.cpp
|
| cfe09ed28d8a65b671e8b7a716a933e98e810e32 |
05-Nov-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
[PATCH] PowerPC: Expand load extend vector operations
This patch expands the SEXTLOAD, ZEXTLOAD, and EXTLOAD operations for
vector types when altivec is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167386 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 426c2bf5cdd2173e4a33aea8cb92cf684a724f4b |
01-Nov-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Revert the majority of the next patch in the address space series:
r165941: Resubmit the changes to llvm core to update the functions to
support different pointer sizes on a per address space basis.
Despite this commit log, this change primarily changed stuff outside of
VMCore, and those changes do not carry any tests for correctness (or
even plausibility), and we have consistently found questionable or flat
out incorrect cases in these changes. Most of them are probably correct,
but we need to devise a system that makes it more clear when we have
handled the address space concerns correctly, and ideally each pass that
gets updated would receive an accompanying test case that exercises that
pass specificaly w.r.t. alternate address spaces.
However, from this commit, I have retained the new C API entry points.
Those were an orthogonal change that probably should have been split
apart, but they seem entirely good.
In several places the changes were very obvious cleanups with no actual
multiple address space code added; these I have not reverted when
I spotted them.
In a few other places there were merge conflicts due to a cleaner
solution being implemented later, often not using address spaces at all.
In those cases, I've preserved the new code which isn't address space
dependent.
This is part of my ongoing effort to clean out the partial address space
code which carries high risk and low test coverage, and not likely to be
finished before the 3.2 release looms closer. Duncan and I would both
like to see the above issues addressed before we return to these
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167222 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.cpp
|
| ece6c6bb6329748b92403c06ac87f45c43485911 |
01-Nov-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Revert the series of commits starting with r166578 which introduced the
getIntPtrType support for multiple address spaces via a pointer type,
and also introduced a crasher bug in the constant folder reported in
PR14233.
These commits also contained several problems that should really be
addressed before they are re-committed. I have avoided reverting various
cleanups to the DataLayout APIs that are reasonable to have moving
forward in order to reduce the amount of churn, and minimize the number
of commits that were reverted. I've also manually updated merge
conflicts and manually arranged for the getIntPtrType function to stay
in DataLayout and to be defined in a plausible way after this revert.
Thanks to Duncan for working through this exact strategy with me, and
Nick Lewycky for tracking down the really annoying crasher this
triggered. (Test case to follow in its own commit.)
After discussing with Duncan extensively, and based on a note from
Micah, I'm going to continue to back out some more of the more
problematic patches in this series in order to ensure we go into the
LLVM 3.2 branch with a reasonable story here. I'll send a note to
llvmdev explaining what's going on and why.
Summary of reverted revisions:
r166634: Fix a compiler warning with an unused variable.
r166607: Add some cleanup to the DataLayout changes requested by
Chandler.
r166596: Revert "Back out r166591, not sure why this made it through
since I cancelled the command. Bleh, sorry about this!
r166591: Delete a directory that wasn't supposed to be checked in yet.
r166578: Add in support for getIntPtrType to get the pointer type based
on the address space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167221 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 42d43351b274603ed0ac28128498a35b8987ce15 |
31-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch addresses an ABI compatibility issue with empty aggregate
parameters. Examples of these are:
struct { } a;
union { } b[256];
int a[0];
An empty aggregate has an address, although dereferencing that address is
pointless. When passed as a parameter, an empty aggregate does not consume
a protocol register, nor does it consume a doubleword in the parameter save
area. Passing an empty aggregate by reference passes an address just as
for any other aggregate. Returning an empty aggregate uses GPR3 as a hidden
address of the return value location, just as for any other aggregate.
The patch modifies PPCTargetLowering::LowerFormalArguments_64SVR4 and
PPCTargetLowering::LowerCall_64SVR4 to properly skip empty aggregate
parameters passed by value. The handling of return values and by-reference
parameters was already correct.
Built on powerpc64-unknown-linux-gnu and tested with no new regressions.
A test case is included to test proper handling of empty aggregate
parameters on both sides of the function call protocol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167090 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c83b5dc625bd85276a23c36c1fbad193203d2bc7 |
30-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Expand FSRQT for vector types
This patch expands FSQRT for floating point vector types when altivec is
used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167034 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 5f41fd685b6e82c3194be782566bbc438d697cc9 |
30-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: More support for Altivec compare operations
This patch adds more support for vector type comparisons using altivec.
It adds correct support for v16i8, v8i16, v4i32, and v4f32 vector
types for comparison operators ==, !=, >, >=, <, and <=.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167015 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| e6c56433de56fb89f1d476332134b6b2e22cfa28 |
29-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch solves a problem with passing varargs parameters under the PPC64
ELF ABI.
A varargs parameter consisting of a single-precision floating-point value,
or of a single-element aggregate containing a single-precision floating-point
value, must be passed in the low-order (rightmost) four bytes of the
doubleword stack slot reserved for that parameter. If there are GPR protocol
registers remaining, the parameter must also be mirrored in the low-order
four bytes of the reserved GPR.
Prior to this patch, such parameters were being passed in the high-order
four bytes of the stack slot and the mirrored GPR.
The patch adds a new test case to verify the correct code generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166968 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 78dab643e0d49cc76ca20409d733c23bc17171dd |
29-Oct-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Allow i32/i64 for 'f' constraint on PowerPC.
This fixes PR12757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166943 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| baafdeae0b1551c73f1a0052414530e061029e14 |
29-Oct-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCSubtarget.h: Add explicit braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166932 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 19ad3e2fa7cee27dd712157f5515c178a27bde8b |
29-Oct-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCSubtarget.h: Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166931 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 01d013ec043407a558b8b87f75ec207336e8a4ae |
29-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch adds alignment information for long double to the 64-bit PowerPC
ELF subtarget.
The existing logic is used as a fallback to avoid any changes to the Darwin
ABI. PPC64 ELF now has two possible data layout strings: one for FreeBSD,
which requires 8-byte alignment, and a default string that requires
16-byte alignment.
I've added a test for PPC64 Linux to verify the 16-byte alignment. If
somebody wants to add a separate test for FreeBSD, that would be great.
Note that there is a companion patch to update the alignment information
in Clang, which I am committing now as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166928 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| edf5e9a1d5f0cb4cfe747c761c73a2e303f365c4 |
26-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Fix for rldcl/rldicl/rldicr MC emission
This patch fixes the rldcl/rldicl/rldicr instruction emission. The issue is
the MDForm_1 instruction defines the PowerISA MB field from 'rldicl'
with the name MBE, but RLDCL/RLDICL/RLDICR definition uses as 'MB'.
It end up by generatint the 'rldicl' enconding at
'lib/Target/PowerPC/PPCGenMCCodeEmitter.inc' to use the fourth argument as the
third. The patch changes it by adjusting to use the fourth argument as
intended.
Fixes PR14180.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166770 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 18560fae0bb122857a61bb36f22628901cdc3dde |
25-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
This patch fixes the MC object emission of 'nop' for external function calls
and also fixes the R_PPC64_TOC16 and R_PPC64_TOC16_DS relocation offset.
The 'nop' is needed so a restore TOC instruction (ld r2,40(r1)) can be placed
by the linker to correct restore the TOC of previous function.
Current code has two issues: it defines in PPCInstr64Bit.td file a LDinto_toc
and LDtoc_restore as a DSForm_1 with DS_RA=0 where it should be
DS=2 (the 8 bytes displacement of the TOC saving). It also wrongly emits a
MC intruction using an uint32_t value while the PPC::BL8_NOP_ELF
and PPC::BLA8_NOP_ELF are both uint64_t (because of the following 'nop').
This patch corrects the remaining ExecutionEngine using MCJIT:
ExecutionEngine/2002-12-16-ArgTest.ll
ExecutionEngine/2003-05-07-ArgumentTest.ll
ExecutionEngine/2005-12-02-TailCallBug.ll
ExecutionEngine/hello.ll
ExecutionEngine/hello2.ll
ExecutionEngine/test-call.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166682 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCMCCodeEmitter.cpp
PCInstr64Bit.td
|
| 37900c5dcb254ef50c17c57a302c30626536917c |
25-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch addresses a PPC64 ELF issue with passing parameters consisting of
structs having size 3, 5, 6, or 7. Such a struct must be passed and received
as right-justified within its register or memory slot. The problem is only
present for structs that are passed in registers.
Previously, as part of a patch handling all structs of size less than 8, I
added logic to rotate the incoming register so that the struct was left-
justified prior to storing the whole register. This was incorrect because
the address of the parameter had already been adjusted earlier to point to
the right-adjusted value in the storage slot. Essentially I had accidentally
accounted for the right-adjustment twice.
In this patch, I removed the incorrect logic and reorganized the code to make
the flow clearer.
The removal of the rotates changes the expected code generation, so test case
structsinregs.ll has been modified to reflect this. I also added a new test
case, jaggedstructs.ll, to demonstrate that structs of these sizes can now
be properly received and passed.
I've built and tested the code on powerpc64-unknown-linux-gnu with no new
regressions. I also ran the GCC compatibility test suite and verified that
earlier problems with these structs are now resolved, with no new regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166680 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| aa71428378c1cb491ca60041d8ba7aa110bc963d |
25-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
Initial TOC support for PowerPC64 object creation
This patch adds initial PPC64 TOC MC object creation using the small mcmodel
(a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC,
R_PPC64_TOC16, and R_PPC64_TOC16DS).
The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter'
is meant to avoid the creation of an unreferenced ".TOC." symbol (used in
the .odp creation) as well to set the R_PPC64_TOC relocation target as the
temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should
not point to any symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166677 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCFixupKinds.h
CTargetDesc/PPCMCCodeEmitter.cpp
PCAsmPrinter.cpp
PCSubtarget.cpp
|
| 270483466124fe1e19d5439e958fef63cebd43cd |
24-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Implement a basic VectorTargetTransformInfo interface to be used by the loop and bb vectorizers for modeling the cost of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166593 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| aa76e9e2cf50af190de90bc778b7f7e42ef9ceff |
24-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Add in support for getIntPtrType to get the pointer type based on the address space.
This checkin also adds in some tests that utilize these paths and updates some of the
clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166578 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 726c23705c056e4d86f0b3d833803f1d43e6eee4 |
23-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This is another TLC patch for separating code for the Darwin and ELF ABIs
for the PowerPC target, and factoring the results. This will ease future
maintenance of both subtargets.
PPCTargetLowering::LowerCall_Darwin_Or_64SVR4() has grown a lot of special-case
code for the different ABIs, making maintenance difficult. This is getting
worse as we repair errors in the 64-bit ELF ABI implementation, while avoiding
changes to the Darwin ABI logic. This patch splits the routine into
LowerCall_Darwin() and LowerCall_64SVR4(), allowing both versions to be
significantly simplified. I've factored out chunks of similar code where it
made sense to do so. I also performed similar factoring on
LowerFormalArguments_Darwin() and LowerFormalArguments_64SVR4().
There are no functional changes in this patch, and therefore no new test
cases have been developed.
Built and tested on powerpc64-unknown-linux-gnu with no new regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166480 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| cbd9a19b5d6ff93efa82c467508ede78b8af3bac |
19-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166248 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 6c28a7eec8d1794fb5476cd9fe14affb479ed1d9 |
18-Oct-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
This patch fixes failures in the SingleSource/Regression/C/uint64_to_float
test case on PowerPC caused by rounding errors when converting from a 64-bit
integer to a single-precision floating point. The reason for this are
double-rounding effects, since on PowerPC we have to convert to an
intermediate double-precision value first, which gets rounded to the
final single-precision result.
The patch fixes the problem by preparing the 64-bit integer so that the
first conversion step to double-precision will always be exact, and the
final rounding step will result in the correctly-rounded single-precision
result. The generated code sequence is equivalent to what GCC would generate.
When -enable-unsafe-fp-math is in effect, that extra effort is omitted
and we accept possible rounding errors (just like GCC does as well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166178 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3b9a911efcf280950f878a050728450423875639 |
18-Oct-2012 |
Bob Wilson <bob.wilson@apple.com> |
Temporarily revert the TargetTransform changes.
The TargetTransform changes are breaking LTO bootstraps of clang. I am
working with Nadav to figure out the problem, but I am reverting it for now
to get our buildbots working.
This reverts svn commits: 165665 165669 165670 165786 165787 165997
and I have also reverted clang svn 165741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166168 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 7a6cb15a929e76955471ef2a7b6db721198320a0 |
16-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch addresses PR13949.
For the PowerPC 64-bit ELF Linux ABI, aggregates of size less than 8
bytes are to be passed in the low-order bits ("right-adjusted") of the
doubleword register or memory slot assigned to them. A previous patch
addressed this for aggregates passed in registers. However, small
aggregates passed in the overflow portion of the parameter save area are
still being passed left-adjusted.
The fix is made in PPCTargetLowering::LowerCall_Darwin_Or_64SVR4 on the
caller side, and in PPCTargetLowering::LowerFormalArguments_64SVR4 on
the callee side. The main fix on the callee side simply extends
existing logic for 1- and 2-byte objects to 1- through 7-byte objects,
and correcting a constant left over from 32-bit code. There is also a
fix to a bogus calculation of the offset to the following argument in
the parameter save area.
On the caller side, again a constant left over from 32-bit code is
fixed. Additionally, some code for 1, 2, and 4-byte objects is
duplicated to handle the 3, 5, 6, and 7-byte objects for SVR4 only. The
LowerCall_Darwin_Or_64SVR4 logic is getting fairly convoluted trying to
handle both ABIs, and I propose to separate this into two functions in a
future patch, at which time the duplication can be removed.
The patch adds a new test (structsinmem.ll) to demonstrate correct
passing of structures of all seven sizes. Eight dummy parameters are
used to force these structures to be in the overflow portion of the
parameter save area.
As a side effect, this corrects the case when aggregates passed in
registers are saved into the first eight doublewords of the parameter
save area: Previously they were stored left-justified, and now are
properly stored right-justified. This requires changing the expected
output of existing test case structsinregs.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166022 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2c39b15073db81d93bb629303915b7d7e5d088dc |
15-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165941 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.cpp
|
| f35c62bf025411393c7df0803851010cc0e597ba |
15-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: add EmitTCEntry class for TOC creation
This patch replaces the EmitRawText by a EmitTCEntry class (specialized for
each Streamer) in PowerPC64 TOC entry creation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165940 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| fb384d61c78b60787ed65475d8403aee65023962 |
11-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Revert 165732 for further review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165747 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.cpp
|
| f3840d2c16a4ec4c879a8ded402835746de380f8 |
11-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Add in the first iteration of support for llvm/clang/lldb to allow variable per address space pointer sizes to be optimized correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165726 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.cpp
|
| a867f378979f26e7d87bb6db5b7665a2ee4c0293 |
11-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch addresses PR13947.
For function calls on the 64-bit PowerPC SVR4 target, each parameter
is mapped to as many doublewords in the parameter save area as
necessary to hold the parameter. The first 13 non-varargs
floating-point values are passed in registers; any additional
floating-point parameters are passed in the parameter save area. A
single-precision floating-point parameter (32 bits) must be mapped to
the second (rightmost, low-order) word of its assigned doubleword
slot.
Currently LLVM violates this ABI requirement by mapping such a
parameter to the first (leftmost, high-order) word of its assigned
doubleword slot. This is internally self-consistent but will not
interoperate correctly with libraries compiled with an ABI-compliant
compiler.
This patch corrects the problem by adjusting the parameter addressing
on both sides of the calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165714 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e3d0e86919730784faaddcb5d9b0257c39b0804b |
11-Oct-2012 |
Nadav Rotem <nrotem@apple.com> |
Add a new interface to allow IR-level passes to access codegen-specific information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 26160f4e6403f3ddd7c4599422578cb46777103d |
10-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
When generating spill and reload code for vector registers on PowerPC,
the compiler makes use of GPR0. However, there are two flavors of
GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0
(X0). The spill/reload code makes use of R0 regardless of whether we
are generating 32- or 64-bit code.
This patch corrects the problem in the obvious manner, using X0 and
ADDI8 for 64-bit and R0 and ADDI for 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| a5d0ab555384baa293b06686bec5a01fb9638ca3 |
10-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
The PowerPC VRSAVE register has been somewhat of an odd beast since
the Altivec extensions were introduced. Its use is optional, and
allows the compiler to communicate to the operating system which
vector registers should be saved and restored during a context switch.
In practice, this information is ignored by the various operating
systems using the SVR4 ABI; the kernel saves and restores the entire
register state. Setting the VRSAVE register is no longer performed by
the AIX XL compilers, the IBM i compilers, or by GCC on Power Linux
systems. It seems best to avoid this logic within LLVM as well.
This patch avoids generating code to update and restore VRSAVE for the
PowerPC SVR4 ABIs (32- and 64-bit). The code remains in place for the
Darwin ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165656 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCISelDAGToDAG.cpp
|
| 6765834754cbb3cb0f15b4b15e98c5e73fa50066 |
09-Oct-2012 |
Bill Wendling <isanbard@gmail.com> |
Create enums for the different attributes.
We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCISelLowering.cpp
PCRegisterInfo.cpp
|
| 1c7d69bbe2de22f386ffd9ef4480f8a77be28130 |
08-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PR12716: PPC crashes on vector compare
Vector compare using altivec 'vcmpxxx' instructions have as third argument
a vector register instead of CR one, different from integer and float-point
compares. This leads to a failure in code generation, where 'SelectSETCC'
expects a DAG with a CR register and gets vector register instead.
This patch changes the behavior by just returning a DAG with the
vector compare instruction based on the type. The patch also adds a testcase
for all vector types llvm defines.
It also included a fix on signed 5-bits predicates printing, where
signed values were not handled correctly as signed (char are unsigned by
default for PowerPC). This generates 'vspltisw' (vector splat)
instruction with SIM out of range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165419 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| cd585084e500a36208a7185edf62cb279f83c26b |
08-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Fix object creation with PPC::MTCRF8 instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165411 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCCodeEmitter.cpp
|
| 51aaadb7bda93040ebfc8341abed7627c99be8f7 |
08-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
Add floating-point to and from integer conversion
This patch add altivec support for v4i32 to v4f32 and for v4f32 to
v4i32 vector rounding conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165409 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrAltivec.td
|
| 3574eca1b02600bac4e625297f4ecf745f4c4f32 |
08-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelLowering.cpp
PCSubtarget.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| b2544ece597192266199ec00ece2ee5bb6273cd9 |
05-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch splits apart PPCISelLowering::LowerFormalArguments_Darwin_Or_64SVR4
into separate versions for the Darwin and 64-bit SVR4 ABIs. This will
facilitate doing more major surgery on the 64-bit SVR4 ABI in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165336 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| d875533b7f362933d2ce9cc24bc5917b07231340 |
05-Oct-2012 |
Will Schmidt <will_schmidt@vnet.ibm.com> |
- Mark the BCC and BLR defs as isCodeGenOnly per error output from
llvm-tblgen -gen-asm-matcher.
PPCInstrInfo.td | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165315 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 916381569aa5cd33e4ed4c1585f48cf5da1a6684 |
04-Oct-2012 |
Will Schmidt <will_schmidt@vnet.ibm.com> |
- add tokens to PPCInstrInfo.td and PPCInstr64Bit.td to resolve
"Instruction 'foo' has no tokens" errors during llvm-tblgen
-gen-asm-matcher attempts. At this time, the added
tokens are "#comment" style rather than the actual mnemonic. This will
be revisited once the rest of the base asmparser bits get straightened
out for ppc64-elf-linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165237 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| e37091931cc409d3189a69eb581871c6e743832d |
04-Oct-2012 |
Will Schmidt <will_schmidt@vnet.ibm.com> |
test commit / whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165233 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 94c22716d60ff5edf6a98a3c67e0faa001be1142 |
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 7e2c793a2b5c746344652b6579e958ee42fafdcc |
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo 'iff' => 'if'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2c189061184925c6a8ecbb5a19e648b230a41c0e |
26-Sep-2012 |
Bill Wendling <isanbard@gmail.com> |
Remove the `hasFnAttr' method from Function.
The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164725 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCISelLowering.cpp
PCRegisterInfo.cpp
|
| 5236ab3fdd4ce9b9990ef58cd8fac695cfbd0eaf |
24-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Specify MachinePointerInfo as refering to the argument value and offset of the
store when handling byval arguments. Thus preventing reordering of the store
with load with post-RA scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164553 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 419f376564d17eaef7e5b4a77b066668e4272ecc |
19-Sep-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Small structs for PPC64 SVR4 must be passed right-justified in registers.
lib/Target/PowerPC/PPCISelLowering.{h,cpp}
Rename LowerFormalArguments_Darwin to LowerFormalArguments_Darwin_Or_64SVR4.
Rename LowerFormalArguments_SVR4 to LowerFormalArguments_32SVR4.
Receive small structs right-justified in LowerFormalArguments_Darwin_Or_64SVR4.
Rename LowerCall_Darwin to LowerCall_Darwin_Or_64SVR4.
Rename LowerCall_SVR4 to LowerCall_32SVR4.
Pass small structs right-justified in LowerCall_Darwin_Or_64SVR4.
test/CodeGen/PowerPC/structsinregs.ll
New test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164228 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 6fc3ea2f997f30827eaeb5e5c279119c79568333 |
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Fix the isLocalCall() by checking for linker weakness as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164155 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f145c135f3a28e2c59bd02e475fbf09f4157c9fb |
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Avoid symbol name clash when filling TOC.
Patch by Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164141 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 4cd56014ae05a6ccc92cdcc66d457ce37558fc31 |
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
On PPC64 emit the environment pointer. Patch by Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164139 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| eb8b7dc5362b66e45f17ce1c6d1ff1f5b79b9534 |
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Optimize local func calls to not emit nop for TOC restoration.
Patch by Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164138 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 536a88ad5bf160232205192a7ce72e50bfadbded |
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend
store this and use it to not emit long nops when the CPU is geode which
doesnt support them.
Fixes PR11212.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164132 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCMCTargetDesc.h
|
| 6ffb4024d875570a01d6b8db900a0385a491403b |
16-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Change unsigned to uint32_t to match base class declaration and other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164001 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 86a1c32e67b23c5e9e42dff9eb86e99ba15bb42f |
15-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163974 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCCodeEmitter.cpp
|
| 6c7ccaa3fd1d6e96d0bf922554b09d2b17c3b0e3 |
12-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Fix PR11985
- BlockAddress has no support of BA + offset form and there is no way to
propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
support BA + offset addressing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ba9d069d797fbe204470c18a5f15e7f3cf763e0b |
12-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Enable exceptions handling on PPC64 now that cr misaligned spilling
was fixed in r163713.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163715 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
|
| 9d760ae5c6bc1d1482e2824efcf9cb11db1cc16f |
12-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
This patch corrects logic in PPCFrameLowering for save and restore of
nonvolatile condition register fields across calls under the SVR4 ABIs.
* With the 64-bit ABI, the save location is at a fixed offset of 8 from
the stack pointer. The frame pointer cannot be used to access this
portion of the stack frame since the distance from the frame pointer may
change with alloca calls.
* With the 32-bit ABI, the save location is just below the general
register save area, and is accessed via the frame pointer like the rest
of the save areas. This is an optional slot, so it must only be created
if any of CR2, CR3, and CR4 were modified.
* For both ABIs, save/restore logic is generated only if one of the
nonvolatile CR fields were modified.
I also took this opportunity to clean up an extra FIXME in
PPCFrameLowering.h. Save area offsets for 32-bit GPRs are meaningless
for the 64-bit ABI, so I removed them for correctness and efficiency.
Fixes PR13708 and partially also PR13623. It lets us enable exception handling
on PPC64.
Patch by William J. Schmidt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163713 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCFrameLowering.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 39646d96e76aea5d20bffb386233a0dbb5932a21 |
07-Sep-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
MC: Overhaul handling of .lcomm
- Darwin lied about not supporting .lcomm and turned it into zerofill in the
asm parser. Push the zerofill-conversion down into macho-specific code.
- This makes the tri-state LCOMMType enum superfluous, there are no targets
without .lcomm.
- Do proper error reporting when trying to use .lcomm with alignment on a target
that doesn't support it.
- .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2.
- Fixes PR13755 (.lcomm crashes on ELF).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
|
| c10d5e9dae40801622c73237b484d51da73f77b9 |
05-Sep-2012 |
Hal Finkel <hfinkel@anl.gov> |
Move the PPC TOC defs into the PPC64 InstrInfo file.
Since TOC is just defined for PPC64, move its definition to PPC64 td file.
Patch by Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163234 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 94b17f334ba28cc11b2bf89911189904d00e99f7 |
03-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Remove always true checks. Noticed by Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163117 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| d2a35f2937af443241fc3d1b0c6104a587170f24 |
30-Aug-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCISelLowering.cpp: Fix r162725.
[Tobias von Koch] What's happening here is that the CR6SET/CR6UNSET is breaking the chain of register copies glued to the function call (BL_SVR4 node). The scheduler then moves other instructions in between those and the function call, which isn't good!
Right. That's the case where there is no chain of register copies before the call, so InFlag == 0... Attached is a new revision of the patch which should fix this for good.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162916 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 25f6b5a5541e34f8e703f0b5e090e4910dc9d0d7 |
30-Aug-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCISelLowering.cpp: Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162915 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bbd169b1d96e1012df9852d41b7fd00381ed9d48 |
29-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Reserve space for the mandatory traceback fields on PPC64.
We need to reserve space for the mandatory traceback fields,
though leaving them as zero is appropriate for now.
Although the ABI calls for these fields to be filled in fully, no
compiler on Linux currently does this, and GDB does not read these
fields. GDB uses the first word of zeroes during exception handling to
find the end of the function and the size field, allowing it to compute
the beginning of the function. DWARF information is used for everything
else. We need the extra 8 bytes of pad so the size field is found in
the right place.
As a comparison, GCC fills in a few of the fields -- language, number
of saved registers -- but ignores the rest. IBM's proprietary OSes do
make use of the full traceback table facility.
Patch by Bill Schmidt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162854 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| c6c2ced38411215e5bf46ded787c23810160dfa7 |
28-Aug-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Emit word of zeroes after the last instruction as a start of the mandatory
traceback table on PowerPC64. This helps gdb handle exceptions. The other
mandatory fields are ignored by gdb and harder to implement so just add
there a FIXME.
Patch by Bill Schmidt. PR13641.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162778 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 621b77ade2ff46d1d8594bddee6931b2f4a14706 |
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC Freescale e500mc and e5500 subtargets.
Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCAsmPrinter.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
PCSchedule.td
PCScheduleE500mc.td
PCScheduleE5500.td
PCSubtarget.h
|
| 8dc440a46a5153a1640a3050480cceca9b8af05d |
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Split several PPC instruction classes.
Slight reorganisation of PPC instruction classes for scheduling. No
functionality change for existing subtargets.
- Clearly separate load/store-with-update instructions from regular loads and stores.
- Split IntRotateD -> IntRotateD and IntRotateDI
- Split out fsub and fadd from FPGeneral -> FPAddSub
- Update existing itineraries
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
PCSchedule.td
PCSchedule440.td
PCScheduleA2.td
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
|
| f3c3828e57d922bbe912ffabbd9252b9f5100c14 |
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Allow remat of LI on PPC.
Allow load-immediates to be rematerialised in the register coalescer for
PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail,
because it relies on a register move getting emitted. The immediate load is
equivalent, so change this test case.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162727 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 82b3821208286aeb43f603fdac98832bd662dad9 |
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Eliminate redundant CR moves on PPC32.
The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and
unset if it doesn't. The solution up to now was to insert a MachineNode to
set/unset the CR bit, which produces a CR vreg. This vreg was then copied
into CR bit 6. When the register allocator saw a bunch of these in the same
function, it allocated the set/unset CR bit in some random CR register (1
extra instruction) and then emitted CR moves before every vararg function
call, rather than just setting and unsetting CR bit 6 directly before every
vararg function call. This patch instead inserts a PPCcrset/PPCcrunset
instruction which are then matched by a dedicated instruction pattern.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162725 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 97d047dec71cb37f31aac102cdc87b3dec0b1c46 |
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Optimize zext on PPC64.
The zeroextend IR instruction is lowered to an 'and' node with an immediate
mask operand, which in turn gets legalised to a sequence of ori's & ands.
This can be done more efficiently using the rldicl instruction.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162724 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 1144af3c9b4da48cd581156e05b24261c8de366a |
25-Aug-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix integer undefined behavior due to signed left shift overflow in LLVM.
Reviewed offline by chandlerc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
PCISelLowering.cpp
|
| 9fb8b49380e7cf6ce88400ad65051e830563bc81 |
24-Aug-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Lower constant pools and jump tables via TOC on PPC64/SVR4.
In collaboration with Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162562 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelLowering.cpp
PCInstr64Bit.td
|
| ea47628cbafb48bf2a51554328a6dd77be40f4df |
24-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add missing SDNPSideEffect flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162557 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 05b2bc8781d9af403a257599613e12cb8fef19e8 |
16-Aug-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Revert r162034, r162035 and r162037.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162039 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCFixupKinds.h
|
| e88d17de99c5f46bc8104bc777f657d0299fd0e6 |
16-Aug-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Define and handle additional fixup kinds. By Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162037 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCFixupKinds.h
|
| 0016f73ae5ebdd8e62ee640d287482fed562b369 |
16-Aug-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Fix typo and grammar. By Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162032 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0c5f5f4916a5c72b2a6a9cb13f0b2c2add95b6f1 |
09-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't use getNextOperandForReg().
This way of using getNextOperandForReg() was unlikely to work as
intended. We don't give any guarantees about the order of operands in
the use-def chains, so looking only at operands following a given
operand in the chain doesn't make sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161542 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 8da94ad6e0947690201c543da556ec0396ad9912 |
07-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add a comment about mftb vs. mfspr on PPC.
Thanks to Alex Rosenberg for the suggestion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161428 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| f45717e985260e9416dbd2fe8df471d48705c86a |
06-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
MFTB on PPC64 should really be encoded using MFSPR.
The MFTB instruction itself is being phased out, and its functionality
is provided by MFSPR. According to the ISA docs, using MFSPR works on all known
chips except for the 601 (which did not have a timebase register anyway)
and the POWER3.
Thanks to Adhemerval Zanella for pointing this out!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 8cc3474f72388836fa4ca7d3622289fb9ee08b41 |
04-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add readcyclecounter lowering on PPC64.
On PPC64, this can be done with a simple TableGen pattern.
To enable this, I've added the (otherwise missing) readcyclecounter
SDNode definition to TargetSelectionDAG.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstr64Bit.td
|
| 4ecaedc771f47e099609c69ed2782c64fc653d05 |
03-Aug-2012 |
Gabor Greif <ggreif@gmail.com> |
allow 'make CPPFLAGS=<something>' work again
this makes this hack a bit more bearable
for poor souls who need to pass custom
preprocessor flags to the build process
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161240 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/Makefile
|
| 68c10a2ff74fe882cfd789983b2d0f12e42fb0ec |
13-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove variable_ops from call instructions in most targets.
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 769951f6cc6323821ce1e9f46a37817a541c884f |
03-Jul-2012 |
Evan Cheng <evan.cheng@apple.com> |
Target option DisableJumpTables is a gross hack. Move it to TargetLowering instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159611 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCTargetMachine.cpp
|
| 564fbf6aff8fb95646a1290078a37c2d4dbe629f |
02-Jul-2012 |
Bob Wilson <bob.wilson@apple.com> |
Add all codegen passes to the PassManager via TargetPassConfig.
This is a preliminary step toward having TargetPassConfig be able to
start and stop the compilation at specified passes for unit testing
and debugging. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 0bcbd1df7a204e1e512f1a27066d725309de1b13 |
28-Jun-2012 |
Bill Wendling <isanbard@gmail.com> |
Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h.
The reasoning is because the DebugInfo module is simply an interface to the
debug info MDNodes and has nothing to do with analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159312 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 0518fca843ff87d069ecb07fc00d306c1f587d58 |
26-Jun-2012 |
Jack Carter <jcarter@mips.com> |
There are a number of generic inline asm operand modifiers that
up to r158925 were handled as processor specific. Making them
generic and putting tests for these modifiers in the CodeGen/Generic
directory caused a number of targets to fail.
This commit addresses that problem by having the targets call
the generic routine for generic modifiers that they don't currently
have explicit code for.
For now only generic print operands 'c' and 'n' are supported.vi
Affected files:
test/CodeGen/Generic/asm-large-immediate.ll
lib/Target/PowerPC/PPCAsmPrinter.cpp
lib/Target/NVPTX/NVPTXAsmPrinter.cpp
lib/Target/ARM/ARMAsmPrinter.cpp
lib/Target/XCore/XCoreAsmPrinter.cpp
lib/Target/X86/X86AsmPrinter.cpp
lib/Target/Hexagon/HexagonAsmPrinter.cpp
lib/Target/CellSPU/SPUAsmPrinter.cpp
lib/Target/Sparc/SparcAsmPrinter.cpp
lib/Target/MBlaze/MBlazeAsmPrinter.cpp
lib/Target/Mips/MipsAsmPrinter.cpp
MSP430 isn't represented because it did not even run with
the long existing 'c' modifier and it was not apparent what
needs to be done to get it inline asm ready.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159203 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| d5c407d2d01ff8797c29343e4da5f765fe52fb5f |
24-Jun-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159112 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 0a2f793d6e24acd00d9209b46436b4899feb1cdb |
23-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Silence an unused variable warning on release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159074 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
|
| 009f7afbeb77d1cc8e962bac7057b73b6d39d62f |
23-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for the PPC isel instruction.
The isel (integer select) instruction is supported on the 440 and A2
embedded cores and on the POWER7.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159045 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
PC.td
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
PCSubtarget.cpp
PCSubtarget.h
|
| 070b8dba809dd75267327cc823118bf7e171d17d |
22-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Convert the PPC backend to use the new FMA infrastructure.
The existing contraction patterns are replaced with fma/fneg.
Overall functionality should be the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158955 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
PCInstrInfo.td
|
| 2bbc9193b4a9b4e53ec114fd98a587a2917c365b |
21-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Treat TargetGlobalAddress as a constant for the purpose of matching pre-inc stores on PPC.
Thanks to Tobias von Koch for pointing out this problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158932 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 0fcdd8b2cc2b1bcf0aa64870d5269f9ac6dc76c0 |
20-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for generating reg+reg (indexed) pre-inc loads on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158823 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| d693cafcfb9e67ba7040cb810e4409a166421482 |
20-Jun-2012 |
Lang Hames <lhames@gmail.com> |
Add DAG-combines for aggressive FMA formation.
This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or
FSUB + FMUL. The combines are performed when:
(a) Either
AllowExcessFPPrecision option (-enable-excess-fp-precision for llc)
OR
UnsafeFPMath option (-enable-unsafe-fp-math)
are set, and
(b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of
the FADD/FSUB, and
(c) The FMUL only has one user (the FADD/FSUB).
If your target has fast FMA instructions you can make use of these combines by
overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for
types supported by your FMA instruction, and adding patterns to match ISD::FMA
to your FMA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 7164288c3eb52e20454fc757440f867f04eb13a4 |
19-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement PPCInstrInfo::isCoalescableExtInstr().
The PPC::EXTSW instruction preserves the low 32 bits of its input, just
like some of the x86 instructions. Use it to reduce register pressure
when the low 32 bits have multiple uses.
This requires a small change to PeepholeOptimizer since EXTSW takes a
64-bit input register.
This is related to PR5997.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| fe5b65827f20a61bef817c6421f32b7e05d65caf |
19-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Mark most PPC register classes to avoid write-after-write.
For processors with the G5-like instruction-grouping scheme, this helps avoid
early group termination due to a write-after-write dependency within the group.
It should also help on pipelined embedded cores.
On POWER7, over the test suite, this gives an average 0.5% speedup. The largest
speedups are:
SingleSource/Benchmarks/Stanford/Quicksort - 33%
MultiSource/Applications/d/make_dparser - 21%
MultiSource/Benchmarks/FreeBench/analyzer/analyzer - 12%
MultiSource/Benchmarks/MiBench/telecomm-FFT/telecomm-fft - 12%
Largest slowdowns:
SingleSource/Benchmarks/Stanford/Bubblesort - 23%
MultiSource/Benchmarks/Prolangs-C++/city/city - 21%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - 16%
MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode - 13%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158719 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| ac81cc3282750d724f824547bc519caec0a01bce |
19-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for generating reg+reg preinc stores on PPC.
PPC will now generate STWUX and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 2741d2cfdff89e45c6b98cd520d5cd3fe97829ad |
16-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup trip-count finding for PPC CTR loops (and some bug fixes).
This cleans up the method used to find trip counts in order to form CTR loops on PPC.
This refactoring allows the pass to find loops which have a constant trip count but also
happen to end with a comparison to zero. This also adds explicit FIXMEs to mark two different
classes of loops that are currently ignored.
In addition, we now search through all potential induction operations instead of just the first.
Also, we check the predicate code on the conditional branch and abort the transformation if the
code is not EQ or NE, and we then make sure that the branch to be transformed matches the
condition register defined by the comparison (multiple possible comparisons will be considered).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158607 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 79248299f6ca12926088a4adebbbbe00b05a2642 |
13-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add another missing 64-bit itinerary definition for the PPC A2 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158393 91177308-0d34-0410-b5e6-96231b3b80d8
PCScheduleA2.td
|
| 04dccea2c352e752e2823fac51051dd4ae0d8e67 |
12-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add some missing 64-bit itinerary definitions for the PPC A2 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158373 91177308-0d34-0410-b5e6-96231b3b80d8
PCScheduleA2.td
|
| 16803097fbefa313fdadc3adede659bd0e52cec1 |
12-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Split out the PPC instruction class IntSimple from IntGeneral.
On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158366 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
PCSchedule.td
PCSchedule440.td
PCScheduleA2.td
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
|
| 6670c82df5ef7b97862ef2a0807aa835498b7306 |
12-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fixes for PPC host detection and features.
POWER4 is a 64-bit CPU (better matched to the 970).
The g3 is really the 750 (no altivec), the g4+ is the 74xx (not the 750).
Patch by Andreas Tobler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158363 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| 4db738ae9862a2d00e2dca5b8fbf9d4dfa706142 |
12-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Reapply r158337, this time properly protect Darwin/PPC host CPU use with __ppc__.
Original commit message:
Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName().
Both the new Linux functionality and the old Darwin functions have been moved.
This change also allows this information to be queried directly by clang and
other frontends (clang, for example, will now have real -mcpu=native support).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158349 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 138c2b4e8a4480f4d956980b24c504c27e18cfc1 |
12-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r158337 "Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName()."
This commit broke most of the PowerPC unit tests when running on
Intel/Apple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158345 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 7bb39d861297398e62e2aed6dda3e80d82c453cd |
12-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName().
Both the new Linux functionality and the old Darwin functions have been moved.
This change also allows this information to be queried directly by clang and
other frontends (clang, for example, will now have real -mcpu=native support).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158337 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 5a53c6e3452229759ad0b2d995bc7e37c167b631 |
11-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Enable MFOCRF generation on the PPC A2 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158324 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| bd5cafd9bbba2180e7179436fb29071201d5ea9f |
11-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Rename the PPC target feature gpul to mfocrf.
The PPC target feature gpul (IsGigaProcessor) was only used for one thing:
To enable the generation of the MFOCRF instruction. Furthermore, this
instruction is available on other PPC cores outside of the G5 line. This
feature now corresponds to the HasMFOCRF flag.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158323 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
PCSubtarget.cpp
PCSubtarget.h
|
| 9770be91de745e4727c65c45d13de2a787aef89f |
11-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add A2 to the list of PPC CPUs recognized by Linux host CPU-type detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158322 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 0a1852b7748212632dc105670fda34c41311fa1e |
11-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Emit the two-operand form of the PPC mfcr instruction as mfocrf.
This is necessary on Linux and supported on Darwin, see PR2604.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158315 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 2bd0acd2506c664573d2f0d7671932101c46899e |
11-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add local CPU detection for Linux PPC.
This functionality mirrors that available on PPC/Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158314 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 622382fc5effb34ccad6e029c9612c598a3dc050 |
11-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add POWER6 and POWER7 CPU types to the PPC backend.
No functional change; these will be used by upcoming scheduler enhancements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158313 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCAsmPrinter.cpp
PCSubtarget.h
|
| 71ffcfe9f8602785d4d9133e029c37f2fac78cc3 |
10-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Enable ILP scheduling for all nodes by default on PPC.
Over the entire test-suite, this has an insignificantly negative average
performance impact, but reduces some of the worst slowdowns from the
anti-dep. change (r158294).
Largest speedups:
SingleSource/Benchmarks/Stanford/Quicksort - 28%
SingleSource/Benchmarks/Stanford/Towers - 24%
SingleSource/Benchmarks/Shootout-C++/matrix - 23%
MultiSource/Benchmarks/SciMark2-C/scimark2 - 19%
MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - 15%
(matrix and automotive-bitcount were both in the top-5 slowdown list from the
anti-dep. change)
Largest slowdowns:
MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28%
MultiSource/Benchmarks/mediabench/gsm/toast/toast - 26%
MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan - 21%
SingleSource/Benchmarks/CoyoteBench/lpbench - 20%
MultiSource/Applications/d/make_dparser - 16%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158296 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 01a90f4f8fc7187883377f69e2725ab5e23cc393 |
10-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Use critical anti-dep. breaking on all PPC targets, but also add other register classes.
Using 'all' instead of 'critical' would be better because it would make it easier to
satisfy the bundling constraints, but, as noted in the FIXME, that is currently not
possible with the crs.
This yields an average 1% speedup over the entire test suite (on Power 7). Largest speedups:
SingleSource/Benchmarks/Shootout-C++/moments - 40%
MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28%
SingleSource/Benchmarks/BenchmarkGame/nsieve-bits - 26%
SingleSource/Benchmarks/McGill/misr - 23%
MultiSource/Applications/JM/ldecod/ldecod - 22%
Largest slowdowns:
SingleSource/Benchmarks/Shootout-C++/matrix - -29%
SingleSource/Benchmarks/Shootout-C++/ary3 - -22%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - -18%
SingleSource/Benchmarks/Shootout-C++/ary - -17%
MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - -15%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158294 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 0a3e33b633aa645465b6bda0bba82788b0644a01 |
10-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Improve ext/trunc patterns on PPC64.
The PPC64 backend had patterns for i32 <-> i64 extensions and truncations that
would leave self-moves in the final assembly. Replacing those patterns with ones
based on the SUBREG builtins yields better-looking code.
Thanks to Jakob and Owen for their suggestions in this matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158283 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 8bf75ed41c95e50b62a4f8b03552d51ad6e86c7a |
09-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Enable tail merging on PPC.
Tail merging had been disabled on PPC because it would disturb bundling decisions
made during pre-RA scheduling on the 970 cores. Now, however, all bundling decisions
are made during post-RA scheduling, and tail merging is generally beneficial (the
average test-suite speedup is insignificantly positive).
Largest test-suite speedups:
MultiSource/Benchmarks/mediabench/gsm/toast/toast - 30%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - 23%
SingleSource/Benchmarks/Shootout-C++/ary - 21%
SingleSource/Benchmarks/Stanford/Queens - 17%
Largest slowdowns:
MultiSource/Benchmarks/MiBench/security-sha/security-sha - 24%
MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 22%
MultiSource/Applications/JM/ldecod/ldecod - 14%
MultiSource/Benchmarks/mediabench/g721/g721encode/encode - 9%
This is improved by using full (instead of just critical) anti-dependency breaking,
but doing so still causes miscompiles and so cannot yet be enabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158259 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 16b16ac8408f2d775db2110451877e5920032b8c |
08-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Remove the TODO statement in the PPC README re: CTR loops
As Chris points out, this can now be removed!
TODO: check if the associated section on viterbi's inner loop can also be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158224 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 7255d2a8084cb6aa96ea0e5f30acfff76df04ee8 |
08-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Enable PPC CTR loop formation by default.
Thanks to Jakob's help, this now causes no new test suite failures!
Over the entire test suite, this gives an average 1% speedup. The largest speedups are:
SingleSource/Benchmarks/Misc/pi - 108%
SingleSource/Benchmarks/CoyoteBench/lpbench - 54%
MultiSource/Benchmarks/Prolangs-C/unix-smail/unix-smail - 50%
SingleSource/Benchmarks/Shootout/ary3 - 32%
SingleSource/Benchmarks/Shootout-C++/matrix - 30%
The largest slowdowns are:
MultiSource/Benchmarks/mediabench/gsm/toast/toast - -30%
MultiSource/Benchmarks/Prolangs-C/bison/mybison - -25%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - -22%
MultiSource/Applications/d/make_dparser - -14%
SingleSource/Benchmarks/Shootout-C++/ary - -13%
In light of these slowdowns, additional profiling work is obviously needed!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158223 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCTargetMachine.cpp
|
| 7e5631202ab5b5f2097d234d0357bc5b3b7f5530 |
08-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Mark the PPC CTRRC and CTRRC8 register classes as non-allocatable.
Marking these classes as non-alocatable allows CTR loop generation to
work correctly with the block placement passes, etc. These register
classes are currently used only by some unused TCRETURN patterns.
In future cleanup, these will be removed.
Thanks again to Jakob for suggesting this fix to the CTR loop problem!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158221 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 09fdc7baae1b6905fe18df48e2278e74d4e39ccd |
08-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Disable the PPC CTR-Loops pass by default.
The pass itself works well, but the something in the Machine* infrastructure
does not understand terminators which define registers. Without the ability
to use the block-placement pass, etc. this causes performance regressions (and
so is turned off by default). Turning off the analysis turns off the problems
with the Machine* infrastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158206 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCTargetMachine.cpp
|
| daa03ec60475a641bcc66799764977f79997ca45 |
08-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix a bug in the new PPC CTR-Loops pass.
The code which tests for an induction operation cannot assume that any
ADDI instruction will have a register operand because the operand could
also be a frame index; for example:
%vreg16<def> = ADDI8 <fi#0>, 0; G8RC:%vreg16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158205 91177308-0d34-0410-b5e6-96231b3b80d8
PCCTRLoops.cpp
|
| 99f823f94374917174f96a7689955b8463db6816 |
08-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form CTR-based loop branching code.
This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon
pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are
no longer otherwise used. Also, invalid preheader DebugLoc is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PC.h
PCBranchSelector.cpp
PCCTRLoops.cpp
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.cpp
PCInstrInfo.td
PCTargetMachine.cpp
|
| 3e77af4318f48228f626bb92bdf73a38d851ae4d |
05-Jun-2012 |
Roman Divacky <rdivacky@freebsd.org> |
PPC32 uses R2 as the TLS register. Fix the copy and paste.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158004 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| fd42ed676e37c29364f53f848320b7cb706111e0 |
04-Jun-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Implement local-exec TLS on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157935 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
PCMCInstLower.cpp
|
| 77a9e0f318a5454ee86bbf64858860fb6548d7d2 |
04-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix a copy-and-paste duplication error in the PPC 440 and A2 schedules (no functionality change).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157912 91177308-0d34-0410-b5e6-96231b3b80d8
PCSchedule440.td
PCScheduleA2.td
|
| 77838f9ca974bda956f4a93c20bb4307cf0c470f |
04-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Enable generating PPC pre-increment (r+imm) instructions by default.
It seems that this no longer causes test suite failures on PPC64 (after r157159),
and often gives a performance benefit, so it can be enabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157911 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| d2ea0e10cbd158c93fb870cdd03001b9cd1156b8 |
25-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 2e8e5c0eca6f34a94f92824fc713afd6dc329e25 |
20-May-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add a missing PPC 64-bit stwu pattern.
This seems to fix the remaining compile-time failures on PPC64 when
compiling with -enable-ppc-preinc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157159 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| b8f2f29467b86a11e777e2ce071caf15ae6fcf75 |
19-May-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add a FIXME about access to negative stack-pointer offsets on PPC32.
The current code will generate a prologue which starts with something like:
mflr 0
stw 31, -4(1)
stw 0, 4(1)
stwu 1, -16(1)
But under the PPC32 SVR4 ABI, access to negative offsets from R1 is not allowed.
This was pointed out by Peter Bergner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157133 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 918f55fe239f00651e396be841f2b3b6e242f98d |
15-May-2012 |
Jim Grosbach <grosbach@apple.com> |
Allow MCCodeEmitter access to the target MCRegisterInfo.
Add the MCRegisterInfo to the factories and constructors.
Patch by Tom Stellard <Tom.Stellard@amd.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156828 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCCodeEmitter.cpp
CTargetDesc/PPCMCTargetDesc.h
|
| d9b41b339d3a8b35fac73e63ad665140b5bc7bdc |
09-May-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Mark .opd @progbits, thus avoiding a warning from asm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156494 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 |
08-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).
So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 338607ae0ddab00e197222e769748e2e0c0b4e18 |
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the SubRegClasses field from RegisterClass descriptions.
This information in now computed by TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 7c4ce30ea6a9d0410f306e805403dd224c3df65c |
01-May-2012 |
Bill Wendling <isanbard@gmail.com> |
Change the PassManager from a reference to a pointer.
The TargetPassManager's default constructor wants to initialize the PassManager
to 'null'. But it's illegal to bind a null reference to a null l-value. Make the
ivar a pointer instead.
PR12468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155902 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 6a8c7bf8e72338e55f0f9583e1828f62da165d4a |
23-Apr-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.
This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.
This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.
The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().
It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.
It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.
Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.
Patch by Andy Zhang!
Thanks to Jakob and Anton for their reviews.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 413ca0d34bfefbe62946a8febc2a4939f837291e |
20-Apr-2012 |
Gabor Greif <ggreif@gmail.com> |
effectively back out my last change (r155190)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155195 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c77d6781d53d4ebdb5e8dba26f34bd58af1ee7cb |
20-Apr-2012 |
Gabor Greif <ggreif@gmail.com> |
fix obviously bogus (IMO) operand index of the load in asserts
(load only has one operand) and smuggle in some whitespace changes too
NB: I am obviously testing the water here, and believe that the unguarded
cast is still wrong, but why is the getZExtValue of the load's operand
tested against zero here? Any review is appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155190 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c909950c384e8234a7b3c5a76b7f79e3f7012ceb |
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155186 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
|
| a4b00b2db79bb97d29bf6b6e55322a70150527a6 |
19-Apr-2012 |
Gabor Greif <ggreif@gmail.com> |
zap tabs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155128 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ef1a3a25b3398768b9fad5526782675b1a8c128f |
17-Apr-2012 |
Jay Foad <jay.foad@gmail.com> |
Remove unused CCIfSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154921 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
|
| 26c8dcc692fb2addd475446cfff24d6a4e958bca |
04-Apr-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| 9cd5e7a47836a6be3d2c274a5b6b019aaad106ce |
03-Apr-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make PPCCompilationCallbackC function to be static, so there will be no need to issue call via
PLT when LLVM is built as shared library. This mimics the X86 backend towards the approach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153938 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 70272aac56830dc4a86de7bf12e591c812ee285b |
02-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
The binutils for the IBM BG/P are too old to support CFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153886 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
PCTargetMachine.cpp
|
| 466958c2a04a74de99efd3d7e0d5bd81cdf1e1fe |
02-Apr-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153876 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c97ef618d2d849a272a353c2b4343fc5902cd921 |
02-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.
All implementations used the same code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
|
| 7c0b3c1fb6395475e262d66ee403645f0c67dee2 |
02-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
|
| 17463b3ef1a3d39b10619254f12e806c8c43f9e7 |
02-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.h
CTargetDesc/PPCMCTargetDesc.cpp
|
| b66e943d4cfa4a48ad028898d232754ecd3202c1 |
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix some 80-col. violations I introduced with the A2 PPC64 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153852 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCScheduleA2.td
|
| 19aa2b5015205456b42c426ff2559e9b930e285c |
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Enable prefetch generation on PPC64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153851 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| 730acfb413849f05e9735145d6634c4429467ab7 |
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add LdStSTD* itin. for the PPC64 A2 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153850 91177308-0d34-0410-b5e6-96231b3b80d8
PCScheduleA2.td
|
| 3f31d492a5d0fadf11290e8453f8c519a89b1302 |
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Set the default PPC node scheduling preference to ILP (for the embedded cores).
The 440 and A2 cores have detailed itineraries, and this allows them to be
fully used to maximize throughput.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153845 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 800125f3a3f77ed4b71f3fbc5d9c4c830a612c77 |
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add ppc440 itin. entries for LdStSTD*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153844 91177308-0d34-0410-b5e6-96231b3b80d8
PCSchedule440.td
|
| 97c9d4c64c870c1eceb1d6264f2457273e6e0738 |
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores.
Post-RA scheduling gives a significant performance improvement on
the embedded cores, so turn it on. Using full anti-dep. breaking is
important for FP-intensive blocks, so turn it on (just on the
embedded cores for now; this should also be good on the 970s because
post-ra scheduling is all that we have for now, but that should have
more testing first).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153843 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 4d989ac93ce608057fb6b13a4068264ab037ecd5 |
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add instruction itinerary for the PPC64 A2 core.
This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCAsmPrinter.cpp
PCInstrInfo.cpp
PCSchedule.td
PCScheduleA2.td
PCSubtarget.cpp
PCSubtarget.h
|
| 20b529b3f90bf17b6023ed6f8983c53c1f5be1ad |
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.
Loads and stores can have different pipeline behavior, especially on
embedded chips. This change allows those differences to be expressed.
Except for the 440 scheduler, there are no functionality changes.
On the 440, the latency adjustment is only by one cycle, and so this
probably does not affect much. Nevertheless, it will make a larger
difference in the future and this removes a FIXME from the 440 itin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153821 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrInfo.td
PCSchedule.td
PCSchedule440.td
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
|
| 5b00ceaeeabff8c25abb09926343c3fcb06053d8 |
31-Mar-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix dynamic linking on PPC64.
Dynamic linking on PPC64 has had problems since we had to move the top-down
hazard-detection logic post-ra. For dynamic linking to work there needs to be
a nop placed after every call. It turns out that it is really hard to guarantee
that nothing will be placed in between the call (bl) and the nop during post-ra
scheduling. Previous attempts at fixing this by placing logic inside the
hazard detector only partially worked.
This is now fixed in a different way: call+nop codegen-only instructions. As far
as CodeGen is concerned the pair is now a single instruction and cannot be split.
This solution works much better than previous attempts.
The scoreboard hazard detector is also renamed to be more generic, there is currently
no cpu-specific logic in it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153816 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.cpp
PCInstrInfo.td
|
| c89c744b69cecac576317a98322fd295e36e9886 |
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary llvm:: qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f1d0f7781e766df878bec4e7977fa3204374f394 |
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune some includes and forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153429 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| 179a4ddd1fe52a3698a4b87e024250ed508df77a |
24-Mar-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix small-integer VAARG on SVR4 ABI PPC64.
The PPC64 SVR4 ABI requires integer stack arguments, and thus the var. args., that
are smaller than 64 bits be zero extended to 64 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153373 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f2f6182f6a88cf4b8d8cb95686d68aa14ddb6857 |
22-Mar-2012 |
Hal Finkel <hfinkel@anl.gov> |
PPC::DBG_VALUE must use Reg+Imm frame-index elimination even for large offsets. Fixes PR12203.
I don't have a small test case yet, but I'll try to construct one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153240 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 79aa3417eb6f58d668aadfedf075240a41d35a26 |
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
PC.h
PCAsmPrinter.cpp
PCHazardRecognizers.h
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.h
PCRegisterInfo.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| c5eaae4e9bc75b203b3a9922b480729bc4f340e2 |
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more static tables of registers used by calling convention to uint16_t to reduce space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b78ca423844f19f4a838abb49b4b4fa7ae499707 |
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers and opcode in static tables in the target specific backends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCISelLowering.cpp
|
| e46137f498fa81a088f13d24c79242eed3ff45a7 |
06-Mar-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Convert PowerPC to register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152122 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| c6449b636f4984be88f128d0375c056ad05e7e8f |
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Make MCRegisterInfo available to the the MCInstPrinter.
Used to allow context sensitive printing of super-register or sub-register
references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.h
CTargetDesc/PPCMCTargetDesc.cpp
|
| 015f228861ef9b337366f92f637d4e8d624bb006 |
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers in callee saved register tables to reduce size of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 |
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 21a1401413f074ffb216f74f94c5bc7a0e6cc1e1 |
28-Feb-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Properly MCize the section switch, removing a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151639 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 20bd5296cec8d8d597ab9db2aca7346a88e580c8 |
28-Feb-2012 |
Daniel Dunbar <daniel@zuster.org> |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| ec52aaa12f57896fc806e849fa21a61603050ac4 |
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 4328f9f1749698fcf7ec0339666f6129847d258b |
27-Feb-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Reapply r151278 with fixes.
MCize function entry label emission on PowerPC64 properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151547 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 9b4d7088681b3386359497d5806b7365d5f6c39a |
25-Feb-2012 |
Hal Finkel <hfinkel@anl.gov> |
Revert r151278, breaks static linking.
Reverting this because it breaks static linking on ppc64. Specifically, it may be linkonce_odr functions that are the problem.
With this patch, if you link statically, calls to some functions end up calling their descriptor addresses instead
of calling to their entry points. This causes the execution to fail with SIGILL (b/c the descriptor address just
has some pointers, not code).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151433 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 3161039cf3318a1634af04e1da2038e9dc1f4b3a |
24-Feb-2012 |
Hal Finkel <hfinkel@anl.gov> |
X11/X2 loads around indirect calls on ppc64 should not be deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151374 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| ca0af3a971eac682b1a60987831ae84b256ce37a |
23-Feb-2012 |
Roman Divacky <rdivacky@freebsd.org> |
MCize function entry label emission on PowerPC64 properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151278 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| d55a2664f9493a4c3be242a75d339fac0ebe2e21 |
22-Feb-2012 |
Hal Finkel <hfinkel@anl.gov> |
Allow the use of an alternate symbol for calculating a function's size.
The standard function epilog includes a .size directive, but ppc64 uses
an alternate local symbol to tag the actual start of each function.
Until recently, binutils accepted the .size directive as:
.size test1, .Ltmp0-test1
however, using this directive with recent binutils will result in the error:
.size expression for XXX does not evaluate to a constant
so we must use the label which actually tags the start of the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151200 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 44d23825d61d530b8d562329ec8fc2d4f843bb8d |
22-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.h
CTargetDesc/PPCBaseInfo.h
CTargetDesc/PPCMCAsmInfo.cpp
CTargetDesc/PPCMCAsmInfo.h
CTargetDesc/PPCMCTargetDesc.cpp
PC.td
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCallingConv.td
PCCodeEmitter.cpp
PCFrameLowering.cpp
PCFrameLowering.h
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrFormats.td
PCInstrInfo.cpp
PCInstrInfo.h
PCInstrInfo.td
PCJITInfo.h
PCMachineFunctionInfo.cpp
PCPerfectShuffle.h
PCRegisterInfo.cpp
PCRegisterInfo.h
PCRegisterInfo.td
PCRelocations.h
PCSchedule.td
PCSchedule440.td
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.h
|
| 61f1e3db43e556f495b6b9360d2f550291f78471 |
08-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Move pass configuration out of pass constructors: BranchFolderPass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150095 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| bc2198133a1836598b54b943420748e75d5dea94 |
07-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
CTargetDesc/PPCAsmBackend.cpp
PCISelLowering.cpp
PCMCInstLower.cpp
|
| 655b8de7b2ab773a977e0c524307e71354d8af29 |
05-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
|
| 061efcfb3e79899493d857f49e50d09f29037e0a |
04-Feb-2012 |
Andrew Trick <atrick@apple.com> |
TargetPassConfig: confine the MC configuration to TargetMachine.
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.
Sorry for the target header churn. Attempting to stabilize them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 843ee2e6a46b2b2d74a84c2eea68dec35cb359cc |
03-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Added TargetPassConfig. The first little step toward configuring codegen passes.
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 8247e0dca6759d9a22ac4c5cf305fac052b285ac |
03-Feb-2012 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149671 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 4f8dc7b17accf4f2ec953b80b2cc79786207492e |
24-Jan-2012 |
Owen Anderson <resistor@mac.com> |
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCCodeEmitter.cpp
PCCodeEmitter.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| 263109d822314305822796a2cc05e98304793051 |
20-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove a bunch of unused variable assignments.
Found by the clang static analyzer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148541 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 71f0fc1ca88965b69b4b2c8794a7144bc93d4bba |
19-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Ignore register mask operands when lowering instructions to MC.
This is similar to implicit register operands. MC doesn't understand
register liveness and call clobbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCInstLower.cpp
|
| bc3af9b618c061294c7df00f3313f9c5234b8450 |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148401 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| ec3433852dd11e8ff60c9610b4c84468e5935f2b |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. MCAsmBackend naming conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148400 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| 17d2dbd5f9dd6c0de86398178f302ef46ba6ec79 |
17-Jan-2012 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC RLWINM8 vs RLWINM
No test case: output assembly will be identical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148261 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| ed4c8c633c52a40ad1a3e8687f290be4aeb1f0e8 |
15-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148218 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2bd335470f8939782f3df7f6180282d3825d4f09 |
10-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
Remove unnecessary default cases in switches that cover all enum values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
|
| f321e1075eabae96f62b1f2570d9dee5d10b8200 |
07-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove VectorExtras. This unused helper was written for a type of API that is discouraged now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147738 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2e95afa04cd1c89de7e4abaeead66cd8e51ec929 |
30-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup stack/frame register define/kill states. This fixes two bugs:
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).
2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147359 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCRegisterInfo.cpp
|
| f51e95a9f2ce10ca0eb8a353e1fc1d9d49ec130c |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting
it. It does need some some tests...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147154 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCELFObjectWriter.cpp
|
| dcc557f1463107d0f2f6b0099c99593b8fce4e36 |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix cmake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147126 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/CMakeLists.txt
|
| f3a86fb03d196994dc7923351f15d8ed9343013e |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move PPC bits to lib/Target/PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147124 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCELFObjectWriter.cpp
CTargetDesc/PPCMCTargetDesc.h
|
| dc9a8a378daf432d8dcfc178507afe149706f9a6 |
21-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Reduce the exposure of Triple::OSType in the ELF object writer. This will
avoid including ADT/Triple.h in many places when the target specific bits are
moved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| cfb75fba735edd44841eb21c72c3a9736a7d9af2 |
20-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Fix up the CMake build for the new files added in r146960, they're
likely to stay either way that discussion ends up resolving itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 2d24e2a396a1d211baaeedf32148a3b657240170 |
20-Dec-2011 |
David Blaikie <dblaikie@gmail.com> |
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
CTargetDesc/PPCMCAsmInfo.h
PCMachineFunctionInfo.cpp
PCMachineFunctionInfo.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 7f370b615515af6422eb0d5d08f1c4c5db95fbbc |
15-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
Ensure that the nop that should follow a bl call in PPC64 ELF actually does
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146664 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
|
| 63974b2144c87c962effdc0508c27643c8ad98b6 |
13-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b0c594fd422417e1e290da166b566c7bee74644b |
12-Dec-2011 |
Daniel Dunbar <daniel@zuster.org> |
LLVMBuild: Introduce a common section which currently has a list of the
subdirectories to traverse into.
- Originally I wanted to avoid this and just autoscan, but this has one key
flaw in that new subdirectories can not automatically trigger a rerun of the
llvm-build tool. This is particularly a pain when switching back and forth
between trees where one has added a subdirectory, as the dependencies will
tend to be wrong. This will also eliminates FIXME implicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146436 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| 4ab406d7fc06b1272d02cd8be46f0c5ebe51a3da |
12-Dec-2011 |
Daniel Dunbar <daniel@zuster.org> |
LLVMBuild: Remove trailing newline, which irked me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146409 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/LLVMBuild.txt
LVMBuild.txt
CTargetDesc/LLVMBuild.txt
argetInfo/LLVMBuild.txt
|
| fed4d19eddcedf2a210a0ff3a290f4bf70927452 |
10-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146318 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 4a4fdf3476473021f62d5b02e8ee8802f5b25e5a |
08-Dec-2011 |
Owen Anderson <resistor@mac.com> |
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146171 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 67724526447efae608ef3c8cf333cd797efa8737 |
08-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146137 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd |
07-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCISelDAGToDAG.cpp
|
| 234bb38d6c421ea22229087a9835afe99e531276 |
07-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146024 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCInstr64Bit.td
PCInstrInfo.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 6d0e014b1fecb35a06e551165614c08edc30194a |
07-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
make base register selection used in eliminateFrameIndex 64-bit clean
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146023 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| ae37cd0a37ccbdf6ca2ddcc18079b1454d784eb4 |
07-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
set mayStore and mayLoad on CR pseudos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146022 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 7ad6b7d35978e1bb89de90aa732cf2f57377d69d |
07-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
64-bit LR8 load should use X11 not R11
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146021 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| d21e930eac3d99dd77ee33ea5826700b4bc97ae8 |
06-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
add RESTORE_CR and support CR unspills
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145961 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 16588e794c7528c24fb15ee8e28653bffe78c3da |
06-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
remove old FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145960 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 6482e9114954def43fc08e83aadec1aadfc64200 |
06-Dec-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145894 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| 370b78d795154899a22ca2b4674e890661ff1d59 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Move target-specific logic out of generic MCAssembler.
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145881 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
|
| 3fd0018af1b692cabfa5a002bf41f1e756aa9dde |
05-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
enable PPC register scavenging by default (update tests and remove some FIXMEs)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 9489487f9863ca9f0ae9b4572d206910f1c5a581 |
05-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
don't include CR bit subregs in callee-saved list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145818 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 2e313caa3631e2c94bb6d81429b77a30b116b520 |
05-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
add register pressure for CR regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145816 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 8a8d479214745c82ef00f08d4e4f1c173b5f9ce2 |
02-Dec-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
PCISelLowering.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| 826941a0af2c8ef695a6424cc5c712ac3df67f4c |
02-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
remove unneeded FIXME comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145679 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| 64c34e253563a8ba6b41fbce2bb020632cf65961 |
02-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
update PPC 940 hazard rec. to function in postRA mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCInstrInfo.cpp
PCInstrInfo.h
PCSubtarget.cpp
PCSubtarget.h
|
| 32e698cc104f4716dabddeae15133ba1b25969a1 |
01-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145553 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| d782bae970e888572f0458ac05369bbd7752f05a |
29-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build/CMake: Finish removal of add_llvm_library_dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145420 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
nstPrinter/CMakeLists.txt
CTargetDesc/CMakeLists.txt
argetInfo/CMakeLists.txt
|
| 768c65f677af3f05c2e94982043f90a1bfaceda5 |
22-Nov-2011 |
Hal Finkel <hfinkel@anl.gov> |
add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145065 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16 |
16-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
PCISelDAGToDAG.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| 978e0dfe46e481bfb1281e683aa308329e879e95 |
15-Nov-2011 |
Jay Foad <jay.foad@gmail.com> |
Make use of MachinePointerInfo::getFixedStack. This removes all mention
of PseudoSourceValue from lib/Target/.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| d9190c0f148b218ab046deadd0c7ae475414cde5 |
15-Nov-2011 |
Jay Foad <jay.foad@gmail.com> |
Remove some unnecessary includes of PseudoSourceValue.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b8ebca83f4dff04ba21cc97673003f0bd35a2e49 |
12-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144444 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/LLVMBuild.txt
|
| 5ed5506f18fcc0a277c863f7a21b39f58e892ca5 |
11-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144344 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| affc6cf9d2b2b74532ce82027ac4524d1e29a658 |
10-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
llvm-build: Add --native-target and --enable-targets options, and add logic to
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144253 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| c352caf168094c83f05a8010ca14c2e643dbf618 |
10-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
llvm-build: Add an explicit component type to represent targets.
- Gives us a place to hang target specific metadata (like whether the target has a JIT).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144250 91177308-0d34-0410-b5e6-96231b3b80d8
LVMBuild.txt
|
| f4e0d5d83db8bf73328d59d35471d0edd0b984f4 |
09-Nov-2011 |
Devang Patel <dpatel@apple.com> |
Remove unnecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144211 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| d752e0f7e64585839cb3a458ef52456eaebbea3c |
08-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Added invariant field to the DAG.getLoad method and changed all calls.
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0839033cbca20a1d1348bdf1c9f63fb263b248a6 |
08-Nov-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCInstrInfo.cpp: Fix one "unused" warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144071 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| b0d9ce567f5aee3af94c290d7cd52b1582c27b4f |
04-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just
added a layer of indirection with no value (not even conciseness).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143727 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| a3a2dfd4a2a8265a9a0c962cb776e2e6ba123956 |
03-Nov-2011 |
Daniel Dunbar <daniel@zuster.org> |
build: Add initial cut at LLVMBuild.txt files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/LLVMBuild.txt
LVMBuild.txt
CTargetDesc/LLVMBuild.txt
argetInfo/LLVMBuild.txt
|
| 95c885d65a0da92f6661fd160d8ce13b30e3892c |
29-Oct-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
PPC: Disable moves for all CR subregisters.
Should fix assertion failures on ppc buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143290 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 15701f8969fcb36899a75ca2df6fdcbc52141106 |
27-Oct-2011 |
Lang Hames <lhames@gmail.com> |
Rename NonScalarIntSafe to something more appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143080 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| ed8db320af68556de5fcfe2cbec688003acc33f5 |
21-Oct-2011 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142630 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 5bdab4a63cab2ed2f96a3490fa2349550da7c7f9 |
20-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Disable the PPC hazard recognizer. It currently only supports
top-down scheduling and top-down scheduling is going away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142621 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| c61291609d5d2044fa9f9fdcb1fe22cfd7c998e2 |
17-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Revert change to function alignment b/c existing logic was fine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142224 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e9e579155614654665ef7a4e3aa5c7a8d4a49f01 |
17-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Remove >80-col line and unicode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142209 91177308-0d34-0410-b5e6-96231b3b80d8
PCSchedule440.td
|
| 98daa9dcc8cf5bf87f06a085793c543c035313d9 |
17-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Instructions for Book E PPC should be word aligned, set function alignment to reflect this
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142194 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b31d3d271f75c17593e917575dc324b50615a630 |
17-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC 440 scheduler and some associated tests (new files)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142171 91177308-0d34-0410-b5e6-96231b3b80d8
PCSchedule440.td
|
| c6d08f10bf797cc78068ef30bd0e8812a5bdc9a2 |
17-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC 440 scheduler and some associated tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCAsmPrinter.cpp
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCInstrInfo.cpp
PCInstrInfo.td
PCSchedule.td
PCSubtarget.cpp
PCSubtarget.h
|
| d712f935f7e027a733741e6ca67b3237a59f65d1 |
14-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Add an implementation of the CanLowerReturn function to the PPC backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141981 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 8ee53e2eb6f669fd69eb146e56c07823cbed99e7 |
14-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
initial test commit (remove whitespace)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141972 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| de8f33c199f3bf2049b0b732169f2bd8717469c6 |
06-Oct-2011 |
Peter Collingbourne <peter@pcc.me.uk> |
Build system infrastructure for multiple tblgens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 01faf432d9d81212b492f326594d43a951fe64f0 |
04-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach PPCInstrInfo to handle sub-classes.
This has already been done for most other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141083 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 519020adf1cf57e2e93cc4fd49c385c47f7ff0f7 |
21-Sep-2011 |
Owen Anderson <resistor@mac.com> |
These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140267 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
|
| 317eaf19937813d630166bfec7b933a98ea89aa5 |
21-Sep-2011 |
Owen Anderson <resistor@mac.com> |
In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140217 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
|
| 98c5ddabca1debf935a07d14d0cbc9732374bdb8 |
16-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
|
| b950585cc5a0d665e9accfe5ce490cd269756f2e |
07-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
|
| 28b77e968d2b01fc9da724762bd8ddcd80650e32 |
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 4a544a79bd735967f1d33fe675ae4566dbd17813 |
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 36a16015ac108e2f0dd2d6d96a6d364bc74c50d7 |
02-Sep-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Don't drop alignment info on local common symbols.
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138976 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
|
| 0aaa9195b53e693eb8618fef305e3799b5b77771 |
30-Aug-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Set CR1EQ only when lowering vararg floating arguments (not any vararg
arguments as before), unset CR1EQ otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138802 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| 4db5acaf48c119b2bb7ad93b10dfcfe8b58dcfdb |
29-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138751 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 |
24-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCMCTargetDesc.cpp
PCAsmPrinter.cpp
PCInstrInfo.cpp
PCSubtarget.cpp
PCTargetMachine.cpp
argetInfo/PowerPCTargetInfo.cpp
|
| 7801136b95d1fbe515b9655b73ada39b05a33559 |
23-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Some refactoring so TargetRegistry.h no longer has to include any files
from MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
|
| 26689ac37ebec3b358588089415509285e558de9 |
03-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 29630ff214085365d11f1a58251ba07326e21398 |
02-Aug-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Remove trailing semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136690 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
|
| 2c0d69fad0e658117922f3d96d9b732bedf9fd47 |
02-Aug-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Sketch out PowerPC ELF writer. This is enough to get clang -integrated-as
to compile a working hello world on FreeBSD/PPC32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136689 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCMCTargetDesc.cpp
|
| 81fd0ba8ab153b8344527a461545dbd87642ed83 |
01-Aug-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Actually finish switching to the new system for Target sublibrary
TableGen deps introduced in r136023. This completes the fixing that
dgregor started in r136621. Sorry for missing these the first time
around.
This should fix some of the random race-condition failures people are
still seeing with CMake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136643 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/CMakeLists.txt
|
| 8ead80db20ec05fd8e613084abfdb8714703fc5f |
01-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Set endianess and pointer size for PPC Linux. Bug noticed by Roman Divacky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136639 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
|
| ac03e736c77bcf7e8deb515fc16a7e55d343dc8d |
29-Jul-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.
I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.
This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.
This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.
Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.
This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136433 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
nstPrinter/CMakeLists.txt
CTargetDesc/CMakeLists.txt
argetInfo/CMakeLists.txt
|
| 4ebc5916e9b3a43af8aff8e1b8744b1644457a4b |
28-Jul-2011 |
Oscar Fuentes <ofv@wanadoo.es> |
Explicitly declare a library dependency of LLVM*Desc to
LLVM*AsmPrinter.
GenLibDeps.pl fails to detect vtable references. As this is the only
referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized
builds, the algorithm that creates the list of libraries to be linked
into tools doesn't know about the dependency and sometimes places the
libraries on the wrong order, yielding error messages like this:
../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function
`llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)':
ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE
[llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo
const&)]+0x2a): undefined reference to `vtable for
llvm::ARMInstPrinter'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136328 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/CMakeLists.txt
|
| 14648468011c92a4210f8118721d58c25043daf8 |
28-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Code generation for 'fence' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 28c85a81a17dd719a254dc00cbeb484774893197 |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136031 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
|
| 06825978176a1438578ab0bf538e705de6a295c1 |
26-Jul-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Remove a file from CMakeLists.txt that Evan removed in r136027.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136030 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 94b9550a32d189704a8eae55505edf62662c0534 |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
CTargetDesc/CMakeLists.txt
CTargetDesc/PPCPredicates.cpp
CTargetDesc/PPCPredicates.h
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
PCPredicates.cpp
PCPredicates.h
|
| b35552d440581265a982d7523c33e7466437bfb0 |
26-Jul-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.
These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.
To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.
This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.
Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136023 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
nstPrinter/CMakeLists.txt
CTargetDesc/CMakeLists.txt
|
| 78c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5c |
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136010 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCMCTargetDesc.cpp
CTargetDesc/PPCMCTargetDesc.h
|
| 4b64e8a9e13ba782da2034e1dee52f077bdb759c |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Separate MCInstPrinter registration from AsmPrinter registration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135974 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
PCAsmPrinter.cpp
|
| 54134708f5debe1631f9ea9b232f78758a2151e4 |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135954 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCBaseInfo.h
PC.h
|
| b024572444d19a6e06624328ea6a75a2f3342eaf |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Missed a file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135943 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCBaseInfo.h
|
| 966aeb5788c242cfaca35c56c0ddc0ff778d4376 |
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Refactor PPC target to separate MC routines from Target routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135942 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
CTargetDesc/CMakeLists.txt
CTargetDesc/PPCAsmBackend.cpp
CTargetDesc/PPCFixupKinds.h
CTargetDesc/PPCMCCodeEmitter.cpp
CTargetDesc/PPCMCTargetDesc.cpp
CTargetDesc/PPCMCTargetDesc.h
PC.h
PCAsmBackend.cpp
PCCodeEmitter.cpp
PCFixupKinds.h
PCFrameLowering.cpp
PCInstrInfo.cpp
PCMCCodeEmitter.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
PCTargetMachine.cpp
|
| d5601cc810486e6ca9b5bfb3634455061eb10f07 |
24-Jul-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Set PPCII::MO_DARWIN_STUB only on MacOSX < 10.5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135866 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a7cfc08ebe737062917b442830eb5321b0f79e89 |
23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135833 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 7f8dff65717b1e4090ba4a648f9ec4f037a66c1e |
23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
createXXXMCCodeGenInfo should be static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135826 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
|
| e78085a3c03de648a481e9751c3094c517bd7123 |
22-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135812 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
|
| 34ad6db8b958fdc0d38e122edf753b5326e69b03 |
20-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
code model for JIT. This eliminates the ugly hack in TargetMachine where
code model is changed after construction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| 439661395fd2a2a832dba01c65bc88718528313c |
19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| 2d28617de2b0b731c08d1af9e830f31e14ac75b4 |
19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for
better location welcome).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
PCFrameLowering.cpp
PCFrameLowering.h
PCRegisterInfo.cpp
|
| 0e6a052331f674dd70e28af41f654a7874405eab |
18-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCTargetDesc.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| db125cfaf57cc83e7dd7453de2d509bc8efd0e5e |
18-Jul-2011 |
Chris Lattner <sabre@nondot.org> |
land David Blaikie's patch to de-constify Type, with a few tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 1be0e271a07925b928ba89848934f1ea6f1854e2 |
15-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatest
solution but it is a small step towards removing the horror that is
TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135237 91177308-0d34-0410-b5e6-96231b3b80d8
CTargetDesc/PPCMCAsmInfo.cpp
|
| 1abf2cb59b8d63415780a03329307c0997b2670c |
15-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
CTargetDesc/CMakeLists.txt
CTargetDesc/PPCMCAsmInfo.cpp
CTargetDesc/PPCMCAsmInfo.h
CTargetDesc/PPCMCTargetDesc.cpp
PCMCAsmInfo.cpp
PCMCAsmInfo.h
PCTargetMachine.cpp
|
| c60f9b752381baa6c4b80c0739034660f1748c84 |
14-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
CTargetDesc/CMakeLists.txt
CTargetDesc/Makefile
CTargetDesc/PPCMCTargetDesc.cpp
CTargetDesc/PPCMCTargetDesc.h
akefile
PC.h
PCInstrInfo.cpp
PCRegisterInfo.cpp
PCSubtarget.cpp
|
| af0a2e6730ffb59405352269e1500b6e83e42d6a |
11-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Most MCCodeEmitter's don't meed MCContext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134922 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| 59ee62d2418df8db499eca1ae17f5900dc2dcbba |
11-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCInstrInfo.cpp
PCMCCodeEmitter.cpp
PCSubtarget.cpp
|
| ffc0e73046f737d75e0a62b3a83ef19bcef111e3 |
09-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 33390848a7eca75301d04a59b89b516d83e19ee0 |
08-Jul-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ebdeeab812beec0385b445f3d4c41a114e0d972f |
08-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
to generate asm matcher subtarget feature queries. e.g.
"ModeThumb,FeatureThumb2" is translated to
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCTargetMachine.cpp
|
| 0ddff1b5359433faf2eb1c4ff5320ddcbd42f52f |
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Compute feature bits at time of MCSubtargetInfo initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
|
| b262799d49891b036daa00eddf51947487346c98 |
06-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
createMCInstPrinter doesn't need TargetMachine anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134525 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.h
PCAsmPrinter.cpp
|
| cbb11869c47bdf8f3fa540dc0ee44075c0da8598 |
04-Jul-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Remove accidentaly left node from previous iteration of the patch.
Noticed by Benjamin Kramer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134376 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b272332e6120413b13dcaef7a5415783a99df073 |
03-Jul-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Make the i64 and f64 be 64bit ABI aligned in the target description.
This is what both the ABI and clang says.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134367 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 385e930d55f3ecd3c9538823dfa5896a12461845 |
02-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
akefile
PCSubtarget.cpp
PCSubtarget.h
|
| 5b1b4489cf3a0f56f8be0673fc5cc380a32d277b |
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
|
| 94214703d97d8d9dfca88174ffc7e94820a85e62 |
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
|
| 4db3cffe94a5285239cc0056f939c6b74a5ca0b6 |
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 276365dd4bc0c2160f91fd8062ae1fc90c86c324 |
30-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.
The fix is to just have the clients explictly pass the CPU name!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| ab8be96fd30ca9396e6b84fdddf1ac6208984cad |
29-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| d5b03f252c0db6b49a242abab63d7c5a260fceae |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 6844f7bcdec8c2691c8d1067d90e4a02cf658c27 |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide more details in tablegen generated MCRegisterInfo ctor function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 22fee2dff4c43b551aefa44a96ca74fcade6bfac |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
akefile
PC.h
PCInstrInfo.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCInstrInfo.cpp
|
| bdb226ec83adf2e052f80f31ead21006b240c82f |
28-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Implement ISD::VAARG lowering on PPC32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134005 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 |
27-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
akefile
PC.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| ba8297ec08cdf7ae0c1e0c18ce07922e1f822643 |
25-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Refactor MachO relocation generaration into the Target directories.
Move the target-specific RecordRelocation logic out of the generic MC
MachObjectWriter and into the target-specific object writers. This allows
nuking quite a bit of target knowledge from the supposedly target-independent
bits in lib/MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133844 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d |
24-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
akefile
PCRegisterInfo.cpp
|
| 8e9d6720c3b62ad45bb97d43b47867a3097b433a |
20-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Don't apply on PPC64 the 32bit ADDIC optimizations as there's no overflow
with 32bit values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133439 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 951cd021c10966f3ae146588b2466deaef730cb6 |
17-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Fix a few places where 32bit instructions/registerset were used on PPC64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133260 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCRegisterInfo.cpp
|
| f28987b76e758b5f2fcc2c5d2c8e073df54ca91e |
16-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| e355b80194ac5c908cecbecd6f3c137b2c9802cb |
15-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Make PPC64CompilationCallback compilable no non-darwin platforms.
Patch by Nathan Whitehorn!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133059 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 4e3adfde653e8216a7f6faa726775f63f16e28d2 |
15-Jun-2011 |
Eli Friedman <eli.friedman@gmail.com> |
PR10136: fix PPCTargetLowering::LowerCall_SVR4 so that a necessary CopyToReg doesn't appear to be dead.
Roman, since you're writing tests for other PPC-SVR4 vararg-related stuff, would you mind writing a test for this?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133018 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a1000742d28f33dd8dd9858e64282e7749c0bd64 |
09-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Fix emission of PPC64 assembler on non-darwin platforms by splitting
VK_PPC_{HA,LO}16 into darwin and gas variants.
Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132802 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCMCInstLower.cpp
|
| 2a9d1ca9c244aeac98044a5fc9a081ff3df7b2ff |
09-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove custom allocation order boilerplate that is no longer needed.
The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.
Some targets still use custom allocation orders:
ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.
X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.
SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 471e4224809f51652c71f319532697a879a75a0d |
09-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Add a parameter to CCState so that it can access the MachineFunction.
No functional change.
Part of PR6965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0c9b559bfd0b476c2dde787285a1195f3142c423 |
03-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.
- Check for MTCTR8 in addition to MTCTR when looking up a hazard.
- When lowering an indirect call use CTR8 when targeting 64bit.
- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.
The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132552 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstr64Bit.td
|
| 100c83341676d8aae8fc34b5452563ed08b14f3e |
03-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| cde4ce411b1ace4a80ea1dd38df97e8508aed0c9 |
02-Jun-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't hardcode the %reg format in the streamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132451 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
|
| 6e032942cf58d1c41f88609a1cec74eb74940ecd |
30-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use the dwarf->llvm mapping to print register names in the cfi
directives.
Fixes PR9826.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
PCFrameLowering.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 67dc11352df491a6be79b615f0920ff377bcae5d |
30-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Split ppc dwarf regnums into ppc64 and ppc32 flavours.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132315 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| 11fd5c0cd989010a2dfa59c75e3d5a5d2a970300 |
29-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Dwarf register 0 is r0, remove incorrect entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132276 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 25b15d8502cf80e8dd332ba359ae2690885e4505 |
27-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove DwarfRegNum from the individual bits of the condition register.
These should be DW_OP_bit_piece of CR (64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132192 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| a5e62019d771fd0b01311cc0136e64b66b299eb1 |
26-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix some dwarf register numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132136 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| fc2bb8c4448fa884d79e437cc2d2627a7d7740a8 |
25-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Replace the -unwind-tables option with a per function flag. This is more
LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132033 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| d76773a22169fae235be98df7034bc2544492333 |
19-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131627 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0113e4e3f242fef41e6c733d1945f9950276cc9c |
19-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointless
piclabel operand. The operand in the tablegen definition doesn't actually turn
into an MI operand, so it just confuses anything checking the TargetInstrDesc
for the number of operands. It suffices to just have an implicit def of LR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131626 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| fc5d305597ea6336d75bd7f3b741e8d57d6a5105 |
06-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make the logic for determining function alignment more explicit. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 108709d4d1ff02317972956540dad571bdf43e95 |
05-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move PPC Linux to CFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130951 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 2866edf1204133b4627358d9d5ccd80a4b699cf1 |
02-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add 130690 back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130693 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| b2d7336fde9bc545dbcf5f47d4d1140f28a8918e |
02-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert while I debug the tests that use march but not mtriple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130691 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 433771c514fbb871f251119f3815c45b29385dc6 |
02-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move ppc OS X to cfi too. I am building it on an old ppc mini, but it will take some time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130690 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 558692fd0a31d4d3ae4fd09a3a02f80da2e44e5c |
20-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OS
triple component.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129838 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCSubtarget.h
|
| 912225e18559a73228099330a4c253fdccf9fa3d |
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()
predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129816 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCTargetMachine.cpp
|
| 18a0929a7a0b87cc50565250e33c33925a57d498 |
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
Target/PPC: Kill off DarwinVers, which is now dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129811 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
|
| 14e2a90b7b0bb4e53e0e66866575d143ce5997b4 |
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
Target/PPC: Eliminate a use of getDarwinVers().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129810 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 869eca129b2560a59b8aa0e8fd57b5d8f7de1f96 |
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
Target/PPC: Add a TargetTriple field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129809 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 5fcb81dace175106024941b09fa27aecba2d7db7 |
04-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Insert code in the right location when lowering PowerPC atomics.
This causes defs to dominate uses, no instructions after terminators, and other
goodness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128836 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| cf3a74824f7c8936fc5c2ebb8ec215621963844e |
04-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
PowerPC atomic pseudos clobber CR0, they don't read it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128829 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 2684c5db84479456b2ff8264df6f414c9d240fa1 |
04-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use X0 instead of R0 for the zero register on ppc64.
The 32-bit R0 cannot be used where a 64-bit register is expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128828 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a5c177e70a42f48e4885075c4c48aad0816a2817 |
21-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
We need to pass the TargetMachine object to the InstPrinter if we are printing
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.
This is part of a work-in-progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127986 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.h
PCAsmPrinter.cpp
|
| 95771afbfd604ad003fa3723cac66c9370fed55d |
25-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 68e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1 |
22-Feb-2011 |
Devang Patel <dpatel@apple.com> |
Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working.
- The debugger needs to be aware of prolog_end attribute attached with line table entries.
- The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 00d78f1348a5980a276bed8f9be09ce2412a6a12 |
20-Feb-2011 |
Oscar Fuentes <ofv@wanadoo.es> |
Use explicit add_subdirectory's for LLVM target sublibraries instead
of testing for its presence at cmake time.
This way the build automatically regenerates the makefiles when a svn
update brings in a new sublibrary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126068 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| a901129169194881a78b7fd8953e09f55b846d10 |
16-Feb-2011 |
Stuart Hastings <stuart@apple.com> |
Swap VT and DebugLoc operands of getExtLoad() for consistency with
other getNode() methods. Radar 9002173.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125665 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e9a7ea68653689966417443b8ac2528c1d9d3ccf |
31-Jan-2011 |
Devang Patel <dpatel@apple.com> |
Keep track of incoming argument's location while emitting LiveIns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 96aa78c8c5ef1a5f268539c9edc86569b436d573 |
23-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for the --noexecstack option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 955ed73d12f2b186ef3f80da872b702cd7f2895b |
18-Jan-2011 |
Jeffrey Yasskin <jyasskin@google.com> |
Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123707 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3965b5e974d57f3e56a2c7f37d76d73e572dfb20 |
14-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add a possibility to switch between CFI directives- and table-based frame description emission. Currently all the backends use table-based stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123476 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 4f28c1c71450c711e96aa283de53739d8b4504cd |
13-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach frame lowering to ignore debug values after the terminators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123399 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameLowering.cpp
|
| 7af6fad0a73f33a6782166676d48073ce8565c47 |
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Update CMake stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123171 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 16c29b5f285f375be53dabaa73e3e91107485fe4 |
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.cpp
PCFrameInfo.h
PCFrameLowering.cpp
PCFrameLowering.h
PCISelLowering.cpp
PCRegisterInfo.cpp
PCRegisterInfo.td
PCTargetMachine.cpp
PCTargetMachine.h
|
| b2581353011673d1241af2d7d334be46088248d8 |
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix the last virtual register enumerations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123102 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2da8bc8a5f7705ac131184cd247f48500da0d74e |
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelDAGToDAG.cpp
PCInstrInfo.cpp
PCInstrInfo.h
|
| 6e8f4c404825b79f9b9176483653f1aa927dfbde |
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelDAGToDAG.cpp
PCInstrInfo.cpp
PCInstrInfo.h
|
| 036609bd7d42ed1f57865969e059eb7d1eb6c392 |
23-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
Flag -> Glue, the ongoing saga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 29d8f0cae425f1bba583565227eaebf58f26ce73 |
23-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
flags -> glue for selectiondag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122509 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| 8e68c3873549ca31533e2e3e40dda3a43cb79566 |
23-Dec-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Change all self assignments X=X to (void)X, so that we can turn on a
new gcc warning that complains on self-assignments and
self-initializations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122458 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| c8bd78c16ba0489835f2eb6101d9bdb96301cfe7 |
18-Dec-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Restore the behavior of frame lowering before my refactoring.
It turns out that ppc backend has really weird interdependencies
over different hooks and all stuff is fragile wrt small changes.
This should fix PR8749
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122155 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.cpp
PCFrameInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| 1ec5bd31fe491e610839ea448bd99fd171785837 |
18-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the MCObjectFormat class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122147 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 7b62afac0a6f967e7466e60ceb26bfdcff2e59f4 |
17-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Target: Remove HasScatteredSymbols target hook variable, which has been
superceded and was effectively dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122024 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 5d05d9769ec98cdee359fd934a56c9455e21232b |
16-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Lift some MachObjectWriter arguments into the target specific
interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121981 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| ae5abd595f5442767313a4c8a24008ad19323ceb |
16-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121973 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 297ed28bf9c633db52ff31115d439a0133b00efb |
16-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
Fix indentation (per style guide).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121972 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| aa4b7dd13ba83152473950d7014a29686dc7eef6 |
16-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121971 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 2761fc427082215c2affcc9d8db8491400bc9e5d |
16-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Move target specific fixup info descriptors to TargetAsmBackend instead of
the MCCodeEmitter, which seems like a better organization.
- Also, cleaned up some magic constants while in the area.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121953 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
PCMCCodeEmitter.cpp
|
| 179821ac1f282ef6f8d24d5ea346028aee8ba4c7 |
06-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the instruction fragment to data fragment lowering since it was causing
freed data to be read. I will open a bug to track it being reenabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121028 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| 0bbe0b440ee2cef47dcb7b281825eb70341c16dd |
06-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Second try at making direct object emission produce the same results
as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc
bootstrap on darwin10 using darwin9's assembler and linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121006 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 5d4918dbd116b0b5e561c431b1ea527ee1b9302a |
04-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
There are two reasons why we might want to use
foo = a - b
.long foo
instead of just
.long a - b
First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.
Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120889 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 3cc52ea33c0b96d1682f14fc45c45b57df0f39b6 |
29-Nov-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
I swear I did a make clean and make before committing all this...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120304 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 94c5ae08750f314bc3cf1bf882b686244a3927d9 |
28-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move more PEI-related hooks to TFI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.cpp
PCFrameInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 36d76a8dbc87b62de82a4a8c0d7cb4bb2a202934 |
27-Nov-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Switch to using MachOFormat.h.
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120187 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| fd46797d0da4970a40f8b5648b8f9b186ce5adb9 |
26-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the unused TheTarget member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120168 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| c62feda741f9d5811b625967c40f1847fb2040e7 |
25-Nov-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Namespacify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120146 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
|
| bf17cfa3f904e488e898ac2e3af706fd1a892f08 |
23-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
EADME.txt
|
| d9e3385ced2dc887e2fe8e1c071bd2611e4d3ede |
19-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move getInitialFrameState() to TargetFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119754 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.cpp
PCFrameInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| d0c38176690e9602a93a20a43f1bd084564a8116 |
18-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move hasFP() and few related hooks to TargetFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.cpp
PCFrameInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
PCRegisterInfo.td
|
| f2dc4aa562e2478a73fe5aeeeec16b1e496a0642 |
17-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
make isVirtualSection a virtual method on MCSection. Chris' suggestion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119547 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmBackend.cpp
|
| b8efa6b475ed2f7d3797a8719cd27ab5fd64ae42 |
16-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Fix a bug I introduced in the ppc refactoring, which caused long
branches to be emitted as:
bne cr0, 2
instead of:
bne cr0, $+8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119317 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 0382a4c98ea8a73cbe2232d71b4bf1303d718274 |
16-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add copy of comment to the code that will survive the mcjit'ization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119308 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| b69cdfa6f3d5a0661354e744a11caa7b3342b83e |
16-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
relax an assertion a bit, allowing the GPR argument of
these instructions to be encoded with getMachineOpValue.
This unbreaks ExecutionEngine/2003-01-04-ArgumentBug.ll
when running on a G5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119307 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCMCCodeEmitter.cpp
|
| bc4434135fca0e0feff89cf6fe3baa25c6bd4ee0 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
fix a pasto that massively broke the ppc jit while the buildbots happened
to be broken for other reasons
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119283 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| b46443a686c29a1aa8f881c48c35d3f61a35f7ac |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Wire up primitive support in the assembler backend for writing .o files
directly on the mac. This is very early, doesn't support relocations and
has a terrible hack to avoid .machine from being printed, but despite
that it generates an bitwise-identical-to-cctools .o file for stuff like
this:
define i32 @test() nounwind { ret i32 42 }
I don't plan to continue pushing this forward, but if anyone else was
interested in doing it, it should be really straight-forward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119136 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PC.h
PCAsmBackend.cpp
PCAsmPrinter.cpp
PCTargetMachine.cpp
|
| b7035d04421112a4585245f67bc564170ec45b29 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
split out an encoder for memri operands, allowing a relocation to be plopped
into the immediate field. This allows us to encode stuff like this:
lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5
; encoding: [0x88,0x64,A,A]
; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16
stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6
; encoding: [0x90,0x65,A,A]
; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16
With this, we should have a completely function MCCodeEmitter for PPC, wewt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119134 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.td
PCMCCodeEmitter.cpp
|
| 17e2c188359769a1df18c42593a94ce0fc2a9a75 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add support for encoding the lo14 forms used for a few PPC64 addressing
modes. For example, we now get:
ld r3, lo16(_G)(r3) ; encoding: [0xe8,0x63,A,0bAAAAAA00]
; fixup A - offset: 0, value: lo16(_G), kind: fixup_ppc_lo14
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119133 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.td
PCMCCodeEmitter.cpp
|
| f3b6e0667996347e8c65e0173352d25d98ff0678 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
fix a regression with the new instprinter: we lost the ability to
print DBG_VALUE instructions. This should unbreak the llvm-gcc-powerpc-darwin9
buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119132 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 85cf7d737dd26e984974e072d28225bd00c625c2 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement the start of support for lo16 and ha16, allowing us to get stuff like:
lis r4, ha16(__ZL4init) ; encoding: [0x3c,0x80,A,A]
; fixup A - offset: 0, value: ha16(__ZL4init), kind: fixup_ppc_ha16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119127 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCFixupKinds.h
PCInstr64Bit.td
PCInstrInfo.td
PCMCCodeEmitter.cpp
|
| b719437325681bec89572cccb53916b7a17f1e60 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add a fixup for conditional branches, giving us output like this:
beq cr0, LBB0_4 ; encoding: [0x41,0x82,A,0bAAAAAA00]
; fixup A - offset: 0, value: LBB0_4, kind: fixup_ppc_brcond14
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119126 91177308-0d34-0410-b5e6-96231b3b80d8
PCFixupKinds.h
PCMCCodeEmitter.cpp
|
| 8d70411dcd5e1af47c3f4fddb993bb93c8eed6d0 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
change direct branches to encode with the same encoding method
as direct calls. Change conditional branches to encode with
their own method, simplifying the JIT encoder and making room
for adding an mc fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119125 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCInstrInfo.td
PCMCCodeEmitter.cpp
|
| 019aef6df791bbccc26b2a18b17ab42aad6aaa0d |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate a now-unneeded operand printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119124 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.h
PCInstrInfo.td
|
| a9d9ab9673ec73817f3059ea430f1930a5b14948 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
split call operands out to their own encoding class, simplifying
code in the JIT. Use this to form the first fixup for the PPC backend,
giving us stuff like this:
bl L_foo$stub ; encoding: [0b010010AA,A,A,0bAAAAAA01]
; fixup A - offset: 0, value: L_foo$stub, kind: fixup_ppc_br24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119123 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCFixupKinds.h
PCInstrInfo.td
PCMCCodeEmitter.cpp
|
| 7192eb873201ff201681fefd1f5bf6ca2b2bc98e |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add proper encoding for MTCRF instead of using a hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119121 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCInstrInfo.td
PCMCCodeEmitter.cpp
|
| a04084e777db923faea0d2c93ce667054fdf576f |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add basic encoding support for immediates and registers, allowing us
to encode all of these instructions correctly (for example):
mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6]
stw r0, 8(r1) ; encoding: [0x90,0x01,0x00,0x08]
stwu r1, -64(r1) ; encoding: [0x94,0x21,0xff,0xc0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119118 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
PCMCCodeEmitter.cpp
|
| a2d602529d4ddde934bde14b43d15a0d009f76d3 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add a dummy entry to fix a build error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119117 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCCodeEmitter.cpp
|
| 5ffe38ef6ae3427b39b2d866ab8d1a73f9f69e56 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Implement a basic MCCodeEmitter for PPC. This doesn't handle
fixups yet, and doesn't handle actually encoding operand values,
but this is enough for llc -show-mc-encoding to show the base
instruction encoding information, e.g.:
mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6]
stw r0, 8(r1) ; encoding: [0x90,0x00,0x00,0x00]
stwu r1, -64(r1) ; encoding: [0x94,0x00,0x00,0x00]
Ltmp0:
lhz r4, 4(r3) ; encoding: [0xa0,0x00,0x00,0x00]
cmplwi cr0, r4, 8 ; encoding: [0x28,0x00,0x00,0x00]
beq cr0, LBB0_2 ; encoding: [0x40,0x00,0x00,0x00]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119116 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
akefile
PC.h
PCMCCodeEmitter.cpp
PCTargetMachine.cpp
|
| 84a04adf3a766c1d40ba100b9b7235531122e468 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
dissolve some more hacks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119115 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
PC.td
|
| 0fe7184ba156c87deee090001ba1d7af05e84fc1 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
fix some fixme's, removing dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119114 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
|
| ab638645647bef87ffe8d545fbcb1b69d3af45ce |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
remove asmstrings (which can never be printed) from pseudo
instructions, allowing is to eliminate some dead operand
printing methods from the instprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119113 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 374c608fcac7fd550ce0cb1826355849a5e015be |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
strength reduce TOC temp label generation, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119112 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| cb22fa6536bd17e54a89dc82cafc9fdf48321c36 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
rip out a ton of old instruction printing junk now that the
new instprinting logic is there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119111 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 3a4dd305ac7a3ddce109b359c8994c1a7868316a |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Turn on the new instprinter by default.
The only change in the output is:
1) we get a better comment on mfcr, we get:
mfcr r2 ; cr2
instead of:
mfcr r2 ; 32
2) we no longer emit $stub's on powerpc/leopard. The Leopard
linker autosynthesizes them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119108 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 6d2ff122af017a24b6e94d4f98f40a3edc0bb62d |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
convert the operand bits into bitfields since they are all combinable in
different ways. Add $non_lazy_ptr support, and proper lowering for
global values.
Now all the ppc regression tests pass with the new instruction printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119106 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCISelLowering.cpp
PCMCInstLower.cpp
|
| 1e61e69d401045c54b15815f15a0fdb3ca56a9b5 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add targetoperand flags for jump tables, constant pool and block address
nodes to indicate when ha16/lo16 modifiers should be used. This lets
us pass PowerPC/indirectbr.ll.
The one annoying thing about this patch is that the MCSymbolExpr isn't
expressive enough to represent ha16(label1-label2) which we need on
PowerPC. I have a terrible hack in the meantime, but this will have
to be revisited at some point.
Last major conversion item left is global variable references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119105 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
PC.h
PCISelLowering.cpp
PCISelLowering.h
PCMCInstLower.cpp
PCSubtarget.cpp
|
| dd57417c08d3fbb52935b70cf14edef34535d045 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
remove some extraneous quotes to make the new instprinter match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119104 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| a460e4a1427260bd46171e674d0a4c41cdd6313f |
15-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Attempt to unbreak cmake-based builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119098 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 33464912237efaa0ed7060829e66b59055bdd48b |
15-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.cpp
PCFrameInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
PCTargetMachine.cpp
|
| 78b4fee8fd040d802e027da7bef3f707b12d8df5 |
15-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119096 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
|
| b908258d59745ab9f150c66f94541951cf9c9211 |
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement support for the MO_DARWIN_STUB TargetOperand flag,
and have isel apply to to call operands as required. This allows
us to get $stub suffixes on label references on ppc/tiger with the
new instprinter, fixing two tests. Only 2 to go.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119093 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCISelLowering.cpp
PCInstrInfo.h
PCMCInstLower.cpp
|
| 749ba48fabc929ae39d750e39231919f2135a500 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
with the picbase nonsense starting to be figured out, implement
lowering support for MovePCtoLR[8]. Down to 4 failures again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119090 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 142b531e024c7b814df74951b378b9e3e11d0d42 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
move the pic base symbol stuff up to MachineFunction
since it is trivial and will be shared between ppc and x86.
This substantially simplifies the X86 backend also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119089 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstr64Bit.td
|
| 6135a96792ca05f6366e5dbaee6208e84589c47f |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement ppc asmprinter "toc" handling to use a VariantKind
on the operand, required for .o file writing and fixing
the PowerPC/mult-alt-generic-powerpc64.ll failure with the new
instprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119087 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstr64Bit.td
|
| 2ead458ae8423d6ecaec7cbd45e1e2c71ce9e618 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
lower PPC::MFCRpseud when transforming to MC, avoiding calling
the aborting printSpecial() method. This gets us to 8 failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119084 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstrInfo.td
|
| 959fb3dd5cfaf2aae44321b58ff87dce4632438d |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
make the stubbed-out printer methods abort instead of
printing nothing. This gets us back up to 24 failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119083 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
|
| b2e477f5463795de8265939300fb5c0abfdded77 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
wire up a few more things, down to 4 test failures, all
about handling $stub, lo/hi etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119082 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
|
| fd6688f59aac65008f1a1ae6ce0529c72288361c |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
properly wire up the instprinter to the ppc64 backend, down to 5 failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119081 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 2e35248f14ac449774de9727b460469fc3c93249 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement pretty printing support for the various pseudo
ops the asmprinter supported, fixing PowerPC/rlwimi2.ll
among others. Down to 20 failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119080 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
|
| 58d014f6031ab95b0057a54dc377e7b0d23d674f |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Wire up symbol hi/lo printing. We don't print hi()/lo(), but this gets
us further along. Only 28 failures now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119079 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
|
| 1520fd60950c1c347457b225dbbd72224d4fcd19 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement basic support for symbol operand lowering,
and printing support for call operands. Down to 77 failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119078 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
PCMCInstLower.cpp
|
| a7217c824d512d6a80fbe97b82f4c2e15ec2a338 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
switch PPC to a simplified MCInstLowering model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119074 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCMCInstLower.cpp
PCMCInstLower.h
|
| 8d63ba8260d26a256a082089e8fe8fcd38b5b949 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
fix PPC.h to not pull in TargetMachine.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119072 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
|
| fdb2ded765316ee2ee2f796b0e2befa2c23acd1d |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement basic support for memory operands and crbit operands,
this fixes 3 more ppc tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119065 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
|
| 99889132f3d6b3f5eab80934b3a0f1687904e5a2 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement several trivial operand printers, reducing
failures in CodeGen/PowerPC from 120 -> 117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119063 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
|
| 0d1b7d9e3dd8512b47655af7d8ea738ea1d4ac51 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Implement support for printing register and immediate operands,
add support for darwin vs aix syntax. We now can print instructions
like this:
add r3, r3, r4
blr
and (in aix mode):
add 3, 3, 4
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119062 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
PCAsmPrinter.cpp
|
| 293ef9ae0fd533429dc54d94c895c39a564466f7 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
stub out PPCMCInstLowering, add a new option that uses it and the new
instprinter when -enable-ppc-inst-printer is passed to llc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119061 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PCAsmPrinter.cpp
PCMCInstLower.cpp
PCMCInstLower.h
|
| 60d5b5fdeec64b69c92db60242d3d90b3f978e69 |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
stub out a powerpc MCInstPrinter implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119059 91177308-0d34-0410-b5e6-96231b3b80d8
nstPrinter/CMakeLists.txt
nstPrinter/Makefile
nstPrinter/PPCInstPrinter.cpp
nstPrinter/PPCInstPrinter.h
akefile
PCAsmPrinter.cpp
|
| 0094345184bc0a791f0811c8d7f5b6f9c8296e0f |
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
move PPCAsmPrinter into the main PPC library, like ARM and X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119054 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
smPrinter/Makefile
smPrinter/PPCAsmPrinter.cpp
MakeLists.txt
akefile
PCAsmPrinter.cpp
|
| 1e96bab329eb23e4ce8a0dc3cc6b33a3f03d15bf |
04-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
In the calling convention logic, ValVT is always a legal type,
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1440e8b918d7116c3587cb95f4f7ac7a0a0b65ad |
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Inside the calling convention logic LocVT is always a simple
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 44ab89eb376af838d1123293a79975aede501464 |
29-Oct-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 6abfa46987e4cb47e2d88ea02574c2c082b0625d |
21-Oct-2010 |
Duncan Sands <baldrick@free.fr> |
Remove some variables that are never really used
(gcc-4.6 warns about these).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117021 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 4f9af2ef65febd20e73ef00d868d3fb94db7afd9 |
11-Oct-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
PowerPC varargs functions store live-in registers on the stack. Make sure we use
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.
This fixes PR8357.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116222 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 749dc72bdcf214b1a3e2b4eee37e836a39e6bdea |
10-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix the expansion of va_arg instruction on PPC to know the arg
alignment for PPC32/64, avoiding some masking operations.
llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116168 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bade37bb8b83deefa166776b1b5185c237a42e71 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 63d66eed16a6ee4e838f2f7a4c8299def0722c20 |
29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add support to model pipeline bypass / forwarding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
|
| 3609eb0de2f786ca6917d0388c37c23873dbd247 |
29-Sep-2010 |
Oscar Fuentes <ofv@wanadoo.es> |
Removed a bunch of unnecessary target_link_libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114999 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 52a261b3c1391c5fec399ddeb3fc6ee9541e8790 |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 6229d0acb8f395552131a7015a5d1e7b2bae2111 |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
update a bunch of code to use the MachinePointerInfo version of getStore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114461 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| da2d8e1032eb4c2fefb1f647d7877910b9483835 |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate an old SelectionDAG::getTruncStore method, propagating
MachinePointerInfo around more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114452 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3d6ccfba314ed38e4506dae2781a060e9a3e07ac |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
propagate MachinePointerInfo through various uses of the old
SelectionDAG::getExtLoad overload, and eliminate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114446 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| d1c24ed81c43635d00ff099844a9d0614021a72b |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert the targets off the non-MachinePointerInfo of getLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e72f2027e9116c55a5b39ac72732df8d6c45d37c |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 59db5496f4fc2ef6111569e542f8b65480ef14c1 |
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert targets to the new MF.getMachineMemOperand interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.cpp
|
| 702917d4e836ec8346c05aadbc2c1a461c6c3ca6 |
19-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add a readme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114303 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.h
|
| 17aa68055beed6faa48ca3a995c5b6fdf5092fd4 |
04-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
zap dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
|
| fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341a |
27-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
to try to re-use scavenged frame index reference registers. rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 11bc1652c9447d85204dc6f7c878b9c95e668a96 |
23-Aug-2010 |
Gabor Greif <ggreif@gmail.com> |
tyops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111835 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 23e70ebf352ff4938210711464c68b5a6e46e61c |
17-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fix emacs language spec's, patch by Edmund Grimley-Evans!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
|
| 90c579de5a383cee278acc3f7e7b9d0a656e6a35 |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Reapply r110396, with fixes to appease the Linux buildbot gods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCodeEmitter.cpp
|
| 1f74590e9d1b9cf0f1f81a156efea73f76546e05 |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Revert r110396 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCodeEmitter.cpp
|
| 9ccaf53ada99c63737547c0235baeb8454b04e80 |
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCodeEmitter.cpp
|
| 40e0bad33193112eab0cc40a556ed347e6568cfe |
05-Aug-2010 |
Devang Patel <dpatel@apple.com> |
Implement target specific getDebugValueLocation().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110256 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 0e3a1a8f8fbe34d47c83d19c8b11a3bfdcacad00 |
04-Aug-2010 |
Torok Edwin <edwintorok@gmail.com> |
Use indirect calls in PowerPC JIT.
See PR5201. There is no way to know if direct calls will be within the allowed
range for BL. Hence emit all calls as indirect when in JIT mode.
Without this long-running applications will fail to JIT on PowerPC with a
relocation failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110246 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCSubtarget.cpp
PCSubtarget.h
|
| e3837014d6793cafdeba99c21dd5682f16131fd5 |
02-Aug-2010 |
Eli Friedman <eli.friedman@gmail.com> |
PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109998 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 38cb1381b5ec8c75242650491c2b8e7e8a302665 |
30-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
PPC doesn't supported VLA with large alignment. This was
formerly rejected by the FE, so asserted in the BE; now the FE only
warns, so we treat it as a legitimate fatal error in PPC BE.
This means the test for the feature won't pass, so it's xfail'd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109892 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 04577efaf2263cc50095500348b2b9b791a43bed |
23-Jul-2010 |
Gabor Greif <ggreif@gmail.com> |
fix constness warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109224 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 2062875a7d8f7dd94a20d9e3a298e9e216efb4b5 |
22-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the TargetInstrInfo::GetInstSizeInBytes hook.
ARM/PPC/MSP430-specific code (which are the only targets that
implement the hook) can directly reference their target-specific
instrinfo classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109171 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 78e6e009223a38739797629ca2d217acf86dda93 |
17-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 7431beaba2a01c3fe299c861b2ec85cbf1dc81c4 |
17-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| a90c3f600d5bea9e01722d7df5752f9adfcf4635 |
16-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Emit COPY instead of FMR/FMSD instructions for floating point conversion on
PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108555 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.td
|
| 7a79fcb55b83b8b98b9853c390cc5bf8ce382dd3 |
16-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memory
operands.
Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't
since missing memoperands should not affect correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108540 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 600f171486708734e2b9c9c617528cfc51c16850 |
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 27689b0affee8fb1bfbef11dcc84287b7757cfe8 |
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace copyRegToReg with copyPhysReg for PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108083 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| bcc8017c738e92d9c1af221b11c4916cb524184e |
08-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c9403659a98bf6487ab6fbf40b81628b5695c02e |
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 0d881dabc1a4e1aefad6dd38de166d8358285638 |
07-Jul-2010 |
Devang Patel <dpatel@apple.com> |
Propagate debug loc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 14152b480d09c7ca912af7c06d00b0ff3912e4f5 |
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply r107655 with fixes; insert the pseudo instruction into
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 258c58cc6257cf61c9bdbb9c4cea67ba2691adf0 |
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Revert r107655.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b81c771c0d9ab5a980caf3383932b051eafd1a39 |
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of custom-inserter functions to handle the case where
the pseudo instruction is not at the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ed2ae136d29dd36122d2476801e7d7a86e8301e3 |
03-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCRegisterInfo.cpp
|
| 90c64f4aac95ebfcdeb8ad78a373fdb9e61b002c |
29-Jun-2010 |
Duncan Sands <baldrick@free.fr> |
Remove initialized but otherwise unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107127 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1784d160e4efa75782884d451d0788b9457e67dc |
25-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| e368b460a206fafa0d31d5d059b1779b94f7df8c |
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Eliminate unnecessary uses of getZExtValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3bf912593301152b65accb9d9c37a95172f1df5a |
18-Jun-2010 |
Stuart Hastings <stuart@apple.com> |
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 99405df044f2c584242e711cc9023ec90356da82 |
09-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| 1087f54ddb70bd2a7ab62608161e4a3f0c345935 |
05-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| 3eca98bb3ab1ec27ab8763298c416d282cdaa261 |
05-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| 42d075c4fb21995265961501cec9ff6e3fb497ce |
02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the TargetRegisterClass member from CalleeSavedInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 6f07bd6ae8c2b11e78f351d7751d1e9b32f38a75 |
02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| ca561ffcf320e9dbfafcac5efcee81471f3259c3 |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| b555609e73f5091bf8180c0875fb1fa6c5ad0e7a |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 6a45d681e53a99b4c4f63e0b1664626a596a8151 |
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 4fda9670f0a9cd448d1905ab669421316b8864c5 |
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove NumberHack entirely.
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 33276d95ef4191663d8e6b972481f9faf37ce541 |
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch SubRegSet to using symbolic SubRegIndices
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 09bc0298650c76db1a06e20ca84c1dcb34071600 |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| a1132276e7513aa08e4f099039243b93e029ccf6 |
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are
never used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104517 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 2457f2c66184e978d4ed8fa9e2128effff26cb0b |
22-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 5f07d5224ddc32f405d7e19de8e58e91ab2816bc |
20-May-2010 |
Dale Johannesen <dalej@apple.com> |
The PPC MFCR instruction implicitly uses all 8 of the CR
registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.h
PCInstrInfo.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
|
| b92187a4103dca24c3767c380f63593d1f6161a7 |
14-May-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| effc8c52693d4b65941ff160cc5ab7f87595e2f0 |
14-May-2010 |
Dan Gohman <gohman@apple.com> |
Set isTerminator on TRAP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103778 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| c0c32ae5c2eb2934d51d8edcb3d7fa4e19f50c48 |
14-May-2010 |
Dan Gohman <gohman@apple.com> |
Don't use isBarrier for the PowerPC sync instruction. isBarrier is for
control barriers, not memory ordering barriers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103777 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| ff7a562751604a9fe13efc75bd59622244b54d35 |
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Implement a bunch more TargetSelectionDAGInfo infrastructure.
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
PCSelectionDAGInfo.cpp
PCSelectionDAGInfo.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 746ad69e088176819981b4b2c5ac8dcd49f5e60e |
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 9f2cda73e470673ab63509adc9d096b0a1d13c54 |
05-May-2010 |
Dan Gohman <gohman@apple.com> |
No-ops emitted for scheduling don't correspond with anything in the
user's source, so don't arbitrarily assign them a debug location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103121 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 08673d295056c93628973c5c54724ac294faef88 |
04-May-2010 |
Dale Johannesen <dalej@apple.com> |
Implement builtin_return_address(x) and builtin_frame_address(x)
on PPC for x!=0. 7624113.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102972 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 8c5358c93675b009ba2d57c3a5980f6bc58ba536 |
29-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Make naked functions work on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102657 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 8601a3d4decff0a380e059b037dabf71075497d3 |
29-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| a00adba6a7e9b0f6600cb6c8c627bb0c705d2f59 |
28-Apr-2010 |
Devang Patel <dpatel@apple.com> |
Use MachineOperand::is* predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102472 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| efc3a6348addd7c9158348fa01f4602e0e0b1688 |
26-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Add PPC AsmPrinter handling for target-specific form of
DBG_VALUE, and a cautionary comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102371 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 0965217e74fe07f1451350a80114ab566ced5de0 |
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add PPC specific emitFrameIndexDebugValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102325 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| e566763b1915c7a4821ce95937b763724d271fec |
21-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCRegisterInfo.cpp
|
| f0757b0edc1ef3d1998485d3f74cadaa3f7180a0 |
21-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers on TargetMachine and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101977 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 928eb49cae286c95dceecf4442997dd561c6e3b7 |
18-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
PCSchedule.td
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
|
| 0d805c33d134d88169e3dc4a3272cff9a5713ce7 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to TargetLoweringObjectFile usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101640 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCTargetMachine.h
|
| 1e93df6f0b5ee6e36d7ec18e6035f0f5a53e5ec6 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCMachineFunctionInfo.h
|
| 2329d66a9f961b5ec463640f67ac451645aa6093 |
17-Apr-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Name these stub files consistently with the SPU and PPC targets' conventions.
Also rename the classes appropriately. The CMake build already used these
names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101631 91177308-0d34-0410-b5e6-96231b3b80d8
PCSelectionDAGInfo.cpp
PCSelectionDAGInfo.h
owerPCSelectionDAGInfo.cpp
owerPCSelectionDAGInfo.h
|
| 53c5e42ab9c1a2cce7ad19bb0b4dffe33c9473e6 |
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add skeleton target-specific SelectionDAGInfo files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101564 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
owerPCSelectionDAGInfo.cpp
owerPCSelectionDAGInfo.h
|
| 37f32ee7ffe77d7c2bc1b185802e98979612f041 |
16-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101531 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 82bcd236937b378e56e46bdde9c17a3ea3377068 |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
EnablePPC64RS and EnablePPC32RS are used in multiple files, so they
can't be static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101377 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| b35798347ea87b8b6d36155b211016a7769f01ab |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of namespace polution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101376 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 46510a73e977273ec67747eb34cbdb43f815e451 |
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelLowering.cpp
|
| 22772214de79aa1c5ca38c4fb1da137d8fb30a05 |
08-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
remove the TargetLoweringObjectFileMachO::getMachoSection
api and update clients to use MCContext instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100808 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c3b0c341e731b27b550ee9dcded9c17232b296b8 |
08-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100751 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| e3a601b648e4cbb916e33f969a1b9d3d40b36734 |
08-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
add newlines at end of files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100706 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
|
| 375be7730a6f3dee7a6dc319ee6c355a11ac99ad |
07-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Educate GetInstrSizeInBytes implementations that
DBG_VALUE does not generate code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100681 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| a267b0076e7887f5566e635ba35790f24d4524d9 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
remove the MMI pointer from MachineFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100415 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| fddb7667ca4d8fe83f96b388295849281ddaa5b4 |
05-Apr-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCInstrFormats.td
|
| 90429c487fe62582241ffe0d3e8acce936f2f8bc |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
just have all targets create the DwarfWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100377 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 8e680482c19a2fab185f88a0dea18313e4be70a9 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
simplify various getAnalysisUsage implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100376 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 3d2251361171b1a41bdb2ac71882e69d48617f49 |
05-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the magic AbsoluteDebugSectionOffsets MAI hook,
which is really a property of the section being referenced.
Add a predicate to MCSection to replace it.
Yay for reduction in magic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100367 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| d290505f0f991268d63a5c5d41f7e40a30dc72fd |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
don't reset the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100352 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| b23569aff0a6d2b231cb93cc4acd0ac060ba560f |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
Momentous day: remove the "O" member from AsmPrinter. Now all
"asm printering" happens through MCStreamer. This also
Streamerizes PIC16 debug info, which escaped my attention.
This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100327 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 1841b34f533f6553acd57b0dd92467c5fbf9fb2e |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
finish eliminating uses of O.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100321 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 2dc6fa67ee80c0e948437ec20df1ca6cf5e1c713 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
mcize more of ppc stub printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100320 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 9d7efd3081ef13b4d1ac7e0ad4854e92e5f132ad |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
mcize a bunch more stuff, using EmitRawText for things we
don't have mcstreamer support for yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100319 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 7ad07c46362500f7291a92742569e94fd3538dfd |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
convert the non-MCInstPrinter'ized EmitInstruction
implementations to use EmitRawText instead of writing
directly to "O".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100318 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c75c028a15a13786eee585aa634b4faf694dd00a |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
fix PrintAsmOperand and PrintAsmMemoryOperand to pass down
raw_ostream to print to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100313 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 35c33bd772b3cfb34fdc6b5c9171f955454d0043 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
change a ton of code to not implicitly use the "O" raw_ostream
member of AsmPrinter. Instead, pass it in explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 20adc9dc4650313f017b27d9818eb2176238113d |
04-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0c08d092049c025c9ccf7143e39f39dc4e30d6b4 |
04-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
asmstreamerize the .size directive for function bodies, force clients
of printOffset to pass in a stream to print to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100296 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c7f3ace20c325521c68335a1689645b43b06ddf0 |
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| f28f8bc40eedc6304ab25dd8bed486fa08f51f70 |
02-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Correctly lower memset / memcpy of undef. It should be a nop. PR6767.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100208 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| e754d3fb852abdeaf910c7331eed60f6303597c1 |
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Revert r100191 since it breaks objc in clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e33c848fa481b038d5ad0c7c898c33b2b27ec71e |
02-Apr-2010 |
Mon P Wang <wangmp@apple.com> |
Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 93d6a7e9c21204c52d6efec6c672163e7de79660 |
02-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Teach AnalyzeBranch, RemoveBranch and the branch
folder to be tolerant of debug info following the
branch(es) at the end of a block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 42642d06c915a26af1400de6ce6a53c333e5c247 |
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add comments about DstAlign and SrcAlign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100132 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 94107ba9ceaa199f8e5c03912511b0619c84226d |
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Avoid using floating point stores to implement memset unless the value is zero.
- Do not try to infer GV alignment unless its type is sized. It's not possible to infer alignment if it has opaque type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100118 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 255f20f7f76e4ca1ac1c73294852cb6fcb18c77d |
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix sdisel memcpy, memset, memmove lowering:
1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
ops more effectively.
rdar://7774704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100090 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 5e1b55d67288874f8669621b9176814ce449f8f5 |
31-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Comment the changes for r98218 and friends inside the source code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100031 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 100f090adde26005b9f1eca96871dff52825b27b |
31-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 808bab0169ab7d2e8dfdc72dd2c991cd8ff2396d |
30-Mar-2010 |
Mon P Wang <wangmp@apple.com> |
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 9b97a73dedf736e14b04a3d1a153f10d25b2507b |
30-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Rip out the 'is temporary' nonsense from the MCContext interface to
create symbols. It is extremely error prone and a source of a lot
of the remaining integrated assembler bugs on x86-64.
This fixes rdar://7807601.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99902 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 34247a0f356edf45ae3ad9ce04e1f90a77c6dba7 |
29-Mar-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make isInt?? and isUint?? template specializations of the generic versions. This
makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99838 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCISelDAGToDAG.cpp
PCRegisterInfo.cpp
|
| e4c868ff6aee68e8a447a39013043b3e015683a0 |
28-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix up vnot matching, eliminating a dead pattern, correcting a couple of
patterns that would never match because of bitcast, and eliminating use
of vnot_conv.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99753 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 5d067fe1580772a8e012ff0acc06e21e9b95d340 |
20-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 60e9eac357dc6e6d9396f02b171baf9e70d97649 |
19-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
set SDNPVariadic on nodes throughout the rest of the targets that
need them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 505ad8bed3321bc4b99af8fba4844efe2fe9e67a |
15-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Now that the default for Darwin platforms is to place the LSDA into the TEXT
section, remove the target-specific code that performs this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98580 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PCISelLowering.cpp
PCTargetObjectFile.cpp
PCTargetObjectFile.h
|
| 149add0d2855aee8f5821542c98121c11293ee83 |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
tidy indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98523 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 63d7836267298f5b6cde43f0a89acbabfc109f48 |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
get MMI out of the label uniquing business, just go to MCContext
to get unique assembler temporary labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98489 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 2e9919a5e5fe76f4b1e3290103c4bfd149ebba9c |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Now that DBG_LABEL is updated, we can finally make MachineMove
contain an MCSymbol instead of a label index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98482 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 6ffcccab5191ef1dcde876800c24a1f58b3b7ad8 |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change the DBG_LABEL MachineInstr to always be created
with an MCSymbol instead of an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98481 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCRegisterInfo.cpp
|
| 7561d480953e0a2faa4af9be0a00b1180097c4bd |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change the LabelSDNode to be EHLabelSDNode and make it hold
an MCSymbol. Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID. Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98463 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 1611273351d75b5cbe2a67485bb9831d5916fe26 |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change EH related stuff (other than EH_LABEL) to use MCSymbol
instead of label ID's. This cleans up and regularizes a bunch
of code and makes way for future progress.
Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places. This is very sad and disturbing. :(
One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction. There should not be any
functionality change from doing this, but I'm not an EH expert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98459 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 1b2eb0e8a6aaf034675b17be6d853cb1c666200f |
13-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the now-unneeded context argument of MBB::getSymbol()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98451 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 11d53c129fc9c2a4510605ec0a1696f58750af52 |
13-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
rearrange MCContext ownership. Before LLVMTargetMachine created it
and passing off ownership to AsmPrinter. Now MachineModuleInfo
creates it and owns it by value. This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code. This also allows MachineFunction to
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98450 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 150ae119761df40ca12f5d975a667778a7d011d7 |
12-Mar-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Fix LLVM build when the user specifies CPPFLAGS on the make command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98394 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/Makefile
|
| d62f1b4168d4327c119642d28c26c836ae6717ab |
12-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
inline GetGlobalValueSymbol into the rest its callers and
remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98390 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 53351a175df59c0f8b96011f30842d87046fc9d6 |
12-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
The same situation that effected ARM effects PPC with regards to placing the
LSDA into the TEXT section. We need to generate non-lazy pointers to it on
Mach-O. However, the object the NLP points to may be local to the translation
unit. If so, then the NLP needs to have the value of that object specified
instead of "0", which the linker interprets as "external".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98325 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
MakeLists.txt
PCISelLowering.cpp
PCTargetObjectFile.cpp
PCTargetObjectFile.h
|
| 08d726c912f74d6ea61bea97e7719fc635927dbf |
12-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
MC-ize PPC's asm printing of stubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98300 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| cebae36f57456fe6b0e13726acd1e0250654f02d |
10-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Add a bit along with the MCSymbols stored in the MachineModuleInfo maps that
indicates that an MCSymbol is external or not. (It's true if it's external.)
This will be used to specify the correct information to add to non-lazy
pointers. That will be explained further when this bit is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98199 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 98cdab53c302a2d6686fa428c0e896b1fb195311 |
10-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
set the temporary bit on MCSymbols correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98124 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630 |
09-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| f7b730425fc45a28cafddf6e9907cd89acdae2aa |
09-Mar-2010 |
Dale Johannesen <dalej@apple.com> |
The address of an indirect call must be in R12 on Darwin.
Make it so. (This patch is in LowerCall_Darwin, which seems
to be used by SVR4 code as well; since that doesn't belong here,
I haven't worried about this case.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98077 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b200f1c28ee49fcb7876406fd26debc20cecbc5f |
08-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Fix a bunch of ambiguous patterns which tblgen happens to infer types
for, due to a bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97953 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 7c306da505e2d7f64e160890b274a47fa0740962 |
02-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 46ada19645c981a0b7932487d163f7582074a4d9 |
02-Mar-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove dead parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97536 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a9445e11c553855a6caacbbbf77a9b993ecc651e |
02-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Floating-point add, sub, and mul are now spelled fadd, fsub, and fmul,
respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97531 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 9fa200d2a2360412465bbd6cfb485af2e9d5b1b4 |
27-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove a bogus pattern, which had the same pattern as STDU
but codegen'd differently. This really wanted to use some
sort of subreg to get the low 4 bytes of the G8RC register
or something. However, it's invalid and nothing is testing
it, so I'm just zapping the bogosity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97345 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCInstr64Bit.td
|
| baafcbb4dbbda50d5b811b6888c77fd64d073865 |
26-Feb-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Merge PPC instructions FMRS and FMRD into a single FMR instruction.
This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so
fextend has a pattern.
Also allow folding of memory operands on FMRSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97275 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.td
|
| 243296690ec78fc918762bd73896b09e26537f47 |
26-Feb-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use the right floating point load/store instructions in PPCInstrInfo::foldMemoryOperandImpl().
The PowerPC floating point registers can represent both f32 and f64 via the
two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to
allow cross-class coalescing. This coalescing only affects whether registers
are spilled as f32 or f64.
Spill slots must be accessed with load/store instructions corresponding to the
class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking
at the instruction opcode which is wrong.
X86 has similar floating point register classes, but doesn't try to fold
memory operands, so there is no problem there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97262 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 6d9f86b7735700f8881e0359fa90c33f984ce2d9 |
23-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove a bunch of dead named arguments in input patterns,
though some look dubious afaict, these are all ok.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96899 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 9f036412ac6f66405f07259185bc63153fb8e059 |
21-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
Eliminate some uses of immAllOnes, just use -1, it does
the same thing and is more efficient for the matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96712 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 5994fd0f4d6bbe6955ac07b39e3befb4f5834134 |
16-Feb-2010 |
Dale Johannesen <dalej@apple.com> |
Really reserve R2 on PPC Darwin. PR 6314.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96399 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| a3b1119977857c7e424f83b25b7e1c7c00783429 |
16-Feb-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Drop support for the InReg attribute on the ppc backend. This was used by
llvm-gcc but has been replaced with pad argument which don't need any
special backend support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96312 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
|
| 362dd0bef5437f85586c046bc53287b6fbe9c099 |
15-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move TLOF implementations to libCodegen to resolve layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96288 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCISelLowering.cpp
|
| 9184b25fa543a900463215c11635c2c014ddb623 |
15-Feb-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96285 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 534502d1e9579ceb843860d6fa886fb4265fee94 |
15-Feb-2010 |
David Greene <greened@obbligato.org> |
Remove an assumption of default arguments. This is in anticipation of a
change to SelectionDAG build APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96236 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 15ce1d71f1dca69eff13e5a56e3209558dcc1fc0 |
13-Feb-2010 |
Dale Johannesen <dalej@apple.com> |
Add the problem I just hacked around in 96015/96020.
The solution there produces correct code, but is seriously
deficient in several ways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96039 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| ee25bc294204ef326994d4142dd6bea9605e6a63 |
12-Feb-2010 |
Dale Johannesen <dalej@apple.com> |
This should have gone in with 26015, see comments there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96020 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| c12da8d30a1394847ee4608fcd54daa24b889b37 |
12-Feb-2010 |
Dale Johannesen <dalej@apple.com> |
When save/restoring CR at prolog/epilog, in a large
stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot. Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.
SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.
Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96015 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| f451cb870efcf9e0302d25ed05f4cac6bb494e42 |
10-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Fix "the the" and similar typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCISelDAGToDAG.cpp
|
| 8e089a9e4d6b7aa2b3968c38644f926f60a7c670 |
10-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
print all the newlines at the end of instructions with
OutStreamer.AddBlankLine instead of textually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95734 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCRegisterInfo.cpp
|
| 1797ed50f488f2030f9f9a0ac7426262abf5220a |
08-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Rename the PerformTailCallOpt variable to GuaranteedTailCallOpt to reflect
its current purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95564 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCRegisterInfo.cpp
|
| 2f82ca904a2146a0cafa4c19568ec379ac1aa44f |
06-Feb-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix alignment on ppc linux. This fixes the build of crtend.o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95477 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| d269a6e460a71a6c5c361a26c56c91fdb9486f45 |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
make MachineModuleInfoMachO hold non-const MCSymbol*'s instead
of const ones. non-const ones aren't very useful, because you can't
even, say, emit them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95205 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| d1ff72b8a797304f146e4293db8c814231ea8cb3 |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
rejigger the world so that EmitInstruction prints the \n at
the end of the instruction instead of expecting the caller to
do it. This currently causes the asm-verbose instruction
comments to be on the next line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95178 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 022d9e1cef7586a80a96446ae8691a37def9bbf4 |
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 56591ab218639d8a6e4c756ca37adaf20215c3b6 |
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
refactor code so that LLVMTargetMachine creates the asmstreamer and
mccontext instead of having AsmPrinter do it. This allows other
types of MCStreamer's to be passed in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95155 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 55fed86353fb39924378dc0e5d29cb273f5e2138 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
tidy some targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95146 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
|
| fc89bc903ca068eac7d311158d19ddee25db7154 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
detemplatize the ppc code emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95142 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 5335bce43dbf72ac364bd59a431f7b50f0e413f3 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95141 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCCodeEmitter.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| f1d6b107d2ea4518d240ee93bf4bffd53e71206d |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate all the dead addSimpleCodeEmitter implementations.
eliminate random "code emitter" stuff in Alpha, except for
the JIT path. Next up, remove the template cruft.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95131 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 942619695f4bd77934c09a1cae0fb39ae59edac3 |
02-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 6914b8611a29933bf23928cc539d5c09e48c5543 |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove PPCMachOWriterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95111 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
PCMachOWriterInfo.cpp
PCMachOWriterInfo.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 6c2e8a9217ced50da49fb79c569317a50b101f90 |
30-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
PPC is not ready for sibcall optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94853 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| d49fe1b6bc4615684c2ec71140a21e9c4cd69ce3 |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Give AsmPrinter the most common expected implementation of
runOnMachineFunction, and switch PPC to use EmitFunctionBody.
The two ppc asmprinters now don't heave to define
runOnMachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94722 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 14c38ec2afeaf25c53a50c2c65116aca8c889401 |
28-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Remove the argument from EmitJumpTableInfo, because it doesn't need it.
Move the X86 implementation of function body emission up to
AsmPrinter::EmitFunctionBody, which works by calling the virtual
EmitInstruction method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94716 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| f0356fe140af1a30587b9a86bcfb1b2c51b8ce20 |
27-Jan-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Kill ModuleProvider and ghost linkage by inverting the relationship between
Modules and ModuleProviders. Because the "ModuleProvider" simply materializes
GlobalValues now, and doesn't provide modules, it's renamed to
"GVMaterializer". Code that used to need a ModuleProvider to materialize
Functions can now materialize the Functions directly. Functions no longer use a
magic linkage to record that they're materializable; they simply ask the
GVMaterializer.
Because the C ABI must never change, we can't remove LLVMModuleProviderRef or
the functions that refer to it. Instead, because Module now exposes the same
functionality ModuleProvider used to, we store a Module* in any
LLVMModuleProviderRef and translate in the wrapper methods. The bindings to
other languages still use the ModuleProvider concept. It would probably be
worth some time to update them to follow the C++ more closely, but I don't
intend to do it.
Fixes http://llvm.org/PR5737 and http://llvm.org/PR5735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94686 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 2cf7251d39f28888af06b6f941eabd1d10995382 |
27-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a new AsmPrinter::EmitFunctionEntryLabel virtual function,
which allows targets to override function entry label emission.
Use it to convert linux/ppc to use EmitFunctionHeader().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94667 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 37469d1ac1e96754fdf42a7112d5f2286a5e5d24 |
27-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
ppc/linux isn't ready for this and it was an accident that it was included.
This should fix a bunch of linux buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94643 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 4129ccdb7048ac9bc671c4f47e86e9144235000d |
27-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Switch MSP430, CellSPU, SystemZ, Darwin/PPC, Alpha, and Sparc to
EmitFunctionHeader:
7 files changed, 16 insertions(+), 210 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94630 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 0c439eb2c8397996cbccaf2798e598052d9982c8 |
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| cee63322eaccc2f1067bdf5eab506e440f867da1 |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Eliminate SetDirective, and replace it with HasSetDirective.
Default HasSetDirective to true, since most targets have it.
The targets that claim to not have it probably do, or it is
spelled differently. These include Blackfin, Mips, Alpha, and
PIC16. All of these except pic16 are normal ELF targets, so
they almost certainly have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94585 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| f71cb015c1386ff8adc9ef0aa03fc0f0fc4a6e3e |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a new MachineBasicBlock::getSymbol method, replacing
the AsmPrinter::GetMBBSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94515 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 1e459c446786f46ed865183f1c6adb17e2e8fcea |
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
don't bother setting the AsmPrinter::MF ivar, now that
AsmPrinter::SetupMachineFunction sets it. Note that systemz
and msp430 didn't. Yay for reduced inconsistency! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94510 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 44e87255e9b7a9d8ecb558690db1181882c08045 |
25-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate redundant argument to EmitJumpTableInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94464 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 75f9b4b63a7c271b29897db35f3453fb89a1cac6 |
24-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
linux/ppc does use alignment in bytes, not pow-2. This fixes PR6129.
It looks like linux/arm and linux/mips have the same setting, which
are probably wrong. Someone who cares about ARM and MIPS should
investigate with the testcase in PR6129.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94381 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 43b5f9312d56be400af031f7487a99b75b7b0f97 |
24-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
make -fno-rtti the default unless a directory builds with REQUIRES_RTTI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94378 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/Makefile
akefile
argetInfo/Makefile
|
| 3f6bfdaedaca984c178f1668c1ca08f52d607aee |
24-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
move PR5945 here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94350 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| abb992d6a3d2dc05d3f3c62a367ea8977a7dd070 |
24-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
change the canonical form of "cond ? -1 : 0" to be
"sext cond" instead of a select. This simplifies some instcombine
code, matches the policy for zext (cond ? 1 : 0 -> zext), and allows
us to generate better code for a testcase on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94339 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| a9cf5b3cc9082acee5b6e30e989a667fed286b05 |
23-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94317 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 9eb158d5b4cd4f6fc80912e2dd77bdf13c3ca0e7 |
23-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
mcize lcomm, simplify .comm, extend both to support 64-bit sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94299 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| a5ad93a10a5435f21090b09edb6b3a7e44967648 |
23-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
move the various directive enums out of the MCStreamer class
into a new MCDirectives.h file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94294 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| d4acde2f493891ed082def4850e460c5a7056c7c |
23-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
remove unneeded directive set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94286 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| e73a31f667ad2fe03e25c97ac45b58c30d7f07c3 |
22-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Stop building RTTI information for *most* llvm libraries. Notable
missing ones are libsupport, libsystem and libvmcore. libvmcore is
currently blocked on bugpoint, which uses EH. Once it stops using
EH, we can switch it off.
This #if 0's out 3 unit tests, because gtest requires RTTI information.
Suggestions welcome on how to fix this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94164 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/Makefile
akefile
argetInfo/Makefile
|
| 717ce2b8d81f0c12145248e92c37ee7547276ce2 |
21-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
remove dead .erase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94098 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 26141721d5923e46b46a54aa8e5ce147f8f63699 |
21-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
fix a problem with a missing _, testcase pending.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94095 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 73a1aa0966af7605b5a15585b1b88ffc7dbd3e3e |
20-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate FnStubInfo, using MachineModuleInfoMachO instead.
this makes function stub emission determinstic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94033 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 917d6282567e4d0bb0e0e4ef4b4cd153661fccfa |
20-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
split function stub printing out to its own function,
no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94030 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| d3ec0b5446441f39988db4107cd37f6e7349f399 |
20-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the GVStubs and HiddenGVStubs maps, and use
MachineModuleInfoMachO instead. This eliminates two sources
of nondeterministic output in the ppc backend, but function
stubs are still bad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94029 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 8eeba35babf3114966fc4e6e8522057e46b610db |
20-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
revert 93934, removing the MCAsmInfo endianness bit. I can't
stomache MCAsmInfo having this, and I found a better solution to
this layering issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93985 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| c7b8814bb4f2e6052060d6118d3bc3b66f5c5b0b |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
give MCAsmInfo a 'has little endian' bit. This is unfortunate, but
I really want clients of the streamer to be able to say "emit this
64-bit integer" and have it get broken down right by the streamer.
I may change this in the future, we'll see how it works out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93934 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 74bfe21b50c14c15f55ce3bd5857d65b588fae3c |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Now that we have everything nicely factored (e.g. asmprinter is not
doing global variable classification anymore) and hookized, sink almost
all target targets global variable emission code into AsmPrinter and out
of each target.
Some notes:
1. PIC16 does completely custom and crazy stuff, so it is not changed.
2. XCore has some custom handling for extra directives. I'll look at it next.
3. This switches linux/ppc to use .globl instead of .global. If .globl is
actually wrong, let me know and I'll fix it.
4. This makes linux/ppc get a lot of random cases right which were obviously
wrong before, it is probably now a bit healthier.
5. Blackfin will probably start getting .comm and other things that it didn't
before. If this is undesirable, it should explicitly opt out of these
things by clearing the relevant fields of MCAsmInfo.
This leads to a nice diffstat:
14 files changed, 127 insertions(+), 830 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93858 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 7517b249caa793a9a01e4b6aff9c47fd88a153cc |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add a bool for whether .lcomm takes an alignment instead of basing this on "isdarwin".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93852 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 48d64ba9d846229339b2431b298620cb8a01ffc5 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
hoist handling of external globals and special globals up to common code.
This makes a similar code dead in all the other targets, I'll clean it up
in a bit.
This also moves handling of lcomm up before acquisition of a section,
since lcomm never needs a section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93851 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 71eae713153e564ec743c5c4162ff258c255de78 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
move production of .reference directives for static ctor/dtor list on
darwin into common code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93849 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c1ef06ac5264cb43f148590091606f0ed90a72e9 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
use BSSLocal classifier to identify 'lcomm' data instead of
duplicating the logic (differently) in lots of different targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93847 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 56b1319fbe18e886f7cff415b45df404fac39623 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
now that elf weak bss symbols are handled correctly, simplify a bunch of code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93845 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| a3839bc3714e6a84222f45cf4c0f1a20a88b10cd |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
introduce a section kind for common linkage. Use this to slightly
simplify and commonize some of the asmprinter logic for globals.
This also avoids printing the MCSection for .zerofill, which broke
the llvm-gcc build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93843 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| e1e0f485f9721a0c4236326f32d0a48561a1af7a |
19-Jan-2010 |
Bill Wendling <isanbard@gmail.com> |
Even more explanation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93841 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 6e3be14be4eadd9aefea654611c808eea9eb8aea |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
change an accessor to a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93839 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| aac138e84dee1cb3ffc1035b2a1e4361fe0b4f80 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
Cleanup handling of .zerofill on darwin:
1. TargetLoweringObjectFileMachO should decide if something
goes in zerofill instead of having every target do it.
2. TargetLoweringObjectFileMachO should assign said symbols to
the right MCSection, the asmprinters should just emit to the
right section.
3. Since all zerofill stuff goes through mcstreamer anymore,
MAI can have a bool "haszerofill" instead of having the textual
directive to emit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93838 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 48814681d72242e0179d7100f263952fdf4f51d6 |
18-Jan-2010 |
Bill Wendling <isanbard@gmail.com> |
- Add getLSDAEncoding to the PowerPC backend.
- Greatly improve the comments to the getLSDAEncoding method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93796 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 10b318bcb39218d2ed525e4862c854bc8d1baf63 |
17-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
now that MCSymbol::print doesn't use it's MAI argument, we can
remove it and change all the code that prints MCSymbols to use
<< instead, which is much simpler and cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93695 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 45111d160cf0910030eeb6a949c69273502e5ad5 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
move the mangler into libtarget from vmcore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93664 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 7a2ba94d03b43f41b54872dacd7b2250dde4c7bd |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
rename GetPrivateGlobalValueSymbolStub -> GetSymbolWithGlobalValueBase,
and add an explicit ForcePrivate argument.
Switch FunctionEHFrameInfo to be MCSymbol based instead of string based.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93646 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 75abc68d324158b72c58b5caf2224b1e35ac0c92 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
more string -> sym, getMangledName is now gone from this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93624 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| a40128c3504b1b650fc57882b7b5d8efd3f7de28 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
use symbols instead of strings, eliminating a bunch of getMangledName
calls. Add FIXMEs about a bunch of nondeterminism in stub output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93621 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 76a3c48e68afd51ba51b354c40d34203679476bb |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
simplify some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93619 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 9c09363637c43ce7c28898993c32b9a63ded5b46 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
switch more stuff onto MCSymbols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93608 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 12164414dd3daa6974985eeb2e89bfb93cf07641 |
16-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
MCize a bunch more stuff, eliminating a lot of uses of the mangler
and CurrentFnName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93594 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 13c10c4e49109054281a8e2c074f8c901ab0404a |
15-Jan-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Teach PPC how to replaceMachineCodeForFunction correctly. (Fixes
JITTest.FunctionIsRecompiledAndRelinked.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93475 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 656bb20d61c38966246fbe94afa68f2045841e34 |
13-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
just finish MCizing FnStubInfo which cleans it up and simplifies it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93334 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 59b34fe55fc2aaec2ebc9fd8e62a96e3686fa5c3 |
13-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
don't call getNameWithPrefix repeatedly and unnecesarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93333 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 0b4bad54f64944880eca9331fbb34545adbe7833 |
13-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
properly use MCSymbol to print the strings aquired from getNameWithPrefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93332 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| ee9250bb4f88364511cfda9ae95ad787bff1a72c |
13-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate some uses of Mangler::makeNameProper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93305 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 4813035b726e7f0a3fd17bec437185fc72a50988 |
13-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
change Mangler::makeNameProper to return its result in a SmallVector
instead of returning it in an std::string. Based on this change:
1. Change TargetLoweringObjectFileCOFF::getCOFFSection to take a StringRef
2. Change a bunch of targets to call makeNameProper with a smallstring,
making several of them *much* more efficient.
3. Rewrite Mangler::makeNameProper to not build names and then prepend
prefixes, not use temporary std::strings, and to avoid other crimes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93298 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| ddac70674723ea8c6f115b39b40528f0d0cd76a6 |
07-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
constant materialization could be improved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92921 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| b7339d079d410524f59066b2987fb91f5193dd32 |
06-Jan-2010 |
Dale Johannesen <dalej@apple.com> |
Reenable debug info on PPC. Works well enough to
bootstrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92818 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| e89c510c0a1d94b3176e3f07e85bf4d75bc45086 |
06-Jan-2010 |
Dale Johannesen <dalej@apple.com> |
Make sure debug info hook gets called when emitting
synonyms for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92817 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| e5319202af267acc1bc876d0da993dde5c3dbf8a |
05-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't specify CR sub-registers as implicit defs of BL instructions.
It is enough to give the super registers CR0, CR1, ..., and specifying the
sub-registers as well causes confusion in the liveness computations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92778 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| eeb3a00b84b7767d236ec8cf0619b9217fc247b9 |
05-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Change SelectCode's argument from SDValue to SDNode *, to make it more
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92564 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 3ea3c2461932d96d3defa0a9aa93ffaf631bb19d |
22-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Add more plumbing. This time in the LowerArguments and "get" functions which
return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| cfcb7997ad4a829de4abd55903863db3c9d414ef |
18-Dec-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Fix wrong frame pointer save offset in the 64-bit PowerPC SVR4 ABI.
Patch contributed by Ken Werner of IBM!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91681 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
|
| 3a84dae654630a89a91a73807201b6067c4774ec |
18-Dec-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add support for calls through function pointers in the 64-bit PowerPC SVR4 ABI.
Patch contributed by Ken Werner of IBM!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91680 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 32d7e6ebde29faeea75ecb718b4281414b0eea0b |
15-Dec-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
Change indirect-globals to use a dedicated allocIndirectGV. This lets us
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface. It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91464 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 864e2efce2cb5d02e376933933d96074723fe77c |
05-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 15217e63bce6c161b355b63d6496c7c327d15817 |
30-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90144 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.h
|
| de9b1dae37877f1b31e8cf42a14195c3fffbae3f |
25-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Tail duplicate indirect branches for PowerPC, too.
With the testcase for pr3120, the "threaded interpreter" runtime decreases
from 1788 to 1413 with this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89877 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.h
|
| 0106a0aafe8a169ad39736ddeb591ccde7cdca97 |
25-Nov-2009 |
Dale Johannesen <dalej@apple.com> |
Fix compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89824 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
|
| 7dbc61030975220ac981117056f4acad127abdc0 |
25-Nov-2009 |
Devang Patel <dpatel@apple.com> |
Revert r89803.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89819 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| f7801b493ef94c3a7edf8d57cc564f08fce6e624 |
24-Nov-2009 |
Dale Johannesen <dalej@apple.com> |
Do not store R31 into the caller's link area on PPC.
This violates the ABI (that area is "reserved"), and
while it is safe if all code is generated with current
compilers, there is some very old code around that uses
that slot for something else, and breaks if it is stored
into. Adjust testcases looking for current behavior.
I've verified that the stack frame size is right in all
testcases, whether it changed or not. 7311323.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89811 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
PCRegisterInfo.cpp
|
| eac79170d2c66f1d6a433b0cac2696926eeff783 |
24-Nov-2009 |
Devang Patel <dpatel@apple.com> |
Enable debug info for ppc-darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89803 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| b60d5194f52349b74914593919764fe8f4396bdf |
24-Nov-2009 |
Dale Johannesen <dalej@apple.com> |
Make capitalization of names starting "is" more consistent.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89724 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCRegisterInfo.cpp
|
| 108c838093704650378b194fe9afc5ebb9e91455 |
24-Nov-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
* Move stub allocation inside the JITEmitter, instead of exposing a
way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816.
* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89715 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
PCJITInfo.h
|
| 735afe14eea8049bf69210ce8a3512e391fc643f |
24-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| 0261d795f83a45dd53d82e511ae672d6d1f4e298 |
23-Nov-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
Allow more than one stub to be being generated at the same time.
It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89708 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| bef8888a9197655512f156e50b10799da7240252 |
21-Nov-2009 |
Devang Patel <dpatel@apple.com> |
We are not using DBG_STOPPOINT anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89536 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 29cbade25aa094ca9a149a96a8614cf6f3247480 |
21-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Target-independent support for TargetFlags on BlockAddress operands,
and support for blockaddresses in x86-32 PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 5ca124691bc81ed013593151c500d8104f7068dd |
20-Nov-2009 |
Dale Johannesen <dalej@apple.com> |
Remove an incorrect overaggressive optimization
(PPC specific).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89496 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 1924aabf996be9335fab34e7ee4fa2aa5911389c |
13-Nov-2009 |
David Greene <greened@obbligato.org> |
Move DebugInfo checks into EmitComments and remove them from
target-specific AsmPrinters. Not all comments need DebugInfo.
Re-enable the line numbers comment test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88697 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 1e608819aa26c06b1552521469f2211339e3bfe0 |
13-Nov-2009 |
Dale Johannesen <dalej@apple.com> |
Adjust isConstantSplat to allow for big-endian targets.
PPC is such a target; make it work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87060 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b9c2fd964ee7dd7823ac71db8443055e4d0f1c15 |
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Make the MachineFunction argument of getFrameRegister const.
This also fixes a build error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87027 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.h
|
| 3f2bf85d14759cc4b28a86805f566ac805a54d00 |
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Add a bool flag to StackObjects telling whether they reference spill
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCRegisterInfo.cpp
|
| b19a5e9be6097eab311678ccbd9e046c72f7e052 |
10-Nov-2009 |
Bill Wendling <isanbard@gmail.com> |
Modify how the prologue encoded the "move" information for the FDE. GCC
generates a sequence similar to this:
__Z4funci:
LFB2:
mflr r0
LCFI0:
stmw r30,-8(r1)
LCFI1:
stw r0,8(r1)
LCFI2:
stwu r1,-80(r1)
LCFI3:
mr r30,r1
LCFI4:
where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other
things are. We generated something more like this:
Leh_func_begin1:
mflr r0
stw r31, 20(r1)
stw r0, 8(r1)
Llabel1:
stwu r1, -80(r1)
Llabel2:
mr r31, r1
Note that we are missing the "mr" instruction. This patch makes it more like the
GCC output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86729 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 2718e43d6ae4f1c15823069566f18f7339cc976e |
09-Nov-2009 |
Bill Wendling <isanbard@gmail.com> |
Similar to r86588, but for Darwin this time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86592 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| b1ec31d71184e318cae8c147658162f7ed019ada |
09-Nov-2009 |
Bill Wendling <isanbard@gmail.com> |
The jump table was being generated before the end label for exception handling
was generated. This caused code like this:
## The asm code for the function
.section __TEXT,__const
.align 2
lJTI11_0:
LJTI11_0:
.long LBB11_16
.long LBB11_4
.long LBB11_5
.long LBB11_6
.long LBB11_7
.long LBB11_8
.long LBB11_9
.long LBB11_10
.long LBB11_11
.long LBB11_12
.long LBB11_13
.long LBB11_14
Leh_func_end11: ## <---now in the wrong section!
The `Leh_func_end11' would then end up in the wrong section, causing the
resulting EH frame information to be wrong:
__ZL11CheckRightsjPKcbRbRP6NSData.eh:
.set Lset500eh,Leh_frame_end11-Leh_frame_begin11
.long Lset500eh ; Length of Frame Information Entry
Leh_frame_begin11:
.long Leh_frame_begin11-Leh_frame_common
.long Leh_func_begin11-.
.set Lset501eh,Leh_func_end11-Leh_func_begin11
.long Lset501eh ; FDE address range
`Lset501eh' is now something huge instead of the real value.
The X86 back-end generates the jump table after the EH information is
emitted. Do the same here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86588 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 59a9178fbedb88427c8ff9e5fa7a8f2038f80a2e |
07-Nov-2009 |
Chris Lattner <sabre@nondot.org> |
indicate what the native integer types for the target are.
Please verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 2928c83b010f7cfdb0f819199d806f6942a7d995 |
06-Nov-2009 |
Daniel Dunbar <daniel@zuster.org> |
Pass StringRef by value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86251 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 73bb251cd7a535fb93bb3a52eda61555fb253f41 |
05-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove uninteresting and confusing debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 3d90dbee695e723f422dafca3fc75f193268ab9e |
04-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add PowerPC codegen for indirect branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86050 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 533297b58da8c74bec65551e1aface9801fc2259 |
29-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| f5a86f45e75ec744c203270ffa03659eb0a220c1 |
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
|
| 6726b6d75a8b679068a58cb954ba97cf9d1690ba |
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
|
| 74cd3b7ceb61b9335fbed1a124324fffd96ded6a |
19-Oct-2009 |
Chris Lattner <sabre@nondot.org> |
emit .subsections_via_symbols through MCStreamer instead of textually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84509 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| ff89dcb06fbd103373436e2d0ae85f252fae2254 |
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2.
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 20270c909357e5e501cac1f5393430dfacfc57d8 |
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Only fixed stack objects and spill slots should be get FixedStack PseudoSourceValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84411 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6553155172a2e74feff1253837daa608123de54a |
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert 84315 for now. Re-thinking the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bf125583f8bd8196a34921276add7f304b7c1433 |
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename getFixedStack to getStackObject. The stack objects represented are not
necessarily fixed. Only those will negative frame indices are "fixed."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3a6b9eb868f579b945aa8ec8fadf65e4dd913555 |
12-Oct-2009 |
Dale Johannesen <dalej@apple.com> |
Revert the kludge in 76703. I got a clean
bootstrap of FSF-style PPC, so there is some
reason to believe the original bug (which was
never analyzed) has been fixed, probably by
82266.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83871 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.h
|
| b58f498f7502e7e1833decbbbb4df771367c7341 |
07-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Add register-reuse to frame-index register scavenging. When a target uses
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| e3cc3f3c84abfdf8eb3bd19dfa806ceea49f15d6 |
06-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Instead of printing unnecessary basic block labels as labels in
verbose-asm mode, print comments instead. This eliminates a non-comment
difference between verbose-asm mode and non-verbose-asm mode.
Also, factor out the relevant code out of all the targets and into
target-independent code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83392 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| af0e2726835e096e32c30c1b88cc7a6232a6ef69 |
06-Oct-2009 |
Devang Patel <dpatel@apple.com> |
Update processDebugLoc() so that it can be used to process debug info before and after printing an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83363 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCCodeEmitter.cpp
|
| b0fdedb3fd123a47e7deca75d1e6f7d64218b07a |
01-Oct-2009 |
Devang Patel <dpatel@apple.com> |
Use MachineInstr as an processDebugLoc() argument.
This will allow processDebugLoc() to handle scopes for DWARF debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83183 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 812209a58c5520c604bc9279aa069e5ae066e860 |
01-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this
to emit target-specific things at the beginning of the asm output. This
fixes a problem for PPC, where the text sections are not being kept together
as expected. The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives. The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text. With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83176 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 26207e5bf1123a793bd9b38bcda2f569a6b45ef2 |
28-Sep-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.
KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| ae03af26635b5831d1370b5bc161ced577397200 |
28-Sep-2009 |
Dan Gohman <gohman@apple.com> |
LBRX no longer has an explicit SrcValueSDNode operand, so the type
operand is now at index 2, rather than 3. This fixes the
"Invalid child # of SDNode!" failures on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82942 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8ff95de83cbe85d939535d2f4fb5f9b2b721081a |
27-Sep-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Use explicit structs instead of std::pair to map callee saved regs to spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82909 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
|
| c76909abfec876c6b751d693ebd3df07df686aa0 |
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 602b0c8c17f458d2c80f2deb3c8e554d516ee316 |
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| 6acaaa8f32a52772952c2171ad8ee1f7a896a1c9 |
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Don't try to use pre-indexed addressing with sthbrx/stwbrx
instructions. This fixes a PowerPC bug exposed by some unrelated
changes I'm working on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82743 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a279bc3da55691784064cb47200a1c584408b8ab |
20-Sep-2009 |
Daniel Dunbar <daniel@zuster.org> |
Tabs -> spaces, and remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82355 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| ce31910eae5bd4896fa6c27798e7b26885691d3b |
19-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82311 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| fb2e752e4175920d0531f2afc93a23d0cdf4db14 |
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 8dffc819c5f4326700262e7d1ff906d0d44ca906 |
18-Sep-2009 |
Dale Johannesen <dalej@apple.com> |
Model the carry bit on ppc32. Without this we could
move a SUBFC (etc.) below the SUBFE (etc.) that consumed
the carry bit. Add missing ADDIC8, noticed along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82266 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.td
|
| 8c6ed05157e9c97ff8f3ccb211dd797e53228da1 |
16-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
Big change #1 for personality function references:
Eliminate the PersonalityPrefix/Suffix & NeedsIndirectEncoding
fields from MAI: they aren't part of the asm syntax, they are
related to the structure of the object file.
To replace their functionality, add a new
TLOF::getSymbolForDwarfGlobalReference method which asks targets
to decide how to reference a global from EH in a pc-relative way.
The default implementation just returns the symbol. The default
darwin implementation references the symbol through an indirect
$non_lazy_ptr stub. The bizarro x86-64 darwin specialization
handles the weird "foo@GOTPCREL+4" hack.
DwarfException.cpp now uses this to emit the reference to the
symbol in the right way, and this also eliminates another
horrible hack from DwarfException.cpp:
- if (strcmp(MAI->getPersonalitySuffix(), "+4@GOTPCREL"))
- O << "-" << MAI->getPCSymbol();
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81991 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
|
| 8deedba8412acdd30dc91cc213c706e94253c5b2 |
16-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate the PPC backend's implementation of EmitExternalGlobal
and use PersonalityPrefix/Suffix to achieve the same effect (like
the x86 backend).
This changes the code generated for ppc static mode, but guess what,
we were generating this before:
.byte 0x9B ; Personality (indirect pcrel sdata4)
.long ___gxx_personality_v0-. ; Personality
which is not correct! (it is not an 'indirect' reference).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81965 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCMCAsmInfo.cpp
|
| 762ccea600158bb317dcccdff3303e942426cb71 |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
remove all but one reference to TargetRegisterDesc::AsmName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81714 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| d95148f073c31924f275a34296da52a7cdefad91 |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
the tblgen produced 'getRegisterName' method does not access
the object, make it static instead of const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81711 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 05af2616d0df19638e799d3e7afadea26d96a4ba |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
make tblgen produce a function that returns the name for a physreg.
Nothing is using this info yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81707 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 70a54c07a0807bf89d1a8b4414e53298c376eb61 |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
replace printBasicBlockLabel with EmitBasicBlockStart,
now that printBasicBlockLabel is only used for starting
a MBB. This allows elimination of a bunch of arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81684 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 325d3dcfe4d5efc91db0f59b20a72a11dea024ed |
13-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
convert some uses of printBasicBlockLabel to use GetMBBSymbol
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81677 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c5ea263a23f4f15587e35c9cb07cf72a9fba7613 |
10-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
remove DebugLoc from MCInst and eliminate "Comment printing" from
the MCInst path of the asmprinter. Instead, pull comment printing
out of the autogenerated asmprinter into each target that uses the
autogenerated asmprinter. This causes code duplication into each
target, but in a way that will be easier to clean up later when more
asmprinter stuff is commonized into the base AsmPrinter class.
This also fixes an xcore strangeness where it inserted two tabs
before every instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81396 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 634cca377a8254cfe8a5afe99ef2e6c6db7f0c6b |
09-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
hoist the call to processDebugLoc out of the generated
asm printer into the "printInstruction" routine. This
fixes a problem where the experimental asmprinter would
drop debug labels in some cases, and fixes issues on ppc/xcore
where pseudo instructions like "mr" didn't get debug locs properly.
It is annoying that this moves the call from one place into each
target, but a future set of more invasive refactorings will fix
that problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81377 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c2d98bc0d682419f09659d94afefd6a6266dd6ee |
06-Sep-2009 |
Duncan Sands <baldrick@free.fr> |
Remove some not-really-used variables, as warned
about by icc (#593, partial). Patch by Erick Tryzelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81115 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 65c3c8f323198b99b88b109654194540cf9b3fa5 |
02-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| c69d74a5d41a6c5e92f9d947f2fa181f48626ca5 |
31-Aug-2009 |
Duncan Sands <baldrick@free.fr> |
Revert commit 80428. It completely broke exception
handling on x86-32 linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80592 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| b4f770b68a2f1890e17f634b695d19bb7d07168d |
31-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Normalize makefile comments and sort cmake file lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80584 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
argetInfo/Makefile
|
| 9b35a09e7e5b1aa26588e3852fe00a42b4f383ba |
29-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
- Add target lowering methods to get the preferred format for the FDE and LSDA
encodings.
- Make some of the values emitted by the FDEs dependent upon the pointer
size. This is in line with how GCC does things. And it has the benefit of
working for Darwin in 64-bit mode now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80428 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 4e68f8803d8e28d52cc2f16a4eef5c175878b0f3 |
26-Aug-2009 |
Dale Johannesen <dalej@apple.com> |
Alter 79292 to produce output that actually assembles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80119 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| a60e51f7e81bdb99ca331776a06c93dfd6043762 |
24-Aug-2009 |
Dale Johannesen <dalej@apple.com> |
Make linkerprivate work for ARM and PPC. Testcase covers
all Darwin targets; could be split into separate tests for
the chip subdirectories, but from Chris' last mail on testing
I assume he'd rather have only one test. Generic seems to be
the best available, maybe there should be a Darwin subdirectory?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79877 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 893e1c90a03a53cf13f73849324e83612688428a |
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate the last DOUTs from the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79833 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| 45cfe545ec8177262dabc70580ce05feaa1c3880 |
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Change Pass::print to take a raw ostream instead of std::ostream,
update all code that this affects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79830 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 705e07f578e2b3af47ddab610feb4e7f2d3063a5 |
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove various std::ostream version of printing methods from
MachineInstr and MachineOperand. This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79813 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| f682f3d019794d4402b73701a06a4bb117f5d5e7 |
23-Aug-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Forgot to update some CMakeLists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79780 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 33adcfb4d217f5f23d9bde8ba02b8e48f9605fc5 |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
rename TAI -> MAI, being careful not to make MAILJMP instructions :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79777 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 2807afa664b579af4c559b3880d6763b9e7e236a |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
rename COFFMCAsmInfo -> MCAsmInfoCOFF, likewise for darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79773 91177308-0d34-0410-b5e6-96231b3b80d8
PCMCAsmInfo.cpp
PCMCAsmInfo.h
PCTargetMachine.cpp
|
| af76e592c7f9deff0e55c13dbb4a34f07f1c7f64 |
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79763 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCInstrInfo.cpp
PCMCAsmInfo.cpp
PCMCAsmInfo.h
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
PCTargetMachine.cpp
|
| 24f20e083280d979e8fa1bc88959ae9e8339ee99 |
22-Aug-2009 |
Devang Patel <dpatel@apple.com> |
Record variable debug info at ISel time directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79742 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 6c2f9e14fdf14d8c1c687c6bd9918183fa7f8a7f |
19-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate AsmPrinter::SwitchToSection and just have clients
talk to the MCStreamer directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79405 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c0823fe7c679ca8f7d1667a310c2fca97b9402d5 |
18-Aug-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify RegScavenger::FindUnusedReg.
- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79369 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 5cfd4ddece1b73a719830ae84eb74d491f87b9d5 |
18-Aug-2009 |
Dale Johannesen <dalej@apple.com> |
PowerPC inline asm was emitting two output operands
for a single "m" constraint; this is wrong because the
opcode of a load or store would have to change in parallel.
This patch makes it always compute addresses into a register,
which is correct but not as efficient as possible. 7144566.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79292 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCISelDAGToDAG.cpp
|
| 6b16eff207f99bbde3c0f7340452a5287218772c |
15-Aug-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add support for the PowerPC 64-bit SVR4 ABI.
The Link Register is volatile when using the 32-bit SVR4 ABI.
Make it possible to use the 64-bit SVR4 ABI.
Add non-volatile registers for the 64-bit SVR4 ABI.
Make sure r2 is a reserved register when using the 64-bit SVR4 ABI.
Update PPCFrameInfo for the 64-bit SVR4 ABI.
Add FIXME for 64-bit Darwin PPC.
Insert NOP instruction after direct function calls.
Emit official procedure descriptors.
Create TOC entries for GlobalAddress references.
Spill 64-bit non-volatile registers to the correct slots.
Only custom lower VAARG when using the 32-bit SVR4 ABI.
Use simple VASTART lowering for the 64-bit SVR4 ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79091 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCFrameInfo.h
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.td
PCSubtarget.h
|
| bd51c677390d8e13560cbf3ea972b95a5fbc1f9a |
15-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Simplify a few more things, eliminating a few more dependencies on
"the current basic block".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79069 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 789457847002f5289dbbc5cfce9d68c72e00bed1 |
14-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
TargetRegistry: Change AsmPrinter constructor to be typed as returning an
AsmPrinter instance (instead of just a FunctionPass)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78962 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| fdf229eda95a542fc34d5182e1a91a22789ba122 |
14-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove HasCrazyBSS and add a flag in TAI to indicate that '.section'
must be emitted for PowerPC-Linux '.bss' section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78958 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCTargetAsmInfo.cpp
|
| 1d0be15f89cb5056e20e2d24faa8d6afb1573bca |
13-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Push LLVMContexts through the IntegerType APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 67d894ea64bc52245abf3f2ba89122a749d99c53 |
13-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
TargetRegistry: Reorganize AsmPrinter construction so that clients pass in the
TargetAsmInfo. This eliminates a dependency on TargetMachine.h from
TargetRegistry.h, which technically was a layering violation.
- Clients probably can only sensibly pass in the same TargetAsmInfo as the
TargetMachine has, but there are only limited clients of this API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78928 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| b42dad4761968b4b052e72494ce1bf0c7b3aba3e |
13-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Revert 78892 and 78895, these break generating working executables on
x86_64-apple-darwin10.
--- Reverse-merging r78895 into '.':
U test/CodeGen/PowerPC/2008-12-12-EH.ll
U lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U include/llvm/Target/DarwinTargetAsmInfo.h
U lib/Target/X86/X86TargetAsmInfo.cpp
U lib/Target/X86/X86TargetAsmInfo.h
U lib/Target/ARM/ARMTargetAsmInfo.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/ARMTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.h
U lib/Target/PowerPC/PPCTargetMachine.cpp
G lib/Target/DarwinTargetAsmInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78919 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
PCTargetMachine.cpp
|
| b2d3169d96ee780e6b8f43230e36e41d97ed3140 |
13-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
fix a minor fixme. When building with SL and later tools, the ".eh" symbols
don't need to be exported from the .o files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78892 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
PCTargetMachine.cpp
|
| cf20ac4fd12ea3510a8f32a24fff69eebe7b6f4a |
13-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Various AsmWriter output cleanups. Use WriteAsOperand instead of
PrintUnmangledNameSafely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78878 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| a7ac47cee1a0b3f4c798ecaa22ecf9d1be9c07e6 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple
pair instead of from a virtual method on TargetMachine. This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use
TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78802 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 23b9b19b1a5a00faa9fce0788155c7dbfd00bfb1 |
12-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78759 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6b883e329734c67f14800ba3264b6b268c1b6c15 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
fix CodeGen/PowerPC/2007-01-15-AsmDialect.ll, fallout from r78742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78747 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 09652df5fc19b088d8baf43dd7839d9c2fc24980 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
second half of commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78744 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 5b67bb1922386615936b2647b5681f6430746ac1 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
pass "is64Bit" flag into PPC TAI ctors instead of a whole targetmachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78743 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| 74da671c36cdaa6bea3fa7889dc9aeab572b609c |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate asmflavor from subtarget, PPCTAI is the only client
and each callee knows that it returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78742 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
PCTargetAsmInfo.cpp
|
| e2b060161c92ddf60b5d020f981451e9e34a3f02 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Change the asmprinter to print the comment character before the
"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character. This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character. This also allows hoisting the darwin stuff up to the
shared TAI class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78737 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| e28a2e8b70e926324575ddec0a1565c6dba7d404 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
factorize more darwin TAI stuff. Note that this gives
darwin/arm support for .no_dead_strip
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78734 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| e2811a74803d24fff45a186d2871377d248cec1c |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
factorize darwin ProtectedDirective and SetDirective.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78732 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| b6ba9c36dbc54c85b86b29d9491c457b4de8b60c |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
all darwin targets have .space and .zerofill, pull up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78730 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| c89ecc5c2f6c089db328e2856aadf9fd4a1a0bd3 |
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move LCOMMDirective = "\t.lcomm\t" up to DarwinTAI, eliminate
template in PPC backend for TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78727 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 0a31d2f6456069adba19b8aeca66c68b633c38b4 |
11-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
pass the TargetTriple down from each target ctor to the
LLVMTargetMachine ctor. It is currently unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78711 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 1b747ad8a0694b86e8d98a8b9a05ddfe74ec0cd3 |
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
SjLj based exception handling unwinding support. This patch is nasty, brutish
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78625 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 70671845adce8ab36ae596bb06d0375459a7a2af |
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Continue the SimpleValueType-ification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78593 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 77547befdc430633aaedf4130ddf17d953ed552e |
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78584 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| f9bdeddb96043559c61f176f8077e3b91a0c544f |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
split MachO section handling stuff out to its out .h/.cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78576 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| e1e8a82986e12f9cf841004c78ff051df9df11d8 |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Fix a weird ppc64-specific link error during an llvm-gcc build:
ld: bad offset (0x00000091) for lo14 instruction pic-base fix-up in ___popcountdi2 from libgcc/./_popcountsi2_s.o
The problem is that the non lazy symbol pointers need to be 8 byte aligned
on ppc64 and .section doesn't have an implicit alignment like ".non_lazy_symbol_pointer"
does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78572 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| ff4bc460c52c1f285d8a56da173641bf92d49e3f |
10-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Make the big switch: Change MCSectionMachO to represent a section *semantically*
instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78547 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 892e18239308f8a02a4c83758616be84a459c19d |
09-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
1. Make MCSection an abstract class.
2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78510 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 41aefdcdd1c1631041834d53ffada106a5cfaf02 |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
make printInstruction return void since its result is omitted. Make the
error condition get trapped with an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78449 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 2698cb6811276736a8e892e545609a9048a917fe |
08-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
don't check the result of printInstruction anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78444 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| e22f4da01d57f51757663fdcae986af0aeca49fe |
05-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78219 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| bccdcb1857f400206ed07984dc04e229c6013cc6 |
05-Aug-2009 |
Devang Patel <dpatel@apple.com> |
Remove dead code. MDNode and MDString are not Constant anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78207 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 98ca4f2a325f72374a477f9deba7d09e8999c29b |
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 1c55fab53455f11fbd7bde69d0c5911031218e35 |
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Don't flush the raw_ostream between each MachineFunction. These flush
calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78137 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 3b24c0172069a2546cd095e4b91f8b88c1ea0722 |
04-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
make MergeableCString be a SectionKind "abstract class", and
add new concrete versions for 1/2/4-byte mergable strings.
These are not actually created yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78055 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 2dfddee396d4e65c5458bcec8513a20336fbc5b4 |
04-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
switch ppc to using SwitchToSection instead of textual section stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78013 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| e28039cfd1a9c43b5fa9274bf19372d96f58f460 |
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Move most targets TargetMachine constructor to only taking a target triple.
- The C, C++, MSIL, and Mips backends still need the module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77927 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 3be03406c9c3b2075d5ae416499af2f15f703d6f |
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Normalize Subtarget constructors to take a target triple string instead of
Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
|
| 18a4c16726db2b8874c7b84d04650dda80746074 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move dwarf debug info section selection stuff from TAI to
TLOF, unifying all the dwarf targets at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77889 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 35039ac24163e99cfab161620a9fb41f944a63d5 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
convert EHFrameSection to be managed by TLOF instead of TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77888 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| d90183d25dcbc0eabde56319fed4e8d6ace2e6eb |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Move the getInlineAsmLength virtual method from TAI to TII, where
the only real caller (GetFunctionSizeInBytes) uses it.
The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 9ba8c6872dc722d0f9f804fcd67bace4acfe67ba |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove the dead ELFTargetAsmInfo.h/cpp file. TargetAsmInfo
defaults to being ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77866 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.h
|
| 8d4a0a328a89d1f3c7ad83048e04ace53b6ba781 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove TargetAsmInfo::TM, which is now dead. The basic TAI class now
no longer depends on TM!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77863 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| 83f08a2efdbe18e1eba866a25aa7e37c555de4c1 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove the x86/ppc impls of getEHGlobalPrefix, which is already dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77861 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| d5bbb07ec806e6fa1e804afd7073987fdacc83e4 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
move getDwarfExceptionSection from TAI to TLOF and rename it to
getLSDASection() to be more specific. This makes it pretty obvious
that the ELF LSDA section is being specified wrong in PIC mode. We're
probably getting a lot of startup-time relocations to a readonly page,
which is expensive and bad.
Someone who cares about ELF C++ should investigate this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77847 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 73e789fd377a0ea5348b76e159aece89fe6ec383 |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
don't override the default of this, the only difference is \t instead of ' '.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77838 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| b80610cd13e7accf6db0924c75d0914bf566922b |
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
REmove dead fields of TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77820 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| a9c1dd7820d0444802d42e5761e36c6e60e404d6 |
01-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Fix typos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77806 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
|
| 1db511cc911be75c18fb8e64a22fc5d25e479b10 |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove the PPCLinuxTargetAsmInfo implementation of PreferredEHDataFormat,
because it just calls the default impl.
Remove the PPCDarwinTargetAsmInfo version of PreferredEHDataFormat because
it just returns DW_EH_PE_absptr unless on 10.6. However, 10.6 doesn't support
PPC, so the default impl is just fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77724 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| a87dea4f8c546ca748f1777a8d1cabcc06515d91 |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
switch off of 'Section' onto MCSection. We're not properly using
MCSection subclasses yet, but this is a step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| ad2afc2a421a0e41603d5eee412d4d8c77e9bc1c |
31-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsage
shouldn't do AU.setPreservesCFG(), because even though CodeGen passes
don't modify the LLVM IR CFG, they may modify the MachineFunction CFG,
and passes like MachineLoop are registered with isCFGOnly set to true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77691 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| f26e03bc7e30162197641406e37e662a15d80f7e |
31-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
refactor section construction in TLOF to be through an explicit
initialize method, which can be called when an MCContext is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77687 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c5b19b21d84814d19692a6bbea11fbd135f4b094 |
31-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Revert r77654, it appears to be causing llvm-gcc bootstrap failures, and many
failures when building assorted projects with clang.
--- Reverse-merging r77654 into '.':
U include/llvm/CodeGen/Passes.h
U include/llvm/CodeGen/MachineFunctionPass.h
U include/llvm/CodeGen/MachineFunction.h
U include/llvm/CodeGen/LazyLiveness.h
U include/llvm/CodeGen/SelectionDAGISel.h
D include/llvm/CodeGen/MachineFunctionAnalysis.h
U include/llvm/Function.h
U lib/Target/CellSPU/SPUISelDAGToDAG.cpp
U lib/Target/PowerPC/PPCISelDAGToDAG.cpp
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/MachineVerifier.cpp
U lib/CodeGen/MachineFunction.cpp
U lib/CodeGen/PrologEpilogInserter.cpp
U lib/CodeGen/MachineLoopInfo.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
D lib/CodeGen/MachineFunctionAnalysis.cpp
D lib/CodeGen/MachineFunctionPass.cpp
U lib/CodeGen/LiveVariables.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77661 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 933c762371fe8cc6e2ef5d00d6866f4924852fed |
31-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Manage MachineFunctions with an analysis Pass instead of the Annotable
mechanism. To support this, make MachineFunctionPass a little more
complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77654 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| debcb01b0f0a15f568ca69e8f288fade4bfc7297 |
30-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Move types back to the 2.5 API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77516 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2cfd52c507bd5790457a171eb9bcb39019cc6860 |
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Give getPointerRegClass() a "kind" value so that targets can
support multiple different pointer register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| e53a600f065075731d0aeb9dc8f4f3d75f5a05f8 |
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
pass the mangler down into the various SectionForGlobal methods.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77432 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 859cc77963d4d3a477abebe62b1ff15e4d849e19 |
29-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Change the "PreferredEHDataFormat" from "absptr" if we're on a Darwin system >
Leopard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77414 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 1711a7c8cf363278d4dae5591b015261d04380dc |
29-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Output the correct format for Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77376 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 0a9f7b9c3ebe7d0ec033462e1a7c9101279956f9 |
28-Jul-2009 |
Devang Patel <dpatel@apple.com> |
Rename MDNode.h header. It defines MDnode and other metadata classes.
New name is Metadata.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77370 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 4bb253c60f895131371aa2ad1bfa5a2bea213f78 |
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
the apple "ld_classic" linker doesn't support .literal16 in 32-bit
mode, and "ld64" (the default linker) falls back to it in -static
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77334 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f0144127b98425d214e59e4a1a4b342b78e3642b |
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rip all of the global variable lowering logic out of TargetAsmInfo. Since
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCISelLowering.cpp
PCTargetAsmInfo.cpp
|
| e346694a81cbead3289d11057111fba46aa30aae |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Eliminate getNamed/getUnnamedSection, adding a new and unified getOrCreateSection
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77186 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 5fe575ff4fdefc1b003a009b1b9282526a26c237 |
27-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Eliminate SectionFlags, just embed a SectionKind into Section
instead and drive things based off of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77184 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCTargetAsmInfo.cpp
|
| 0fcf4dc6d367216ff51501af282e33e93da8586f |
26-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
untangle a TargetAsmInfo hack where ELFTargetAsmInfo would create a
'unnamed' bss section, but some impls would want a named one. Since
they don't have consistent behavior, just make each target do their
own thing, instead of doing something "sortof common" then having
targets change immutable objects later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77165 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 93b67e40de356569493c285b86b138a3f11b5035 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Eliminate some uses of DOUT, cerr, and getNameStart().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77145 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 8977d087c693fd581db82bcff134d12da0f48bd3 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Factor commonality in triple match routines into helper template for registering
classes, and migrate existing targets over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77126 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/PowerPCTargetInfo.cpp
|
| fa27ff296d3694a68e7abb3b6b7629588def3e58 |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill Target specific ModuleMatchQuality stuff.
- This was overkill and inconsistently implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77114 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/PowerPCTargetInfo.cpp
|
| 03d7651c3652e1f0cc86e79b26585d86818da9cf |
26-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove Value::{isName, getNameRef}.
Also, change MDString to use a StringRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77098 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| b4fc419d83bc4afc8ce5a204dd226d5ae58f5896 |
25-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
this is (unfortunately) several changes mixed together:
1. Spell SectionFlags::Writeable as "Writable".
2. Add predicates for deriving SectionFlags from SectionKinds.
3. Sink ELF-specific getSectionPrefixForUniqueGlobal impl into
ELFTargetAsmInfo.
4. Fix SectionFlagsForGlobal to know that BSS/ThreadBSS has the
BSS bit set (the real fix for PR4619).
5. Fix isSuitableForBSS to not put globals with explicit sections
set in BSS (which was the reason #4 wasn't fixed earlier).
6. Remove my previous hack for PR4619.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77085 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| d6fd377f3333922c4e928019cdfa124ff7f4dd2e |
25-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Simplify JIT target selection.
- Instead of requiring targets to define a JIT quality match function, we just
have them specify if they support a JIT.
- Target selection for the JIT just gets the host triple and looks for the best
target which matches the triple and has a JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77060 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/PowerPCTargetInfo.cpp
|
| 0c795d61878156817cedbac51ec2921f2634c1a5 |
25-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add new helpers for registering targets.
- Less boilerplate == good.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77052 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
|
| 23ed52752bb40a9085c9d36bbc6603972c3e0080 |
24-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove unused member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| c440cc7f2c1e1e02fb4526babc9ab99986beb6e0 |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
use section flags more correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76944 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| fb3431aec52f1d4d9305159d9f4e652c81b4d9fb |
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
reduce api exposure: clients shouldn't call SectionKindForGlobal directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76941 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| d2cb3d2c32b8f53bf94d56fbdd48503ace28df4b |
24-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Remove the IA-64 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76920 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| fc6ad402fb267cba1625801444aad30da43d383a |
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it.
This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76703 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.h
|
| e922c0201916e0b980ab3cfe91e1413e68d55647 |
22-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Get rid of the Pass+Context magic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 40bbebde9d250b875a47a688d0c6552834ada48f |
21-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make AsmPrinter::doFinalization iterate over the global variables
and call PrintGlobalVariable, allowing elimination and simplification
of various targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76604 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 5c0ba804c02777c53c0842d0be2d16d1d92b9a46 |
20-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Rename Mangler linkage enums to something less gross.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76456 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 3d10a5a75794356a0a568ce283713adc3a963200 |
20-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add plumbing for the `linker_private' linkage type. This type is meant for
"private" symbols which the assember shouldn't strip, but which the linker may
remove after evaluation. This is mostly useful for Objective-C metadata.
This is plumbing, so we don't have a use of it yet. More to come, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76385 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| b384c85877d9fd3e9f3ae8d1b68c7c610bc5a1f4 |
19-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add dependencies from TargetInfo onto .td generation.
- Shouldn't really be necessary, but currently .inc files get included into
some main target headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76349 91177308-0d34-0410-b5e6-96231b3b80d8
argetInfo/CMakeLists.txt
|
| 4cb1e13769856716261a4d315f8202bd918502c3 |
19-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Put Target definitions inside Target specific header, and llvm namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76344 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
argetInfo/PowerPCTargetInfo.cpp
|
| 75402822d6acc1fe62d911771cd7cf8358c718d7 |
17-Jul-2009 |
Jeffrey Yasskin <jyasskin@google.com> |
r76102 added the MachineCodeEmitter::processDebugLoc call and called it from
the X86 Emitter. This patch extends that to the rest of the targets that can
write to a MachineCodeEmitter: ARM, Alpha, and PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76211 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| f366beca480087841330c1e19865139cb3fc2963 |
16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Do not put bunch of target-specific stuff into common namespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75971 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrBuilder.h
|
| 64cc97212346992892b6c92158c08cd93149a882 |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill off <TARGET>MachineModule variables, and <TARGETASMPRINTER>ForceLink
variables.
- Module initialization functions supplanted the need for these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75886 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCTargetMachine.cpp
|
| fe2fe7094e7dff91acb52b030dec097910000a54 |
16-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
fix section switching to ensure that stubs are emitted to the right
section on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75881 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 5d77cad60bd82dfa2d00f78e26443d667922efbf |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Lift addAssemblyEmitter into LLVMTargetMachine.
- No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75859 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| cfe9a605eea542d91e3db74289b69b7e317d90a6 |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Lift DumpAsm / -print-emitted-asm functionality into LLVMTargetMachine.
- No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75848 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| f05522974b3c1b9dc2644831364e19d5132e751b |
16-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove old style hacks to register AsmPrinter into TargetMachine.
- No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75843 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| 51b198af83cb0080c2709b04c129a3d774c07765 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Reapply TargetRegistry refactoring commits.
--- Reverse-merging r75799 into '.':
U test/Analysis/PointerTracking
U include/llvm/Target/TargetMachineRegistry.h
U include/llvm/Target/TargetMachine.h
U include/llvm/Target/TargetRegistry.h
U include/llvm/Target/TargetSelect.h
U tools/lto/LTOCodeGenerator.cpp
U tools/lto/LTOModule.cpp
U tools/llc/llc.cpp
U lib/Target/PowerPC/PPCTargetMachine.h
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/PowerPC/PPCTargetMachine.cpp
U lib/Target/PowerPC/PPC.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/ARMTargetMachine.h
U lib/Target/ARM/ARM.h
U lib/Target/XCore/XCoreTargetMachine.cpp
U lib/Target/XCore/XCoreTargetMachine.h
U lib/Target/PIC16/PIC16TargetMachine.cpp
U lib/Target/PIC16/PIC16TargetMachine.h
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/Alpha/AlphaTargetMachine.cpp
U lib/Target/Alpha/AlphaTargetMachine.h
U lib/Target/X86/X86TargetMachine.h
U lib/Target/X86/X86.h
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.h
U lib/Target/CppBackend/CPPTargetMachine.h
U lib/Target/CppBackend/CPPBackend.cpp
U lib/Target/CBackend/CTargetMachine.h
U lib/Target/CBackend/CBackend.cpp
U lib/Target/TargetMachine.cpp
U lib/Target/IA64/IA64TargetMachine.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/IA64/IA64TargetMachine.h
U lib/Target/IA64/IA64.h
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/CellSPU/SPUTargetMachine.h
U lib/Target/CellSPU/SPU.h
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/CellSPU/SPUTargetMachine.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
U lib/Target/Mips/MipsTargetMachine.cpp
U lib/Target/Mips/MipsTargetMachine.h
U lib/Target/Mips/Mips.h
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Sparc/SparcTargetMachine.cpp
U lib/Target/Sparc/SparcTargetMachine.h
U lib/ExecutionEngine/JIT/TargetSelect.cpp
U lib/Support/TargetRegistry.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75820 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 2286f8dc4cec0625f7d7a14e2570926cf8599646 |
15-Jul-2009 |
Stuart Hastings <stuart@apple.com> |
Revert 75762, 75763, 75766..75769, 75772..75775, 75778, 75780, 75782 to repair broken LLVM-GCC build.
Will revert 75770 in the llvm-gcc trunk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75799 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| f3f4715ac1de3ae4c89eeb96f23d6cd4876cc323 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Replace large swaths of copy-n-paste code with obvious helper function...
- Which was already present in the module!
- I skipped this xform for Alpha, since it runs an extra pass during assembly
emission, but not when emitting assembly via the DumpAsm flag.
- No functionality change.
--
ddunbar@giles:llvm$ svn diff | grep '^- ' | sort | uniq -c
18 - PM.add(AsmPrinterCtor(ferrs(), *this, true));
18 - assert(AsmPrinterCtor && "AsmPrinter was not linked in");
18 - if (AsmPrinterCtor)
18 - if (DumpAsm) {
18 - }
ddunbar@giles:llvm$ svn diff | grep '^+ ' | sort | uniq -c
18 + addAssemblyEmitter(PM, OptLevel, true, ferrs());
18 + if (DumpAsm)
--
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75782 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 6c05796294a7a0693d96c0c87194b9d5ddf55a94 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Kill off old (TargetMachine level, not Target level) match quality functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75780 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 03f4bc5d6cf777c8aa559c299ef7f85126872881 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Provide TargetMachine implementations with reference to Target they were created
from.
- This commit is almost entirely propogating the reference through the
TargetMachine subclasses' constructor calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75778 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 4246790aa84a530b0378d917023584c2c7adb4a9 |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Register Target's TargetMachine and AsmPrinter in the new registry.
- This abuses TargetMachineRegistry's constructor for now, this will get
cleaned up in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75762 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| c984df8602a8b2450cbdb6ff55fd49ba709a391e |
15-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add TargetInfo libraries for all targets.
- Intended to match current TargetMachine implementations.
- No facilities for linking these in yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75751 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
argetInfo/CMakeLists.txt
argetInfo/Makefile
argetInfo/PowerPCTargetInfo.cpp
|
| 392db3e11d93990e5c8382776b91d73ef40db005 |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
get the PPC stub temporary label from the mangler instead of
using horrible string hacking. This gives us a different label,
but it's just an assembler temporary, so the name doesn't matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75733 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 1a87c05ec011eaccb950e5f0160e2162e5747553 |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
turn some if/then's into ?:
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75732 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| defd3000dc34cc237dc44530f930ebf184d5e890 |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate a bunch of printSuffixedName's by using info computed from
Mangler in FnStubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75731 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 9ec8facd10e48d1ec62c7c91cbd5f003771764d8 |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
convert FnStubs to using a more structured form, eliminating
a couple instances of printSuffixedName (in favor of having
the mangler do stuff).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75729 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 0f6c8f25aa96f765f19b555e4d610d5a7557ee95 |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
simplify "EmitExternalGlobal": it is only used to output a
reference to the personality function for a module, and
those are all added to the GVStubs array by looping
over MMI->getPersonalities()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75720 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 8f831cbf0d9d1eb7de08d50b5d55ef84fdacba2e |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Convert GVStubs and HiddenGVStubs to work more like the X86 backend, this
eliminates a bunch of uses of "printSuffixedName" and "getGlobalLinkName".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75719 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| ea56f109db4d27475999af9b64ae6d74a858e329 |
15-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
minor cleanups: only switch sections once before all function stubs, instead of
before each one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75718 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 71847813bc419f7a0667468136a07429c6d9f164 |
14-Jul-2009 |
David Greene <greened@obbligato.org> |
Have asm printers use formatted_raw_ostream directly to avoid a
dynamic_cast<>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75670 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| b8158acc23f5f0bf235fb1c6a8182a38ec9b00b2 |
14-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Reapply my previous asmprinter changes now with more testing and two
additional bug fixes:
1. The bug that everyone hit was a problem in the asmprinter where it
would remove $stub but keep the L prefix on a name when emitting the
indirect symbol. This is easy to fix by keeping the name of the stub
and the name of the symbol in a StringMap instead of just keeping a
StringSet and trying to reconstruct it late.
2. There was a problem printing the personality function. The current
logic to print out the personality function from the DWARF information
is a bit of a cesspool right now that duplicates a bunch of other
logic in the asm printer. The short version of it is that it depends
on emitting both the L and _ prefix for symbols (at least on darwin)
and until I can untangle it, it is best to switch the mangler back to
emitting both prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75646 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCCodeEmitter.cpp
PCHazardRecognizers.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
PCJITInfo.cpp
PCMachOWriterInfo.cpp
PCPredicates.cpp
PCRegisterInfo.cpp
|
| 192957d376923cefc993c1b5c04127c42f1008ec |
14-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Revert r75615, which depended on 75610.
--- Reverse-merging r75615 into '.':
U lib/Target/XCore/XCoreAsmPrinter.cpp
U lib/Target/PIC16/PIC16AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/MSP430/MSP430AsmPrinter.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75637 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 481d15a12289ec4d058b863da93794fd8be1e702 |
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
eliminate extra space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75630 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| b09d2ccc0f23107fc1047694ce266a9cf5e0a3c2 |
14-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rename getValueName -> getMangledName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75615 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCCodeEmitter.cpp
PCHazardRecognizers.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCJITInfo.cpp
PCMachOWriterInfo.cpp
PCPredicates.cpp
PCRegisterInfo.cpp
|
| d1474d09cbe5fdeec8ba0d6c6b52f316f3422532 |
09-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Thread LLVMContext through MVT and related parts of SDISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75153 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| dac237e18209b697a8ba122d0ddd9cad4dfba1f8 |
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
PCJITInfo.cpp
PCRegisterInfo.cpp
|
| ac57e6e498abccb117e0d61c2fa0f733845e50cb |
06-Jul-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add the Object Code Emitter class. Original patch by Aaron Gray, I did some
cleanup, removed some #includes and moved Object Code Emitter out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74813 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCCodeEmitter.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| 6a3a1ba97e996bfdc061f9a51bd4cf4915962913 |
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Various small changes related to the Condition Register on PowerPC.
Don't spill to the CR save area when using the SVR4 ABI for now.
Don't rely on constants assigned for registers to be in order (they aren't assigned in order).
Make sure CR bits are mapped to the corresponding CR field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74767 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
PCInstrInfo.cpp
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| 2a9ddfb903ae3baede7282348afae1f750905248 |
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Refactor ABI code in the PowerPC backend.
Make CalculateParameterAndLinkageAreaSize() Darwin-specific.
Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin().
Rename MachoABI to DarwinABI for consistency.
Rename ELF ABI to SVR4 ABI for consistency.
Factor out common call return lowering between the Darwin and SVR4 ABI.
Factor out common call lowering between the Darwin and SVR4 ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74766 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCCodeEmitter.cpp
PCFrameInfo.h
PCHazardRecognizers.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
PCJITInfo.cpp
PCRegisterInfo.cpp
PCRegisterInfo.td
PCSubtarget.h
|
| ffd0200abfd63177257f949a3674b91dcf87bf23 |
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Implement the SVR4 ABI for PowerPC.
Implement LowerFORMAL_ARGUMENTS_SVR4().
Implement LowerCALL_SVR4().
Add support for split arguments.
Implement by value parameter passing for aggregates.
Add support for variable argument lists.
Create the spill area for argument registers of variable argument functions no longer at a fixed offset.
Make sure callee saved registers are spilled to the correct stack offsets.
Change allocation order of non-volatile floating-point registers.
Add VRSAVE to the list of callee-saved registers, add CallConvLowering for vararg calls.
Add support for variable argument calls with Vector arguments.
Add support for VR and VRSAVE save area, improve allocation order for non-volatile vector registers.
Stop creating illegal i8 values in LowerVASTART().
Add memory access width hints.
Make sure to reserve space on the stack for the frame pointer.
When using the SVR4 ABI, reserve r13 for the Small Data Area pointer.
Assure that the frame pointer is spilled to the correct location on the stack.
Some FP registers were not marked as volatile.
Make sure the i64 words from a long double are passed either both in registers or both on the stack.
Only put integer arguments in registers which are not marked with the inreg flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74765 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCFrameInfo.h
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.h
PCRegisterInfo.td
|
| 6b61cd185eeb90bec93f042535594132ae1f0f41 |
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.
With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74764 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 667ee3cb436029e55cc788a3648ddd9f94678744 |
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Small cleanups in the PowerPC backend.
Small refactoring in LowerFORMAL_ARGUMENTS().
Correct minor formatting issues.
Remove size argument of CreateCopyOfByValArgument().
Remove dead argument from CalculateStackSlotSize().
Remove unused variable ReturnAddrIndex from various targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74763 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 033080cf6a6f6ca94f20c410204405471c19c535 |
02-Jul-2009 |
Douglas Gregor <dgregor@apple.com> |
CMake build fixes, from Xerxes Ranby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74720 91177308-0d34-0410-b5e6-96231b3b80d8
MakeLists.txt
|
| 20674338529dc034211b41d9224e536ab3893e8d |
02-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
simplify some logic by using isWeakForLinker(). Thanks to Anton for
pointing this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74700 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c4b0b400b0546aab03be16b8fe1dd27e2fbb041c |
02-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
clarify: stub emission depends on the version of the linker you use, it has nothing
to do with the target. Also, the stub elimination optimization *requires* making the
stub explicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74682 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 7074feab96ef137eb6c6afb4cea8765d430f601a |
02-Jul-2009 |
Dale Johannesen <dalej@apple.com> |
Add darwin stub removal to wishlist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74667 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| b4202b84d7e54efe5e144885c7da63e6cc465f80 |
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 4fb75e542539153acaf31d9221845a7d0feccbf6 |
01-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Fix codegen for references to available_externally symbols. This fixes
PR4482.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74613 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 2578ba26e72e36dde64be0f52a2788480aad3378 |
01-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 5bcc8bd0c60cfe583ee47852950aad9e532c932e |
01-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove unused AsmPrinter OptLevel argument, and propogate.
- This more or less amounts to a revert of r65379. I'm curious to know what
happened that caused this variable to become unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74579 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 20c568f366be211323eeaf0e45ef053278ec9ddc |
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| 0f05d22a31bf76a1e066592a567217b73fcc4d7d |
26-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Let's ignore MDStrings also!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74255 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 4b73893d82866fc6889e550bedda0e4d76ad930a |
25-Jun-2009 |
Douglas Gregor <dgregor@apple.com> |
Add missing dependencies to the CMake build system.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74161 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
|
| e4c0c0fab8caadd8159f6bdd6fa03e66d4b4af9c |
25-Jun-2009 |
Devang Patel <dpatel@apple.com> |
No need to code gen MDNodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74150 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 0de1fc4f416b3e94749ca84cdaede55b040a8b60 |
24-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
sink management of DwarfWriter & MachineModuleInfo into the AsmPrinter base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74101 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 1f522feabf25134249bc7894e04f5b89fa071b7f |
24-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
sink dwarf finalization out of each target into AsmPrinter::doFinalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74097 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 0a7befa8bd56621f51eaf9196417b866962bf7b1 |
24-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate the ExtWeakSymbols set from AsmPrinter. This eliminates
a bunch of code from all the targets, and eliminates nondeterministic
ordering of directives being emitted in the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74096 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| a96751fc8ff1cc9a225ffbba73de53e2b9e1ae35 |
24-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Provide InitializeAllTargets and InitializeNativeTarget functions in the
C bindings. Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74026 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCTargetMachine.cpp
|
| 7e9e36a23e07dfb0d7ceda3e76450073c0534f35 |
23-Jun-2009 |
Douglas Gregor <dgregor@apple.com> |
Eliminate object-relinking support from CMake. Fixes PR 4429 and
cleans up the CMake-based build system a bit. Started by a patch from
Xerxes Rånby.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73969 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
|
| 66b4d3ba52f37e38a112f57612343b8f6dd7719e |
20-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Initialize MMI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73813 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 14a55d952cf238fff42da53a75f39cf06dab184b |
19-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Move up dwarf writer initialization in common AsmPrinter class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73784 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 4e0f25b603c96ce43474441e99252c5cd88c2e2e |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
merge the common darwin settings from the X86/PPC/ARM targets
into DarwinTargetAsmInfo.cpp. The remaining differences should
be evaluated. It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73742 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| a93ca92379129e87e0130609ac78422fcf6dd21e |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
move mangler quote handling from asm printers to TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73738 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCTargetAsmInfo.cpp
|
| b839c3f577e03467bce8904eb2a02b124ec19ec8 |
19-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
simplify macro debug info directive handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73736 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| b13bafe5c12dd908b55c559c93adaeb1627ed096 |
18-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73720 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 1555a23335400143f2b54a66aedc4b5cbbb79f8d |
16-Jun-2009 |
Douglas Gregor <dgregor@apple.com> |
Introduce new headers whose inclusion forces linking and
initialization of all targets (InitializeAllTargets.h) or assembler
printers (InitializeAllAsmPrinters.h). This is a step toward the
elimination of relinked object files, so that we can build normal
archives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73543 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCTargetMachine.cpp
|
| 0da9975299aa68b34464cea4344102466743c28f |
07-Jun-2009 |
Eli Friedman <eli.friedman@gmail.com> |
PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73009 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 2392efef1bd2599231ab659dd6ba4233bf5df94c |
06-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72969 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachineFunctionInfo.h
|
| d18e31ae17390d9c6f6cf93d18badf962452031d |
05-Jun-2009 |
Devang Patel <dpatel@apple.com> |
Add new function attribute - noredzone.
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72894 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 4c9369df57a52cec5e1fc735e61a979766288074 |
04-Jun-2009 |
Dale Johannesen <dalej@apple.com> |
Fix FP_TO_UINT->i32 on ppc32 -mcpu=g5. This was
using Promote which won't work because i64 isn't
a legal type. It's easy enough to use Custom, but
then we have the problem that when the type
legalizer is promoting FP_TO_UINT->i16, it has no
way of telling it should prefer FP_TO_SINT->i32
to FP_TO_UINT->i32. I have uncomfortably hacked
this by making the type legalizer choose FP_TO_SINT
when both are Custom.
This fixes several regressions in the testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72891 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 434dd4fd94f5f248492c675e4285e7d67342d4c4 |
01-Jun-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72697 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCTargetMachine.cpp
|
| a3f99f90338d89354384ca25f53ca4450a1a9d18 |
30-May-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
First patch in the direction of splitting MachineCodeEmitter in two subclasses:
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCCodeEmitter.cpp
PCJITInfo.cpp
PCJITInfo.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| c06441e5ea55d1e48a85e99ed2615ff4f459b4c2 |
28-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Return the operand rather than a null SDValue when the given SELECT_CC
is actually legal. Part of LegalizeDAG cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72513 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ba2352b0663e718855d1898fab6d3308dedd14fc |
27-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Ger rid of some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72494 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1a8229b1628831da37778e9200824e48c5a38172 |
24-May-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Make the PPC backend use a legal type for the operands to the BUILD_VECTOR
nodes it generates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72356 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 41a024385f1220eadc48b48cb4c044a5fbc1b361 |
23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate CPU string out of SubtargetFeatures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4 |
13-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 8d730fbde54b7ac9809fc12852c2a8d30f5bec3d |
11-May-2009 |
Jay Foad <jay.foad@gmail.com> |
Don't #include DerivedTypes.h from TargetData.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71468 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 777d2306b36816a53bc1ae1244c0dc7d998ae691 |
09-May-2009 |
Duncan Sands <baldrick@free.fr> |
Rename PaddedSize to AllocSize, in the hope that this
will make it more obvious what it represents, and stop
it being confused with the StoreSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71349 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 82ae933e55839713ea039e7c6353483b14dc5724 |
09-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
PPC::B and PPC::BCC's target operand may be an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71282 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 98a366d547772010e94609e4584489b3e5ce0043 |
30-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b |
29-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| c69d56f1154342a57c9bdd4c17a10333e3520127 |
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
r70270 isn't ready yet. Back this out. Sorry for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 2e9d5f912a9841d3685ba0241abe1131943fed29 |
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 9008ca6b6b4f638cfafccb593cbc5b1d3f5ab877 |
27-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
|
| 15684b29552393553524171bff1913e750f390f8 |
24-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert 69952. Causes testsuite failures on linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
|
| b706d29f9c5ed3ed9acc82f7ab46205ba56b92dc |
24-Apr-2009 |
Nate Begeman <natebegeman@mac.com> |
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
|
| f1d012c5956fc94ef9570855f4d276598c297eda |
24-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Fix spurious indentation in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69934 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
|
| 9062d9a55b0b8b473b927d8b020e36990e147a58 |
17-Apr-2009 |
Chris Lattner <sabre@nondot.org> |
Fix some failures in targets on available_externally functions,
this fixes a crash on CodeGen/Generic/externally_available.ll
on ppc hosts. Thanks to Nicholas L for pointing this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69333 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 7d16e85bfc2c6423c81ce87a177bf3b1b1012a04 |
10-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Pass in the std::string parameter instead of returning it by value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68747 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 022a27e363dcd3b8d4f7e6426559ab29d7a86d70 |
26-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
fix warning in -asserts build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67736 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 42bf74be1402df7409efbea089310d4c276fde37 |
25-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| f1c0ae9de5365a578fbdfebe4625fb281b0be592 |
24-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not emit comments unless -asm-verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 4dc2b39bf89d7c87868008ef8a0f807e0419aca6 |
11-Mar-2009 |
Duncan Sands <baldrick@free.fr> |
It makes no sense to have a ODR version of common
linkage, so remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66690 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 667d4b8de6dea70195ff12ef39a4deebffa2f5c7 |
07-Mar-2009 |
Duncan Sands <baldrick@free.fr> |
Introduce new linkage types linkonce_odr, weak_odr, common_odr
and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| f2950b00513e3d3c67c957e664eb3533adc3da22 |
03-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
Use early exit to reduce indentation. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65962 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0f8b53f19d29013ab18f3d444cea1e6305405611 |
03-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of Doxygen syntax issues. Escape special characters,
and put @file directives on their own comment line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65920 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCRegisterInfo.cpp
|
| 24e338e8a3dab2923db30fe63d77a5ac95456ff9 |
03-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
Generalize BuildVectorSDNode::isConstantSplat to use APInts and handle
arbitrary vector sizes. Add an optional MinSplatBits parameter to specify
a minimum for the splat element size. Update the PPC target to use the
revised interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65899 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a27ea9e89f38e9bcca4d67defb0bae887a16d72c |
01-Mar-2009 |
Bob Wilson <bob.wilson@apple.com> |
Combine PPC's GetConstantBuildVectorBits and isConstantSplat functions to a new
method in a BuildVectorSDNode "pseudo-class".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65747 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ded2b20e7e5399c90ee7cb560e70ab92ba620dcd |
27-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Alignment values for i64 and f64 on ppc64 were wrong,
possibly for the reason suggested by the comment.
No wonder it didn't work very well. This unblocks
bootstrap with assertions on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65601 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| a87008d90b7d894cfca53d407642acfd7be2af3c |
25-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert BuildVectorSDNode related patches: 65426, 65427, and 65296.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65482 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| df38043a46b873acb98e7ce0c700d82c1d888772 |
25-Feb-2009 |
Scott Michel <scottm@aero.org> |
Remove all "cached" data from BuildVectorSDNode, preferring to retrieve
results via reference parameters.
This patch also appears to fix Evan's reported problem supplied as a
reduced bugpoint test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65426 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 57f0db833dc30404f1f5d28b23df326e520698ec |
24-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Overhaul my earlier submission due to feedback. It's a large patch, but most of
them are generic changes.
- Use the "fast" flag that's already being passed into the asm printers instead
of shoving it into the DwarfWriter.
- Instead of calling "MI->getParent()->getParent()" for every MI, set the
machine function when calling "runOnMachineFunction" in the asm printers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65379 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 4214a5531cdbe538a358033f1847e55c4436be1b |
23-Feb-2009 |
Scott Michel <scottm@aero.org> |
Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65296 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 97357614b5957cc167c261d3be54713802715d9a |
18-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Factor out the code to add a MachineOperand to a MachineInstrBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| caa0c2caddcfb56de09e016c4c153d0609ffcf6e |
18-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64877 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| fdc40a0a696c658d550d894ea03772e5f8af2c94 |
17-Feb-2009 |
Scott Michel <scottm@aero.org> |
Remove trailing whitespace to reduce later commit patch noise.
(Note: Eventually, commits like this will be handled via a pre-commit hook that
does this automagically, as well as expand tabs to spaces and look for 80-col
violations.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64827 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 536a2f1f8467a17f6d145bd83f25faae1f689839 |
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove refs to non-DebugLoc version of BuildMI from PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64431 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 21b5541814d57d0a31f353948e4e933dbb1af6a4 |
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Eliminate a couple of non-DebugLoc BuildMI variants.
Modify callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| f902d246b69c972fa3e8f652b44d10abbb1f9355 |
12-Feb-2009 |
Chris Lattner <sabre@nondot.org> |
fix PR3538 for PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64383 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| d1c321a89ab999b9bb602b0f398ecd4c2022262c |
12-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Move debug loc info along when the spiller creates new instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| dc54d317e7a381ef8e4aca80d54ad1466bb85dda |
09-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 6f38cb61a94b3abab70f0ee463bdcf55d86d334e |
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Use getDebugLoc forwarder instead of getNode()->getDebugLoc.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64026 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1fdbc1dd4e9cb42c79a30e8dc308c322e923cc52 |
07-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| b300d2aa3ef08b5074449e2c05804717f488f4e4 |
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of the last non-DebugLoc versions of getNode!
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base. There's no
sensible way to associate debug info with these. I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands.
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63992 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e8d7230f480654cdb8ff1c3d0a38e1e9ab0bd55f |
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc getNode variants. Use
getCALLSEQ_{END,START} to permit passing no DebugLoc
there. UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63978 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| de06470330260f5937e7ca558f5f5b3e171f2ee5 |
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc versions of getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63969 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f5f5dce897269885754fc79adeb809194da52942 |
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Eliminate remaining non-DebugLoc version of getTargetNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63951 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| 770bcc7b15adbc978800db70dbb1c3c22913b52c |
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| ed2eee63a6858312ed17582d8cb85a6856d8eb34 |
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode. Lots of
caller changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| 3484c09e0da3c05c8a78946e090c7610208d937b |
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove a non-DebugLoc version of getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63889 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 4be0bdf7c1162824927dd3de89e016ae4934d0d6 |
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of getMergeValues, ZeroExtendInReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63800 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a05dca4f9e051fad19fe9b5f6cce2715c1e5d505 |
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63789 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| 33c960f523f2308482d5b2816af46a7ec90a6d3d |
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of getLoad and getStore.
Adjust the many callers of those versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63767 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 39355f9fea790c5a1b12ef0fdcfeac3f533232ea |
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc forms of the exotic forms
of Lod and Sto; patch uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63716 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f5d9789a7fddc9173cee104c8f25a7564bad3f28 |
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove some more non-DebugLoc versions of construction
functions, with callers adjusted to fit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63705 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8ad9b43e690e8773cf836b30e8da26bc71e18844 |
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove a few non-DebugLoc versions of node creation
functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63703 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 7d2ad624fa749a6d3edac0d94e9c107989c16304 |
31-Jan-2009 |
Dale Johannesen <dalej@apple.com> |
Make LowerCallTo and LowerArguments take a DebugLoc
argument. Adjust all callers and overloaded versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1465d61bdd36cfd6021036a527895f0dd358e97d |
28-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Rename getAnalysisToUpdate to getAnalysisIfAvailable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63198 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 9e79091f1a2c8a4ef0d238dbddaea273d27ef404 |
27-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Respect the DisableRedZone flag on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63119 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 1902a129a5b9fc9ac1ecbaf76d2ff7a1bf04691a |
25-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Private linkage support for PPC / Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62955 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 |
20-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| c1a168a0fcbc7483a879e617e91824c4a7e6eece |
19-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix 80 col violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62518 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 5fc742d5b2b647b3dce2c9ba943a2499d980c347 |
19-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Handle ISD::DECLARE with PIC relocation model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62516 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| ee5c2b8ba2bd9670931705ca04a46052d534ade9 |
16-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62373 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| 2836c283bb1c14baa50994f60769d665da608ad7 |
16-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Initial hazard recognizer support in post-pass scheduling. This includes
a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62291 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
|
| fc54c552963545a81e4ea38e60460590afb2d5ae |
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Generalize the HazardRecognizer interface so that it can be used
to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62284 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelDAGToDAG.cpp
|
| bb46f52027416598a662dc1c58f48d9d56b1a65b |
15-Jan-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add the private linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 79ce276083ced01256a0eb7d80731e4948ca6e87 |
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 73e0914848662404cf2aa18eb049ff5aae543388 |
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Const-qualify getPreIndexedAddressParts and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62259 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| ceb4d1aecb9deffe59b3dcdc9a783ffde8477be9 |
12-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Rename getABITypeSize to getTypePaddedSize, as
suggested by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62099 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 9b8f542e2746b28721b3ec603c3aaaa10ea708fc |
09-Jan-2009 |
Misha Brukman <brukman+llvm@gmail.com> |
Removed trailing whitespace from Makefiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61991 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/Makefile
akefile
|
| eb3fc289141ad44883acbb91e839ab1b9a0f2025 |
09-Jan-2009 |
Devang Patel <dpatel@apple.com> |
Convert DwarfWriter into a pass.
Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61955 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| d68a07650cdb2e18f18f362ba533459aa10e01b6 |
05-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Tidy up #includes, deleting a bunch of unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCSubtarget.cpp
|
| 5480c0469e5c0323ffb12f1ead2abd169d6cc0e7 |
01-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType. In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61542 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 2f6fea90a54787d873cfc25f33668cb4cc7d6e1e |
19-Dec-2008 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix bug 3202.
The EH_frame and .eh symbols are now private, except for darwin9 and earlier.
The patch also fixes the definition of PrivateGlobalPrefix on pcc linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61242 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| ae94e594164b193236002516970aeec4c4574768 |
05-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Re-did 60519. It turns out Darwin's handling of hidden visibility symbols are a bit more complicate than I expected. Both declarations and weak definitions still need a stub indirection. However, the stubs are in data section and they contain the addresses of the actual symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60571 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCSubtarget.cpp
|
| a8103dad4e84e031c5845e18268655cc0bfbdb8d |
04-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert r60519. It was causing a bootstrap failure:
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT barrier.lo -MD -MP -MF .deps/barrier.Tpo -c ../../../llvm-gcc.src/libgomp/barrier.c -fno-common -DPIC -o .libs/barrier.o
checking for sys/file.h... /var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:non-relocatable subtraction expression, "_gomp_tls_key" minus "L1$pb"
/var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:symbol: "_gomp_tls_key" can't be undefined in a subtraction expression
make[4]: *** [barrier.lo] Error 1
make[4]: *** Waiting for unfinished jobs....
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT alloc.lo -MD -MP -MF .deps/alloc.Tpo -c ../../../llvm-gcc.src/libgomp/alloc.c -o alloc.o >/dev/null 2>&1
yes
checking for sys/param.h... make[3]: *** [all-recursive] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libgomp] Error 2
make[1]: *** Waiting for unfinished jobs....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60527 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCSubtarget.cpp
|
| eb83dfde66b4614fe48a572ea2ee1d7b91bcbc19 |
04-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Visibility hidden GVs do not require extra load of symbol address from the GOT or non-lazy-ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60519 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCSubtarget.cpp
|
| f94a3273617e7f28518e871516a24ddc272bb1e8 |
03-Dec-2008 |
Dale Johannesen <dalej@apple.com> |
A step towards geting linux ppc to work (see PR 3099)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60497 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c54baa2d43730f1804acfb4f4e738fba72f966bd |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 15511cf1660cfd6bb8b8e8fca2db9450f50430ee |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrInfo.td
|
| 952b839ce9bc0c6d605d8b202c9cd76f7f05a77d |
03-Dec-2008 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix bug 3140.
Print a single parameter .file directive if we have an ELF target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60480 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 41474baac839da410302950305722cb0e026a094 |
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add a sanity-check to tablegen to catch the case where isSimpleLoad
is set but mayLoad is not set. Fix all the problems this turned up.
Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| aaffa05d0a652dd3eae76a941d02d6b0469fa821 |
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
There are no longer any places that require a
MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60349 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1607f05cb7d77d01ce521a30232faa389dbed4e2 |
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
Change the interface to the type legalization method
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 25cf2275ff7de3de3bc0e508abaf457413d74725 |
24-Nov-2008 |
Duncan Sands <baldrick@free.fr> |
If the type legalizer actually legalized anything
(this doesn't happen that often, since most code
does not use illegal types) then follow it by a
DAG combiner run that is allowed to generate
illegal operations but not illegal types. I didn't
modify the target combiner code to distinguish like
this between illegal operations and illegal types,
so it will not produce illegal operations as well
as not producing illegal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59960 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 19ea77f09d7226d4515b67e72be2f7b4dfee36dd |
24-Nov-2008 |
Matthijs Kooijman <matthijs@stdin.nl> |
Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59958 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/Makefile
|
| 027fdbe3ba6762b9867c6f891d64f76b7d6a4557 |
24-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| 03228089d5235f8c90477f88809139464e9c6ea5 |
23-Nov-2008 |
Duncan Sands <baldrick@free.fr> |
Rename SetCCResultContents to BooleanContents. In
practice these booleans are mostly produced by SetCC,
however the concept is more general.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59911 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 7751ad92daeea5a3502fbc266ae814baec5c03e6 |
22-Nov-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make a convenient helper for printing offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59872 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 343f0c046702831a4a6aec951b6a297a23241a55 |
20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Experimental post-pass scheduling support. Post-pass scheduling
is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.
This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.
The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59676 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.h
|
| cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2 |
18-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers. This fixes build breakage from r59540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| a7647e68a451994c5ae012b6a39e0d8d76d95653 |
17-Nov-2008 |
Dale Johannesen <dalej@apple.com> |
Move some former testcases (low-probability codegen
optimizations) into this wishlist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59455 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 92adc19be95347225f713db8cc1b5e22ac08bb5e |
15-Nov-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
Adds extern "C" ints to the .cpp files that use RegisterTarget, as
well as 2 files that use "Registrator"s. These are to be used by the
MSVC builds, as the Win32 linker does not include libs that are
otherwise unreferenced, even if global constructors in the lib have
side-effects.
Patch by Scott Graham!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59378 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCTargetMachine.cpp
|
| 0b45c9957fb7ad47e653fb43d455f6727170dad0 |
09-Nov-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Temporary revert my last commit: it seems it's triggering some subtle bug in backend
and breaks llvm-gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58926 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 0f569535676325a94981881eba6f8c7e61630992 |
08-Nov-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Factor out offset printing code into generic AsmPrinter.
FIXME: it seems, that most of targets don't support
offsets wrt CPI/GlobalAddress', was it intentional?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58917 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| ce4a70bd7608861e104b04265a0c71e5df8ecefe |
08-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename startFunctionStub to startGVStub since it's also used for GV non-lazy ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58897 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 53e4e4478c69c2c2115db833b54385117c764d14 |
07-Nov-2008 |
Dale Johannesen <dalej@apple.com> |
Make FP tests requiring two compares work on PPC (PR 642).
This is Chris' patch from the PR, modified to realize that
SETUGT/SETULT occur legitimately with integers, plus
two fixes in LegalizeDAG to pass a valid result type into
LegalizeSetCC. The argument of TLI.getSetCCResultType is
ignored on PPC, but I think I'm following usage elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58871 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| e5f4de42b5d26f60cec6fab0482eaf579246b218 |
07-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Flush the raw_ostream after emitting the assembly for a function.
This is a temporary fix for the -print-emitted-asm option, where
errs() is used as the stream, in the case where other code is
using stderr without using errs()' buffer. Hopefully soon we'll
fix errs() to be non-buffered instead. Patch by Preston Gurd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58859 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| cbb7ab259d08ac5aa5a4764b48628c4bcb5110c7 |
05-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Reintroduce a comment that was removed with the AddToISelQueue
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58760 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 8be6bbe5bfd50945ac6c5542e0f54a0924a5db8d |
05-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2fbfbd2a052fc3935271e441ceb1e401f26d145f |
30-Oct-2008 |
Duncan Sands <baldrick@free.fr> |
Shift amounts should have type getShiftAmountTy
(i32 for PPC, not i8). Correct this, and some
formatting while there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58451 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b384ab9ea113ad22a9c7034b98060c7470f0dcc5 |
29-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Add a RM pseudoreg for the rounding mode, which
allows ppcf128->int conversion to work with
DeadInstructionElimination. This is now turned
off but RM is harmless. It does not do a complete
job of modeling the rounding mode.
Revert marking MFCR as using all 7 CR subregisters;
while correct, this caused the problem in PR 2964,
plus the local RA crash noted in the comments.
This was needed to make DeadInstructionElimination,
but as we are not running that, it is backed out
for now. Eventually it should go back in and the
other problems fixed where they're broken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58391 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| 57760d96e2dfb485dc53fe2799df24bd18157abb |
28-Oct-2008 |
Duncan Sands <baldrick@free.fr> |
Fix darwin ppc llvm-gcc build breakage: intercept
ppcf128 to i32 conversion and expand it into a code
sequence like in LegalizeDAG. This needs custom
ppc lowering of FP_ROUND_INREG, so turn that on and
make it work with LegalizeTypes. Probably PPC should
simply custom lower the original conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58329 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8ad4c00c00233acb8a3395098e2b575cc34de46b |
27-Oct-2008 |
David Greene <greened@obbligato.org> |
Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag. Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like. This really helps when debugging instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58278 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| f14df0234030edee0ae02dfc1de3a4eb0c3b5977 |
25-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Mark MFCR as reading all condition code registers.
Prevents some more overzealous deletions (mostly
in AltiVec code).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58121 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| c12e5812be4dacc30781db84b045775c46580240 |
24-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Rewrite logic to figure out whether LR needs to
be saved/restored in the prolog/epilog. We need
to do this iff something in the function stores
into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58116 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
|
| 639076fb84ab02e75d39415bd426a6a576ddef62 |
23-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Mark defs and uses of CTR and LR correctly.
Prevents DeadMachineInstructionElim from thinking
things like MTCTR are dead (fixes massive
testsuite breakage at -O0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58043 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 5c5b6dfd0e1525305674560dd5d995e5f7eff2e5 |
22-Oct-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
CMake: Turned some libraries into partially linked objects. Corrected
names of LLVMCore and ARMCodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57943 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
|
| 54aeea39a743effe88eedb43d2f7f4805e806ab5 |
21-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Disable constant-offset folding for PowerPC, as the PowerPC target
isn't yet prepared for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57886 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| f522068412218cd14b2c2df74a3437717d255381 |
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Trim #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57649 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCJITInfo.cpp
|
| e79f5ef4e7b6dd5a2cc88de412c7dd65a7afbf44 |
16-Oct-2008 |
Duncan Sands <baldrick@free.fr> |
Fix warnings about mb/me being potentially used
uninitialized in these functions with gcc-4.3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57635 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 8e8b8a223c2b0e69f44c0639f846260c8011668f |
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Const-ify several TargetInstrInfo methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 0329466b6b4927f4e6f5d144891fef06a027fec5 |
14-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename LoadX to LoadExt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57526 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b8cab9227a0f6ffbdaae33e3c64268e265008a6a |
14-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Fix command-line option printing to print two spaces where needed,
instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| e563bbc312f8b11ecfe12b8187176f667df1dff3 |
12-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| 4520dd2b7b20af07d5a3e4d06d964a532044eb10 |
08-Oct-2008 |
Duncan Sands <baldrick@free.fr> |
Add <cstdio> include where needed by gcc-4.4.
Patch by Samuel Tardieu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57291 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriterInfo.cpp
|
| 6381a1334afa211fea8ec76ca7b22d26aee940dd |
05-Oct-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix weird think-o and unbreak build on all gcc-3.4.x-based platforms (e.g. mingw)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57106 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| da8ac5fd9130b70b61be61e4819faa8d842d708f |
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| d735b8019b0f297d7c14b55adcd887af24d8e602 |
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 4ae641f4d12c60ee1aaca5e42b6de231c6a02c40 |
02-Oct-2008 |
Devang Patel <dpatel@apple.com> |
Remove OptimizeForSize global. Use function attribute optsize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56937 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 5df3186f598163258fabf3448d9372843804d1ab |
29-Sep-2008 |
Duncan Sands <baldrick@free.fr> |
Rename isWeakForLinker to mayBeOverridden. Use it
instead of hasWeakLinkage in a bunch of optimization
passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56782 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| d5d8191b202c0f96f33c826c93d9796451ff7fca |
27-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56703 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 7810bfed5570c192e0714a8fd0e5130a0c38dd2e |
26-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode's getSignExtended to getSExtValue, for
consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56700 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 36a55023c1daae86afedf6e6672c0adad7bbe5ea |
26-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56683 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 86098bd6a63d2cdf0c9be9ef3151bd2728281fd7 |
26-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add "inreg" field to CallSDNode (doesn't increase
its size). Adjust various lowering functions to
pass this info through from CallInst. Use it to
implement sseregparm returns on X86. Remove
X86_ssecall calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56677 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e1ad087fcbb51ed66e450d010f849b5792b4b6fc |
26-Sep-2008 |
Oscar Fuentes <ofv@wanadoo.es> |
CMake: Builds all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56641 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/CMakeLists.txt
MakeLists.txt
|
| d751c64a679148bfe111bbba47f4a344ba813df9 |
26-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
If we have a function with an unreachable statement such that the ending debug
information is in an unreachable block, then it's possible that the high/low pc
values won't be set for the dwarf information. E.g., this function:
void abort(void) __attribute__((__noreturn__));
void dead_beef(void) __attribute__ ((noreturn));
int *b;
void dead_beef(void) {
*b=0xdeadbeef;
abort();
}
has a call to "@llvm.dbg.region.end" only in the unreachable block:
define void @dead_beef() noreturn nounwind {
entry:
call void @llvm.dbg.func.start(...)
call void @llvm.dbg.stoppoint(...)
...
call void @abort( ) noreturn nounwind
unreachable
return: ; No predecessors!
call void @llvm.dbg.stoppoint(...)
call void @llvm.dbg.region.end(...)
ret void
}
The dwarf information emitted is something like:
0x00000084: TAG_subprogram [5]
AT_name( "dead_beef" )
AT_external( 0x01 )
AT_prototyped( 0x01 )
AT_decl_file( 0x01 )
AT_decl_line( 0x08 )
Note that this is *not* the best fix for this problem, but a band-aid for an
gaping wound. This code needs to be changed when we revamp our debugging
information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56628 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 32b952a2a60d1091e0e17bb6ce788cd1d41e6f8b |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Reapply 56585:56589 with proper fix for some gcc versions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56621 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| 688535e005f370a98e82c10be7346eb981b3dfc7 |
25-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Temporarily backing out 56585:56589 to unbreak the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56607 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| 742fd195a687d8b22bde060783c1032dd62b07ab |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Minor cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56588 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| 93ed1029ecbd6975d7158881ffcc51235f8dd826 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of virtual inheritance for PPC TAI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56586 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| 00181a33d87d0c7676547d979b2faa1c08c91732 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of ReadOnlySection duplicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56582 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 6481873dc042d33c974399a7761a72524d1fe957 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of now unused {Four,Eight,Sixteen}ByteConstantSection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56580 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| d7ca416d6c9ae1966e0df8193112e3c5f430a053 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of duplicate char*/Section* TextSection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56574 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| c25e1ea5e9aa54952b6736a9579e25a5c2d8139f |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move actual section printing stuff to AsmPrinter from TAI reducing heap traffic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56573 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| 0c8e80607bc3296a4775f05c02f0d11df8e5cb04 |
25-Sep-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Drop obsolete hook and change all usage to new interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56572 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
|
| da43bcf624acb56a3d77bb5ae9a02728af032613 |
24-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| eaf42abab6d465c38891345d999255871cf03943 |
24-Sep-2008 |
Devang Patel <dpatel@apple.com> |
s/ParameterAttributes/Attributes/g
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56513 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0ba2bcfcc3149a25d08aa8aa00fb6c34a4e25bdd |
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Fix these enums' starting values to reflect the way that
instruction opcodes are now numbered. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56497 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
|
| 0bb41608e94adfe9884bc188457c4f6ae47ea43c |
22-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Make log, log2, log10, exp, exp2 use Expand by
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56471 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 7795932d41a84c921a5d348b7fa70f5d32e146d0 |
17-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Add trampoline support to PPC. GCC simply calls the "__trampoline_setup"
function with appropriate parameters. This allows us to support blocks on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56267 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 056292fd738924f3f7703725d8f630983794b5a5 |
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 9468a9b6beed640eca64274c8dcc5aed3b94450b |
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 014278e6a11fa0767853b831e5bf51b95bf541c5 |
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 095cc29f321382e1f7d295e262a28197f92c5491 |
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56183 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| f5aeb1a8e4cf272c7348376d185ef8d8267653e0 |
12-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 209a4099f96f0dfd340fab4ffaf2c2d8fc15aad6 |
11-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Succumb utterly to compatibility and implement
__sync_fetch_and_nand as ANDC, even though that's
not what nand means.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56087 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b2dfb89e0e7f1ee3e4fe4a3a1b3af148f0aec34f |
09-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Fix logic for not emitting no-dead-strip for some
objects in llvm.used (thanks Anton). Makes visible
the magic 'l' prefix for symbols on Darwin which are
to be passed through the assembler, then removed at
linktime (previously all references to this had been
hidden in the ObjC FE code, oh well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55973 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 3b217c6f5c21a5f16670b14e3beeaff5ee74df1c |
06-Sep-2008 |
Owen Anderson <resistor@mac.com> |
Fix constant pool loads, and remove broken versions of addConstantPoolReference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55868 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrBuilder.h
|
| ae73dc1448d25b02cabc7c64c86c64371453dda8 |
04-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Tidy up several unbeseeming casts from pointer to intptr_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55779 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCodeEmitter.cpp
|
| 6448d91ad1e5497fe2f7015d61b57cb5f3040879 |
04-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Clean up uses of TargetLowering::getTargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55769 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 7794f2a3a7778bdbc9bdd861db1fe914450e0470 |
04-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a619d012c13bee0572b96b045723dff5a117a5c2 |
02-Sep-2008 |
Dale Johannesen <dalej@apple.com> |
Fix some bugs in the code sequences for atomics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55643 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| acff339e391d23e748b69f61ae5c27fd5620c69f |
02-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55623 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 93c53e5583427ee567293a9a21c6c76fccf218ca |
31-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
fix a bunch of 80-col violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55588 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| 3156b62855667566bf48641252526b57a8c46a49 |
31-Aug-2008 |
Bill Wendling <isanbard@gmail.com> |
Expand for ROTR with MVT::i64.
Dale, Could you please review this?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55581 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ea9eedb7877008082b314b7ab322843fe2d402b5 |
30-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Add ppc partial-word ATOMIC_CMP_SWAP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55554 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0e55f0678cf3b40aa6e6d6139419254e568d7227 |
29-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Add partial word version of ATOMIC_SWAP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55546 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ba36cb5242eb02b12b277f82b9efe497f7da4d7f |
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrAltivec.td
|
| 5ad0bf658aa1e3df4b15b64647a6f91e0641c294 |
28-Aug-2008 |
Mon P Wang <wangmp@apple.com> |
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55499 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 97efa365869d3b7b62836434585360a232836f0e |
28-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Implement partial-word binary atomics on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55478 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 99a6cb92d173c142073416c81efe6d3daeb80b49 |
27-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
disallow direct access to SDValue::ResNo, provide a getter instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 940f83e772ca2007d62faffc83094bd7e8da6401 |
26-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| bdab93a2ef5d9574bb4e322e020849f9bc9c90d7 |
26-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Implement 32 & 64 bit versions of PPC atomic
binary primitives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55343 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 140a8bb00640a5af4ae29516ac7c18c22f75c2be |
25-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Remove PPC-specific lowering for atomics; the
generic stuff works fine.
Mark rewritten cmp-and-swap as not using CR1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55336 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 65e3973dff46a54ff764d09f57ebe59fbff6bbdf |
25-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
It's important for the cmp-and-swap to balance
loads and stores but it's even more important for
it to store the right value.:(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55319 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f350b277f32d7d47f86c0e54f4aec4d470500618 |
23-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| f87d6c02f5ef43c2ed54d14e4cd137758401a947 |
22-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Implement __sync_synchronize on ppc32. Patch by Gary Benson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55186 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrFormats.td
PCInstrInfo.td
|
| 5f0cfa299d16e6d43577317176cab1a463c912da |
22-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Rewrite ppc code generated for __sync_{bool|val}_compare_and_swap
so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55163 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| ad3460c3c968e33c5b9a07104b9fe5a5c27ff55b |
21-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Simplify SelectRoot's interface, and factor out some common code
from all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55124 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| cb3718832375a581c5ea23f15918f3ea447a446c |
21-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Use raw_ostream throughout the AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55092 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/PPCAsmPrinter.cpp
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 676fa7df9c53f97fd1a9419780573dfb788049b4 |
17-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use correct name for PPC codegen library
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54888 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 06be997654120c92f99850bf1a1704a2042ef639 |
17-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Factor out asmprinter out of ppc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54887 91177308-0d34-0410-b5e6-96231b3b80d8
smPrinter/Makefile
smPrinter/PPCAsmPrinter.cpp
akefile
PCAsmPrinter.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| afc20ae0e538a731f379dc1ae9ac564023078978 |
16-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
PPC/Linux normally uses named section for bss
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54847 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 888839e5edfa7e6678272f38f4d8b6ce7ff9029c |
16-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use proper strings section name for PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54846 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 44eb65cf58e3ab9b5621ce72256d1621a18aeed7 |
15-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 1db3c92306f551a81440dffd88ce07b9fbea97f4 |
11-Aug-2008 |
Nate Begeman <natebegeman@mac.com> |
Implement ISD::TRAP support on PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54644 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrFormats.td
PCInstrInfo.td
EADME.txt
|
| f5b6a47bb57fb5ffc734416d4d5d993e1a06273b |
08-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Handle visibility printing with all generality. Remove bunch of duplicate code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54540 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 382f0022726bff5ed088a171005c1ebde3635925 |
08-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use chars, where possible
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54539 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 7396e595434285d210fdafe51c41385b9fa709e3 |
08-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Convert PPC/Linux to new section printing stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54538 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| bc331a8d6f8231ba383e00b9f8adcf72db8f5358 |
08-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Switch PPC/Darwin to new section handling stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54537 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| 34da127be57c4d153f3ceae7a04b31aec373641f |
08-Aug-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54536 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 7232464bdaae5e6e48986a1e3b9a95fac7aa7bdf |
31-Jul-2008 |
Dale Johannesen <dalej@apple.com> |
Add a flag to disable jump table generation (all
switches use the binary search algorithm) for
environments that don't support it. PPC64 JIT
is such an environment; turn the flag on for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54248 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCTargetMachine.cpp
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| 8968450305c28444edc3c272d8752a8db0c2f34a |
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Tidy SDNode::use_iterator, and complete the transition to have it
parallel its analogue, Value::value_use_iterator. The operator* method
now returns the user, rather than the use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54127 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 982a05955ae9cfa71b8c6f3e80fed8ce5b778a1e |
24-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a catastrophic PPC64 ABI bug: i32 operands which are passed in memory (all of the parameter registers are used) are loaded from sp offsets that were off by 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53979 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| d038e04188047eca4749d025ef1f05f7ae660bca |
21-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Add VerifyNode, a place to put sanity checks on
generic SDNode's (nodes with their own constructors
should do sanity checking in the constructor). Add
sanity checks for BUILD_VECTOR and fix all the places
that were producing bogus BUILD_VECTORs, as found by
"make check". My favorite is the BUILD_VECTOR with
only two operands that was being used to build a
vector with four elements!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53850 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| badd8df972e158548d7014a193e44ff1bce55686 |
19-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak build: 'DarwinTargetAsmInfo' was already taken as PPC TAI flavour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53801 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
PCTargetMachine.cpp
|
| a7360f0178327e1ef4b1789612dbded46a704156 |
19-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Make sure custom lowering for LegalizeTypes
returns a node with the right number of
return values. This fixes codegen of
Generic/cast-fp.ll, Generic/fp_to_int.ll
and PowerPC/multiple-return-values.ll
when using -march=ppc32 -mattr=+64bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53794 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e8be6c63915e0389f1eef6b53c64300d13b2ce99 |
17-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.
Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.
This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.
These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCISelDAGToDAG.cpp
|
| 5330192ab59d65f285799ff5a9acd67d27417a56 |
12-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement llvm.atomic.cmp.swap.i32 on PPC. Patch by Gary Benson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53505 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| a54cf176613f9ae8301519a61b8935652c0fb8ae |
12-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Include a frame index in the "fixed stack" pseudo source value
instead of using the frame index for the SVOffset, which was
inconsistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53486 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| dc2fbddd9d204e904b8e61d1da1428579e7c55af |
11-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Trim unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53471 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 6291d69c4cf6cfff1d23c4363dc627872b825da0 |
10-Jul-2008 |
Chris Lattner <sabre@nondot.org> |
Remove extraneous vertical whitespace before Eric gets the wrong idea ;-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53411 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 85e7ac0353d6be357e6cab49f40304793ee601a1 |
10-Jul-2008 |
Chris Lattner <sabre@nondot.org> |
Fix an altivec constant miscompilation that Duncan found through
his work on legalizetypes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53410 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 03b5ee77620483408a36c09e67ef2db1c5164de9 |
09-Jul-2008 |
Dale Johannesen <dalej@apple.com> |
Remove extra call to DW.SetModuleInfo on Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53365 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 757809a1709dc939ae875f08419de158df04913d |
09-Jul-2008 |
Dale Johannesen <dalej@apple.com> |
Emit debug into for data-only files for Linux PPC.
I cannot test this target, let me know if it breaks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53362 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 94618eb8887e34ead9afb711186526e7b080535c |
09-Jul-2008 |
Dale Johannesen <dalej@apple.com> |
Emit debug info for data-only files. This version
applies to ppc Darwin only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53353 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 526be70f94538a2cc131ab1b0fd9f7264e00d297 |
09-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Back out 53254. It broke ppc debug info codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53280 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| f71cb9b3ed1d7b3e438e9990ce1587ba275e70bf |
08-Jul-2008 |
Dale Johannesen <dalej@apple.com> |
Make debug info come out in data-only files.
This is a question of the debugging setup code not
being called at the right time, and it's called from
target-dependent code for some reason. I have only
attempted to fix Darwin, but I'm pretty sure it's
broken elsewhere; I'll leave that to people who can
test it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53254 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 8e5f2c6f65841542e2a7092553fe42a00048e4c7 |
08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.cpp
PCInstrInfo.h
|
| 19d6d424aaa15788c590c2334081da744e6e9f64 |
08-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Clean up PPC register specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53209 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 2d97918ce9a41cbcb97ea5dfaaf740a0e833861a |
07-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Simplify this use of BuildMI. This is also in preparation for
pool-allocating MachineInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53198 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 1002c0203450620594a85454c6a095ca94b87cb2 |
07-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53179 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 126d90770bdb17e6925b2fe26de99aa079b7b9b3 |
04-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Rather than having a different custom legalization
hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes. No change if the
new LegalizeTypes infrastructure is not turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53137 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| ececf99c07febbcaeec73822519f0d36d3ee50c4 |
04-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Linux also does not require exception handling
moves in order to get correct debug info. Since
I can't imagine how any target could possibly
be any different, I've just stripped out the
option: now all the world's like Darwin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53134 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 9f1c8317a4676945b4961ddb9827ef2412551620 |
03-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53097 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 4bdcb61af33399d4e01fdf3c47ca1f1f5356e370 |
02-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Add a new getMergeValues method that does not need
to be passed the list of value types, and use this
where appropriate. Inappropriate places are where
the value type list is already known and may be
long, in which case the existing method is more
efficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53035 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| aa8f8889a861aadc061aec71fb7ed7f628848a2d |
02-Jul-2008 |
Bill Wendling <isanbard@gmail.com> |
Darwin doesn't need exception handling information for the "move" info when
debug information is being output, because it's leet!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52994 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 4406604047423576e36657c7ede266ca42e79642 |
01-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 7f460203b0c5350e9b2c592f438e40f7a7de6e45 |
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect its
purpose, and give it a custom SDNode subclass so that it doesn't
need to have line number, column number, filename string, and
directory string, all existing as individual SDNodes to be the
operands.
This was the only user of ISD::STRING, StringSDNode, etc., so
remove those and some associated code.
This makes stop-points considerably easier to read in
-view-legalize-dags output, and reduces overhead (creating new
nodes and copying std::strings into them) on code containing
debugging information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52924 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| db8d56b825efeb576d67b9dbe39d736d93306222 |
30-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Split scheduling from instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52923 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| f9516208e57364ab1e7d8748af1f59a2ea5fb572 |
30-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Revert the SelectionDAG optimization that makes
it impossible to create a MERGE_VALUES node with
only one result: sometimes it is useful to be able
to create a node with only one result out of one of
the results of a node with more than one result, for
example because the new node will eventually be used
to replace a one-result node using ReplaceAllUsesWith,
cf X86TargetLowering::ExpandFP_TO_SINT. On the other
hand, most users of MERGE_VALUES don't need this and
for them the optimization was valuable. So add a new
utility method getMergeValues for creating MERGE_VALUES
nodes which by default performs the optimization.
Change almost everywhere to use getMergeValues (and
tidy some stuff up at the same time).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52893 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b2931f29f3bb345eefe7d63bde1f230d235bca2e |
27-Jun-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide correct encoding for PPC LWARX instructions.
Patch by Gary Benson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52828 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| bc52cada0933f353d30da7b49af9a641bdb2c57d |
25-Jun-2008 |
Chris Lattner <sabre@nondot.org> |
Switch the PPC backend and target-independent JIT to use the libsystem
InvalidateInstructionCache method instead of calling through
a hook on the JIT. This is a host feature, not a target feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52734 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
PCJITInfo.h
|
| 28873106309db515d58889a4c4fa3e0a92d1b60e |
25-Jun-2008 |
Mon P Wang <wangmp@apple.com> |
Added MemOperands to Atomic operations since Atomics touches memory.
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 09d3fdc254c0b922c38f7c2bcad27c02fa0904f3 |
22-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Remove unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52613 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0011dc4738fbe624d44197ef9496517fd093eaa4 |
21-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Use MachineBasicBlock::transferSuccessors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52594 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0b725f17e0fade6820813557fe4b6f8208b7510d |
17-Jun-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add one more 'magic' define :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52420 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 7a17ff7b3f859024f5c8a6d247d8a2fd6e83f9b1 |
17-Jun-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak non-PPC builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52419 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 210539ebc466521e41e69b119649d59cc721b006 |
17-Jun-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide generic hooks for icache invalidation. Add PPC implementation.
Patch by Gary Benson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52418 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCJITInfo.cpp
PCJITInfo.h
|
| 16228c08b4cbad0620fe09b8afb3da70e3fbb040 |
16-Jun-2008 |
Chris Lattner <sabre@nondot.org> |
Add support for icache invalidation on non-darwin ppc systems.
Patch by Gary Benson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52332 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 58dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6 |
16-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 8e4eb09b1e3571965f49edcdfb56b1375b1b7551 |
08-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Remove comparison methods for MVT. The main cause
of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits. Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52098 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a8a8f427d6aecfde48fa34367925423170bab41e |
08-Jun-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily reverting r52056. It's causing PPC to fail to bootstrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52085 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 929b39f0a03bb6ae7c7b4ba0fac3e3aa4216b822 |
06-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52062 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6b4a65f4e7a668815593eb9dea2b994eaad70a86 |
06-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
PPC preferred loop alignment is 16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52056 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| 428ac54894f80ba4848d5f13576643f289412e6f |
03-Jun-2008 |
Dale Johannesen <dalej@apple.com> |
Add StringConstantPrefix to control what the
assembler names of string constants look like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51909 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| e7a83dfac62eb01a1dcc71b98363d3bf3a893a6c |
24-May-2008 |
Chris Lattner <sabre@nondot.org> |
Add FreeBSD/PPC support, patch by Marcel Moolenaar!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51538 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 247580b5695b948a0eb3ddaa236c9e206a4103fe |
24-May-2008 |
Dale Johannesen <dalej@apple.com> |
Put initialized const weak objects into correct
sections on ppc32 darwin. g++.dg/abi/key2.C
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51527 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 80d7e265138b3876c82c077c48c8f2a5cd103a46 |
23-May-2008 |
Dale Johannesen <dalej@apple.com> |
Add a missed CommonLinkage check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51503 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| c215b3ef5d9627f5fb6fe9034e46bc29ae592916 |
19-May-2008 |
Dale Johannesen <dalej@apple.com> |
Handle quoted names when constructing $stub's,
$non_lazy_ptr's and $lazy_ptr's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51277 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| ea7dd407149332e5ab1ffc42c8344ecd1751008f |
16-May-2008 |
Dale Johannesen <dalej@apple.com> |
Record weak external linkage in a case where we were
missing it. gcc.dg/darwin-weakimport-2.c.
Handle common and weak differently for darwin ppc32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51201 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| aafce77b17d340aace52bcd49d1944109d82f14a |
14-May-2008 |
Dale Johannesen <dalej@apple.com> |
Add CommonLinkage; currently tentative definitions
are represented as "weak", but there are subtle differences
in some cases on Darwin, so we need both. The intent
is that "common" will behave identically to "weak" unless
somebody changes their target to do something else.
No functional change as yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51118 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6 |
14-May-2008 |
Dan Gohman <gohman@apple.com> |
Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.h
PCTargetMachine.h
|
| 844731a7f1909f55935e3514c9e713a62d67662e |
13-May-2008 |
Dan Gohman <gohman@apple.com> |
Clean up the use of static and anonymous namespaces. This turned up
several things that were neither in an anonymous namespace nor static
but not intended to be global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51017 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCTargetMachine.cpp
|
| 30e62c098b5841259f8026df1c5c45c7c1182a38 |
30-Apr-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| 5e764233f398b6929b67701672a5e78fec20ce2e |
27-Apr-2008 |
Chris Lattner <sabre@nondot.org> |
A few inline asm cleanups:
- Make targetlowering.h fit in 80 cols.
- Make LowerAsmOperandForConstraint const.
- Make lowerXConstraint -> LowerXConstraint
- Make LowerXConstraint return a const char* instead of taking a string byref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50312 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 7c400dcb03074059776e39432c12c2a560c94223 |
25-Apr-2008 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50267 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| 8608f2eff2dab5345243c40d0bca9138f2dce6f1 |
19-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
64-bit atomic operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49949 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| 54fc97dcdc0ab747f49bd09c5a877bfd2a00e364 |
19-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
PPC32 atomic operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49947 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 51cc3c13eac78da242f0518fc42580e48dd5304f |
16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function
the stub will resolve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49814 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
PCJITInfo.h
|
| 52e724ad7e679ee590f4bd763d55280586a8f1bc |
16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCInstrInfo.cpp
PCInstrInfo.h
|
| 6ccbbd89906157187ac04b2b3237c4aee7acd095 |
15-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Change Divided flag to Split, as suggested by Evan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49715 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3541af73b6b8a083cf2d7784438d60e8bcce3883 |
14-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Reverse sense of unwind-tables option. This means
stack tracebacks on Darwin x86-64 won't work by default;
nevertheless, everybody but me thinks this is a good idea.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49663 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| c0cb28fd3abee9a8b40856990e04f1af2f9bd7b8 |
13-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Add a divided flag for the first piece of an argument divided into mulitple parts. Fixes PR1643
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49611 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 707e0184233f27e0e9f9aee0309f2daab8cfe7f8 |
12-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 4e1b79459fcf72216cdc42a59953e172c60e15ca |
08-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Implement new llc flag -disable-required-unwind-tables.
Corresponds to -fno-unwind-tables (usually default in gcc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49361 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 36b5c1338a03453ba1c110b120269ca972fb65a3 |
07-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Rename MemOperand to MachineMemOperand. This was suggested by
review feedback from Chris quite a while ago. No functionality
change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49348 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| dc1adac582fa120861f18ae7221bfe1421fea59f |
07-Apr-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Re-commit of the r48822, where the infinite looping problem discovered
by Dan Gohman is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49330 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6397c64441ddce3822ab0e712f224a11bd75811c |
03-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Backing out 48222 temporarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49124 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e00406281d94ebb9c69b7803311936f07994da43 |
02-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Cosmetic changes per EH patch review feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49096 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 1532f3ddd77c362dd5f613af06b4de636e3c5b0e |
02-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Recommitting EH patch; this should answer most of the
review feedback.
-enable-eh is still accepted but doesn't do anything.
EH intrinsics use Dwarf EH if the target supports that,
and are handled by LowerInvoke otherwise.
The separation of the EH table and frame move data is,
I think, logically figured out, but either one still
causes full EH info to be generated (not sure how to
split the metadata correctly).
MachineModuleInfo::needsFrameInfo is no longer used and
is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49064 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.cpp
|
| b6d5b1439047609c050576f3dc52b722e76bd30b |
01-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Revert 49006 for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49046 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.cpp
|
| 1544e4713be68edcf042de5aed7265dff7169d9d |
01-Apr-2008 |
Dale Johannesen <dalej@apple.com> |
Emit exception handling info for functions which are
not marked nounwind, or for all functions when -enable-eh
is set, provided the target supports Dwarf EH.
llvm-gcc generates nounwind in the right places; other FEs
will need to do so also. Given such a FE, -enable-eh should
no longer be needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49006 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.cpp
|
| ca1267c02b025cc719190b05f9e1a5d174a9caf7 |
31-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| d27c991cebe48fdf82b5d9eec6c2a1a244f82622 |
30-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Fix "Control reaches the end of non-void function" warnings,
patch by David Chisnall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48963 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e326332acd5fefb9854118603b4d07d4e44b64c5 |
26-Mar-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Use a linked data structure for the uses lists of an SDNode, just like
LLVM Value/Use does and MachineRegisterInfo/MachineOperand does.
This allows constant time for all uses list maintenance operations.
The idea was suggested by Chris. Reviewed by Evan and Dan.
Patch is tested and approved by Dan.
On normal use-cases compilation speed is not affected. On very big basic
blocks there are compilation speedups in the range of 15-20% or even better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48822 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e22e62b5c07616782cc3dca50f5f369965eb095c |
25-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Smaller function alignment when optimizing for size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48805 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 950a4c40b823cd4f09dc71be635229246dfd6cac |
25-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48801 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.h
|
| cfbb2f074da2842e42956d3b4c21e91b37f36f06 |
25-Mar-2008 |
Dan Gohman <gohman@apple.com> |
A quick nm audit turned up several fixed tables and objects that were
marked read-write. Use const so that they can be allocated in a
read-only segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48800 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 3e98c30cf5dd450879c0b9d6404353b02e2429c3 |
25-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
Use the bit size of the operand instead of the hard-coded 32 to generate the
mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48750 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 276dcbdc8db6614cfd5004dc7dc35e437ddf9c58 |
21-Mar-2008 |
Duncan Sands <baldrick@free.fr> |
Introduce a new node for holding call argument
flags. This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines. There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness. As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48640 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 71a2cb25ebc818383dd0f80475bc166f834e8d99 |
20-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
detabify llvm, patch by Mike Stump!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48577 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 7925ed05d0245aca0b0b2ea8d8a0b35b77c5ebd4 |
19-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add support for multiple return values for the PPC target by
converting call result lowering to use the CallingConvLowering
infastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48552 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 257f75d0b88a7d3d5ba5b7b7908a97f6dd56e27d |
17-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Make Complex long long/double/long double work
in ppc64 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48459 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCISelLowering.cpp
|
| d18330763965745fea05536939f5aadffcc6a5a6 |
17-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48447 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| fdd3ade005c7bd60f3dc74a49db82f91654e99ae |
17-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Next round of PPC32 ABI changes. Allow for gcc
behavior where a callee thinks a param will be
present in memory, even though the ABI doc says
it doesn't have to be. Handle complex long long
and complex double (4 and 8 return regs).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48439 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCISelLowering.cpp
|
| da47e6e0d003c873da960361549e57ee4617c301 |
15-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrInfo.td
|
| 8f5422c24b318d2680eafc177f199a180d5054da |
14-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Implement the real calling convention for ppc32 Altivec:
vectors go at the end of the memory area, after all
non-vector parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48364 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| d75686a471ee6ed5260e29d22d54f15152bbc9b4 |
13-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Do not promote float params to double in varargs
calls here. This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48310 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 404d99010d2d31398a16aa1ecfa9fb198b9e0afd |
12-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
One more bit of Altivec parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48269 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 75092de483561e3dcfa09cfc4420577272f7ac2d |
12-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Implement Altivec passing to varargs functions on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48264 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bfae83139dcb4fffd50b939e1b1224b0126f04d4 |
11-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Use PassManagerBase instead of FunctionPassManager for functions
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48256 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 034f60ed24c53c1e37f7695965f782faec2dff2b |
11-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Generalize ExpandIntToFP to handle the case where the operand is legal
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48206 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 82e4289fc7fed755442c215e9d3175c1badb831e |
10-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Disable prolog code that aligns the stack when a
local object of >16 byte alignment exists. It does not
work and getting it to work is not trivial, as explained
in the comment. This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.
(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec. So I think disabling it is OK.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48188 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 4a66e9a57e679b4f3243bf2061daf53c70102030 |
10-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
Change the "enable/disable" mechanism so that we can enable PPC register
scavenging for 32-bit and 64-bit separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48186 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
PCRegisterInfo.cpp
|
| d2cde68855125b6815b1575f29cd96927614b0cd |
10-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Default ISD::PREFETCH to expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48169 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| cb341de0e238f80dabf3da7b4f2aad58de6914bd |
10-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
fix 80 col violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48166 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 9348c69dcfe1aa1e7f92752a18222dcfbcd96214 |
10-Mar-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Stylistic modifications. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48158 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 5b8f82e35b51bf007de07a7ca9347d804084ddf8 |
10-Mar-2008 |
Scott Michel <scottm@aero.org> |
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 0404cd97e4f6ebfe4f8057d4e21119d77654dff2 |
10-Mar-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Add description of individual bits in CR. This fix PR1765.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48143 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| b8cafe3427a168414400e5dfcbea78996792d2c3 |
10-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48122 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| dc9971a2e322ddeff9eb97a6b03909094f1b8357 |
09-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Darwin PPC64 indirect call target goes in X12, not R12. This fixes these
two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48120 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 7f96f3912e20b94627fde28edc0a292f660b9197 |
08-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
More ppc32 byval handling (bug fixes). Things
are looking pretty good now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48043 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 27b7db549e4c5bff4579d209304de5628513edeb |
08-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a2fcff4d97c8fecd58cd977c45f1a883bc6ae1c3 |
08-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add support for calls with i128 return values on ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48041 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 5f5bf3a3fd06704e5752c91561a711fbaa856d58 |
07-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48030 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 9ed06db5c800c347b3ceac70df420f66c62e11c1 |
07-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add support for lowering 128-bit shifts on ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48029 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8419dd6aa6e8a26307222bdda473ac4bdccbb693 |
07-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Next bits of PPC byval handling. Basically functional
but there are bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48028 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| af8ee84fe5a0d61db29f5489352f98d13842729c |
07-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48027 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 49bd37d369e1124fa0844f60bf80ffb9247d4519 |
07-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
with 32 or 64-bit operands/results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48026 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 1f797a32fdc5e3841e9975756ff8c8e62cb41414 |
06-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Next bit of PPC ByVal handling; call-site code seems
correct now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47978 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2b5fab67c1a2d3ec1184c065e0a6bdaaaec9253a |
05-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
Removed spurious EnablePPCRS check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47918 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 5b3b695c2f1e11b6f5e0c89e1644211a92edab49 |
05-Mar-2008 |
Dale Johannesen <dalej@apple.com> |
Move PPC lowering functions into PPCTargetLowering
class (cosmetic). First piece of byval implementation;
this doesn't work yet. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47917 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 880d0f6018b6928bdcad291be60c801238619955 |
05-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
Use a command-line option to turn register scavenging on/off for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47915 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 7194aaf738a1b89441635340403f1c5b06ae18ef |
03-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
This is the initial check-in for adding register scavenging to PPC. (Currently,
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.td
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 150943c17867ad87cd372efc7a030d0c099d326e |
02-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47830 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 3be4893dcecaec7acc21ea445321e27a03ef99b2 |
02-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Evan implemented this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47827 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 8213f9cf94c740d078b444ecb125b9a581350837 |
29-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use enumeration for preffered EH dwarf encoding reason
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47770 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| 28d08fdb9f6572cafd5aae95c7caffa3cd136d8e |
28-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Interface of getByValTypeAlignment differed between
generic & x86 versions; change generic to follow x86
and improve comments. Add PPC version (not right
for non-Darwin.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47734 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| fb8075d03f5c87bd57dcc9c5f2304f6b13c55aad |
28-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47703 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 7b1b7f5c5a3fa4ece1d64a5e86a3d59622c282f6 |
28-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
EHPreferredDataFormat hook for PPC targets. Looks like Darwin
uses the same encoding everywhere. Linux FIXME'ed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47701 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| ec59b95a19f59c075c74f01016a57218775b5d55 |
27-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Don't hard-code the mask size to be 32, which is incorrect on ppc64
and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47692 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6ef781f3ce0d0311004adba9d1e7dbd7950918dd |
27-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Final de-tabification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| b3564aa8367fc38efdab0a812868f6f93b9d883e |
27-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert the last remaining users of the non-APInt form of
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47654 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| e6d088acc90e422451e098555d383d4d65b6ce6b |
26-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Rename PrintableName to Name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47629 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 74ab84c31ef64538a1b56e1f282e49303412ad17 |
26-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
would have been a Godsend here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.td
|
| 181eb737b28628adc4376b973610a02039385026 |
24-Feb-2008 |
Bill Wendling <isanbard@gmail.com> |
Some platforms use the same name for 32-bit and 64-bit registers (like
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47534 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 7c1c261272b43f2a9397c3052819b92c53918075 |
20-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove bunch of gcc 4.3-related warnings from Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47369 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCTargetMachine.cpp
|
| d497d9fab6e90499c703f3e672ec001dbfa074f9 |
16-Feb-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47213 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ec321b4d64ee02a1b90021c09d9513618787c6e8 |
15-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
Handle \n's in value names for more targets. The asm printers
really really really need refactoring :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47171 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 3b407444c9a45feb74b70b43138580d5f0299597 |
15-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Cosmetics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47168 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| ab1a0354ecff51d27098d6f11fbeabc65dec7123 |
15-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Remove warning about 64-bit code on processor
that doesn't support it. Per Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47162 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| db01c8ba26f288636d3f574a96af3499ee6d2579 |
15-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Rewrite tblgen handling of subtarget features so
it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to. Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47143 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCSubtarget.cpp
PCSubtarget.h
|
| e179584f9b740cf3a36bde70f8cab40de59b8081 |
14-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Change how FP immediates are handled.
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
if it is legal.
This allows ConstantFP to be handled like Constant, allowing for
targets that can encode FP immediates as MachineOperands.
As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants! Hooray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47121 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3 |
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| afe6c2b001a924cd74bd0aacfed5984d9af004b0 |
13-Feb-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Enable exception handling int JIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47079 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| a1998d1cbab495aad05c97b36836788809903b79 |
13-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47067 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 9f72d1a73029ed3bfb1f8ced755a1aeeb36fb4f1 |
13-Feb-2008 |
Chris Lattner <sabre@nondot.org> |
don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS.
DAGCombine is now quite good at zapifying them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47053 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b5041b30851b1173170a8d281b2e9571a2a04bdd |
13-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
readme updates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47051 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| ba8d51c1d7bf4ada96ff27550ac3576b31323b3a |
13-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Make register scavenging happy by not using a reg (CR0) that isn't defined
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47045 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| a4d16a1f0dcdd1ab2862737105f900e2c577532d |
13-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
commuteInstr() can now commute non-ssa machine instrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| fd29e0eb060ea8b4d490860329234d2ae5f5952e |
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 394d28048c2df33cdb48edba74720ff75f0e623c |
12-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert r46916 PPCTargetAsmInfo.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47020 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| a6ed0aa8ec1d374857cf94f56eead7f0b775ac28 |
11-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
additional missing feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46948 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
PCInstrInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
PCTargetMachine.h
|
| 16b0bd6c83821e6f56631c10717e5d0b6bab5cc0 |
10-Feb-2008 |
Nick Lewycky <nicholas@mxc.ca> |
Match GCC's behaviour for these sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46916 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 5fd79d0560570fed977788a86fa038b898564dfa |
08-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 3069b8743769527ce7af6cfb6591a2f0fc2faee4 |
07-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Follow Chris' suggestion; change the PseudoSourceValue accessors
to return pointers instead of references, since this is always what
is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46857 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 69de1932b350d7cdfc0ed1f4198d6f78c7822a02 |
06-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Re-apply the memory operand changes, with a fix for the static
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46827 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 5a804e3e21f8cfeb8b1a65aae0ef8d0e063a5256 |
05-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Ident mnemonics appropriately
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46746 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 4e3f5a4e9c13f216856515e6f000881f2c850736 |
05-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46724 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 4eecdeb3faf5df864790175da5d58301b751ec11 |
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of the annoying blank lines before labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46667 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| fcf5d4f456e5bb2547164c150797a023d22780a4 |
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak ppc debug support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46665 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a844bdeab31ef04221e7ef59a8467893584cc14d |
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 1b08bbca5592351a940bcd164bdec724ee954326 |
01-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove the nasty LABEL hack with a much less evil one. Now llvm.dbg.func.start implies a stoppoint is set. SelectionDAGISel records a new source line but does not create a ISD::LABEL node for this special stoppoint. Asm printer will magically print this label. This ensures nothing is emitted before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46635 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 334dc1f58d617dcff969a2e107febaae42bbc883 |
31-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46623 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bb81d97feb396a8bb21d074db1c57e9f66525f40 |
31-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add an extra operand to LABEL nodes which distinguishes between debug, EH, or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46609 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 0a75538a68cda3bddbda3980ea0128d9f6e6339d |
31-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Makes the same change in ppc backend: avoid inserting prologue before debug labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46596 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 1a0248690aaa9f7baaf1247e5f65a1c0c9e3783c |
31-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Rename ISD::FLT_ROUNDS to ISD::FLT_ROUNDS_ to avoid conflicting
with the real FLT_ROUNDS (defined in <float.h>).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46587 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c6c391daddbafa722d9ca87d18f204e9a6e617a3 |
31-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Create a new class, MemOperand, for describing memory references
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.
Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.
Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46585 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ff9b373e8f5006c629af81e2619778b4c4f5249e |
30-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| b625f2f8960de32bc973092aaee8ac62863006fe |
30-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46538 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| 824a721560f29eedb1427f81182e81cacf7e3ad4 |
26-Jan-2008 |
Bill Wendling <isanbard@gmail.com> |
If there's no instructions being emitted on X86 for a function, emit a
nop. Emit the nop directly for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46398 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 381802f8e06668d0ec5fc760804c83e511dafc7c |
26-Jan-2008 |
Bill Wendling <isanbard@gmail.com> |
If there are no machine instructions emitted for a function, then insert
a "nop" instruction so that we don't have the function's label associated
with something that it's not supposed to be associated with.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46394 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 1910e2f3ecec461d1eab8c44b16c977539080a6e |
25-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
JITEmitter.cpp was trying to sync the icache for function stubs, but
was actually passing a completely incorrect size to sys_icache_invalidate.
Instead of having the JITEmitter do this (which doesn't have the correct
size), just make the target sync its own stubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46354 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| f9c98e650d2795b8edfae8e1560c221029df218b |
23-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
The last pieces needed for loading arbitrary
precision integers. This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on. While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46280 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 25edeb32e77fdabbb986787a91a46435dfbaf716 |
23-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Honor explicit section information on Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46267 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 5c5eb80255293ece142b59e170256be0880b6bfb |
18-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Implement flt_rounds for PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46174 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ef97c676f97d33312eb5009522a9d51f2c25ccb1 |
18-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
get symbolic information for ppc ldbl nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46165 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a7a02fb828382afffd51596ee63822aa141a7147 |
18-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a latent bug exposed by my truncstore patch. We compiled stfiwx-2.ll to:
_test:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of:
_test:
fctiwz f0, f1
stfd f0, -8(r1)
nop
nop
lwz r2, -4(r1)
stb r2, 0(r4)
blr
The former is not correct (stores 4 bytes, not 1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46161 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| d15d086956f0b9fabd95d729023468e068e930c9 |
18-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Revert the part of 45848 that treated weak globals
as weak globals rather than commons. While not wrong,
this change tickled a latent bug in Darwin's strip,
so revert it for now as a workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46144 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| ddf89566a93081cb230bb9406a72ab2d3eada4a7 |
17-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
This commit changes:
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0bd4893a0726889b942405262e53d06cf3fe3be8 |
17-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
* Introduce a new SelectionDAG::getIntPtrConstant method
and switch various codegen pieces and the X86 backend over
to using it.
* Add some comments to SelectionDAGNodes.h
* Introduce a second argument to FP_ROUND, which indicates
whether the FP_ROUND changes the value of its input. If
not it is safe to xform things like fp_extend(fp_round(x)) -> x.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46125 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 4af349445222fa2a66b6248217ecd18eb6930646 |
16-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Fix and enable EH for x86-64 Darwin. Adds
ShortenEHDataFor64Bits as a not-very-accurate
abstraction to cover all the changes in DwarfWriter.
Some cosmetic changes to Darwin assembly code for
gcc testsuite compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46029 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| e46307a54c4fb49fea879f67cb399339b2899240 |
15-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
If someone wants to implement ppc TRAP, they can go for it :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46019 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 48be23cd65313b055ca80acb843ed244b18cd980 |
15-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename SDTRet -> SDTNone.
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 5080f4d9919d39b367891dc51e739c571a66036c |
11-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename MachineInstr::setInstrDescriptor -> setDesc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45871 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| c7406ae773a88b496b34d03896310631576c48a7 |
11-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Weak things initialized to 0 don't go in bss on Darwin.
Cosmetic changes to spacing to match gcc (some dejagnu
tests actually care).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45848 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
|
| 007f9847c44ddbe7fd04cba362b4ec0f0f40964b |
10-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
Output sinl for a long double FSIN node, not sin.
Likewise fix up a bunch of other libcalls. While
there I remove NEG_F32 and NEG_F64 since they are
not used anywhere. This fixes 9 Ada ACATS failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45833 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| dd41527a7dc6e2dacfad02ca8d4cbcb803b017da |
10-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove explicit sets of 'neverHasSideEffects' that can now be
inferred from the instr patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45824 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 9b37aaf04c633c68c9ef09d3991d9acfbef9f754 |
10-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
get def use info more correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 038129dd58acbb2cd6e80bee05649903897df967 |
10-Jan-2008 |
Dale Johannesen <dalej@apple.com> |
Emit unused EH frames for weak definitions on Darwin,
because assembler/linker can't cope with weak absolutes.
PR 1880.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45811 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| e51775dc5e3503092313fe77174127f4f4d17374 |
08-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
Use size_t to store Pos, avoid truncating value
on 64-bit builds. Analysis and original patch
by Török Edwin. Code audit found another place
with the same problem, also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45746 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| fe39edde27147d4645aff715d5a7630fa07fa885 |
08-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Finally implement correct ordered comparisons for PPC, even though
the code generated is not wonderful. This turns a miscompilation into
a code quality bug (noted in the ppc readme). This fixes PR642, which
is over 2 years old (!). Nate, please review this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45742 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
EADME.txt
|
| 749c6f6b5ed301c84aac562e414486549d7b98eb |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCISelDAGToDAG.cpp
PCRegisterInfo.cpp
|
| c17d69fa1e084668d6bb27441dbb505e2024f579 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
use predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45691 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| 7358c193fd2c7e6cc844f72e2203cbdb7692759f |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
no need to explicitly clear these fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45683 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 349c4952009525b27383e2120a6b3c998f39bd09 |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCRegisterInfo.cpp
|
| cc8cd0cbf12c12916d4b38ef0de5be5501c8270e |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove MachineOpCode typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 69244300b8a0112efb44b6273ecea4ca6264b8cf |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 43dbe05279b753aabda571d9c83eaeb36987001a |
07-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 834f1ce0312e3d00d836f9560cb63182c2c4570f |
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrInfo.td
|
| 2e48a70b35635165703838fc8d3796b664207aa1 |
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isStore -> mayStore to more accurately reflect what it captures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| c8478d8b12c2d7e4cea32d0c9940f5cac2baa4dd |
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Change the 'isStore' inferrer to look for 'SDNPMayStore'
instead of "ISD::STORE". This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores). This allows us to remove
more explicit isStore flags from the .td files.
Finally, add a warning for when a .td file contains an explicit
isStore and tblgen is able to infer it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45654 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 9c9fbf8e9c48f40d53cb434347d18395d9e0e02c |
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove some isStore flags that are now inferred automatically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45652 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrInfo.td
|
| 165b60de0b4a17e7d270e63fd4223b6c1c318fdd |
04-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Correct order of parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45562 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 02aabbf96b1f22144afe2bec8ad480a9b803f6b8 |
03-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Change MachineRelocation::DoesntNeedFnStub to NeedStub. This fields will be used
for non-function GV relocations that require function address stubs (e.g. Mac OS X in non-static mode).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45527 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 564da5d646dfeb56df931b42fefa7c5f2591057e |
02-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
leopard and above support alignment for common symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45493 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCSubtarget.cpp
PCSubtarget.h
|
| f6372aa1cc568df19da7c5023e83c75aa9404a07 |
01-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 264e6fec9f3962cb269031d6d84cee9f896e0286 |
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in my previous patch: refer to the impl not the pure virtual version. It's unclear why gcc would ever compile this...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45476 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 641055225092833197efe8e5bce01d50bcf1daae |
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 |
31-Dec-2007 |
Owen Anderson <resistor@mac.com> |
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
PCRegisterInfo.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCRegisterInfo.cpp
|
| 8aa797aa51cd4ea1ec6f46f4891a6897944b75b2 |
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| f73823000e2d5d6e1cf65bdf5a107297e18d35fb |
30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
More cleanups for MachineOperand:
- Eliminate the static "print" method for operands, moving it
into MachineOperand::print.
- Change various set* methods for register flags to take a bool
for the value to set it to. Remove unset* methods.
- Group methods more logically by operand flavor in MachineOperand.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45461 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 9a1ceaedc282f0cae31f2723f4d6c00c7b88fe90 |
30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PC.td
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCallingConv.td
PCCodeEmitter.cpp
PCFrameInfo.h
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrBuilder.h
PCInstrFormats.td
PCInstrInfo.cpp
PCInstrInfo.h
PCInstrInfo.td
PCJITInfo.cpp
PCJITInfo.h
PCMachOWriterInfo.cpp
PCMachOWriterInfo.h
PCMachineFunctionInfo.h
PCPerfectShuffle.h
PCPredicates.cpp
PCPredicates.h
PCRegisterInfo.cpp
PCRegisterInfo.h
PCRegisterInfo.td
PCRelocations.h
PCSchedule.td
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
PCSubtarget.cpp
PCSubtarget.h
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| fc643c5e88c596f217750dd91fcc66488dfed73d |
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
remove attribution from lib Makefiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45415 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 5a6c91a3eceb701396c30dd126079903006c5e0b |
21-Dec-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Fix unintented change from last commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45282 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 616585bbff926d806f154a0ae45f327c63abe54f |
21-Dec-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Enable EH for linux/ppc32 targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45281 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCTargetAsmInfo.cpp
|
| 696f768daf61044abff279b20326cf0138d02e1a |
19-Dec-2007 |
Dale Johannesen <dalej@apple.com> |
Enable EH on PPC Darwin. This basically works; there
are a couple of issues that show up with the optimizer,
but I don't think they're really EH problems.
(llvm-gcc testsuite users note: By default the testsuite
uses the unwinding code that's built as part of your local
llvm-gcc, which does not work. You need to trick it into
using the installed system unwinding code to get useful
results.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45221 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| ee912540e7870cd388ab0d8ed1aaa2d0204da54e |
19-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
Mark the "isRemat" instruction as never having side effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45190 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6e141fd04897e5eb4925bb6351297170ebd8a756 |
13-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| d96428597b9a4bcf3c0702bbb497796b922c2e91 |
08-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a significant code quality regression I introduced on PPC64 quite
a while ago. We now produce:
_foo:
mflr r0
std r0, 16(r1)
ld r2, 16(r1)
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
instead of:
_foo:
mflr r0
std r0, 16(r1)
lis r0, 0
ori r0, r0, 16
ldx r2, r1, r0
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
for:
void foo(void **X) {
*X = __builtin_return_address(0);
}
on ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44701 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 3fc027df4fca0355717515abb4d6e3753e6dee2a |
08-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
implement __builtin_return_addr(0) on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44700 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
EADME.txt
|
| 73944fb22270697e75408cba52cca276be371a1f |
08-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
refactor some code to avoid overloading the name 'usesLR' in
different places to mean different things. Document what the
one in PPCFunctionInfo means and when it is valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44699 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 5a759616b63a1e5dca76a2170ad0ba6410a11504 |
08-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix a compilation warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44691 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 0f940c95d4506f8d04fa2aeda8a79cadb3105fe3 |
07-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44687 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 8c24e74b02bea8681eac497075e6c27ef15aa2ea |
05-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added canFoldMemoryOperand for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44623 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| d64b5c82b97ad1b74eb9fd2f23257a7899b0c307 |
05-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| aee4af68ae2016afc5b4ec0c430e539c5810a766 |
02-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove redundant foldMemoryOperand variants and other code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44517 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| e62f97c094dba44e4c259d20135167fa91912eea |
01-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44479 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.h
|
| 1f873003266fbdec7c2c48a965c60f4e2e35a158 |
28-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Implement ExpandOperationResult for ppc i64 fp->int, which fixes
CodeGen/Generic/fp_to_int.ll among others. Its unclear why this
just started failing...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44407 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 789db09cde5f0cb2a0a5fc175c1141c760a3e807 |
27-Nov-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a crash on invalid code due to memcpy lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44378 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 1d4ce2ab962fee691239d58c8157c12b8037f9de |
21-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
Fix .eh table linkage issues on Darwin. Some EH support
for Darwin PPC, but it's not fully working yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44258 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
|
| 50cdabcfd52e88381ade61450d98a1c757195bef |
19-Nov-2007 |
Dan Gohman <gohman@apple.com> |
Remove meaningless qualifiers from return types, avoiding compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44240 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| b1d40d9dd791bd72a5c76c6286f963e1cec13082 |
13-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
Revert previous; these files aren't ready to go in yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44057 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| b97aec663b1591e71c9ddee6dbb327d1b827eda5 |
13-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
PCTargetAsmInfo.cpp
|
| c69107ca11282a905c252d1b62091951087f13dc |
13-Nov-2007 |
Bill Wendling <isanbard@gmail.com> |
Unifacalize the CALLSEQ{START,END} stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44045 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 0f8d9c04d9feef86cee35cf5fecfb348a6b3de50 |
13-Nov-2007 |
Bill Wendling <isanbard@gmail.com> |
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| 3809fbe789cd8d1c5b71d9428401799564aed26c |
13-Nov-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Completely forgot, that we have some debug information emission on PPC. This should fix
some regressions on ppc nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44029 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 20ab29068d8a8ec31f26f022634f1e0bc4b1da56 |
12-Nov-2007 |
Owen Anderson <resistor@mac.com> |
Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| f191c80cd79ee35e47b5a4feed98d687782dfe85 |
11-Nov-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
PCRegisterInfo.td
|
| ca0ed744852a7d9625572fbb793f65e81225a3e8 |
05-Nov-2007 |
Duncan Sands <baldrick@free.fr> |
Eliminate the remaining uses of getTypeSize. This
should only effect x86 when using long double. Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment). This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43688 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| f4c164c2b5bbaa2be4f1d8fedcf9df621378340d |
04-Nov-2007 |
Nick Lewycky <nicholas@mxc.ca> |
Fix crash before main on ppc/linux with static constructors. PR1771
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43676 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
|
| 79217064c618afecd4979aec6d2e8fe784565931 |
24-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Disable a couple more things for ppcf128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43267 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 152b7e18748f7e06a93260f22cc9dac8eb3abee2 |
23-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with right callee-saved defs set for ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43248 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 3311876c3c3147688b08f64c441e5bfaaa3412b3 |
22-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use ptr type in the immediate field of a BxA instruction so we don't end up selecting 32-bit call instruction for ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43228 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 26cb2862e982e5527ffb904568e204907ca9be17 |
19-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
comment fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43168 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| fabd32deb025ebd47c5eb47259d2424fd789b05c |
19-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
More ppcf128 issues (maybe the last)?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43160 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f0a0cddbcda344a90b7217b744c78dccec71851c |
19-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 58184e6878fdab651bc7c9a59dab2687ca82ede2 |
18-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| f602a2566845dc57444b9d40538c947b5ed23111 |
16-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a bug handling frame references in ppc inline asm when the frame offset
doesn't fit into 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43032 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 1de7c1dd6fdedc8ab2e450ba74e4b81d13e49af2 |
15-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
Change LowerFP_TO_SINT to create the specific code it needs instead of
unconditionally creating an i64 bitcast. With the future legalizer
design, operation legalization can't introduce new nodes with illegal
types.
This fixes the rest of olden on ppc32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43005 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 347d39f1fd8ad825a7ec5b8a3dce816723a56d42 |
14-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Revert 42908 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42960 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 296c1761416df3eb706dbcf5319f1f2267e1b4f7 |
14-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Fix type mismatch error in PPC Altivec (only causes
a problem when asserts are on). From vecLib.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42959 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8ddde0a151c5297ae5694a4b9201b2d3fe56b196 |
12-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Change the names used for internal labels to use the current
function symbol name instead of a codegen-assigned function
number.
Thanks Evan! :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42908 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| a3f269f7f6211958774f151833870935c91feaee |
12-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Mark vector pow, ctpop, cttz, and ctlz as Expand on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42904 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f96e4de403453e57aea75bcac1ed99af686d33c4 |
12-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Set ISD::FPOW to Expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42881 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6eaeff29b8a6990107735f7e5f5e49da38f56223 |
10-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Next PPC long double bits: ppcf128->i32 conversion.
Surprisingly complicated.
Adds getTargetNode for 2 outputs, no inputs (missing).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42822 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrFormats.td
PCInstrInfo.td
|
| 3ce990dc051622755afc22b55f95954c5a19e779 |
08-Oct-2007 |
Dan Gohman <gohman@apple.com> |
When we start enabling SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM in
target-indepenent lowering, don't use them on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42755 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 638ccd52b9fa2d1d03a1e85992c09e2bf6800fc6 |
06-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
Next powerpc long double bits. Comparisons work,
although not well, and shortening FP converts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42672 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 161e897b0fb35d156b2fe720fadabd975b0d6723 |
05-Oct-2007 |
Dale Johannesen <dalej@apple.com> |
First round of ppc long double. call/return and
basic arithmetic works.
Rename RTLIB long double functions to distinguish
different flavors of long double; the lib functions
have different names, alas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42644 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCISelLowering.cpp
|
| 66f0f640820b61cf9db814b6d187bae9faf7279c |
05-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Added a few target hooks to generate load / store instructions from / to any
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| cb406c25973b4e88a6c10ad839ef1beeb3664715 |
03-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Use empty() member functions when that's what's being tested for instead
of comparing begin() and end().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42585 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 82482944edd810c7a1803d6694d435adf341e611 |
28-Sep-2007 |
Dan Gohman <gohman@apple.com> |
TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets
other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42419 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 9efce638d307b2c71bd7f0258d47501661434c27 |
26-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 677ccc6e8b912e1a39259952b125954820062541 |
25-Sep-2007 |
Dan Gohman <gohman@apple.com> |
More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42316 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.h
|
| 76a4023096fc330db11d711197388d9f3ba91cc6 |
21-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Honor user-defined section specification of a global, ignores whether its initializer is null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42182 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 0f0daea654791f48f17f7bd87eeb97c0868adee4 |
21-Sep-2007 |
Devang Patel <dpatel@apple.com> |
Do not override user specified section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42179 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 92dfe2001e96f6e2b6d327e8816f38033f88b295 |
14-Sep-2007 |
Dan Gohman <gohman@apple.com> |
Remove isReg, isImm, and isMBB, and change all their users to use
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCBranchSelector.cpp
|
| fdd9f006bceaa4f24a969d1411917b9558cd156d |
14-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41947 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| fe4afb17d3370a1c3d4945d6558de544462b4ce6 |
12-Sep-2007 |
Bill Wendling <isanbard@gmail.com> |
Enable indirect encoding for the personality function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41873 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 071a279e94e30d51aff3b46a4651d686982488a0 |
11-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| f7331b3dd72409e644833ecaf62a0f6db03c97ee |
11-Sep-2007 |
Duncan Sands <baldrick@free.fr> |
Fold the adjust_trampoline intrinsic into
init_trampoline. There is now only one
trampoline intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bf8ae84a21011a7263c2a4183fdfd8e5755765a1 |
10-Sep-2007 |
Chris Lattner <sabre@nondot.org> |
Add some notes about better flag handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41808 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 82d25148a7aab0b7e048ab9b774207b3766d1bbf |
08-Sep-2007 |
Bill Wendling <isanbard@gmail.com> |
Add missing index versions of instructions to the map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41776 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 718cb665ca6ce2bc4d8e8479f46a45db91b49f86 |
07-Sep-2007 |
Owen Anderson <resistor@mac.com> |
Add lengthof and endof templates that hide a lot of sizeof computations.
Patch by Sterling Stein!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.cpp
|
| 399ea50dc3321b4cc16e0a5ea7c41495c55a01ba |
06-Sep-2007 |
Bill Wendling <isanbard@gmail.com> |
LVXL and STVXL are also a load and store resp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41733 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| c3536b8ecbe49b60cdf9ab76ca79dcea765f2802 |
05-Sep-2007 |
Bill Wendling <isanbard@gmail.com> |
Add the 64-bit versions of the DS* Altivec instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41717 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 67c906dce729d64861af8ca708f5e19d6a058b35 |
04-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix for PR1613: added 64-bit rotate left PPC instructions and patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41711 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| eaf089430e7681fcddc3465c3b33b9645273ab02 |
31-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Enhance APFloat to retain bits of NaNs (fixes oggenc).
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 35b35c5c320a71e4611fe2101452da685f8eeda0 |
30-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.h
|
| b8a80f03bf573a36b6f63b834aae2e91b82f96c6 |
30-Aug-2007 |
Bill Wendling <isanbard@gmail.com> |
Use i64 on a PPC64 machine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41590 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 48884cd80b52be1528618f2e9b3425ac24e7b5ca |
25-Aug-2007 |
Chris Lattner <sabre@nondot.org> |
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
changing the interface to allow for future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41384 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 90e167a908d8020133a9af901225e25d9c8d19be |
24-Aug-2007 |
Chris Lattner <sabre@nondot.org> |
Disable EH generation until PPC works 100%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41360 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| aabd0359a3441fc300834b13b1cd265f22d7d011 |
23-Aug-2007 |
Chris Lattner <sabre@nondot.org> |
new example
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41318 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 48bd15ed72bcf9464989516c078ed9d15030c95e |
09-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Fix arguments for some Altivec instructions. From SWB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40957 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 84109cd0158140f8590116fbf2240c678c951a5d |
08-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Fix spelling of mtvscr and mfvscr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40908 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 8c1e6a119a68b258365677a9ee5176af3525a26f |
03-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
long double patch 2 of N. Handle it in TargetData.
(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40792 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 61e729e2e9517ab2d8887bab86fb377900fa1081 |
02-Aug-2007 |
Dan Gohman <gohman@apple.com> |
More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
|
| caf778ab3b57f978d430ff9f56cfa7d2dec5aabb |
02-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Some out operands were incorrectly specified as input operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40697 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 66ffe6be0c7b50100a00cb0cc87a5d4983818572 |
30-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Vector fneg must be expanded into fsub -0.0, X.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40586 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
|
| 36397f50343639ce9a25996f2d790c656791ab92 |
27-Jul-2007 |
Duncan Sands <baldrick@free.fr> |
Support for trampolines, except for X86 codegen which is
still under discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b8275a3f6f6497889653cb2452d82a46f92b4926 |
25-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Don't ignore the return value of AsmPrinter::doInitialization and
AsmPrinter::doFinalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40487 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| e2b905232f8cc61a601bc4003de42d32f4b97dd2 |
25-Jul-2007 |
Nick Lewycky <nicholas@mxc.ca> |
Fix debug info and globals filled with zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40483 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
|
| ffbaccae029ac238972e3814967260f029b6058a |
21-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
No more noResults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrInfo.td
|
| 8bd6035750f1b290832a3b1c90766d9b45ed8d6b |
20-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added -print-emitted-asm to print out JIT generated asm to cerr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40123 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| d5f181a665be91d58019f3dbffedc8ebe49e6b9d |
20-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Oops. These stores actually produce results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40074 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 64d80e3387f328d21cd9cc06464b5de7861e3f27 |
19-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrFormats.td
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 2365f51ed03afe6993bae962fdc2e5a956a64cd5 |
14-Jul-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Long live the exception handling!
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| e7e7d0d7e39d0c7c659d26b97e8081fce0fcd749 |
13-Jul-2007 |
Dale Johannesen <dalej@apple.com> |
Skeleton of post-RA scheduler; doesn't do anything yet.
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39816 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| 75ce010f7b6a47d9656e546b5db4a9cd77ba1dee |
11-Jul-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Assert when TLS is not implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39737 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 532dc2e1f2473b16b48566c1cbc9eefe94a4e58e |
09-Jul-2007 |
Dan Gohman <gohman@apple.com> |
Change getCopyToParts and getCopyFromParts to always use target-endian
register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38471 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 87bdba6d6a1684373c94df0363a3b620de6dab6c |
09-Jul-2007 |
Chris Lattner <sabre@nondot.org> |
The various "getModuleMatchQuality" implementations should return
zero if they see a target triple they don't understand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38463 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 06aae67b8315aa915f55abd5927453dbe8b11169 |
07-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Do away with ImmutablePredicateOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37961 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| a99be51bf5cdac1438069d4b01766c47704961c8 |
05-Jul-2007 |
Gabor Greif <ggreif@gmail.com> |
Here is the bulk of the sanitizing.
Almost all occurrences of "bytecode" in the sources have been eliminated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCSubtarget.cpp
|
| 7e36966de44a35f83e8dec22ed2f25b8c83736ed |
05-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
PPC conditional branch predicate does not change after isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37893 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| e644ef7b098460ce831220c780cbe25eaef3fb28 |
29-Jun-2007 |
John Criswell <criswell@uiuc.edu> |
Convert .cvsignore files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37801 91177308-0d34-0410-b5e6-96231b3b80d8
cvsignore
|
| 2bda17c92229e7116adf2edd3eea98c0a12f43cb |
29-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37790 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| ea859be53ca13a1547c4675549946b74dc3c6f41 |
22-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| 3ee774091ba6d25c7db4b0481b963454bd6d9903 |
19-Jun-2007 |
Chris Lattner <sabre@nondot.org> |
describe an argument, hide it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37650 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 52387be1e00291a88edc4c2b8a0b5c22478bcd83 |
19-Jun-2007 |
Chris Lattner <sabre@nondot.org> |
If a function is vararg, never pass inreg arguments in registers. Thanks to
Anton for half of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37641 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 51eaa86758338d5935c0eff0469c418b1256aba7 |
15-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37579 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 13e8b51e3ec014c5d7ae83afdf3b8fd29c3a461d |
13-Jun-2007 |
Dale Johannesen <dalej@apple.com> |
Handle blocks with 2 unconditional branches in AnalyzeBranch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8 |
08-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a utility routine to check for unpredicated terminator instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 2fb813d70b8928f355b35f782889c55c1aa891ef |
29-May-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Implementation of compilation callback in PPC ELF32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37340 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| e6e435498c0e35d98644f868886d39c4665bb83a |
22-May-2007 |
Dale Johannesen <dalej@apple.com> |
name change requested by review of previous patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37289 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 81da02b553b86868637f27b89c6e919c31ed5b51 |
22-May-2007 |
Dale Johannesen <dalej@apple.com> |
Make tail merging the default, except on powerPC. There was no prior art
for a target-dependent default with a command-line override; this way
should be generally usable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37285 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 126f17a17625876adb63f06d043fc1b1e4f0361c |
21-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
BlockHasNoFallThrough() now returns true if block ends with a return instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37266 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| f5135be3fc20534ccaee52cbfa80a8408af5672b |
19-May-2007 |
Dan Gohman <gohman@apple.com> |
Apply this patch:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37240 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b5cdaa257e167a08a8a54ea9249d847ccc415ce0 |
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37192 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| ccde4cb8ab6ba78296ffa0cb261757cd9cacb18a |
17-May-2007 |
Chris Lattner <sabre@nondot.org> |
add support for 128-bit add/sub on ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37158 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 9f5d5783ecdb02ebf2000fcf50ee67628bc2e07d |
15-May-2007 |
Chris Lattner <sabre@nondot.org> |
fix some subtle inline asm selection issues
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37067 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f88b3a5698dc419f5f2c48e39e4058577599fa00 |
08-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
PredicateOperand can be used as a normal operand for isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36947 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 43182ac0d6c2fa99b71cac66fa3da1fa063b2413 |
08-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
R0 is a sub-register of X0, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36939 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 5f696035e5d96a64b58d654f1608de349bee0f5e |
03-May-2007 |
Chris Lattner <sabre@nondot.org> |
revert accidental commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36668 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
|
| 4105a9fec0b7aa57de3455fb69de1861a5d74752 |
03-May-2007 |
Chris Lattner <sabre@nondot.org> |
add support for printing offset of global
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36667 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCCallingConv.td
|
| 1997473cf72957d0e70322e2fe6fe2ab141c58a6 |
03-May-2007 |
Devang Patel <dpatel@apple.com> |
Drop 'const'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36662 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCodeEmitter.cpp
|
| 3e15bf33e024b9df9e89351a165acfdb1dde51ed |
02-May-2007 |
Devang Patel <dpatel@apple.com> |
Use 'static const char' instead of 'static const int'.
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCodeEmitter.cpp
|
| 794fd75c67a2cdc128d67342c6d88a504d186896 |
01-May-2007 |
Devang Patel <dpatel@apple.com> |
Do not use typeinfo to identify pass in pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCodeEmitter.cpp
|
| 97de9138217d6f76f25100df272ec1a3c4d31aad |
01-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
eliminateFrameIndex() change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 7bf1c272ab27297a7bbab329de3f17ddb26e02a3 |
01-May-2007 |
Nate Begeman <natebegeman@mac.com> |
llvm bug #1350, parts 1, 2, and 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36618 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 6c087e5585b227f3c1d8278304c7cfbc7cd4f6e8 |
26-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Match MachineFunction::UsedPhysRegs changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36452 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 1e341729dd003ca33ecea4abf13134f20062c5f8 |
25-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Relex assertions to account for additional implicit def / use operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 6c2d2601614ba769c0371f01e22ebebd92643be5 |
25-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
Fix PR1351 and CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36410 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 7c7ba9d2d587303a486f29c68416bd8391499f77 |
10-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in PPCTargetLowering::isLegalAddressingMode, scales other than 0/1/2
are always unsupported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35835 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6733a1661a6ca9e904d132cfe92b2a828193e95d |
05-Apr-2007 |
Reid Spencer <rspencer@reidspencer.com> |
Squelch a warning about mismatch between sign of constant and sign of return
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35674 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
|
| 0111999a88077f237c49d03c5e7891ec874b33a9 |
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Starting implementation of the ELF32 ABI specification of varargs handling.
LowerVASTART emits the right code if the subtarget is ELF32, the other intrinsics
(VAARG, VACOPY and VAEND) are not yet implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35625 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| ec58d9f9ddfbfe16ea40822164f340b256c89191 |
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF tests to ELF32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCFrameInfo.h
PCISelLowering.cpp
PCInstr64Bit.td
PCRegisterInfo.cpp
PCSubtarget.h
|
| cfcd8da70b33118ab3765ed54d63f497321932ce |
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Addition to the previous commit for getCalleeSavedRegClasses:
"The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35623 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| ef3c030e0e08b7d9446445823f4972fcf18c1ce1 |
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35622 91177308-0d34-0410-b5e6-96231b3b80d8
PCCallingConv.td
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.cpp
|
| aa43e9f73b4ccd700530803803e074eff9b3dca5 |
02-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a bug which caused us to never be able to use signed comparisons for
equality comparisons of a constant. This allows us to codegen the 'sintzero'
loop in PR1288 as:
LBB1_1: ;cond_next
li r4, 0
addi r2, r2, 1
stw r4, 0(r3)
addi r3, r3, 4
cmpwi cr0, r2, -1
bne cr0, LBB1_1 ;cond_next
instead of:
LBB1_1: ;cond_next
addi r2, r2, 1
li r4, 0
xoris r5, r2, 65535
stw r4, 0(r3)
addi r3, r3, 4
cmplwi cr0, r5, 65535
bne cr0, LBB1_1 ;cond_next
This implements CodeGen/PowerPC/compare-simm.ll, and also cuts 74
instructions out of kc++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35590 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| fcb1e61a4375c4bdb015aafcec559fc8e577da99 |
31-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35530 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| c9addb74883fef318140272768422656a694341f |
31-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
implement the new addressing mode description hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35521 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 1baa1971a66d6a250d07b7bee249653bd91453a0 |
27-Mar-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
"The C standards do say that "char" may either be a "signed char" or "unsigned
char" and it is up to the compilers implementation or the platform which is
followed."
http://www.arm.linux.org.uk/docs/faqs/signedchar.php
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35382 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 86c9c341e97a4f08e4984077af57bf106d980db0 |
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35334 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 013e051aac1c3d5d4468eb83b3bc8cfa58cef421 |
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35330 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| b6ead97b7e576721f47a3bc3739fea52f261e22f |
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/PowerPC/2007-03-24-cntlzd.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35329 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 4234f57fa02b1f04a9f52a7b3c2aa22d32ac521c |
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 82d4264c1fe71480bcaa63235e385a01e38dbe8c |
21-Mar-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Protect R31's frame offset from being used by callee-saved registers, when R31
is the frame pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35233 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| bf2c8b3c96f5c885095a10b0fcb29438f92d73c2 |
20-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added MRegisterInfo hook to re-materialize an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| b2ec1cc6cb1c34d3e43559ab59619b29f010684b |
13-Mar-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Stack and register alignment of call arguments in the ELF ABI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35083 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 861939152debbaa15a55a196a4321837c7bc379d |
13-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35074 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 032953d74746fa89b62e49b63a38ba6d8827b81a |
08-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Putting more constants which do not contain relocations into .literal{4|8|16}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35026 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 98ded765c2dc2f256e9f11502ca302f2b24f31e8 |
08-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
For Darwin, put constant data into .const, .const_data, .literal{4|8|16}
sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35017 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
|
| 28b3c45109153bc50d3d9e97dccb25ffd043fa50 |
06-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Minor interface change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34967 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| b9a7bea99c8aac6eb3509df93a25fe9cc3858bde |
06-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
Switch PPC return lower to use an autogenerated CC description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34940 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
PC.td
PCCallingConv.td
PCISelLowering.cpp
|
| f54949dc494ced20b24b968284a25037fca06743 |
03-Mar-2007 |
Nick Lewycky <nicholas@mxc.ca> |
Emit low/high immediate loads properly for Linux/PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34871 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 43c6e7cd9b0d9a3b0006650ddfac256848f10d51 |
01-Mar-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Implemented the frameaddress intrinsic for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34787 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| fec910c3b9ba5790e5a627e1801fce25fbdddbaa |
28-Feb-2007 |
Nate Begeman <natebegeman@mac.com> |
More Mach-O writer improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34740 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriterInfo.cpp
PCMachOWriterInfo.h
|
| 5e6df4647e15c50daea9a8a4e7f4f417a266335c |
28-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34707 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 05c180b34763c2891a2bf467c48bcf2a96f7e660 |
27-Feb-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Fix parenthesis for BCTRL_{ELF|Macho} test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34668 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| 63f8fb1993bf2b4286c5a6763e2eee414a751699 |
27-Feb-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Differentiate between the MachO and the ELF ABI the CALL instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34667 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
|
| d313a9b1484c52e3f784de5064ce86bdbd9b26dc |
27-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Duplicate use of LR, take 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34666 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 3d3d6275134f3c6d35a97a028a8556fd2e62243a |
27-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrapping
to infinite loop:
PPCMachineFunctionInfo.h updated: 1.2 -> 1.3
PPCRegisterInfo.cpp updated: 1.110 -> 1.111
PPCRegisterInfo.h updated: 1.28 -> 1.29
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34652 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| caddd44be776e0dc97baf40ca8afdd405cb705a1 |
26-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
always lower to RETFLAG, never leave it as just ret.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34639 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| 4ddf7a4ca69c3f5872b568bcb523d491b29a2592 |
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
no really, this is the right patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34605 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 640c0ac01d17ce907a601b9fea4c29c87c37edee |
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
always promote float varargs to double.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34604 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1fa3d9ef93578970b2e0506104b96c3ffaa42bcf |
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
one important bugfix: PPC32 didn't have both elf and macho support for
external symbols and global addresses. Add the missing ones.
one important workaround: PPCISD::CALL is matched by both PPCcall_ELF
and PPCcall_Macho, disable the _ELF patterns for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34601 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 9f0bc659c8d2f1e401a9690e4900b0fd2a70bdfe |
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
implement support for the linux/ppc function call ABI. Patch by
Nicolas Geoffray!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34574 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCFrameInfo.h
PCHazardRecognizers.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.cpp
|
| eb95d41cd364f3526d1c39455a0131185495c51a |
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Add XLForm_1_ext template, patch by Nicolas Geoffray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34573 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 456bc87e78af18331b9579069a059c723da517d9 |
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Improve JIT support for linux/ppc: Patch by Nicolas Geoffray!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34572 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
PCSubtarget.h
PCTargetMachine.cpp
|
| 2a27a7598b90359696e31cb665914206f369d1f0 |
23-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Don't spill LR as a callee saved register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34533 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 0fa1b6d1b1ce5437c30585baddcba20e691d31e0 |
23-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
By default, spills kills the register being stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34515 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| c740d062903c568a32b6e614a4bcd949413b05ed |
23-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
remove obsolete file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34506 91177308-0d34-0410-b5e6-96231b3b80d8
ICENSE.TXT
|
| 2ad9f17fee5d6395cd8db81668853e6dbf94060b |
22-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Simplify lowering and selection of exception ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34488 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 62819f31440fe1b1415473a89b8683b5b690d5fa |
21-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Support to provide exception and selector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| bda9b0ec7bd6974cebf751ecd23c5434b34054e9 |
21-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Add support for changes in DwarfWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34478 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| a15be8ce3aaaebc675f99302e2c5e1c564268322 |
21-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Add TAI field for exception table section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34477 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| b371f457b0ea4a652a9f526ba4375c80ae542252 |
19-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34428 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| a284cbf667e11660840dc7bae3ee9eeaa3c7cbd2 |
19-Feb-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1207:
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34399 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| eceada67286f0d8081c23aedd242f4deeffa85ad |
17-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added getReservedRegs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34376 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| dee5a5a52c45d04aa9f64a7b6e2adae37878a304 |
17-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Fix ixaddrs as well, allowing ppc64 to compile to:
_test2:
li r2, 0
lis r3, 1
std r2, 9024(r3)
blr
instead of:
_test2:
lis r2, 1
li r3, 0
ori r2, r2, 9024
std r3, 0(r2)
blr
This implements CodeGen/PowerPC/LargeAbsoluteAddr.ll:test2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34373 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bc681d6af490a7e67bcc8c4a4b17d18cb38ca455 |
17-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to:
_test:
lis r2, 743
li r3, 0
stw r3, 32751(r2)
blr
instead of:
_test:
li r2, 0
stw r2, 32751(48693248)
blr
Implement support for ppc64 as well, allowing it to produce better code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34371 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3dd074afcb820bbb677967bdd116aee219e07920 |
16-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
fix incorrect encoding of vminsw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34351 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| d2b7cec527a0efa552628378ebca7a8ca63bb45d |
14-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Generalize TargetData strings, to support more interesting forms of data.
Patch by Scott Michel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34266 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 8abcfe11b5e3c7a6ec6b13b17f7542317368e38f |
09-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34101 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 8c541bcc56fd7327f3d8d74653ae6df25921250e |
09-Feb-2007 |
Nate Begeman <natebegeman@mac.com> |
Remove fixed item
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34081 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 2f5bcb5f38e051ffa41b6257d9c0a0e94067dee4 |
08-Feb-2007 |
Bill Wendling <isanbard@gmail.com> |
Fixed comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34040 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriterInfo.cpp
|
| eb1ac3385096dd6f45a1548f3492f21648f55b4c |
08-Feb-2007 |
Bill Wendling <isanbard@gmail.com> |
Moved the MachOWriter and ELFWriter out of the Target/* files. Placed the
definition of it into the CodeGen library. This is so that a backend doesn't
necessarily add in these writers if it doesn't use them (like in the lli
program).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34034 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCMachOWriterInfo.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| 449c57a0f9b550e4a43d7c1c1ef37ebff20650b4 |
08-Feb-2007 |
Bill Wendling <isanbard@gmail.com> |
Dead files. Functionality has been taken over by the Add*Writer functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34029 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
|
| 736610c8741687cb666b5964f45b3ed92d9ef081 |
03-Feb-2007 |
Bill Wendling <isanbard@gmail.com> |
Moved the GetTargetRelocation method from PPCMachOWriter to here. It uses
non-Mach-O-specific information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33819 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriterInfo.cpp
PCMachOWriterInfo.h
|
| e318391d4d3673fbe41e5ef00ce489d85167260b |
03-Feb-2007 |
Bill Wendling <isanbard@gmail.com> |
Moved the GetTargetRelocation method to the PPCMachOWriterInfo object. The
PPCMachOWriter is now trivial.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33818 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
|
| b82313fdc21e8190768addf0f16710b94f0e1441 |
01-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Support for non-landing pad exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33755 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCTargetAsmInfo.cpp
|
| 9aa2895360bd3951fc4f204d8699b84fd9ea6ba5 |
01-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33732 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.cpp
|
| 95b9d6e5d8f35ccefccea0680ed733e752ff7d65 |
31-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
A relatively simple PPC optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33709 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 5cbf985dcbc89fba3208e7baf8b6f488b06d3ec9 |
30-Jan-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid
confusion with external linkage types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33663 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCSubtarget.cpp
|
| b267ca17d1351b28d597e7807b5ed398e92d65e4 |
30-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Darwin -static should codegen static ctors / dtors to .constructor / .destructor sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33657 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
|
| e078d1a14a2633d5fe5b5b9d9dec90669f5c7082 |
30-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Only gather frame info if debug or eh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33639 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| bcc5f36765e8111c13873a0c0dc874c92385d808 |
29-Jan-2007 |
Nate Begeman <natebegeman@mac.com> |
Finish off bug 680, allowing targets to custom lower frame and return
address nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33636 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1f259e9d7aa346861785c4a2a7e3220fec113706 |
29-Jan-2007 |
Nate Begeman <natebegeman@mac.com> |
We'd still like to register allocate r2 on darwin before the callee-save
regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33635 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 908049b7b6d089dde6f75f6ac47034150c948e7e |
29-Jan-2007 |
Nate Begeman <natebegeman@mac.com> |
Update some of the llvm in the readme
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33630 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 072200c36dd96b94e772029fd72edf9fa120c467 |
29-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Landing pad-less eh for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33622 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCTargetAsmInfo.cpp
|
| b10308e440c80dd6ffb4b478f741ff7e5f30cb48 |
28-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33597 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3c983c3dc19bb83807f978c04737b4572be90a93 |
26-Jan-2007 |
Nate Begeman <natebegeman@mac.com> |
Fix a spelling error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33556 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
|
| 6635f35cae9d5a5d363d3ba425d4b1f323fc689d |
26-Jan-2007 |
Nate Begeman <natebegeman@mac.com> |
Handle multiple functions, properly mangle symbols, and fix support for
scattered relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33555 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
|
| 44c3b9fdd416c79f4b67cde1aecfced5921efd81 |
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Change the MachineDebugInfo to MachineModuleInfo to better reflect usage
for debugging and exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33550 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.cpp
|
| 1ee29257428960fede862fcfdbe80d5d007927e9 |
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Make LABEL a builtin opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCISelLowering.cpp
PCInstrInfo.h
PCInstrInfo.td
PCRegisterInfo.cpp
|
| fab0439c62984b3dc851eb99c31c4f6edda092a1 |
25-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33508 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 99403b6964aead64c1039a8f4007437ef96dfd88 |
25-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Tell PEI that PPC will handle stack frame rounding itself.
- Do not round up to max. alignment of stack object if it is > stack alignment.
It will have to be handled with dynamic aligning code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33505 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 78192b620450ce7897b68c48cd5d3f1a6defbb7b |
25-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
Fix test/CFrontend/2007-01-24-InlineAsmCModifier.c on PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33494 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 5e73d5bd2e98afda12fa69a7ea83050c69be0d34 |
24-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
by value so that clean up is less confusing (these vectors tend to be small.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33488 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 2b7218218faa02d9ece90f2ae6e009d7c55534df |
24-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Make ivars private and use getters. Have the MachOWriter return "Mach-O
Writer" for the pass name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33483 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriterInfo.h
|
| 0ea18ff8e78fd10ba210c70ca928b47c7de0e6b0 |
24-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Add a field for and construction of the PPCMachOWriterInfo object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33480 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 3d6d609aaed02b6d9a8e2ede029710c82c728fe2 |
24-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Move the getJTRelocation method out of here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33479 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
|
| 841056a2ad6fce7786378a27aced46e37122259f |
24-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
New "TargetMachOWriterInfo" class. It holds target-specific information
that the MachOWriter needs in order to do its writing stuff 'n things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33475 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriterInfo.cpp
PCMachOWriterInfo.h
|
| dc77540d9506dc151d79b94bae88bd841880ef37 |
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
hasFP() is now a virtual method of MRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 74fc22d484f053908c12861bae82a6460b00326c |
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Double and long preferred alignment set to 8 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33447 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| bd92d81d22c90433e968077aa0a4157d631d6365 |
19-Jan-2007 |
Nick Lewycky <nicholas@mxc.ca> |
Needed to build on PPC Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33352 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| afd7a08a76a13bfc379702e6c07fc76c1fdbf7c5 |
18-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
move contents of PR587 to here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33333 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| c904a5b925ce9981ad7501b14ee39cbc8795e23c |
18-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Have the OutputBuffer take the is64Bit and isLittleEndian booleans.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33316 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
|
| b266ccd0f41b3ac9d9ad733e73204d9177c12e9f |
18-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
Modify emission of jump tables on darwin to emit an extra "l" label that
delimits the boundaries of jump tables. This lets the linker's dead code
stripping optimization do a better job.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33315 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 203d3e4386ff2b8e66378bf7cfb12ec25869b866 |
17-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Changed to use the OutputBuffer instead of the methods in MachO and ELF
writers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33311 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
|
| e911615c4769d793588087b5321d303ecb9661c7 |
17-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Revert patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33298 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
PCTargetMachine.cpp
PCTargetMachine.h
PCTargetObjInfo.cpp
PCTargetObjInfo.h
|
| 22fb30231b87e7b090ab1b135cb478c0c3feefe4 |
17-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Create the specified TargetObjInfo and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33291 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| 34f03fff2d117068b4d627922484d2d79ed9c025 |
17-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
New "TargetObjInfo" class. This holds information that the object writers will
use to write things to the file. It's abstract so each target should implement
its own version for each writer type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33286 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetObjInfo.cpp
PCTargetObjInfo.h
|
| cb9009993b20ab41fab56518d666ba69533db4b3 |
16-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Instead of yet another enum indicating the "assembly language flavor",
just use the one that's in the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33255 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
PCTargetAsmInfo.cpp
|
| eb9a42c90bf7e21ad8544315a65f86b668cc0277 |
16-Jan-2007 |
Bill Wendling <isanbard@gmail.com> |
Fix for PR1095:
LLVM would miscompile ASM dialects when compiling for PPC. Added dialects for
the X86 and PPC backends. It defaults to "0", the first variant of a compound
inline asm expression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33246 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 70d4107a45ab39e1bc3e7a67a86b59655cba34ec |
14-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
add support for hidden visibility to darwin/ppc and linux/ppc targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33200 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
|
| 15c91887e47f7301255d838c4706509fe8677faa |
06-Jan-2007 |
Chris Lattner <sabre@nondot.org> |
Disable the macho writer until it is 100% functional. Enabling it when
broken invites bug reports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32961 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| d08d23315d20c568fe35b8732d4a49d298b228c2 |
06-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
setSetCCIsExpensive is gone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32941 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c2b861da18c54a4252fecba866341e1513fa18cc |
02-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix naming inconsistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32823 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| bf1118285c0f784b120a69b4a4207e15ef065ead |
21-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Changes from Nick Lewycky with a simplified PPCTargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32735 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.td
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
PCTargetMachine.cpp
|
| 2aa14aad985aac64076437cdf91ec5b54f07f011 |
20-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Oops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32724 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 40ee69f3ca4433dc14072b2b29f7b47fc75a5dca |
20-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Original patch was overly complicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32723 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| b608a4dd4c9f8693054362ab8156b6039ee07a88 |
20-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Changes to target powerpc for non-Darwin assemblers.
1. Patches from Nick Lewycky.
2. Code to filter register names and print them as numeric values on
non-Darwin systems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32721 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 95b2c7da5e83670881270c1cd231a240be0556d9 |
19-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
eliminate static ctors for Statistic objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32703 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCISelDAGToDAG.cpp
|
| 15404d060ba8b604c03b9223a0f2e2abcd0fdded |
18-Dec-2006 |
Rafael Espindola <rafael.espindola@gmail.com> |
move ExtWeakSymbols to AsmPrinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32648 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 3381f0a09da038e857b2df7b7a4aba1df34a2a4e |
16-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Apply B. Scott Michel's patch for PR1054, thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32630 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
|
| ba74cdf7f6044de319e118c28c84e076b421376f |
15-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Patterns no longer needed due to fix in the DAG combiner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32612 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 352235515ff58d8a250797c62aebb4767b3b229f |
15-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Not all test cases are created equal. This fix is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32605 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 182a5acdeb58db5467c08c34f1db42af47b0c44c |
15-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Not needed. Misinterpreted error message from other bug (Missing load/store
relocations.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32604 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 34da72645a82e11bc7008bc567d63426ec4c5949 |
15-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Missing load/store relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32601 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| c4a81dc9357987bd0f4a4dc1593e8f38d6567fbd |
15-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Provide 64-bit support for i64 sextload<i8>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32600 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| ca367b4e259efdd9366d358addbb983cce7c4360 |
15-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Provide support for FP_TO_UINT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32599 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c35010d3a44397dd04ed3bff5287f9c718dacd4a |
12-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Honor cpu directive, take two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32492 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCAsmPrinter.cpp
PCSubtarget.h
|
| 9a7dfa3fd465aa7cf275003dbb11234e34bb2d8c |
12-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Rollback changes to take a different tack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32488 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 55a7ec33d7cafa703a1b6e6410d7c26d5b7ded0b |
12-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Honor the command line specification for machine type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32483 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 78f97f3118c0d7fbebf4084e24689c596d5e4fb7 |
12-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Reduce number of instructions to load 64-bit constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32481 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstr64Bit.td
|
| 57fc62c8d2bf056b0d2a0e3d1b82b3b787b899f8 |
12-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Another step forward in PPC64 JIT support: we now no-longer need stubs
emitted for external globals in PPC64-JIT-PIC mode (which is good because
we didn't handle them before!).
This also fixes a bug handling the picbase delta, which we would get wrong
in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32451 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCISelLowering.cpp
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
|
| 442b9a69811b68bc169b3eb9305fca7adfb325eb |
11-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
getInstrItineraryData shouldn't copy the itineraries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32448 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 2060a822fee8a500017e3afc1d91cf3644553d44 |
11-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Missing opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32439 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 18e2f4433e3bc8b95e1bd0c9e5de7b384eb7db3b |
11-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Layout proper frame for ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32436 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| bfaaaa6e0f105cc57933afa9a380763fe87a5ff3 |
11-Dec-2006 |
Nate Begeman <natebegeman@mac.com> |
Properly mangles symbol table names
Supports constant pools
Supports relocations to jump tables
Supports relocations within the data segment (global = address of global)
Allocates memory in a non-hacky for all non-code objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32430 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
|
| d27a258d2d7691db3731135a448b7654d260cc07 |
11-Dec-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32415 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0eadd73bd78b00379e9f78d1a372bcd28efe855c |
10-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Reverting until finding the cause of secondary bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32413 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 630def54f4de86f3909bfd10ff9bd94c87525ea7 |
10-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
__PPC64CompilationCallback code was allowing registers to be clobbered by stub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32412 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| e150b8eb873fc1bdde17d8ecfd3c38168a5cdcee |
08-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
this is an initial patch to switch the ppc64 jit over to working in PIC mode,
which allows the code to be above the 2G marker. We still need to JIT emit
dyld stubs to support external, weak, common, etc globals, but that will
happen tomorrow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32348 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCJITInfo.cpp
PCTargetMachine.cpp
|
| eb63b0a9d5089dd3119ba9c3cad9cf9ad79df0f7 |
08-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
fix incorrect encoding of rldicr, used by ppc64 function stubs, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32341 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 |
07-Dec-2006 |
Bill Wendling <isanbard@gmail.com> |
What should be the last unnecessary <iostream>s in the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCHazardRecognizers.cpp
PCISelDAGToDAG.cpp
PCInstrInfo.cpp
PCJITInfo.cpp
PCRegisterInfo.cpp
PCSubtarget.cpp
|
| c88fa749eb85371f54917446b69eb89527fd12b7 |
07-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
fix CodeGen/PowerPC/2006-12-07-LargeAlloca.ll on ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32331 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 85c671b90870705ba7e10baf99aa306c843f1325 |
07-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Fix i64 uint_to_fp on ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32297 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 94c96cc5197f527a8cb9f953be3a2e8f2f5aa9e3 |
06-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
implement sextinreg i8->i64 and i16->i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32293 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| c5d24596d6a87632cbc08219bc8cd48285030854 |
06-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
fix another sradi encoding bug. This fixes Olden/health with the ppc64 jit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32291 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| c5e241b40aa9ea1426a8f7df637cea7b20603030 |
06-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
fix the jit encoding of sradi, simplify the MDForm1 description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32285 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| fae2c19de91ae9a31046aaed27d1e5afa8d3e158 |
06-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
add relocation support for ppc64 branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32284 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| ac0b6ae358944ae8b2b5a11dc08f52c3ed89f2da |
06-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Detemplatize the Statistic class. The only type it is instantiated with
is 'unsigned'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32279 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCISelDAGToDAG.cpp
|
| 51fe9d9aa432cbde6497cad4ea5c8f0276c67b82 |
06-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Make it easier for gdb to find the return address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32277 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| efc7e52183a384917ff4deac06e829433602150a |
04-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Restoration of the stack pointer after a deallocation of a alloca was not
updating the SP link.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32202 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8752ce61e1ba3973e0082085c1c3c9b8069ea2b7 |
01-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add weak reference directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32091 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
|
| 9382e29c1ebc6524618b173ed04bc25295d02c6e |
01-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Copy and paste error. An initialized global cannot be a weak reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32075 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| fbb74e6941ebf6c108a4e385902e5e2cd35b739d |
01-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
1. In ppc64 mode we need only use one GPR.
2. Float values need to be promoted to double when they are vararg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32074 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 45e507ca9bb09f02e24496cc0885b4ea7debdba9 |
01-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
ExternalWeak case in wrong location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32073 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 81cf60fceb411b5cc8a161d4332c5c9d0784f326 |
01-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
A initialized global variable cannot be extern weak. However, if a global value's initializer is itself a external weak symbol, emit the weak reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32069 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 1c45a6687399d57d8da234d61f936ee37a108a45 |
01-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Darwin PPC external weak linkage support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32068 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 70fa493613142f2ad99003de91b46e701f9bd605 |
01-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the CodeGen/PowerPC/vec_constants.ll regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32057 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 12a447898a3c68c1a9489f71b82650b46244d00a |
30-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
MachineInstr::setOpcode -> MachineInstr::setInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32034 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 15eb329dae1dea7a5a38cf0c1074aaa3e0f78ab6 |
29-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Fix bug codegen'ing FP constant vectors with integer splats. Make sure the
created intrinsics have the right integer types. This fixes
PowerPC/2006-11-29-AltivecFPSplat.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32024 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 619965d32e2cb961cc315aaece2e32f53f236784 |
29-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Offset for load of 32-bit arg in 64-bit world was incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32019 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 7fc4a94bdd5fb2933fecf27ca0cf377e1dc70cb0 |
28-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Remove debug code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31970 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2ada08536e30dbcbea21addc814f3bf8a394a4ee |
28-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Prime text sections to improve branch locality in large object files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31969 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| e9bd7b2e03252391dce5cacd4fcf68df4d4eef7a |
28-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
32-bit int space was not accounted for properly in lowerCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31966 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c0f64ffab93d11fb27a3b8a0707b77400918a20e |
28-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 24652d16f84e4fd605aaffdd5112a606be6c8074 |
25-Nov-2006 |
Reid Spencer <rspencer@reidspencer.com> |
Add newline at end of file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31902 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachineFunctionInfo.h
|
| e9c9f98f719cc597444181cd6634fac247f8f68c |
20-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
in ppc64-mode, don't allocate the 32-bit version of r13 either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31884 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| bdc571b7d578091059aa7bc5c3a190ceb70f9542 |
20-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
r13 is the thread pointer on darwin/ppc64, don't allocate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31882 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| b1eb987ccd86e58d81dde75424d37369785910d7 |
18-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
on ppc64, float arguments take 8-byte stack slots not 4-byte stack slots.
Also, valist should create a pointer RC reg class value, not a GPRC value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31840 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ff790894bdffb263c9448ed9402b92927c0b59dd |
18-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
make sure to safe LR8 in the right stack slot for PPC64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31839 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
PCTargetMachine.cpp
|
| 566c1b1a0442ccbf9f52b176dbca9764d94e5f93 |
18-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Pretty print 'rldicr r2, r2, 2, 61' as 'sldi r2, r2, 2'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31838 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 54e853b8a6435591f5733f3d0d3f196ae755079b |
18-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Rewrite the branch selector to be correct in the face of large functions.
The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model. This fixes assembler errors when compiling 403.gcc with
tail merging enabled.
Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion. Only if branches need expansion are instructions rewritten
and created. This should make branch select faster, and eliminates the
Bxx instructions from the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31837 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCInstrFormats.td
PCInstrInfo.td
EADME.txt
|
| d5275157b540f53fe3795489229c021390e90b3f |
18-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add encoding for BCC, after finally wrestling strange ppc/tblgen endianness
issues to the ground.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31836 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 18258c640466274c26e89016e361ec411ff78520 |
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
convert PPC::BCC to use the 'pred' operand instead of separate predicate
value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31835 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
PCInstrInfo.td
|
| 289c2d5f4566d8d7722e3934f4763d3df92886f3 |
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
rename PPC::COND_BRANCH to PPC::BCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31834 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
PCInstrInfo.td
|
| df4ed6350b2a51f71c0980e86c9078f4046ea706 |
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
start using PPC predicates more consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31833 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.cpp
PCInstrInfo.h
PCInstrInfo.td
PCPredicates.cpp
PCPredicates.h
|
| d6fa8c166ace05779ebefe511c615223b12fe7db |
17-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Assert unhandled case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31828 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 2ff5cdb16cea04f562402c2a33732840857a66e2 |
17-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
1. Ignore the -disable-fp-elim when the routine is a leaf.
2. Offsets on 64-bit stores are still in bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31824 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| c1c2f4b52bbb71c8ff3afc924ac49a7cae0f87f0 |
17-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Typo. Fix the nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31823 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 280b714cd064224c6cfe1724f22cca4d6b8eed37 |
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
implement a todo: change a map into a vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31805 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 8781466176e261f25268becc61f82e2f969f0cdb |
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31799 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| e28a12a3b8d42543bb291d5aacf0b65a95dd3653 |
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
implicit_def_vrrc doesn't generate code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31797 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 2f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173 |
16-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
This is a general clean up of the PowerPC ABI. Address several problems and
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31792 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
PCISelLowering.cpp
PCISelLowering.h
PCInstr64Bit.td
PCInstrInfo.td
PCMachineFunctionInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
PCRegisterInfo.td
|
| 1b0a2d8370b28de0d3998b0303bc3dad983989d9 |
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
fix a regression that I introduced. stdu should scale the offset by 4
before printing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31791 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstr64Bit.td
|
| cb53595d70c33c2f11b9dd95653649372a5fe489 |
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add a statistic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31785 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 0403862158a5a908b868b0b64b7725b39919a506 |
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
fix broken encoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31778 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 80df01d2cf68b680b1c90eb0d3b0f2defcdf202b |
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add ppc64 r+i stores with update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31776 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCInstr64Bit.td
|
| 74531e49ef97cc2bef8fc9c35963368fc63153cf |
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add patterns for ppc32 preinc stores. ppc64 next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31775 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| ef20fefa65f5ac422e65e644c6380ea480b7f507 |
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
switch these back to the 'bad old way'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31774 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 5e797a5b1c05147bd68c989e8c9b9de37ee06243 |
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Fix ppc64 epilog bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31771 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 8e28b5c4265ea636e5b737d9352096498be28d3b |
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Stop using isTwoAddress, switching to operand constraints instead.
Tell the codegen emitter that specific operands are not to be encoded, fixing
JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate
even when general preinc loads are not enabled).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31770 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.td
|
| 6ce7dc2a97260eea5fba414332796464912b9359 |
15-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Properly transfer kill / dead info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31765 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 0851b4f3eda110cc21c8d4b59f0d55bc84d9d088 |
15-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri
addrmodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31757 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 5e14b821cdab1fa42baeb2ed1f663597d8345824 |
15-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the PPC regressions last night
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31752 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCRegisterInfo.cpp
|
| f8e07f448a241789ff987179d67fd7c87d844ee8 |
15-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Switch loads over to use memri as the operand instead of a reg/imm operand
pair for cleanliness. Add instructions for PPC32 preinc-stores with commented
out patterns. More improvement is needed to enable the patterns, but we're
getting close.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31749 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCInstrInfo.td
|
| 26e552b04c79e5a5cbe139441d9c37770fa507ca |
14-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
group load and store instructions together. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31736 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6a5339ba656805a9cd3bf7d884f99bb87ec84e98 |
14-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls
clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31734 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCInstr64Bit.td
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| d10434215da983b58389d2a0880dfcd2cd3b7f35 |
14-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
remove a ton of custom selection logic no longer needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31733 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| ac011bce9e8a69f99f92d46133adbf883a91cb6f |
14-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of
'(shr (ctlz (sub Y, Z)), 5)'.
The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner. For example, this:
typedef struct {
unsigned prefix : 4;
unsigned code : 4;
unsigned unsigned_p : 4;
} tree_common;
int foo(tree_common *a, tree_common *b) {
return a->code == b->code;
}
Now compiles to:
_foo:
lwz r2, 0(r4)
lwz r3, 0(r3)
xor r2, r3, r2
rlwinm r2, r2, 28, 28, 31
cntlzw r2, r2
srwi r3, r2, 5
blr
instead of:
_foo:
lbz r2, 3(r4)
lbz r3, 3(r3)
srwi r2, r2, 4
srwi r3, r3, 4
subf r2, r2, r3
cntlzw r2, r2
srwi r3, r2, 5
blr
saving a cycle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31725 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2fe4bf453b433cfe7113e282a59bf0f1e7fb0195 |
14-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
minor tweaks, reject vector preinc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31717 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 7ce45783531cfa81bfd7be561ea7e4738e8c6ca8 |
14-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Matches MachineInstr changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| c9dcf289557017742fb507f985b3bf9f44982031 |
13-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
teach the g5 hazard recognizer about update loads. This fixes
Ptrdist/anagram among others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31708 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| dfc55885e257f0c73eccadf257814dc2221f10fe |
11-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Make sure stack link is set in 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31690 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| a94a203f346e65d40c4c3fe478c5d8d7a2ff5df6 |
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
implement proper PPC64 prolog/epilog codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31684 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCRegisterInfo.cpp
|
| 4bfd1e9b43f589c7a2e2d45baa226496bb46d865 |
11-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
Running with frame pointers prevented debugging, external probes and
potentially some system calls/exception handling from working. TOS must always
link to previous frame. This is a short term workaround until alloca scheme is
reworked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31677 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 5b3bbc7cd7bff4275b94003d4bf1fa296c6a10d0 |
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
allow the offset of a preinc'd load to be the low-part of a global. This
produces this clever code:
_millisecs:
lis r2, ha16(_Time.1182)
lwzu r3, lo16(_Time.1182)(r2)
lwz r2, 4(r2)
addic r4, r2, 1
addze r3, r3
blr
instead of this:
_millisecs:
lis r2, ha16(_Time.1182)
la r3, lo16(_Time.1182)(r2)
lwz r2, lo16(_Time.1182)(r2)
lwz r3, 4(r3)
addic r4, r3, 1
addze r3, r2
blr
for:
long %millisecs() {
%tmp = load long* %Time.1182 ; <long> [#uses=1]
%tmp1 = add long %tmp, 1 ; <long> [#uses=1]
ret long %tmp1
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31673 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| d181c0120c6c82a6b5370e4d3040b803093e169b |
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Mark operands as symbol lo instead of imm32 so that they print lo(x) around
globals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31672 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| f6edf4dcf0907427f5e07012b0fe51e43fb09c45 |
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
ppc64 doesn't have lwau, don't attempt to form it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31656 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 94e509caeab08edb27849ea9be5dc80e74d95f38 |
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
implement preinc support for r+i loads on ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31654 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrFormats.td
|
| 6a944e2592461acfa17e5b25458e2f5e863159e4 |
10-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
dform 8/9 are identical to dform 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31637 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 4eab71497d10622bd209c53f8e56152877ac5638 |
10-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add an initial cut at preinc loads for ppc32. This is broken for ppc64
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)
This is disabled unless -enable-ppc-preinc is passed to llc for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31621 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.td
|
| 26ddb506ec08789d33298efb3a5c142dea22e320 |
10-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add note about ugly codegen with preinc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31617 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| cd633192272c9c433af6f40621b2bf5a38a68f30 |
09-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
PPC supports i32 / i64 pre-inc load / store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31599 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 144d8f09e139f691cafadbc17873943ba4c465f3 |
09-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31595 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 0d53826f3653a789cf1491c3c40a1f4a993992b6 |
08-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tblegen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31571 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| fc5b1ab94959879a91c34aee8859e652a50270d0 |
08-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Refactor all the addressing mode selection stuff into the isel lowering
class, where it can be used for preinc formation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31536 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| 302bf9c973d8793cc13a066765e97644a530a234 |
08-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
correct the (currently unused) pattern for lwzu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31535 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6e11295b2354fb8828b15964038a1d60fb3df88a |
07-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add a note from viterbi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31506 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 0921365b886186be7636b55c357ee82f9064b89d |
07-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
fix encoding of BLR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31485 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 6fc40079f374cfeeb63808fd96ea670ae036f809 |
04-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
encode BLR predicate info for the JIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31450 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCInstrFormats.td
PCInstrInfo.td
|
| af53a87052f41664ff5962731d0b64e3b51a5501 |
04-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Go through all kinds of trouble to mark 'blr' as having a predicate operand
that takes a register and condition code. Print these pieces of BLR the
right way, even though it is currently set to 'always'.
Next up: get the JIT encoding right, then enhance branch folding to produce
predicated blr for simple examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31449 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCInstrInfo.td
|
| 0638b260dcf691752cbff29d5183e89bf01132d1 |
04-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Describe PPC predicates, which are a pair of CR# and condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31438 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 7049540de55741611545829ad47572432a187771 |
04-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
remove dead vars
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31433 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 4d5c0014b6e1e820e50e306b9306ceb0a133ee0c |
03-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
fix a bug reid noticed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31385 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
|
| 3ed469ccd7b028a030b550d84b7336d146f5d8fa |
02-Nov-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR786:
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCMachOWriter.cpp
PCRegisterInfo.cpp
|
| 331d1bc5dfe1be9090e29f9af9579888a63a9a79 |
02-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Implement the getRegForInlineAsmConstraint method for PPC. With recent
sdisel changes, this eliminates a ton of copies around common inline asms.
For example:
int test2(int Y, int X) {
asm("foo %0, %1" : "=r"(X): "r"(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31367 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| dba1aeedd8179114a45be655b985455218d20806 |
31-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Change the prototype for TargetLowering::isOperandValidForConstraint
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31318 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| ab4022f196059745c0ca0780b71a80fa67e896be |
31-Oct-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
1. Clean up code due to changes in SwitchTo*Section(2)
2. Added partial debug support for mingw\cygwin targets (the same as
Linux\ELF). Please note, that currently mingw\cygwin uses 'stabs' format
for storing debug info by default, thus many (runtime) libraries has
this information included. These formats shouldn't be mixed in one binary
('stabs' & 'DWARF'), otherwise binutils tools will be confused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31311 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 1d75400e2ed5704c4c156782a94ee139d638bb1b |
31-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
fix miscompilation of llvm.isunordered, where we branched on the opposite
condition. This fixes miscompilation of Olden/bh and many others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31301 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| c35497fc2a8b984dbacede5b75b7be74c6756948 |
30-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
All targets expand BR_JT for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31294 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ef13982aa7f3e57e82cd48370e79033dff0da295 |
28-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
implement the BlockHasNoFallThrough hook
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31264 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 31b6ddad31689b996c94dcde5f32fb2585df4af6 |
28-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Doh. Must check if GV is constant first before putting it in .cstring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31253 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 985384c41de6c061a76a4723ecc101a505575606 |
28-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
don't dist internal readme's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31246 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 7a498cbc606e8070a3ca1448c6e14a270d4772fe |
28-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
this doesn't occur any more in mason
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31236 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 4ccf63d8cf2a38fe74556b46dc8e013cc9d6a488 |
28-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
the code in question is now:
cmpw cr0, r7, r3
ble cr0, LBB1_5 ;bb25
LBB1_8: ;bb17
cmpw cr0, r8, r5
bgt cr0, LBB1_2 ;bb
which is just as good as crnand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31235 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 80aa9a122fa8fab00b2431314cf57680f6807ad7 |
26-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Place cstrings in .cstring section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31207 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
|
| f9c197e022521a83f8876890b4241fc23e63572c |
24-Oct-2006 |
Devang Patel <dpatel@apple.com> |
Move getPreferredAlignmentLog from AsmPrinter to TargetData
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31171 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| e90c53756efa19d1068f416ad8932eff8241e894 |
24-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Add intrinsics for the rest of the DCB* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31148 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 7c4fe259f8bfeae542cfef25c1f1e9b1ff25a39b |
21-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Implement support for branch reversal, fix a bug in branch analysis.
This provides stuff like:
cmpw cr0, r15, r29
mr r14, r15
- bge cr0, LBB3_111 ;bb656
- b LBB3_90 ;bb501
+ blt cr0, LBB3_90 ;bb501
LBB3_111: ;bb656
lwz r18, 68(r1)
which is particularly good for dispatch group formation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31101 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 879d09cf130f3760a08865913c04d9ff328fad5f |
21-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Simplify code, no functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31097 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 54108068b71a7dbc48f4ebf1b2d7d87ca541070a |
21-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
implement support for inserting a cond branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31096 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 10da9575740d9515c70a171a7c40405302d62f4a |
18-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
set the ppc64 stack pointer right, dynamic alloca now works for ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31028 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 56a752e00ff6fb078fd0466d9be438f7b8a1dd79 |
18-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Expand alloca for ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31027 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ae1dc403274d3a64bcee31f15e2d25e4b7178811 |
18-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
expose DWARF_LABEL opcode# so the branch folder can update debug info properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31024 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.h
|
| 2dc7723474c54efcbcac6265dad0a7271902f1a5 |
17-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
add support for inserting an uncond branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31003 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 5059dda6bd88f60beb925b9c64a458c93af78d0e |
17-Oct-2006 |
Jim Laskey <jlaskey@mac.com> |
Use S_debug for dwarf info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30994 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| c50e2bcdf7bff1f9681ab80e52691f274950fab5 |
13-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
implement branch inspection/modification methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30946 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 8b2794aeff151be8cdbd44786c1d0f94f8f2e427 |
13-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 6a250ecc99c76dcb07e6431c5cb99e495895ad82 |
13-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
add note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30937 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 594f4c69e6b67f9af648adfe3d05c2b72b313795 |
13-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
set isBarrier correctly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30936 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| eea52d3297c4c59e62b10477a3ebd1895430b508 |
13-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Correctly handle instruction separators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30935 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 1e5e97462b09f2dc6b6105d403c090a6dda59232 |
12-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
mark adjcallstack up/down as clobbering and using the SP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30908 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| af9db75943c11eebd642c1645d3c3f4003fe37e3 |
11-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add properties to ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30891 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 466685d41a9ea4905b9486fea38e83802e46f196 |
09-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 786225adf09e606c795ef68a1f789c12f37869f2 |
06-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Make use of getStore().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30759 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a66ba5f70ba15370fd68a84ccaf220d60f7d1b95 |
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Don't bother setting JumpTableTextSection, it is about to disappear
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30745 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 1da31ee472b9615d7329c656e2cc17c419ed7c95 |
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Pass the MachineFunction into EmitJumpTableInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30742 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 9b7ce7da820ada2cdada185de9c9aa94298e485e |
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Move getSectionForFunction to AsmPrinter, change it to return a string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30735 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| b56dcc453e1bd3fc75e4393b3b1bd1b07d86903e |
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
implement DarwinTargetAsmInfo::getSectionForFunction, use it when outputting
function bodies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30733 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| fea13d33e50a9d6777237e76bb59b3be5422bdbc |
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
emit jump table before debug info
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30731 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 37dfa02788711b72618497ce5acf39596e3a0211 |
05-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Always emit the jump table after the function so it's part of the same 'atom'
as the function body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30730 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| c548428c5d7328592f4db6f6cd815af18b3152a3 |
04-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30714 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 7be164c0eaa6c1ab2e69262036e54870176c10a4 |
29-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
wrap long lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30662 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 7c395ad06f0eaaffa638da58899b51daba2041a4 |
28-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Shift amounts are always 32-bits, even in 64-bit mode. This fixes
CodeGen/PowerPC/2006-09-28-shift_64.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30652 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 546896661416be9321f22136c73a1656b3fe407b |
27-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Use abstract private/comment directives, to increase portability to ppc/linux
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30621 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| a53115b4c254885fa19bbedf96d8d491204b86e8 |
26-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Compile:
int x __attribute__((used));
to:
.data
.comm _x,4 ; 'x'
.no_dead_strip _x
on both x86 and ppc darwin targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30605 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| f42f133938545d4f5c249bcfef63db772ce8e942 |
22-Sep-2006 |
Nate Begeman <natebegeman@mac.com> |
Fold AND and ROTL more often
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30577 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
EADME.txt
|
| 4da1c82f724adba2832f79b3b49fc96c1467076d |
20-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
The DarwinAsmPrinter need not check for isDarwin. createPPCAsmPrinterPass
should create the right asmprinter subclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30542 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCTargetMachine.cpp
|
| dadceedbdb9ef642c49283b632dcfefe48ee4cf4 |
20-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Wrap some darwin'isms with isDarwin checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30541 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| f142713a30796e9fc625b795cb5df2fe24b40b51 |
20-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
item done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30518 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| ac924c8248c66ed643a342e8ac902ebe6148c4b8 |
20-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
This is already done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30512 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 711762497c27357adc1edf8d4237c2770fa303bb |
20-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Improve PPC64 equality comparisons like PPC32 comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30510 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 3836dbd3bde1100c1df847a582784cf83d18daf6 |
20-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Two improvements:
1. Codegen this comparison:
if (X == 0x8000)
as:
cmplwi cr0, r3, 32768
bne cr0, LBB1_2 ;cond_next
instead of:
lis r2, 0
ori r2, r2, 32768
cmpw cr0, r3, r2
bne cr0, LBB1_2 ;cond_next
2. Codegen this comparison:
if (X == 0x12345678)
as:
xoris r2, r3, 4660
cmplwi cr0, r2, 22136
bne cr0, LBB1_2 ;cond_next
instead of:
lis r2, 4660
ori r2, r2, 22136
cmpw cr0, r3, r2
bne cr0, LBB1_2 ;cond_next
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30509 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
EADME.txt
|
| cc96ac3a7d1513e48c452f11d39ff00ecc8820fe |
20-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Add a note that we should match rlwnm better
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30508 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 3fe6c1d38901929d65d6d8a61bd9b1594af0ffdd |
20-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| cf9d0acfef1503439c231f2717b3d4b3afce67e1 |
19-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Fold the PPCISD shifts when presented with 0 inputs. This occurs for code
like:
long long test(long long X, int Y) {
return 1ULL << Y;
}
long long test2(long long X, int Y) {
return -1LL << Y;
}
which we used to compile to:
_test:
li r2, 1
subfic r3, r5, 32
li r4, 0
addi r6, r5, -32
srw r3, r2, r3
slw r4, r4, r5
slw r6, r2, r6
or r3, r4, r3
slw r4, r2, r5
or r3, r3, r6
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
Now we produce:
_test:
li r2, 1
addi r3, r5, -32
subfic r4, r5, 32
slw r3, r2, r3
srw r4, r2, r4
or r3, r4, r3
slw r4, r2, r5
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30479 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f0613e1e7cc8aae41350fb0b983ce5b43115b93a |
14-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30377 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| c356a572e34131bf767f35e3fecefae36fab744a |
12-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflects MachineConstantPoolEntry changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 019f851ab26511c089e41b61901f743e75f90714 |
11-Sep-2006 |
Nate Begeman <natebegeman@mac.com> |
Behold, more work on relocations. Things are looking pretty good now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30240 91177308-0d34-0410-b5e6-96231b3b80d8
PCMachOWriter.cpp
PCRelocations.h
|
| 94be248dbb2d2a44e8f4d47f161b93704d33d279 |
09-Sep-2006 |
Nate Begeman <natebegeman@mac.com> |
First pass at supporting relocations. Relocations are written correctly to
the file now, however the relocated address is currently wrong. Fixing
that will require some deep pondering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30207 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
PCMachOWriter.cpp
PCRelocations.h
|
| f45c25f7207e46592c577c549c2e215840c3e647 |
08-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
Missing tab
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30188 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
|
| 6fe6084ebfa583fbbfbb971fca1d90de79ddb33f |
08-Sep-2006 |
Nate Begeman <natebegeman@mac.com> |
We actually do support object file writing, so don't return true (error)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30173 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| fde1b3bb2f15b74c713d98a79fcddaff1ac00dd1 |
08-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
1. Remove condition on delete.
2. Protect and outline createTargetAsmInfo.
3. Misc. kruft.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30169 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| a0f3d17daac73c9c71aad497b298cbe82848f726 |
08-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
Make target asm info a property of the target machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30162 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetMachine.h
|
| 8e8de8f7765a08ab3aa4f48b302cf19ccb9740e2 |
08-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
Break out target asm info into separate files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30161 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetAsmInfo.cpp
PCTargetAsmInfo.h
|
| 563321a2582851c653d0863e8e0bba3d483734f9 |
06-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
Separate target specific asm properties from the asm printers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30126 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCTargetMachine.cpp
|
| 09e460662a8d7328da1b938d5581a6ef3740b51d |
05-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Completely eliminate def&use operands. Now a register operand is EITHER a
def operand or a use operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30109 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 1911fd4f85aebcd4d7b8f27313c5a363eebf49cb |
04-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Completely rearchitect the interface between targets and the pass manager.
This pass:
1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
output, move all this to common code, and give targets hooks they can
implement.
3. Commonalize the target population stuff between file emission and JIT
emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
paves the way for "fast -O0" stuff in the CFE later, and now LLC could
lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
which is now orthogonal to the fact that JIT'ing is being done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30081 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCJITInfo.h
PCMachOWriter.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| c4fa386471cb1ff9d1f2acc24e2d0682e5a17b1b |
03-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Simplify target construction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30070 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| ce50a165c784d71abf1b2f981be18f867787d972 |
29-Aug-2006 |
Jim Laskey <jlaskey@mac.com> |
Handle callee saved registers in dwarf frame info (lead up to exception
handling.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29954 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 06abd22b1ad203103c1a07a030ebc5c1c4cfbb14 |
29-Aug-2006 |
Nate Begeman <natebegeman@mac.com> |
Make ppc64 jit kinda work right. About 2/3 of Olden passes with this,
there are clearly some encoding bugs lurking in there somewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29949 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
PCJITInfo.h
PCTargetMachine.cpp
|
| 3a9ec2463ddeba0820f284e2952bd6919cd5e080 |
28-Aug-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR387:
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29934 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| a4f0b3a084d120cfc5b5bb06f64b222f5cb72740 |
27-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29911 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCMachOWriter.cpp
|
| 0b828e08f94459ac0046b864871d92fed4aaef7c |
27-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Do not use getTargetNode() and SelectNodeTo() which takes more than 3
SDOperand arguments. Use the variants which take an array and number instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29907 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 95514bae7309ffacfc0a79b267159dcfde2b7720 |
26-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
SelectNodeTo now returns a SDNode*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29901 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 9ade218533429146731213eacb7e12060e65ff58 |
26-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Select() no longer require Result operand by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29898 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 6da2f3268d12a9e64f2635dbb94b63e1c4142f59 |
26-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tblgen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29895 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 1822ffbab7b2d9051ff57c0d8d7b9c1c2c086e2b |
26-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29889 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| b9ca92661cf145bfb3bd9705e5629fc5f411a42f |
25-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Encode pc-relative conditional branch offset as pc+(num of bytes / 4). The
asm printer will print it as offset*4. e.g. bne cr0, $+8.
The PPC code emitter was expecting the offset to be number of instructions, not
number of bytes. This fixes a whole bunch of JIT failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29885 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCBranchSelector.cpp
|
| 4c2c9031acd1314440cdd0952182fa39b4efe90d |
25-Aug-2006 |
Jim Laskey <jlaskey@mac.com> |
Fix some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29880 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| eb883af3903286ac20f5bbf549c555c9ef961e14 |
23-Aug-2006 |
Nate Begeman <natebegeman@mac.com> |
Initial checkin of the Mach-O emitter. There's plenty of fixmes, but it
does emit linkable .o files in very simple cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29850 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCCodeEmitter.cpp
PCMachOWriter.cpp
PCTargetMachine.cpp
|
| 5ea64fd9eb0027ad20a66ea29211eef79d8842a0 |
18-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Constify some methods. Patch provided by Anton Vayvod, thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| ccbe2ec890ca41b8fd8c4e8ef0f7bcb42c2f69ec |
16-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Fix PowerPC/2006-08-15-SelectionCrash.ll and simplify selection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29715 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 52a51e38dc312aa262b0d771419afe1785f3cb22 |
12-Aug-2006 |
Nate Begeman <natebegeman@mac.com> |
Emit .set directives for jump table entries when possible, which reduces
the number of relocations in object files, shrinkifying them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29650 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| f6e190fae02174d465ae1f9000192269a5978c73 |
12-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in a recent refactoring that broke a bunch of stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29649 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e219945348207453a2d5e21021ba3211f8f94e25 |
11-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Eliminate use of getNode that takes a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29614 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 79e490aa23d29c20471163b28faf916af610b921 |
11-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Convert vectors to fixed sized arrays and smallvectors. Eliminate use of getNode that takes a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29609 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 325f0a129e57ff5d1842edd0b4b7473a4d6b47f6 |
11-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Fix miscompilation of float vector returns. Compile code to this:
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
blr
instead of:
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
*** vor f1, v2, v2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29607 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 64a752f7c7cf160f2887d0a16d5922359832c9c2 |
11-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tablegen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29604 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| bb7b844bec6c53ac29ac4c50d7b3963e7f193efb |
11-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
CALLSEQ_* produces chain even if that's not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29603 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| bd564bfc63163e31f320c3da9749db70992dc35e |
08-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29566 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2ef88a09b71f458ad415b35a1fb431c3d15d7eb1 |
08-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tablegen isel changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29549 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 0d72a20630ebde26c302518077a28c9faffbd747 |
28-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Fix some ppc64 issues with vector code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29384 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2641cad180e94c0d26630d4ed455352f19be3d3e |
28-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove InFlightSet hack. No longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29373 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| f141cc46faf6f0525f0baa10b6a6c976301874a5 |
27-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Resolve BB references with relocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29351 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCJITInfo.cpp
PCJITInfo.h
PCRelocations.h
|
| 7e6e44139429d1b8003426b29f14126b89591262 |
27-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
synchronizeICache removeed from TargetJITInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29348 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
PCJITInfo.h
|
| 33e9ad96c8506313cc263893e9915d0a3457fc82 |
27-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove NodeDepth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29338 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2f1ae88445c696a9b9d61e14747ba721190cdc99 |
27-Jul-2006 |
Nate Begeman <natebegeman@mac.com> |
Support jump tables when in PIC relocation model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29318 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 35d86fef1f1fc5845366c7c36803a6a3334d8a2e |
26-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29307 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelLowering.cpp
PCTargetMachine.cpp
|
| 55fc28076fa48723bd170e51638b3b5974ca0fa1 |
25-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Refactor the code that resolve basic block references to a TargetJITInfo
method.
- Added synchronizeICache() to TargetJITInfo. It is called after each block
of code is emitted to flush the icache. This ensures correct execution
on targets that have separate dcache and icache.
- Added PPC / Mac OS X specific code to do icache flushing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29276 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCJITInfo.cpp
PCJITInfo.h
|
| 2a785500e03e22dd91824327fbf4b1f6d29dbf53 |
19-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
bswapped load/store instructions are only availble in indexed addressing form.
As such, use xoaddr (indexed only), not xaddr for address selection.
This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29208 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 303c695529f58ec12f7c31a6406c560cd23cc4f2 |
18-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Make the implicit def instructions look like other instrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29174 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrAltivec.td
PCInstrInfo.td
|
| ba4733d901b1c2b994f66707657342b8c81c92bc |
15-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Remove what little AIX support we have. It has never been tested and isn't
complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29156 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
|
| 518f9c7ad0566a69886a4db1b76e995df22bca0f |
14-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Add missing PPC64 extload/truncstores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29140 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCInstr64Bit.td
|
| 1eeedaea59c7d6d9f231989c81013c2c0ea10d2a |
14-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29139 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| a606b70cf5167e37b92a2b41a0fc0e280ac6aaa3 |
13-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Another fix in the rotate encodings, needed when the first two operands are not
the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29136 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 45c04fc676027c2db5e20939c487dea54b3db151 |
13-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Print negative immediates as negative values instead of large constants
when using the immshifted addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29130 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| b2c0650ad363b7e7621cb0e1dffe89316e74166e |
13-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Fix encoding of rotates, such as rldicl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29128 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 3bc8a765a98015e6d55510b6ea6e387cbfd793cd |
12-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Implement PPC64 relocations types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29125 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCJITInfo.cpp
PCRelocations.h
|
| 3d6721a4a1cf9e9a27d05b268f86b7a9ce663d6f |
12-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
An overaggressive #ifdef allows a function to fall off the bottom of the
function instead of returning a value. This sometimes allowed the ppc32 jit
to be used in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29123 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| be6a039ad4c6314176b0834c341a25504fded32e |
11-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
The PPC64 JIT needs register numbers to encode instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29114 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| e37fe9b3a1cadceb42ac27fa0718f5a10ea2f0e6 |
11-Jul-2006 |
Jim Laskey <jlaskey@mac.com> |
Ensure that dump calls that are associated with asserts are removed from
non-debug build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29105 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 804e06704261f233111913a047ef7f7dec1b8725 |
11-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29096 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| d9989384592a3bd9dd374470a723ca8303071a2d |
10-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps
into i16/i32 load/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29089 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
EADME.txt
|
| 90ac1c07759460e4b07f9ffe0e44fec219eddfdf |
06-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Undisable ppc64 jit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29011 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 9525528a7dc5462b6374d38c81ba5c07b11741fe |
29-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Use hidden visibility to make symbols in an anonymous namespace get
dropped. This shrinks libllvmgcc.dylib another 67K
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28975 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCodeEmitter.cpp
|
| 2a41a98fb70923e2d6780220eb225ac0e8b4ff36 |
29-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
shrink libllvmgcc.dylib another 25K
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28971 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
|
| cccef1c6fffa292c227a289d447f6b848ab56c62 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28944 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstr64Bit.td
|
| 6b76b96c69334f3b6a2a895ff810ed047b4b75e5 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix ppc64 jump tables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28941 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 9f029a61e91b83c89b221bfce75d16a5442340c7 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Print stubs for external globals right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28936 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| f89437d049b4a3dff2b04e2635b45068db0a6b34 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Implement 64-bit select, bswap, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28935 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e4172be9209a81a41cbea97b9307e368e7e3ea4c |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add a pattern for i64 sra. Print 8-byte units with a space between the .quad
and the data
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28934 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstr64Bit.td
PCInstrFormats.td
|
| 7ffa9abdadd7e51726240b6a8352abda8edde869 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix rewriting frame offsets with ixaddr instructions, which implicitly shift
the offset two bits to the left.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28933 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 5f9faeaa78a79e03df6bb32e9b3c779e554fe8a2 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
PPC doesn't have bit converts to/from i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28932 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2e6b77d8035459c17d7f0b7055e579a0d9090bdd |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add 64-bit MTCTR so that indirect calls work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28931 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 1fd81107f3b0d8c5cea1c4f66f7bddbc61e76a19 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix an incorrect store pattern. This fixes em3d.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28930 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 563ecfbf8207ce941ddc0ee60c65378c6b9c572f |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Implement 64-bit undef, sub, shl/shr, srem/urem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28929 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 7b0c58cd257d2197bc178818bc081c72aae57e46 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Use i32 for shift amounts instead of i64. This gets bisort working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28927 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 00659b17817b3b5af4d9e9b93fed2a91fe27b019 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add zextload from i32 -> i64, with this, perimeter works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28926 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 7e097e463314baa3c964a977408aa51ecabe7796 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Print darwin stub stuff correctly in 64-bit mode. With this, treeadd works in
ppc64 mode!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28923 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 529c233498c59a544b26b277f8fe30e6a80cc6f8 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix variable shadowing issue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28922 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| c08f902bb7bfcc8a97a4c7c9eb9187882dc2d6d7 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but
doesn't work right).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28921 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.td
|
| 041e9d345f57249e5d9fad21514778c0ba5633b6 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Rearrange compares, add ADDI8, add sext from 32-to-64 bit register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28920 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| c91a4757b60094ade6fc82afde7f94bbe1988a7d |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Improve PPC64 calling convention support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28919 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 924c576e9f7a94153e710e562016fec68fa6d33b |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Remove two more definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28918 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 7b4e478768326b4f67379c1f8a83e4837ad46450 |
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
remove two unused instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28917 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 89d67faf30ed1a8b5364f53c9a0f5e07a9a0719c |
23-Jun-2006 |
Jim Laskey <jlaskey@mac.com> |
Add and sort "sections" in debug lines. This always stepping through
code in sections other than ".text", including weak sections like ctors and
dtors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28909 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| ef957105833fad1baadabbeb48632eb0d51f9262 |
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Correct returns of 64-bit values, though they seemed to work before...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28892 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 7f7b346e3d596ccd3d8b5ff1ba39b40a9b90900e |
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Make these predicates correct in 64-bit mode too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28890 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| b410dc99774d52b4491750dab10b91cca1d661d8 |
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28889 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstr64Bit.td
PCInstrFormats.td
PCInstrInfo.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 96dc5e5f6d2bdad7b24f191998e324888afacf83 |
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
remove unused flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28888 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| f2c5bca165fa654ad46f2b232773b2116b734b63 |
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
add some logical ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28887 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 4b25b404860c2e4a2845adfb9d78e46c303ac328 |
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
remove some unused patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28886 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 3ae5eef0278db0cff59f714ab4b2124ec31b942e |
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add some more immediate patterns. This allows us to compile:
void test6() {
Y = 0xABCD0123BCDE4567;
}
into:
_test6:
lis r2, -21555
lis r3, ha16(_Y)
ori r2, r2, 291
rldicr r2, r2, 32, 31
oris r2, r2, 48350
ori r2, r2, 17767
std r2, lo16(_Y)(r3)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28885 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| eded521a17fa2b39f6b1f9af5943036312bb3149 |
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is
set, so disable the pattern in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28884 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 0ea70b219a8408a25eaa522cbfc7e09f6dbc9d87 |
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| dd58343857eea0ecc90b2601d7908e054cd4f667 |
20-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
64-bit bugfix: 0xFFFF0000 cannot be formed with a single lis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28880 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| f27bb6de10b8a1b4b2e52b137ffda68c6ba0b9f4 |
20-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add some patterns for globals, so we can now compile this:
static unsigned long long X, Y;
void test1() {
X = Y;
}
into:
_test1:
lis r2, ha16(_Y)
lis r3, ha16(_X)
ld r2, lo16(_Y)(r2)
std r2, lo16(_X)(r3)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28879 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 4e85e64007e8561558e7d3e05a59cbfcc48d5bcc |
20-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Remove some now-unneeded casts from instruction patterns. With the casts
removed, tblgen produces identical output to with them in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28867 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
PCInstrInfo.td
|
| 047854f2b7a3f070f1bf4e5c24be2fc597bc544e |
20-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add some patterns for ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28866 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| b1d26f66658cff3ceb7d44a72fbc8c8e975532f9 |
17-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Implement the getPointerRegClass method, which is required for the ptr_rc
magic to work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28847 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
PCTargetMachine.cpp
|
| a24b7618f8a64976a5846c97261b2b5fb92da23e |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Upgrade some load/store instructions to use the proper addressing mode stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28841 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
|
| 66d7ebb7773c0521019eb578d9898c35519d9d5e |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
In 64-bit mode, addr mode operands use G8RC instead of GPRC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28840 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 059ca0f5b712e5460dcbccfa802b7adb3bccbac9 |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
fix some assumptions that pointers can only be 32-bits. With this, we can
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28839 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstr64Bit.td
PCInstrInfo.td
|
| 956f43c3109f207bb91ef5f5a3cb12303ed28f8c |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Split 64-bit instructions out into a separate .td file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28838 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstr64Bit.td
PCInstrInfo.td
|
| 8fa05dac3962202eeb6de434aeb9f720e384345b |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Force 64-bit register availability in 64-bit mode. For real.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28837 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| af89fa609bce1004c9ea9737d9fdb32f4224ef1c |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Remove the -darwin and -aix llc options, inferring darwinism and aixism from
the target triple & subtarget info. woo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28835 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCRegisterInfo.td
PCSubtarget.cpp
PCTargetMachine.cpp
|
| 1790d44d0dbe3412e012be5e43b89e67064bdb86 |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Don't pass target name into TargetData anymore, it is never used or needed.
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28830 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 7c1fb5f08c7c1e9550b7eb2d8d32c93648a6d08e |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Document the subtarget features better, make sure that 64-bit mode, 64-bit
support, and 64-bit register use are all consistent with each other.
Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently. This not makes ppc64 blow up on lots
of stuff :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28825 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
|
| a7a5854f1c3710f4bedf069be4771b81e449f2a3 |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCISelLowering.cpp
PCSubtarget.cpp
PCSubtarget.h
|
| 94de9a8951339536af1cc0ca947bc1005eb8f5f3 |
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
First baby step towards ppc64 support. This adds a new -march=ppc64 backend
that is currently just like ppc32 :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28813 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| f8a01a966120a041fe96300271573a8bf5a3e668 |
15-Jun-2006 |
Jim Laskey <jlaskey@mac.com> |
1. Support standard dwarf format (was bootstrapping in Apple format.)
2. Add vector support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28807 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| a7dc4a59cbb19cfb5dbc0f9ca500f26dddfbb7f6 |
15-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Type of extract_element index operand should be iPTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28797 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 014f98c7e5cbf41104ab9a86e32b8ce869982934 |
14-Jun-2006 |
Jim Laskey <jlaskey@mac.com> |
Place dwarf headers at earliest possible point. Well behaved when skipping
functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28781 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| e67304fb7880bd55d194d68b827c0eb2366c0a91 |
13-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register
allocated, thus live across the save/reload. This fixes
llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg
and probably others, with -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28761 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| b47e0897a090d31d952957ba873db6c1e487b50e |
12-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix spilling and reloading of CR regs to reload the right values. This fixes
Olden/power (and probably others) with -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28760 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| cf0063171995c97ee52dfdf5d6bbbe090d2f5f03 |
10-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Work around a nasty tblgen bug where it doesn't add operands for varargs
nodes correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28745 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 4a45abf66ee33ce3b8404ace90c4bfefda7105f8 |
10-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a problem exposed by the local allocator. CALL instructions are not marked
as using incoming argument registers, so the local allocator would clobber them
between their set and use. To fix this, we give the call instructions a variable
number of uses in the CALL MachineInstr itself, so live variables understands
the live ranges of these register arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28744 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| 001db453f5df586af9625d68e715950106e4f961 |
06-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add PowerPC intrinsics to support dcbz[l]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28696 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 08a9a985dc7881cad0321ae95147f0a4b04647a8 |
01-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Silence -pedantic warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28633 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 7b053509063f21aa0bf6ffc82b274e8cf6b0e182 |
30-May-2006 |
Chris Lattner <sabre@nondot.org> |
Always reserve space for 8 spilled GPRs. GCC apparently assumes that this
space will be available, even if the callee isn't varargs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28571 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6848be1a27e08a89dcd4dd69f746471a608012cd |
27-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8e2a04e21dc8299bdaba4321a6e690712dab9617 |
25-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix build failure of povray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28473 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 5d634ce466173f6fde49470fad125eb09532caeb |
25-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix Benchmarks/MallocBench/cfrac
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28471 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 4360bdcf1fc92a0bd29cc1a8ec1d2338def29cfc |
25-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
CALL node change (arg / sign pairs instead of just arguments).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28462 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6a3d5a62f09d4093468525a07a0143cae0e9df41 |
25-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Assert if InflightSet is not cleared after instruction selecting a BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28459 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| afe358e7d46da9d29ba02fbbf81bdfb4ac4a4520 |
24-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
non-deterministic behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28454 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| d74ea2bbd8bb630331f35ead42d385249bd42af8 |
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.h
PCJITInfo.cpp
PCRelocations.h
|
| 2ef5e89dc964ffb6a84d1e1a2a29c429dc4aa715 |
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/Generic/vector.ll:test_div with altivec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28445 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 573401237578297310a6be764805b8dfad702938 |
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Handle SETO* like we handle SET*, restoring behavior after Evan's setcc
change. This fixes PowerPC/fnegsel.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28443 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bcd8a8264e35e147e23c219f0435c9277e24ec66 |
21-May-2006 |
Owen Anderson <resistor@mac.com> |
Make TargetData strings less redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28423 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| d988b32abad0634df07c18629e899f256935fde7 |
20-May-2006 |
Owen Anderson <resistor@mac.com> |
Make all of the TargetMachine subclasses use the new string TargetData methods.
This is part of the on-going work on PR 761.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28414 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 0f3ac8d8d4ce23eb2ae6f9d850f389250874eea5 |
18-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| c01d497255f0d344163178c5f827e8b73f6f04d6 |
17-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove PointerType from class Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28368 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| 9d62fa4d162745f8812736473e41764bb0435b42 |
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
Add a note about a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28355 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| c703a8fbf8653ac8302ae368391a4954c307ca2c |
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
Make PPC call lowering more aggressive, making the isel matching code simple
enough to be autogenerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28354 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 9a2a497284e2233345c4bb9cdc1044d8395fddde |
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
Switch PPC over to a call-selection model where the lowering code creates
the copyto/fromregs instead of making the PPCISD::CALL selection code create
them. This vastly simplifies the selection code, and moves the ABI handling
parts into one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28346 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.td
|
| c8b682ca196c90bfae1ea4a411a97cccc2f4bd62 |
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
3 changes, 2 of which are cleanup one of which changes codegen:
1. Rearrange code a bit so that the special case doesn't require indenting lots
of code.
2. Add comments describing PPC calling convention.
3. Only round up to 56-bytes of stack space for an outgoing call if the callee
is varargs. This saves a bit of stack space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28342 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c04ba7a97d5ad599d92a1817de2d7c5fbb145810 |
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
implement passing/returning vector regs to calls, at least non-varargs calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28341 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| abde460d4f4e2fb6a4493b2a938055e48abaf239 |
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
Instead of implementing LowerCallTo directly, let the default impl produce an
ISD::CALL node, then custom lower that. This means that we only have to handle
LEGAL call operands/results, not every possible type. This allows us to
simplify the call code, shrinking it by about 1/3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28339 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| af4ec0c56d2162a369fcdeba740ddda21be359b9 |
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Simplify the argument counting logic by only incrementing the index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28335 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b375b5e629d12db6ec2b2b816af9784c0709656e |
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Simplify the dead argument handling code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28334 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| be4849aabe957019bd73dd465859c7c081c9fddd |
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Vector args passed in registers don't reserve stack space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28333 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8ab5fe574a388598b7ca945b4cd12e2485268027 |
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Switch the PPC backend over to using FORMAL_ARGUMENTS for formal argument
handling. This makes the lower argument code significantly simpler (we
only need to handle legal argument types).
Incidentally, this also implements support for vector argument registers,
so long as they are not on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28331 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 00402c7ec3aaf4d6a22c1eb97b9e1c1bb3136f46 |
16-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fit in 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28311 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f1d2337be1adf74888d1709977fdeda393c8d532 |
15-May-2006 |
Chris Lattner <sabre@nondot.org> |
Remove some dead code, identified by coverity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28303 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| b65e7256ed711aa473973744403efc86e1cb2c6d |
12-May-2006 |
Chris Lattner <sabre@nondot.org> |
Remove dead var, fix bad override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28264 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCTargetMachine.h
|
| b57b516f6d009ca3683f598a6026e23c7d1386e9 |
12-May-2006 |
Chris Lattner <sabre@nondot.org> |
remove dead variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28248 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 0949ed5412c0902113aaefe106fed5b383fcc696 |
12-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix PowerPC/2006-05-12-rlwimi-crash.ll
Nate, please verify that if InsertMask is 0, rlwimi shouldn't be used.
This fixes the crash and causes no PPC testsuite regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28243 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 07000c6f01d8f57170f2d4c77a86d934bdc5c696 |
12-May-2006 |
Owen Anderson <resistor@mac.com> |
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28238 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.h
|
| 3e6a35076ed072525d3eda1945033863b613aef8 |
10-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is
really a bad codegen bug that LLC happens to get lucky with. I must chat with
Nate for the proper fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28213 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 219f1b535dd65cf49d783f846bd8da80e3700c2e |
09-May-2006 |
Chris Lattner <sabre@nondot.org> |
Indent .data/.text in the .s file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28204 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 4632d7a57008564c4b0f8246e85bd813a200d2c6 |
09-May-2006 |
Chris Lattner <sabre@nondot.org> |
Split SwitchSection into SwitchTo{Text|Data}Section methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28184 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 7514620052208c7669ebaada1eebd5d00ce29a60 |
08-May-2006 |
Nate Begeman <natebegeman@mac.com> |
Yet more readme updating
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28172 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| fcf64a91d65ece1168c2108271c4b2c7e4271e5e |
08-May-2006 |
Nate Begeman <natebegeman@mac.com> |
New note about something bad happening in target independent optimizers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28170 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| d8624ed07f1fc903580da17173b1f29e7eb98377 |
08-May-2006 |
Nate Begeman <natebegeman@mac.com> |
Proving once again that I am not as smart as the compiler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28169 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 4667f2cbad246beccfca5411a26add24d1007035 |
08-May-2006 |
Nate Begeman <natebegeman@mac.com> |
Fold more shifts into inserts, and update the README
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28168 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
EADME.txt
|
| 93376b083e11f6dfcc678fe68abbc801eaa0a348 |
08-May-2006 |
Nate Begeman <natebegeman@mac.com> |
Update some stuff now that the new rlwimi code has gone in
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28162 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
EADME.txt
|
| 77f361f5b3ac6ed080d6b0f401b62cd6e08614e5 |
07-May-2006 |
Nate Begeman <natebegeman@mac.com> |
New rlwimi implementation, which is superior to the old one. There are
still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same bitfield. More regression tests
to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28156 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 35c3913328b254871731f1f5cc092c303a2cd378 |
05-May-2006 |
Chris Lattner <sabre@nondot.org> |
Print a grouping around inline asm blocks so that we can tell when we are
using them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28134 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 55c63257f31e2fa0b4a606f15d809cf615bc960c |
05-May-2006 |
Chris Lattner <sabre@nondot.org> |
New note, Nate, please check to see if I'm full of it :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28118 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 2d90ac7ca6117d3b160dde8a4f322c1079a6ffce |
04-May-2006 |
Chris Lattner <sabre@nondot.org> |
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28104 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| e53f4a055f74bded20d6129b4724ddd17fd199f6 |
04-May-2006 |
Chris Lattner <sabre@nondot.org> |
Move some methods out of MachineInstr into MachineOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 63b3d7113d93fda622c4954c6b1d046ce029044e |
04-May-2006 |
Chris Lattner <sabre@nondot.org> |
There shalt be only one "immediate" operand type!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28099 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCInstrBuilder.h
PCRegisterInfo.cpp
|
| e45aa737ba902a5caf2f259b3116bfc7d29b2990 |
04-May-2006 |
Chris Lattner <sabre@nondot.org> |
Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones).
Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of
CRRC seems to cause failures as well. Further investigation is required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28097 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| ea50fabfd4e5fad25a25b312f64a9b2a53363586 |
04-May-2006 |
Chris Lattner <sabre@nondot.org> |
Remove a bunch more SparcV9 specific stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28093 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 10f3597c4e0c13ecf0272b7ca0be741a91ade48c |
04-May-2006 |
Chris Lattner <sabre@nondot.org> |
Remove some more unused stuff from MachineInstr that was leftover from V9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28091 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 5a032de387831b9de3a707292eade95934938da9 |
03-May-2006 |
Chris Lattner <sabre@nondot.org> |
Change from using MachineRelocation ctors to using static methods
in MachineRelocation to create Relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28088 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| b4432f3d4754e16c918428d34a9d8ec18ab79204 |
03-May-2006 |
Chris Lattner <sabre@nondot.org> |
Suck block address tracking out of targets into the JIT Emitter. This
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28082 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| a69571c7991813c93cba64e88eced6899ce93d81 |
03-May-2006 |
Owen Anderson <resistor@mac.com> |
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
This fixes PR 759.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28074 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| af1563fb62ed76f4818ac172ab1c6cf15fa35a82 |
03-May-2006 |
Chris Lattner <sabre@nondot.org> |
Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28069 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| f75f9be3fb89eb6661a0ed8bfee8a6328ee5a4d1 |
03-May-2006 |
Chris Lattner <sabre@nondot.org> |
Several related changes:
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
from the MachineCodeEmitter interface, and reducing the amount of target-
specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
*right* next to the functions that they belong to, instead of in a separate
pool of memory. This makes all memory for a function be contiguous, and
means the JITEmitter only tracks one block of memory now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28065 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| d3f0aefc33965d3d0ca6f92af4ebaea354b063c4 |
02-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a purely hypothetical problem (for now): emitWord emits in the host
byte format. This doesn't work when using the code emitter in a cross target
environment. Since the code emitter is only really used by the JIT, this
isn't a current problem, but if we ever start emitting .o files, it would be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28060 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCJITInfo.cpp
|
| 43b429b05989075b60693d57395c99b0ad789f8d |
02-May-2006 |
Chris Lattner <sabre@nondot.org> |
Refactor the machine code emitter interface to pull the pointers for the current
code emission location into the base class, instead of being in the derived classes.
This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments. This implements feature request #1 of PR469.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28059 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 426cd7c25fc3f5d064f9e88af0ecad26c836135a |
02-May-2006 |
Nate Begeman <natebegeman@mac.com> |
Since we don't handle callee-save CRs right yet, don't allocate them. Also
don't step on R11 in the middle of a function when saving and restoring CRs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28058 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| 6e0f3868965612fbd391ec9d4c5eeec6ffebb351 |
02-May-2006 |
Nate Begeman <natebegeman@mac.com> |
Hooray, everyone now uses the same printBasicBlockLabel implementation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28056 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| cdf38c4edb892c356cfaa3c09c57728bc8d6bfd0 |
02-May-2006 |
Nate Begeman <natebegeman@mac.com> |
Extend printBasicBlockLabel a bit so that it can be used to print all
basic block labels, consolidating the code to do so in one place for each
target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28050 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 5425267e84946676f1e7424ee056f71b23497ee7 |
02-May-2006 |
Nate Begeman <natebegeman@mac.com> |
Update the PPC compilation callback code to not need weird abi-violating
prologs and epilogs, keep all the asm in one place, and remove use of
compiler builtin functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28049 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 25b8b8cb2cd8653712b0a567edf8573a067f8ff1 |
28-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28017 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e481e8bc8f08ec79e7b61d200fd826b81ff7cf35 |
28-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27999 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| b3f70d7d556913126e4066d61328b701ce59c55a |
25-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
No functionality changes, but cleaner code with correct comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27966 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 37efe6764568a3829fee26aba532283131d1a104 |
22-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
JumpTable support! What this represents is working asm and jit support for
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.td
|
| ea4a9c575fa0a8c8c1dce5223a637a166e5c1f8c |
22-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Teach the JIT how to relocate LI, this fixes the JIT on Prolangs-C/TimberWolfMC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27943 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| d9993b0b2d05d0c65f3a319be8dc36fb4add29e8 |
22-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
Fix the comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27938 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 6fcbd6961d9f14d75e2b314b06ca823d43a70353 |
22-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
Change the PPC JIT to use a Static relocation model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27937 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCJITInfo.cpp
PCTargetMachine.cpp
|
| ba2194ae84b04b37120b189e2e23eac3daa3b0a0 |
20-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the CodeGen/PowerPC/buildvec_canonicalize.ll regression last night.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27908 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 0231007269c675ac12178cf675639ff95ee106f8 |
20-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Make sure that the new instructions selected have the right type. This fixes
CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27868 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 8cc5ffb27fa0c9c2e520b117d2ad1203b44c3b6d |
19-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27832 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| bf9b3716eda91629d1597e290034d9ce050d0b13 |
19-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27828 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| 80f362a48f27958c1ce9145638884283d9e9bbe2 |
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
These are correctly encoded by the JIT. I checked :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27810 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 87140126e88d4fe4f9aedac06dd4e9beec3b5301 |
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27809 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| 0090120c2b8ac3fea5427f6fae6f36fc3dc50dca |
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a crash on:
void foo2(vector float *A, vector float *B) {
vector float C = (vector float)vec_cmpeq(*A, *B);
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
*A = C;
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27808 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f70f8d91a79a3474345ad51c1899276eac7825c1 |
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
pretty print node name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27806 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 90564f26d17701e11effa2f4e0fb9a18d8a91274 |
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
EADME_ALTIVEC.txt
|
| 3be29059abc5652fd7db2f64704e1359d325964d |
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
move some stuff around, clean things up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27802 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| cea2aa77eb815d41ad59ecdd110ec42bc5b567c8 |
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Use vmladduhm to do v8i16 multiplies which is faster and simpler than doing
even/odd halves. Thanks to Nate telling me what's what.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27793 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 19a815238e55458e95f99b4dad31ed053c9f635c |
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Implement v16i8 multiply with this code:
vmuloub v5, v3, v2
vmuleub v2, v3, v2
vperm v2, v2, v5, v4
This implements CodeGen/PowerPC/vec_mul.ll. With this, v16i8 multiplies are
6.79x faster than before.
Overall, UnitTests/Vector/multiplies.c is now 2.45x faster with LLVM than with
GCC.
Remove the 'integer multiplies' todo from the README file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27792 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
EADME_ALTIVEC.txt
|
| 72dd9bdcc57a71d7e9a6f3e68ca1a35ad437a980 |
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Lower v8i16 multiply into this code:
li r5, lo16(LCPI1_0)
lis r6, ha16(LCPI1_0)
lvx v4, r6, r5
vmulouh v5, v3, v2
vmuleuh v2, v3, v2
vperm v2, v2, v5, v4
where v4 is:
LCPI1_0: ; <16 x ubyte>
.byte 2
.byte 3
.byte 18
.byte 19
.byte 6
.byte 7
.byte 22
.byte 23
.byte 10
.byte 11
.byte 26
.byte 27
.byte 14
.byte 15
.byte 30
.byte 31
This is 5.07x faster on the G5 (measured) than lowering to scalar code +
loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27789 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e7c768ea24027938b52abd6ee94755b6d17f3da3 |
18-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Custom lower v4i32 multiplies into a cute sequence, instead of having legalize
scalarize the sequence into 4 mullw's and a bunch of load/store traffic.
This speeds up v4i32 multiplies 4.1x (measured) on a G5. This implements
PowerPC/vec_mul.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27788 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 22fcbb132008fcc6004dd4047b5a6ae06dbb7548 |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
remove done item
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27778 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| f9568d8700d5389799796262cde313bb5c7d588a |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Don't diddle VRSAVE if no registers need to be added/removed from it. This
allows us to codegen functions as:
_test_rol:
vspltisw v2, -12
vrlw v2, v2, v2
blr
instead of:
_test_rol:
mfvrsave r2, 256
mr r3, r2
mtvrsave r3
vspltisw v2, -12
vrlw v2, v2, v2
mtvrsave r2
blr
Testcase here: CodeGen/PowerPC/vec_vrsave.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27777 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 402504b1ba250839102ba384be0210d248b6e3e8 |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Vectors that are known live-in and live-out are clearly already marked in
the vrsave register for the caller. This allows us to codegen a function as:
_test_rol:
mfspr r2, 256
mr r3, r2
mtspr 256, r3
vspltisw v2, -12
vrlw v2, v2, v2
mtspr 256, r2
blr
instead of:
_test_rol:
mfspr r2, 256
oris r3, r2, 40960
mtspr 256, r3
vspltisw v0, -12
vrlw v2, v0, v0
mtspr 256, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27772 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 939274fcfd65047d516d5afff0dc5ac1817c5550 |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Prefer to allocate V2-V5 before V0,V1. This lets us generate code like this:
vspltisw v2, -12
vrlw v2, v2, v2
instead of:
vspltisw v0, -12
vrlw v2, v0, v0
when a function is returning a value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27771 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 369503f8412bba4a0138074c97107c09cc4513e0 |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Move some knowledge about registers out of the code emitter into the register info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27770 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| f7d2372b7407c7f8966df39a2b5a067c72bd6b9b |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Use a small table instead of macros to do this conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27769 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| dbce85dedf5d37794cf5237a78f609dda6b6608d |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Make sure to check splats of every constant we can, handle splat(31) by
being a bit more clever, add support for odd splats from -31 to -17.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27764 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bdd558cd94a816df83526ab5e5d309f3fc0e210a |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Teach the ppc backend to use rol and vsldoi to generate splatted constants.
This implements vec_constants.ll:test_vsldoi and test_rol
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27760 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 966083fd1ad5adf801b767bba008ebaf0b9e06fa |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27758 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| 6876e66e5dbab2847f10ca89a75964fabda4489c |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Make some code more general, adding support for constant formation of several
new patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27754 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c408382ecade09f66343b084fa0ab437781de593 |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Learn how to make odd splatted constants in range [17,29]. This implements
PowerPC/vec_constants.ll:test_29.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27752 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 4a998b9ca8372038ac92ea6057290c2cad73f988 |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Pull some code out into a helper function.
Effeciently codegen even splats in the range [-32,30].
This allows us to codegen <30,30,30,30> as:
vspltisw v0, 15
vadduwm v2, v0, v0
instead of as a cp load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27750 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 5913810b8286191053853b7495f324e091ab208f |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Implement a TODO: for any shuffle that can be viewed as a v4[if]32 shuffle,
if it can be implemented in 3 or fewer discrete altivec instructions, codegen
it as such. This implements Regression/CodeGen/PowerPC/vec_perf_shuffle.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27748 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
EADME_ALTIVEC.txt
|
| cffeb86169e3211766ea01ecb855f0ca2041fd73 |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Regenerate with adjusted costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27746 91177308-0d34-0410-b5e6-96231b3b80d8
PCPerfectShuffle.h
|
| 586d6a808dc80abe1b00e5fe943b1042cb4422e9 |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Regenerate with correct offset
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27744 91177308-0d34-0410-b5e6-96231b3b80d8
PCPerfectShuffle.h
|
| c74e7100007ed830af146afe7194b08764a38ee7 |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Increase the opcodes by one each to disambiguate COPY from VMRGHW.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27742 91177308-0d34-0410-b5e6-96231b3b80d8
PCPerfectShuffle.h
|
| 6703461f04988a82cbd62cbe08c393965ae3c2df |
17-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Check in a table, generated by llvm-PerfectShuffle, of optimal shuffles
of various 4-element vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27739 91177308-0d34-0410-b5e6-96231b3b80d8
PCPerfectShuffle.h
|
| f3f69decca93d2465957e5ebf1f64b20e2845967 |
16-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Implement a TODO: have the legalizer canonicalize a bunch of operations to
one type (v4i32) so that we don't have to write patterns for each type, and
so that more CSE opportunities are exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27731 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrAltivec.td
EADME_ALTIVEC.txt
|
| b17f1679e3ce2b40fc2141fc50ef3def4bbd00bc |
16-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Make the BUILD_VECTOR lowering code much more aggressive w.r.t constant vectors.
Remove some done items from the todo list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27729 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
EADME_ALTIVEC.txt
|
| 730b45694bd910efe0c5c38897854222f74c92bb |
16-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a crash when faced with a shuffle vector that has an undef in its mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27726 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6e94af75de7f21b667046063dde49181c233b973 |
16-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add patterns for matching vnots with bit converted inputs. Most of these will
go away when I start using evan's binop type canonicalizer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27725 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| b097aa9353121cf6713408402022b8843a0f6acc |
15-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Allow undef in a shuffle mask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27714 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1a635d617aae63a759bc9d8abc6ee4315b9277ea |
14-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Move the rest of the PPCTargetLowering::LowerOperation cases out into
separate functions, for simplicity and code clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27693 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f1b4708950cb0dc2a0cafb572d5a56d99b8140c0 |
14-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Pull the VECTOR_SHUFFLE and BUILD_VECTOR lowering code out into separate
functions, which makes the code much cleaner :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27692 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a39d798e0af289956848b8583b2f80d4801656ec |
13-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Force non-darwin targets to use a static relo model. This fixes PR734,
tested by CodeGen/Generic/vector.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27657 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ed9379051708a6ef858bcfa4e300f126eb69c178 |
13-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add a note, move an altivec todo to the altivec list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27654 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
EADME_ALTIVEC.txt
|
| 3758552428737f2467cc58ae81a064789637b4aa |
13-Apr-2006 |
Reid Spencer <rspencer@reidspencer.com> |
Add the README files to the distribution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27651 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| ac225ca0514b75e29347933d75e86d03ab8a28e1 |
12-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add a new way to match vector constants, which make it easier to bang bits of
different types.
Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1. This compiles:
typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
*P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
*P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
*P3 = vec_abs((vector float)*P3);
}
to:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
vspltisw v0, -1
vslw v0, v0, v0
lvx v1, 0, r3
vand v1, v1, v0
stvx v1, 0, r3
lvx v1, 0, r4
vandc v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vandc v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
instead of (with two constant pool entries):
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
li r6, lo16(LCPI1_0)
lis r7, ha16(LCPI1_0)
li r8, lo16(LCPI1_1)
lis r9, ha16(LCPI1_1)
lvx v0, r7, r6
lvx v1, 0, r3
vand v0, v1, v0
stvx v0, 0, r3
lvx v0, r9, r8
lvx v1, 0, r4
vand v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vand v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
GCC produces (with 2 cp entries):
_test:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc00c
mtspr 256,r0
lis r2,ha16(LC0)
lis r9,ha16(LC1)
la r2,lo16(LC0)(r2)
lvx v0,0,r3
lvx v1,0,r5
la r9,lo16(LC1)(r9)
lwz r12,-4(r1)
lvx v12,0,r2
lvx v13,0,r9
vand v0,v0,v12
stvx v0,0,r3
vspltisw v0,-1
vslw v12,v0,v0
vandc v1,v1,v12
stvx v1,0,r5
lvx v0,0,r4
vand v0,v0,v13
stvx v0,0,r4
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27624 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
EADME_ALTIVEC.txt
|
| e87192a854ff0f2f1904dd9ea282eb36059bb5af |
12-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Rename get_VSPLI_elt -> get_VSPLTI_elt
Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each
form, eliminating a bunch of Pat patterns in the .td file and allowing us to
CSE stuff more aggressively. This implements
PowerPC/buildvec_canonicalize.ll:VSPLTI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27614 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
|
| 2b1c3258d68271098172e52d4e1f8424d855025f |
12-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Ensure that zero vectors are always v4i32, which forces them to CSE with
each other. This implements CodeGen/PowerPC/vxor-canonicalize.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27609 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrAltivec.td
|
| 218629813a47d3e398f37b5be284e179a0ec855f |
11-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
Fix SingleSource/UnitTests/Vector/sumarray-dbl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27594 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 030514cd96e9b8bb08fd9585d890bd7a5f0dbb77 |
11-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
Fix PR727, correctly handling large stack aligments on ppc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27593 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 95c7570f3231660071be9becb185678df268c936 |
11-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
we have a shuffle instr, add an example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27592 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| 52fa2449c9c1c8f8373faccb8968588211101e68 |
11-Apr-2006 |
Jim Laskey <jlaskey@mac.com> |
Suppress debug label when not debug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27588 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| bee9836c0f21be0bd5034f60caa9594c3949910d |
11-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Vector function results go into V2 according to GCC. The darwin ABI doc
doesn't say where they go :-/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27579 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 06c24350a92dff027cf1b4ddb91704cb82d976ae |
11-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Move some return-handling code from lowerarguments to the ISD::RET handling stuff.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27577 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a1d95e16df0949fcd33b1ee938a4791dac6f6cad |
09-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
properly mark vector selects as expanded to select_cc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27544 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 710ff32983ca919fa0da14e077450b6a7654274f |
09-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add VRRC select support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27543 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.td
|
| 957e1674e797c8880114fb27a3aa1c32f9967329 |
08-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
Disable switch lowering for targets based on the selection dag isel,
letting the code generator handle them directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27539 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 79d9a881651689a3814e2d471ba4ab0ff37a4ca8 |
08-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Implement PowerPC/CodeGen/vec_splat.ll:spltish to use vsplish instead of a
constant pool load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27538 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 140a58f9dfda30dbb80edd3da1b5632c178f7efc |
08-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Change the interface to the predicate that determines if vsplti* can be used.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27536 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
|
| 6b92b8e50d7e5b48407865c3aaf9966c01416c69 |
07-Apr-2006 |
Jim Laskey <jlaskey@mac.com> |
Make sure that debug labels are defined within the same section and after the
entry point of a function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27494 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 4188699f80c233a20b6ddc61570a8a8c1804cb85 |
07-Apr-2006 |
Jim Laskey <jlaskey@mac.com> |
Foundation for call frame information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27491 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 1c8010301676dd72274573455014386d45e57e47 |
07-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add an item
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27470 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| 90217999bdb00fdb1e6d7ee98f75fca8930b2ba5 |
07-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Make sure to return the result in the right type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27469 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f24380e78ecc8a2db1b2116867d878b1e7c6f6ed |
07-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Match vpku[hw]um(x,x).
Convert vsldoi(x,x) to work the same way other (x,x) cases work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27467 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
|
| caad163496a3ad207a75009f4ad16bae1b1527ae |
07-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for matching vmrg(x,x) patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27463 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
|
| 116cc48e30b9c307bf3eec29c890b4ba25cd18db |
06-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Pattern match vmrg* instructions, which are now lowered by the CFE into shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27457 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
EADME_ALTIVEC.txt
|
| 58d665c1828d8a97260a0eefa6924dd59b43209c |
06-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
remove two done items
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27453 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| d0608e191ff9c00af68985f246410c219d1bec57 |
06-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. to
lower it and LLVM to have one fewer intrinsic. This implements
CodeGen/PowerPC/vec_shuffle.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27450 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
EADME_ALTIVEC.txt
|
| ddb739e5ea6ccf6fa4f4e2a23e3da550868efaa1 |
06-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of into
vperm with a perm mask lvx'd from the constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27448 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
|
| d8242b49b24a46f685599834b6ca33dfbeba9382 |
06-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add all of the data stream intrinsics and instructions. woo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27442 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
PCInstrFormats.td
EADME_ALTIVEC.txt
|
| 99bdc654e565193e17245979a3df8c60eabf0c6d |
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27440 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 9b42bdd7bced1d31d309dca2932d0a063ea6c863 |
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/PowerPC/2006-04-05-splat-ish.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27439 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 278158b4877c64b741fd37b2eb9ca1bdbc2eb3d7 |
05-Apr-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27433 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3827f712dac3362419ee722ca4c8c0ecea72e257 |
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add vsl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27425 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 0d2cf6b1d1af80c69d6a70e9eebd6a2fcb0a791b |
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add vmladduhm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27423 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
EADME_ALTIVEC.txt
|
| 4d9100ddc9d38bf64e5fa37355fd188742cc0973 |
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add m[tf]vscr instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27421 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
PCInstrFormats.td
|
| 8b4684247aa23cb3b022de9a45b009e66aa9b51d |
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27419 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| 72e241cff78869a0bc309f8522c313071b2baec6 |
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add missing byte merges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27418 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| a046d4ac116964996b348e1aa2efc262924b412c |
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add FP -> Int Conversions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27417 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 3f0b7ff39fcf50fc2b57718cd2264137f11614b6 |
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add average intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27416 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 298b68422956ec6f640f508bf089110674418ca6 |
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27414 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| 098e699f21a532d37b1ad44bb1bc24a87b3f9962 |
05-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Fix some broken logic that would cause us to codegen {2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27413 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 7ff7e674580adad7a5bccdbd74cf9c9f05e46d0f |
04-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Ask legalize to promote all vector shuffles to be v16i8 instead of having to
handle all 4 PPC vector types. This simplifies the matching code and allows
us to eliminate a bunch of patterns. This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27400 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
|
| 684ad7702f5196c2b1efd93aec4eb7283c3c24c6 |
04-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Plug in the byte and short splats
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27387 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| b68314480d693f2d431c9d1748f4c8c084f3e5f5 |
04-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Revert accidentally committed hunks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27386 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 01cae0799dd4a43c02edc3b5e08e9010ac4ae459 |
04-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27385 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 4f91a4c497fb1032550b7f163004efc5fce1d7f1 |
04-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Force use of a frame-pointer if there is anything on the stack that is aligned
more than the OS keeps the stack aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27381 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| c461a51234b1b631b9be3992ecf82abf7eca30f4 |
03-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add the full set of min/max instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27372 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 220d2b89d69b7f78b6baac357b857475d53f6407 |
02-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27360 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| bbe77de450ef36b4f83cc3b57705a9758adbd925 |
02-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Inform the dag combiner that the predicate compares only return a low bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27359 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 02b72556d738b9086129518eef4991b5b6012666 |
02-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Remove done item
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27351 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| c55bfd0265214f18ddd6bf4515bcf2c5a3973f00 |
02-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27348 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| 541f91b17c33712e2c92f02916082832e6d73c46 |
02-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into
"vspltisb v0, 8" instead of a constant pool load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27335 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c3837d49178c2d3f8e80347f93f4859d46175cc0 |
02-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27331 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 348ba3f9bfe82fe602e52063566318dd77aa1d4d |
01-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Shrinkify some more intrinsic definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27322 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 6cea814f2c2268f19b28ea1443cd5f55f932bb1e |
01-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Pull operand asm string into base class, shrinkifying intrinsic definitions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27320 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| b5c4d17a6c03af1ec8e3fd4fd9d5b07b9c2694a4 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Fix 80 column violations :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27315 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 7376a5e1292cf848880ebced00131c54a2194ac9 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
fix a pasto
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27308 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| a9cb44164256daaf7e4937eeb04706a316e5c1ea |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add vperm support for all datatypes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27307 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| e3fea5a1c12c668ae659a9f68c2d9c711607d8fd |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Rearrange code a bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27306 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 32a988a095ac93f54ca058bbeb7561f694c66b07 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add, sub and shuffle are legal for all vector types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27305 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 9f7e1271336954d5319189c64f96bf187bb55cd9 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27302 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| 33497cc99210b45eede30b35909929eebe06d734 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
note to self: *save* file, then check it in
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27291 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 4468c224586ba0f75e17ed7520a39a30e8caf636 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Implement an item from the readme, folding vcmp/vcmp. instructions with
identical instructions into a single instruction. For example, for:
void test(vector float *x, vector float *y, int *P) {
int v = vec_any_out(*x, *y);
*x = (vector float)vec_cmpb(*x, *y);
*P = v;
}
we now generate:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v0, v1, v0
mfcr r4, 2
stvx v0, 0, r3
rlwinm r3, r4, 27, 31, 31
xori r3, r3, 1
stw r3, 0(r5)
mtspr 256, r2
blr
instead of:
_test:
mfspr r2, 256
oris r6, r2, 57344
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v2, v1, v0
mfcr r4, 2
*** vcmpbfp v0, v1, v0
rlwinm r4, r4, 27, 31, 31
stvx v0, 0, r3
xori r3, r4, 1
stw r3, 0(r5)
mtspr 256, r2
blr
Testcase here: CodeGen/PowerPC/vcmp-fold.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27290 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
EADME_ALTIVEC.txt
|
| 9492151e32ca70e08789a69f9c22415cb9d7a5ae |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
compactify some more instruction definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27288 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 5f7b01963fa44b45b89a57c5c0d1995288a69a30 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Compactify comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27287 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| a17b1557ad705c56c41624e6841e19093ed31f21 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Lower vector compares to VCMP nodes, just like we lower vector comparison
predicates to VCMPo nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27285 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
PCInstrInfo.td
|
| 8f5d316ff2b29a31671aebefb4596505f3a999de |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
These are done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27284 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| 36f4b0da9d71b06fce6277be2d9594fafdcb26e0 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Mark INSERT_VECTOR_ELT as expand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27276 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8768bf6ee33a9186272b6eede9e13c3dc5cb7168 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add the rest of the vmul instructions and the vmulsum* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27268 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 3c4f4e9f1b17ea3f116cfb711b6c5404c071a129 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Use a new tblgen feature to significantly shrinkify instruction definitions that
directly correspond to intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27266 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 30a6abaef089654497d262e685c14e85d04241d0 |
31-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add a bunch of new instructions for intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27265 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| f3a627262c55d86052f2efbd8a5cd94b8a0c4492 |
29-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27243 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| d732a2915bcfe52b5bcbd364ca45c426f3b214af |
28-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27227 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4 |
28-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Expose base register for DwarfWriter. Refactor code accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27225 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 816cee2216a7b77eec6395500123d49c2fbf22e5 |
28-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Fix a couple typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27216 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 98e70cc124a1b522611dfc61e085bc755b5616c1 |
28-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Add a few more altivec intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27215 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrAltivec.td
EADME_ALTIVEC.txt
|
| ecc219b8d4546af0ad56e984d0a4120ec2ab61b3 |
28-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
implement a bunch more intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27209 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
EADME_ALTIVEC.txt
|
| 7f20b13518b3e45b1c594d3faac3b649571d48d8 |
28-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Use normal lvx for scalar_to_vector instead of lve*x. They do the exact
same thing and we have a dag node for the former.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27205 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
PCInstrInfo.td
|
| 48b61a729df6576c8833a83893d4086bddff69a5 |
28-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27201 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrAltivec.td
|
| 414e682bac7c7fb618aef6bb0caf8ae501f7a2ed |
27-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Translate llvm target registers to dwarf register numbers properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27180 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 3ee9ffb0e543328bea4052fba0f47ebc16314f79 |
27-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add a bunch of notes from my journey thus far.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27170 91177308-0d34-0410-b5e6-96231b3b80d8
EADME_ALTIVEC.txt
|
| b86bd2cee25c15862247b4641700d448fbd0fa24 |
27-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Split out altivec notes into their own README
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27168 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
EADME_ALTIVEC.txt
|
| fb143ce459bafde02a7c6d625cc8974966fa5dff |
27-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the JIT encoding of VSEL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27160 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
PCInstrFormats.td
|
| eeaf72af39afce402236f71702d878ce65491b6a |
27-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the JIT encoding of VSPLTI*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27159 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
PCInstrFormats.td
|
| f15485a8d0dff5f720b7ad27346129ac5c3ec503 |
27-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
SelectionDAGISel can now natively handle Switch instructions, in the same
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27156 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bd6be6f52d74b15081480c382eb3e3deaaabd574 |
27-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add vsel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27153 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 6d92caddc4aa5fc946b294259e00cc35536e61e8 |
26-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Codegen vector predicate compares.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27151 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
PCInstrInfo.td
|
| 5b6a01b59c570a32baeab52f7080e6bf1739926a |
26-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27149 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrAltivec.td
|
| b8a45c27986806220c6b112e5b6ee7baa1ab2efe |
26-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add all of the altivec comparison instructions. Add patterns for the
non-predicate altivec compare intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27143 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
PCInstrFormats.td
|
| 5d72907e00d13e6d451f459f507fbe37f17e6df7 |
26-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add and 8/16-bit adds, add all integer subtracts, add saturating subtract
intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27142 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| e7d959c069add37bd8928f088d86ebd1444a29eb |
26-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
implement the vsldoi intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27139 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
PCInstrFormats.td
|
| af9136bc0c7ce213271495801033e332b8d38bda |
26-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
fix the pattern for vandc, it's NOT vnand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27136 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 6509ae859a7fd7ac1b7c1590a9f102072637c260 |
26-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add patterns for VANDC/VNOR, implementing
CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27135 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 2430a5f0c7f7416bac6086e382eac73af75cf173 |
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add some logical operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27127 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| 984f38bf4fbf7c8ccf6d207966393e79201f25ef |
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
implement a bunch of intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27118 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
|
| b22a04d881ccf9b67628ec1ea4b32eda60134ef3 |
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Move all Altivec stuff out into a new PPCInstrAltivec.td file.
Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27117 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrAltivec.td
PCInstrInfo.td
|
| 8d052bc711f1f451e79a2923829d2590d2951601 |
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add some basic patterns for other datatypes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27116 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| 150ffa7842e3ce96bb3d86ee47c0ec7e34df4906 |
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add all supported formats to the vector register file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27115 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 5a2025465b773e4c7f43f196ca8067ef6221f75f |
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for __builtin_altivec_vnmsubfp /vmaddfp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27112 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 420736dc85c01702bb7bc40495f8a4be5e5f8a6c |
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
#include Intrinsics.h into all dag isels
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
EADME.txt
|
| 9c61dcf1aaf275a1733b6785c54d34eda5426ae1 |
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Codegen things like:
<int -1, int -1, int -1, int -1>
and
<int 65537, int 65537, int 65537, int 65537>
Using things like:
vspltisb v0, -1
and:
vspltish v0, 1
instead of using constant pool loads.
This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27106 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 47622e37215429c20d8278ff57496d840811cc13 |
24-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Add dwarf register numbering to register data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 057f09bc0b6ff4e0995995010b123ad6e9fefd39 |
24-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add another note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27077 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 8edd11f33d1cadfddcd97a74ebdc8c7603266593 |
24-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27069 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 54e869e18cd3d7c6ea6e2bce668c961b6f46f0ea |
24-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Like the comment says, prefer to use the implicit add done by [r+r] addressing
modes than emitting an explicit add and using a base of r0. This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27068 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 7fbcef7102732769e2dab1d37f68166b2868c963 |
24-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Disable the i32->float G5 optimization. It is unsafe, as documented in the
comment.
This fixes 177.mesa, and McCat/09-vor with the td scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27060 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 64b3a08bc696b2ef8733d72ce81e49be175cbbff |
24-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add support for using vxor to build zero vectors. This implements
Regression/CodeGen/PowerPC/vec_zero.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27059 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 9d5da1d96cc90cc04a57c1cb1aa6f47e6bb99ef7 |
24-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Gabor points out that we can't spell. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27049 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 716aefcd910ae849ffb42d4149ac6aecc818c515 |
23-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27000 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| dc6af72781507383ba244cace39293fc244bb753 |
23-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add PPC vector bit-convert support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26995 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| f1d78e83356a412e525c30ac90dabf090a8cfc99 |
23-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Add support to locate local variables in frames (early version.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26994 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 99db0442f03f75aa36b560a7f4327bfa992ac15c |
23-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Change interface to DwarfWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26991 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| bc641b9d8b5ecafe0137c1a49f4777608981d81b |
23-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Eliminate IntrinsicLowering from TargetMachine.
Make the CBE and V9 backends create their own, since they're the only ones that use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26974 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 9d86a9dff23fa56b7de60fa79baf9351cf921f99 |
22-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
This has been implemented. Tweak it into another note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26944 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| ecfe55e65b6a72fddd543c42f2e2df4c96c647ba |
22-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
PCRegisterInfo.cpp
|
| e5ba580ab05b18eaa9fd4d36e31466e41f693ad9 |
22-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for "ri" addressing modes where the immediate is a 14-bit field
which is shifted left two bits before use. Instructions like STD use this
addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26942 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
|
| eb8b09f69f0949f7ab7426d9c44ec45acd9dbdaa |
22-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 9b3bd467d02e73a02afed6d50aaaa149a6a69701 |
21-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26930 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| f3ce43210a5f6e89cff40674919890329a46ef13 |
21-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Don't emit pseudo instructions!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26926 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| c0a8b6df2adc690998cd6e523e6bd37dd4c16bd3 |
21-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Update readme
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26924 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 13feb58aa1042ed01962ade548459b8f01ba1a48 |
21-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Print absolute memory references like this:
lwz r2, 8(0)
instead of this:
lwz r2, 8(r0)
This fixes the llc/llc-beta failures on PPC last night.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26922 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 8151914321a67b16d7183248593171e670a28e4c |
21-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26917 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 8593f9891da4782719e49ef1fb2554072ed1e52d |
21-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26913 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| ef040dd4a326c5dd23e6f055fc05b6f18e3a786e |
21-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
minor note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26912 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| d97964457e972cc0c0ae0e293f975112c3d65c46 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Handle constant addresses more efficiently, folding the low bits into the
disp field of the load/store if possible. This compiles
CodeGen/PowerPC/load-constant-addr.ll to:
_test:
lis r2, 2838
lfs f1, 26848(r2)
blr
instead of:
_test:
lis r2, 2838
ori r2, r2, 26848
lfs f1, 0(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26908 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 23baa1b3106993bc9e8a5807d8b1f9e486bdf845 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
remove dead variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26907 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bd83afd3cdaa89b8a378e92518a5aec7dc7f46c5 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
figuring these out! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26904 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| e376e00247aa957ebc8e83191853599ea4065eed |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
reenable this hack, the tblgen version isn't quite ready
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26902 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 32f57d9e261da7b4ad6de4cc75dc8b20d19bd6b2 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the pattern for VADDUWM, add i32 splat
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26901 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| e63d746ef6e75d5461c9e29bcaf04b2755455c7f |
20-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use tblgen'd VECTOR_SHUFFLE selection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26900 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| dd4d2d0e4086905d85bc3011c2de78822d873d83 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for generating vspltw, instead of a vperm instruction with a
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26898 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.td
|
| 88a99ef7cc69febf4e9feb89a087fd40d74c47a4 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26897 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ef819f8fbb68793cc21396fcc1563ec481dacb2f |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
fix duplicate definition errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26896 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 3c0f9cc90cdcb70caf0dc517b9f9206d731aeb70 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Check in some intermediate code that adds a skeleton for matching vsplt*
instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26894 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
PCInstrInfo.td
|
| 08e25de4d3c6a8e9b75be0a22f148c1b94cd8167 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26889 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 556aae0df03e13ae80361a4d4ec9ec6018b9b321 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add vsplat instructions, fix sched description for vperm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26888 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| f1d0b2bedaa065972a5ba17259055c1176cd1497 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26887 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 2bc6dc27e952dd0225b3eb2f68d9195f8b415cec |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Claim to have v16i8 for perm masks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26886 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| abdff1ee6dbede6a95ce80c8040f2b21200ea2c1 |
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add the vperm instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26883 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 28097d086f72cd2cd6e267a8dfa179633ef1494e |
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add a note about the MUL -> FMADD vector bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26874 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| b2177b9405e43a66bd5e76dfeed1b40aaedd9271 |
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Custom lower SCALAR_TO_VECTOR into lve*x.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26868 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| ab515b09bfba19c671aa2f8635d595552876189d |
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
PPC doesn't have SCALAR_TO_VECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26865 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 528180ed7ba092f5767163f567fd80f0887d9e4c |
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add support for vector undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26863 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| a17409dfd689f9f9c089e51d0671954f176af34c |
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
minor fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26857 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 28b1a0b5323eb6953f40c28b4a2b02c6602d49ac |
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
notes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26856 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 0a7bff01d0117f1c73f96fed842f6b31a4f71b4f |
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
we don't use lmw/stmw. When we want them they are easy enough to add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26853 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| a064d28843b425905ed981e693b7730a183ee31b |
19-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
rename these nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26848 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 79691bc1f3434f08f2014ecaa31c7213b71b0b34 |
17-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Fix subfic to match subc by default instead of sub so that it is correctly
cost-modeled as producing a flag. This fixes the test I just added for neg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26835 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 81e8097377529dc3b666f33bb525c49cfbac3f51 |
17-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.td
EADME.txt
|
| e261c474cac3fe1ca5bb8528c150095ffb81bbca |
17-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
remove dead variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26813 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 1ad9b3a3cc27c1cf960bd3f72ca8c6b39954b451 |
16-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Notes on how to kill the eeevil brtwoway, and make ppc branch selector
more target independant, generate better code, and be less conservative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26809 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| be80fc8d0951d6976881bb449d0354b30ae688ad |
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Strangely, calls clobber call-clobbered vector regs. Whodathoughtit?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26808 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| ed51169cd8c63ad336cb196b5a433c2e56c5fa20 |
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26807 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 9c09c9ec9dab61450800b42cbf746164aa076b88 |
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
teach the ppc backend how to spill/reload vector regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCRegisterInfo.cpp
|
| 419ed530068a70155bbb90efc58d3608186bc119 |
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add callee saved vector regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26805 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| 714554d70717c73e0542ca93df36fa78765f87af |
16-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added a way for TargetLowering to specify what values can be used as the
scale component of the target addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26802 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 8aa777d5ea8e73e2edf79fd35fd6b5c4e9949ca7 |
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
in functions that use a lot of callee saved regs, this can be more than
5 instructions away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26801 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 335fd3c7c2057b4e5fedb3161df44d7bc1759791 |
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for copying registers. still needed: spilling and reloading them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 2df992883b2efbcb5aae55c6dc2b50861224e6f9 |
16-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Another case we could do better on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26795 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 4bb189507281af0da8aff91743b5198acbf2398b |
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Save/restore VRSAVE once per function, not once per block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26793 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 133decdcebcd591d2ccc20cbf362a07322a1ffa2 |
15-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Update scheduling info for vrsave instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26776 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| a08610c8a534501bc4301c5037e883f180b19a99 |
14-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Fix an off by one error that caused PPC LLC failures last night.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26758 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 9c543b2299b706c4ebc3fed6e5227e5930087ff8 |
14-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
PPC LSR pass should use target lowering hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26743 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| c4c6257c1a154279bf10e9498d46d6c1793dbaa7 |
14-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCJITInfo.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 1877ec9b02511e111998596b9ba9c3a2275d6a92 |
13-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.td
|
| 64ce964673ca5c71f46933d8699aa557fbc5f15a |
13-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a couple of bugs that broke the alpha tester build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26722 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| 3faad495bc5c23de4852e7a3a13c25203cabfc3e |
13-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Handle cracked instructions in dispatch group formation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26721 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
|
| fd97734f3636f54a86890918096d3d692df0b939 |
13-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Mark instructions that are cracked by the PPC970 decoder as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26720 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCInstrFormats.td
PCInstrInfo.h
PCInstrInfo.td
|
| 88d211f82304e53694ece666d4a2507b170e4582 |
12-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Several big changes:
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelDAGToDAG.cpp
PCInstrFormats.td
PCInstrInfo.h
PCInstrInfo.td
|
| 9c2c38674a204452eeb50f1f0e3e7d26005a8cde |
11-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
blr is a branch too
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26710 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| e928a7277296ce4fb06010d42c580929562c31f8 |
10-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
teach the JIT to encode vector registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26697 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| b0d21ef20c29f4ea46d21b488f17feaa6a8760e1 |
08-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Change the interface for getting a target HazardRecognizer to be more clean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelDAGToDAG.cpp
|
| 49f398b96a026034c2e92ffeca692d0f57fa771a |
08-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26605 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 7809811e4ed3c2462efa327cef0464b9844baea2 |
07-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Use "llvm.metadata" section for debug globals. Filter out these globals in the
asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26599 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| b84225b080a6ad72c4eecececc0a4fdffc9455a8 |
07-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add another missing store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26595 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| ab5801cb28168b22444a95dd4c3783f4eba25801 |
07-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add a couple more load/store instrs, add a newline to the end of file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26594 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
|
| 3acbe5d4f0d6163cb761368692c830c1a4f27e31 |
07-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
This kinda sorta implements "things that have to lead a dispatch group".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26591 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
|
| 2046371e70e90d4435fcdf1b2ebeb64a2e5b2626 |
07-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add some new instructions to the classifier. With this, we correctly insert
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26590 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| 7ce64852e8fc260f8a7434217c1b57b85a70a1c8 |
07-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add some comments that describe what we model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26588 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
|
| c6644188208d4aee9a9d6c428710ec1f69837944 |
07-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
flushes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26587 91177308-0d34-0410-b5e6-96231b3b80d8
PCHazardRecognizers.cpp
PCHazardRecognizers.h
PCISelDAGToDAG.cpp
|
| 5a63c47fb5fd610a98a3425f06a683833c30693b |
07-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26585 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| bbf1c72d51a77bf54c9c684b90a78e59f0b70b2f |
06-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
implement TII::insertNoop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
PCInstrInfo.td
|
| 9601a86a644fa036168ff173d3539550b2e9206e |
05-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
implement copysign as a native op if they have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26541 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0f6ab6ff97decd0150a7cdeda600216cd050d18a |
01-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26450 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 00d18f0879fb02d90aaf27e53a8a6bab2513ab5d |
01-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26448 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 5126984b1da4bda0e93961da07e883699f1f2d57 |
01-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Compile this:
void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
PCSubtarget.cpp
EADME.txt
|
| 8c13d0a5734a2f9d2b1c3870732cafffb20e3a55 |
01-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26445 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
EADME.txt
|
| d30bf01e9064a668eaa896a3e9c79d8f0290b6a7 |
01-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Vector op lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| bf751e2d6f3779b78c9a00fb9887e1b25faa880c |
28-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCSubtarget.h
|
| f4c8575c271c70edffd48a5c23276f18a0b5900d |
28-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
remove implemented item
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26418 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 6e53ceb0d4b2dd1f886284242493ab43500e32a8 |
27-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
readme updates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26405 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 2c003e26e583e6acafca142ef93efa95a84866a1 |
24-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Add memory printing support for PPC. Input memory operands now work with
inline asms! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26365 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| e5d8861126959d01cf847b6ef280dd9ef38d33cf |
24-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Implement selection of inline asm memory operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26348 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| d0839f3071f687de505dba26a16c125b10f982ef |
23-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
PPC JIT relocation model should be DynamicNoPIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26338 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| e3f01570c172570fb2c0bacc6b8860ee6809362d |
23-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Implement the PPC inline asm "L" modifier. This allows us to compile:
long long test(long long X) {
__asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
return X;
}
to:
foo r2 r3 r2 r3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26333 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 4c1aa866578f7a358407a22fe55b454f52a24325 |
22-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Added option -relocation-model to set relocation model. Valid values include static, pic,
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelLowering.cpp
PCSubtarget.cpp
PCTargetMachine.cpp
|
| 0420f2aaf9551a10e2060d076de2fcdd7b316370 |
22-Feb-2006 |
Jim Laskey <jlaskey@mac.com> |
Coordinate activities with llvm-gcc4 and dwarf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26314 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 1efa40f6a4b561cf8f80fe018684236010645cd0 |
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
split register class handling from explicit physreg handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 4217ca8dc175f7268a4335c8406dedd901e8e631 |
22-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Updates to match change of getRegForInlineAsmConstraint prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| d2ee218b499fcd364aae7da031819b738f009cd1 |
18-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Moved PICEnabled to include/llvm/Target/TargetOptions.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26272 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelLowering.cpp
|
| 551bf3f80058a026b6a128dffd5530019e1df1b9 |
17-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| 298ebf2bd80ca415e58bbcbd9866ee58f167b620 |
16-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
If the false case is the current basic block, then this is a self loop.
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26231 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 0d7db6f79a61803fff87d12d9c75c0f54d863d10 |
14-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
If we have zero initialized data with external linkage, use .zerofill to
emit it (instead of .space), saving a bit of space in the .o file.
For example:
int foo[100];
int bar[100] = {};
when compiled with C++ or -fno-common results in shrinkage from 1160 to 360
bytes of space. The X86 backend can also do this on darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26185 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 33d5082779c0957f80253c01e10cbddfbf2825c8 |
14-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Make sure that weak functions are aligned properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26181 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 45b3976db7f20abe99035962596698008a60033f |
13-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Switch to using getCALLSEQ_START instead of using our own creation calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26142 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 789fd42320857a13ecca110b3e83a450063f5c73 |
12-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/
PowerPC/and-imm.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26136 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 7e9b26fc73425ae215fbc9c8010cb53059a93b3a |
09-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26085 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 34167215a8da717b21e44f1b834dc34d15279bf1 |
09-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change Select() from
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26067 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 418caa135640833fda641997dae657062dccf0f4 |
09-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Darwin doesn't support #APP/#NO_APP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26066 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 6f4a072e1f41fb2d0392ab818266efe8120c5a03 |
08-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Rename BSel -> PPCBSel for the benefit of doxygen users.
Move the methods out of line.
Remove unused Debug.h stuff.
Teach getNumBytesForInstruction to know the size of an inline asm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26064 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 4d73a5a204b2e9f409347102fc0701e5b68699cb |
08-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Emit the 'mr' pseudoop for easier reading.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26053 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 8d3f490991a190e26ec9aaa5c9d3c21f809666a5 |
08-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Move emails from nate into public places
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26051 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| ad3bc8d8add8204195aeb5106036eb7992541bdb |
07-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Implement getConstraintType for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26042 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 763317de1bda41581b12915b31ba06c2e16450fe |
07-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Add the simple PPC integer constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26027 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 815ef5b3dd7536e62038c091f6bf17f7badbfe5a |
06-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Change prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26022 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 984cb3773f78ed290e33e05d25a6620deec6ca04 |
06-Feb-2006 |
Jim Laskey <jlaskey@mac.com> |
We seem to have settled to __DWARF for section name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26015 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 7564e0b46d68abbd43a9910882568f4f9875af50 |
05-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Complex pattern isel code shouldn't select nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26010 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| ba2f0a9ee53512ce840aca34281e126802a125d1 |
05-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use SelectRoot() as entry of any tblgen based isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25997 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 213845367cb394237cbf10ccfba5a219bbec4781 |
05-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25984 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 7d8d5a522fb6d9d83f5d89f30fe1badf68832efd |
05-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Use the asmprinter to find out what the preferred alignment of a global is.
This patch speeds up 172.mgrid from 31.81s to 11.39s on darwin/ppc.
Many many thanks to Nate for tracking down the root cause of the issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25979 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| a6973c348bb92e672cad5b599cc4bff09c9e4b10 |
04-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove some stuff that now works
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25963 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 1541bc3a233b6a8b7e7ad0be877a3b3b45d18e11 |
03-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25944 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 33c1dab0bdb2f1a1a75405aa82b9dd9d01d76cd1 |
03-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
remove some target-indep and implemented notes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25930 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| a63fee898b36ac21ad5189929f4e630713fe3231 |
03-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Flesh out a couple of the items in the README
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25928 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| d463f7f698f98333cfa4358db203fb8106bf1e2f |
03-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25921 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 39b248b79e7842dce6c71e50c557ebaf325d55e1 |
03-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
update a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25918 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 3b478b31e297208ef2c9f74750a8a603eb3726fb |
02-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
add 64b gpr store to the possible list of isStoreToStackSlot opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25916 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 6524287c53cf727a8ef33517403fcb1bbd7adff9 |
02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
implement isStoreToStackSlot for PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25914 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
|
| 408396014742a05cad1c91949d2226169e3f9d80 |
02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 275b8846d519ac91777e6cad00b8650b252d2ed6 |
02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
new example
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25903 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 93c740bbbb47280cee38872eb58bfad70f93be66 |
02-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Update the README
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25902 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 588732748ba804e1e258df8856e20b3b73348ac3 |
01-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
add a method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25884 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 5a7efc9d4f3b1fd09873a7377bcca7f513d2ad80 |
01-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25876 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 750ac1bdfa6f09bddfd9efce1d6360dde8fa74c0 |
01-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
Fix some of the stuff in the PPC README file, and clean up legalization
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25875 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
EADME.txt
|
| 0ddc18047d7e16d1d325415fc015dc687dc0655f |
01-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
another testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25862 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| b8973bd8f50d7321635e1e07b81a880a0828d185 |
31-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Allow the specification of explicit alignments for constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25855 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ddc787dfdc75fb2d78eb3e5793ca0f417ad74fd3 |
31-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
add info about the inline asm register constraints for PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25853 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 4477590ef64796e4716f7322d8b2d1cffbaadfa1 |
31-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Codegen
bool %test(int %X) {
%Y = seteq int %X, 13
ret bool %Y
}
as
_test:
addi r2, r3, -13
cntlzw r2, r2
srwi r3, r2, 5
blr
rather than
_test:
cmpwi cr7, r3, 13
mfcr r2
rlwinm r3, r2, 31, 31, 31
blr
This has very little effect on most code, but speeds up analyzer 23% and
mason 11%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25848 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 83e64baaef3d62e4cf5b17d9900582b6849f2de9 |
31-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
example nate pointed out
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25841 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 56b6964473cb0e69a8739e6c7e20239c2f19e8f7 |
31-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
add the 'lucas' optimization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25830 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 37dd6f1b79bd888cb88ced7e5ce5a8ebc7aa44e2 |
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Functions that are lazily streamed in from the .bc file are *not* external.
This fixes llvm-test/SingleSource/UnitTests/2006-01-29-SimpleIndirectCall.c
and PR704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25793 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCISelLowering.cpp
|
| d9b55dd21ae4168d131b344d53eb19ac4468b23c |
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Now that OpActions is big enough, we can specify actions for vector types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25784 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3fd327fe7fdcc9cfdf0ecc2e069120672c37c0c9 |
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
disable this for now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25778 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ec4a0c7c6bd689572d8f432950867e6ee9d777f4 |
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Request expansion of ConstantVec nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25773 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a54aa94197d5af9a72c0de422a58e938da80b2a4 |
29-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Targets all now request ConstantFP to be legalized into TargetConstantFP.
'fpimm' in .td files is now TargetConstantFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25771 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e00ebf0acaa47a9aa8bfeba025f281432c4e9957 |
28-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in my elimination of ISD::CALL this morning. PPC now has to
provide the expansion for i64 calls itself
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25735 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 969097968c2f845caa6085abfc357ad53eb18956 |
28-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
add a note about how we should implement this FIXME from the legalizer:
// FIXME: revisit this when we have some kind of mechanism by which targets
// can decided legality of vector constants, of which there may be very
// many.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25733 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
EADME.txt
|
| eb20ed6c86837870e749cf9d6272ae596dbef303 |
28-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Add a couple more things to the readme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25724 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 281b55ebeccd3f0d723888c1bb9ec6e476f708f1 |
28-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Use PPCISD::CALL instead of ISD::CALL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25717 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| bba534dc6676fa6a91dfb4492b30faf67bd22abe |
27-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Make llvm.frame/returnaddr not crash on ppc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25710 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| ee625573b5b39b91441fc6ea23f3ba415abdc71f |
27-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 19c95507443ebd4f1cee80917d540c8bd27f8fe1 |
27-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Subtarget feature can now set any variable to any value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25678 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| cedc6f4b30c1fd5f7ad1df0b65b870e6f107e8ff |
27-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
PHI and INLINEASM are now built-in instructions provided by Target.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| b3e789ac2548a4382d0db03b573fd8a127617f8f |
26-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Set up MachineDebugInfo to scan for debug information form "llvm.db"g globals.
Global Variable information is now pulled from "llvm.dbg.globals"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25655 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 0577a22c678bd5e31047e6b8038c6917202271ee |
25-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Set SchedulingForLatency to be the default scheduling preference for all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25607 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| acc398c195a697795bff3245943d104eb19192b9 |
25-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
First part of bug 680:
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25606 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| 7558b0e80c058c148ef9f45220bbbe6bc8a146dd |
25-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Default scheduling preference is SchedulingForLatency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25603 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 52060a0e7190d7713042f18b1b949d1ae953638f |
24-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Crude Dwarf global variable debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25569 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 2c2c6c61f100bc7c3df873b11203fcea1b5e18fe |
23-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Add explicit #includes of <iostream>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25515 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
|
| 86a5484079abc8a20f24066aaf3f5efcccebb673 |
22-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Add explicit #includes of <iostream>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25509 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| bc1c2154534e8469ac5258ea145e3ce2ccd7ee07 |
21-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
trivial formatting improvement: don't insert extra blank lines between .comm
vars.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25492 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 3cda14ff3e70a5124db396645b108be51ebb31af |
19-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25439 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| bc38dbfd9b88c021378c647f6c169f4f76a775da |
18-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Don't assert on 'select_cc SETUO'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25423 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c16257f05391b8aeccef62d6b543f1cb5a8185fe |
18-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
fix out of date comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25422 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.h
|
| e44b2d16ee088c44ebbe6f21a2af8b5321b68e48 |
18-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fix Regression/CodeGen/PowerPC/2006-01-18-InvalidBranchOpcodeAssert.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25421 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.h
|
| e719a7c40b58a382144212828bfecd4e64210b92 |
18-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Added minimum Dwarf aranges. Cleaned up some section headers. Line number
support now works in gdb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25417 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 19ef4efa70b29aa2ef2d68a60e9bdfa7a4b47d89 |
17-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Add frame work for additional dwarf sections. Comments will improve as code
is added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25410 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 063e765345fd49df0f53b807e57ada7c2ded7e16 |
17-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Adding basic support for Dwarf line number debug information.
I promise to keep future commits smaller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25396 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 98fbc2fd1b4976923a81accff6ec19afdd7c42ab |
16-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
add notes from my *other* email acct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25362 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 1db4b4f5c4229d69ca7a3125d59cb20676795858 |
16-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
transfer some notes from my email to somewhere useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25361 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| b22c08b8082cdf0026a8d429f37e8c16a1ca8caf |
15-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Use the default impl of DYNAMIC_STACKALLOC, allowing us to delete some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25334 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| d88fc03602947b5baa35c8b09fe8bcfa2b4a03c1 |
14-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
bswap implementation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25312 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6283760cd13fa3f41c7f6462456661ea54ded980 |
14-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove some redundant stuff out of the readme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25308 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| cadd7420f9e705735b794e61cd24aab16ce2fa18 |
13-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
implement stacksave/stackrestore on PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25277 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| b99329e8a0ec3b5a0004dd649e3546939f5c31e7 |
13-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
expand unsupported stacksave/stackrestore nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25272 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a613d267ea9e7f64336d9c3605b5361d901bf452 |
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
ahem :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25239 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| e699ef56186ec4aec379a98c646f263bdaa61624 |
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
these cases are autogenerated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25238 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 17e82d2858f0c003b7fcfaf7c025ca3d0aaa7a88 |
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25237 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 05f1fe8d448013531f86a24b5173fe57330291ef |
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Goodbye PPC pattern isel. You have served us well, but it is now time for
you to ride off into the sunset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25236 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCISelPattern.cpp
PCTargetMachine.cpp
|
| ba625726a1fc3b18b6a5386978d33f1943f5df84 |
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fix an off-by-one error that Nate's eagle eyes caught
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25231 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| c6d48d36a349f593aab2194c141a1e24da1aec3e |
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Use the auto-insert BuildMI constructor to avoid an explicit insert. No
functionality change, just code cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25230 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 64da172b1435d132ce867dcd5c652577664b55a3 |
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
If a function has a non-zero sized frame, use an add to adjust the stack
pointer in the epilog, not a load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25229 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 35ef913ec21de0f4f1b39c811b4335438717a9b8 |
11-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Add bswap, rotl, and rotr nodes
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25222 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCInstrInfo.td
|
| a243db8c41bd8ace6e002c9e1fdcdc7256ebf677 |
11-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fix calls that need to store values in stack slots, to not copy the stack
pointer. This allows us to emit stuff like this:
li r10, 0
stw r10, 56(r1)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
instead of this:
or r2, r1, r1 ;; Extraneous copy.
li r10, 0
stw r10, 56(r2)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
wowness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25221 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 413b979fe4b3482f347fc7b613d7dcda81e34874 |
11-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Dead FP arguments still use an incoming FP reg. This fixes
Regression/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll, which was
distilled from a miscompilation in 252.eon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25217 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 49dddb273dd5aa0e30d70fdab1549c5f766beaf7 |
10-Jan-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove a comment that no longer applies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25167 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| da6d20f0c15205923cb2c3ef4bf9b5d77de88881 |
10-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Give PPCISD:: nodes legible names in dumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25166 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
|
| e5cf122869fcace7dbdc40b5a351f76f338cd35b |
10-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
add ret void support back
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25164 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6da8d99f70826552b3a4e7bd5d1376881574b4b1 |
09-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
hasInFlag, hasOutFlag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25155 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 5fe0e28650dd49f290fce2b80c0052fbc12d2385 |
07-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the PPC JIT failures last night, which were due to mishandling of linkonce globals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25141 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| a35ef6350defdc09eb912c52603cffa6afbd78e2 |
06-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
linkonce symbols have an extra indirection, just like weak ones do. This fixes
Prolangs-C++/family and Prolangs-C++/primes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25119 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c9a5ef524a9f461717bbf647b2d3da061aed720d |
05-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a compile crash building MultiSource/Applications/d with the new front-end.
The PPC backend was generating random shift counts in this case, due to an
uninitialized variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25114 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| e0bce71c42a021d897b51425dab16841a0ebc5bd |
05-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Had expand logic backward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25105 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| abf6d1784b2d4bbcb7d20ab64881f77d755059f6 |
05-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Added initial support for DEBUG_LABEL allowing debug specific labels to be
inserted in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25104 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelLowering.cpp
PCInstrInfo.td
|
| b2efb853f00d45b1c8d57f92acd0028fbdeffda6 |
04-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Applied some recommend changes from sabre. The dominate one beginning "let the
pass manager do it's thing." Fixes crash when compiling -g files and suppresses
dwarf statements if no debug info is present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25100 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 5bf6f25b4a888afaf3e37acd18c43186d45cac2e |
04-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Add unique id to debug location for debug label use (work in progress.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25096 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| a7cea6f599418a579ab5ce66413fba7efa8bf581 |
04-Jan-2006 |
Jim Laskey <jlaskey@mac.com> |
Tie dwarf generation to darwin assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25093 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetMachine.cpp
|
| b73628b5abee86ef76e1ed8c7f9eaed85bea61a8 |
30-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support for generating v4i32 altivec code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25046 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 1166bf3f4ca4d2bf9509ec2f243eb9c41360364b |
30-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove a fixme
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25045 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2b4ea795a23ff9d900b9e1f26c92975ef78db1b6 |
26-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Added field noResults to Instruction.
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 50fb3c498601a84e0d82d7bab3e28c820dd64598 |
24-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix one of the things in the todo file, and get a bit closer to folding
constant offsets from statics into the address arithmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24999 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
EADME.txt
|
| 171049d10f71fdeffdfd9592243d7af40db86c71 |
23-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24997 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 53e884587bd4b56c14dc39600eb655e77ae7b905 |
23-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
make sure bit_converts are expanded
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24978 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 1b95e0ba92a08dd90c9f06fe175d7a62b055b5f3 |
23-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Simplify some code by using BIT_CONVERT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24974 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 0fcd40f501d99ce50b23f67e578a37f0943dec36 |
22-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24965 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| cec26fc3bf1f9d177a4befabd278410f0cb7d2b8 |
22-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
fix handling of weak linkage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24964 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 39706e68a5a645d85d0f24c2e43d67cb6024829d |
22-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
move some random notes out of my email into someplace useful
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24956 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 5bc4da48933a097924c4b80c9fa1cdb133978a54 |
22-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Bye bye HACKTROCITY.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24935 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 6a3bfd97f287ba46f532b304e90dded147825797 |
20-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Flip the meaning of FPContractions to reflect Requires<[]> change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24884 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 9e4dd9dfc97f3930f58ca6e47bebbd8eb5cdd8a1 |
20-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Pattern-match return. Includes gross hack!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24874 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrFormats.td
PCInstrInfo.td
PCRegisterInfo.td
|
| 88276b887c426cf5d998b705a14663bfa38f8efd |
20-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix a couple of the FIXMEs, thanks to suggestion from Chris. This allows
us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register. This also requires some asm printer work
to satisfy the darwin assembler.
For
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
We now produce:
_foo:
lvx v0, 0, r3
vaddfp v0, v0, v0
stvx v0, 0, r3
blr
Instead of:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24872 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
|
| 7fd1edd32e9a6782dbcd00818bbdaf82f14284a1 |
20-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Convert load/store over to being pattern matched
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24871 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.td
|
| cf198eca97af9a939decdc4866398bcc7b370ac6 |
18-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
This is handled by the autogen'd code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24834 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| f5395cee6a24699a016b2e379cf4804b09ce5030 |
16-Dec-2005 |
Jim Laskey <jlaskey@mac.com> |
Added source file/line correspondence for dwarf (PowerPC only at this point.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24748 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstrInfo.td
|
| d9e0ba49a4cf288eee9b58857b92a89f5a141c4b |
16-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Weak and linkonce global vars should still have a .globl emitted for them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24747 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| f492f9901aa9e6c5d1005f0c244be233d296d046 |
16-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Add a second vector type to the VRRC register class, and fix some patterns
so that tablegen can infer all types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24746 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
PCRegisterInfo.td
|
| a637c32e381316da47285961111e1793c542cc15 |
16-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Update the darwin handling of linkonce & weak functions and GV stubs. This
should work in all permutations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24728 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| b5f8e62d712c94aa5324d8816f6ca2c47c5ce86b |
14-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove a now unused statistic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24720 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| a07da92624219599e6569460b3b56b49d60a4b46 |
14-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Use the new predicate support that Evan Cheng added to remove some code
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24719 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| 8c75ef9228cfa5dc98adbfe011e87ca2fc65cd0c |
14-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24716 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 3fb6877cb4d49883726850e0bc6ca6550000abdf |
14-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support for fmul node of type v4f32.
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24701 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 993aeb2ed93f99faf1438f1b67cd922989306828 |
13-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Prepare support for AltiVec multiply, divide, and sqrt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24700 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.h
PCInstrInfo.td
|
| d1239b7c69e3c8f36d21c30d5df923cfeb96583e |
13-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Use the shared asmprinter code for printing special llvm globals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24695 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| deea416570f31a82081f1bbbc65f0c06d44462bf |
13-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
reindent a loop, unswitch a loop. No functionality changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24692 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| d717b19933f1e99617205c5f0c0340e6c9cccbfc |
11-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Remove type casts that are no longer needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24661 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstrInfo.td
|
| e54645a6fb9887b3eccf2eade24531165f84b0ed |
11-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Fix the JIT failures from last night.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24659 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 28a6b02626c29b1fe9bb16c14c193549fab4cab8 |
10-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support for TargetConstantPool nodes to the dag isel emitter, and use
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24657 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCInstrInfo.td
|
| 0976122abcea58fc9be081a431bd8390cb00c367 |
10-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support patterns to many load and store instructions which will
hopefully use patterns in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24651 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 646f7afb797630020f02c6f552c6c5c8d7e73ad6 |
09-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Teach the PPC backend about the ctor and dtor list when not using __main and
linking the entire program into one bc file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24645 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 62c08dd4a1a1e8755ec6cc7cd458fa532c8b5c85 |
08-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Add another important case we miss
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24639 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 85961d5ec126bbc0c111d52dd7361d5159265ca5 |
06-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Silence another annoying GCC warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24627 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 4172b10ca1adfc1026428e5f522aaab98bd939ad |
06-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Use new PPC-specific nodes to represent shifts which require the 6-bit
amount handling that PPC provides. These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits. This fixes a miscompilation of crafty with
the new front-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24615 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| bd05982b487e1e672a6c6316fff6b3260a78b9c7 |
05-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Add some explicit type casts so that tblgen knows the type of the shift
amount, which is not necessarily the same as the type being shifted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24594 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| bead6612a5591003b84df52d8656a1fee54db82c |
04-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
The basic fneg cases are already autogen'd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24592 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 937a79dbe3d71320e2bda8050541080f04412f14 |
04-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen
improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24591 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| 60a4ab2d5c5e0e2647590882d77fe5d21d0c4990 |
04-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Finish moving uncond br over to .td file, remove from .cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24590 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| 1e48478557587d3931d5e8277fe79719d78ab245 |
04-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Define BR in the .td file now that Evan made tblgen smarter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24589 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 05f56a529c0c9ac37b41c7472ceb7d2e95feff1e |
01-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Make sure these get added into the codegenmap when appropriate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24566 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 6510b22cec7de4f0acc9965ec24c3668a6a8a87e |
01-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 5dfc55c304b051a33f4ee30a2e1b4bca85ddb75e |
01-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Cosmetic change, better reflects actual values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24562 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| db1cb2b3a15301c000c2bc5a99d5807510b2a456 |
01-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a regression caused by a patch earlier today
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24561 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| c121e33e35b2e7292e6d99d8db91f73b84269e36 |
01-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Use a getCopyToReg() variant to generate a flaggy CopyToReg node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24558 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 71d3d50b4a2182ce34d383c00a6f0e6231685cbf |
30-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
SelectNodeTo now returns N. Use it instead of return N directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24549 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 80720a921987e36c83236d375919172afd20d79c |
30-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24547 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 391c5d231a1d251ea9dc3d8745547c957db94ca4 |
30-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24541 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| f43a3ca26d7bf431be5cdfb5963350a158e840af |
30-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
First chunk of actually generating vector code for packed types. These
changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
for this llvm:
void %foo(<4 x float>* %a) {
entry:
%tmp1 = load <4 x float>* %a
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float>* %a
ret void
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24534 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 7ac8e6b6a85525e81a39d2a48c40b3b652583902 |
29-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Represent the encoding of the SPR instructions as they actually are, so
that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24521 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 425a96971f0b0298222a51b5692aacaa9229dce3 |
29-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Hook up one type, v4f32, to the VR RegisterClass for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24517 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 9b14f66320d18ea194122a0786c7ea9446e1740c |
29-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Add the remainder of the AltiVec 4 x float instructions. Further
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24516 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| f73bae1b73211c77238f64029ee2bec7ce90bba2 |
29-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
No targets support line number info yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24513 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6a648614e88586e85a36ceb5c1d3b84e4f55b458 |
29-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Add the majority of the vector machien value types we expect to support,
and make a few changes to the legalization machinery to support more than
16 types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24511 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 5ee16ea41792e38ce9240c0bd7b165cefb752612 |
29-Nov-2005 |
Evan Cheng <evan.cheng@apple.com> |
Fixed a comment bug:
createPPCPatternInstructionSelector -> createPPCISelPattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24510 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| fd5df2b2030ab13e0ada031fc10f52d27c8595b4 |
29-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
don't say this is i128, because it isn't yet. Hopefully nate will change
this to be something sane, but in the mean time it is unused, so safe to
make something bogus.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24504 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 01595c52b32b8e40b87dd9d36753f8e972ab6f74 |
26-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Small tweaks noticed while on the plane.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24492 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
PCRegisterInfo.td
|
| e4f17a5f9b6b5c94dccfd14babcf58d9d5dab4e8 |
23-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24489 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
PCRegisterInfo.td
|
| c569e6108adf701bc51635b35cb18bd35a843d18 |
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Use generic constant pool emission code in the AsmPrinter class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24465 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 0745536c0006f291c3fb98bdd71aa19130a561fd |
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Use the FunctionNumber provided by the AsmPrinter class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24462 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 6d5a4f6a8ed7347bbe4880ac3f3bb87d62836e01 |
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Use CommentString where possible, fix a bug where aix mode wouldn't assemble
due to basic blocks being misnamed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24459 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| ef658741519db6e7091329c3fe57a771f67c237a |
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
unify the darwin and aix constant pool printers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24458 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 8b8b9515d6b18f9fdd0303a6ce603f5b5997ef50 |
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Adjust to capitalized AsmPrinter method names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24456 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 7f9ccde91eb1532af2571f0f001e4d919fd61410 |
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
use PrivateGlobalPrefix for basic blocks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24453 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| f6163a00793b4bae585d7b77a10faf3f51eb431b |
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
This is now implemented in common codegen code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24446 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| f55366e3c269505b2ecb0173a2ece59acf1b5df8 |
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
set PrivateGlobalPrefix on darwin, use it when printing out CP references
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24441 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 9542f9714e4b4b1c5cf7b0faef40c67af1f1e0bb |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
only use dyld stubs if not in ppc-static mode. This completes support for
non-static codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24403 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 9ba13e4aeff453cdc8ed26fb927ec65dd44625b4 |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
refactor call operand handling to eliminate special cases from printOp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24401 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 3e7f86a037181bf8804600c1000da2dc8a2f2f70 |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
disentangle call operands from branch operands a bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24400 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstrInfo.td
|
| 1d05cb47a94bb5639b690519c6027447791e06f7 |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
add an option to generate completely non-pic code, corresponding to what
gcc -static produces on PPC. This is used for building kexts and other things.
With this, materializing the address of a global looks like:
lis r2, ha16(L_H$non_lazy_ptr)
la r3, lo16(L_H$non_lazy_ptr)(r2)
we're still emitting stubs for functions, which is wrong. That is next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24399 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCISelLowering.cpp
PCSubtarget.cpp
|
| 1df747867cc1e7d37447bc3072e55e380c6720e8 |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a bug that resistor on IRC hit where we tried to create token factor
nodes of load results, not of their chain results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24398 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 3eef4e377cad01d5fbef2d67a12fe96171e0d860 |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Enable global address legalization, fixing a todo and allowing the removal
of some code. This exposes the implicit load from the stubs to the DAG, allowing
them to be optimized by the dag combiner. It also moves darwin specific stuff
out of the isel into the legalizer, and allows more to be moved to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24397 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
EADME.txt
|
| 4f0f86de5f183b09d07b17d1f940bd3e298abfcd |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Teach the selector to fold lo(g) into load instruction immediate fields
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24396 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 490ad0809767499519602d4aaf6ba5548bbef215 |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Generate LA and ADDIS when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24395 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 1566613ca4aecaf0143b41c97ae3b3be80660c56 |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Use the right accessor to create this node
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24394 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 860e8862c1fbd3b261da4a64a8c0096f9f373681 |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Add an initial hack at legalizing GlobalAddress into the appropriate nodes
on Darwin to remove smarts from the isel. This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file. However, we can currently emit stuff like
this: :)
li r2, lo16(L_x$non_lazy_ptr)
lis r3, ha16(L_x$non_lazy_ptr)
lwzx r2, r3, r2
The obvious improvements will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24390 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| bae5b3c1c6e1009898f66211a6fd466c1e809ccc |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
LI could theoretically be used for the lo-part of a global address, just like
lis can be used for the high part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24388 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 2823b3e70ee7a5ed7482c45c503659a16a879a61 |
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
When lowering direct calls, lower them to use a targetglobaladress directly
instead of a globaladdress. This has no effect on the generated code at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24386 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| 422b0cee7a32636303398d8788f98a59bf15381c |
16-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Patch to clean up function call pseudos and support the BLA instruction,
which branches to an absolute address. This is required to support objc
direct dispatch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24370 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCISelPattern.cpp
PCInstrInfo.td
|
| 2c3d3d2a59e8c241de43a7c50272ab6443794a19 |
15-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Make sure to use SwitchSection to switch sections so that we don't accidentally emit
functions into the .const section. Whoops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24363 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| ced704ba608ce0675bdba1677b612288b6e0956f |
14-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Handle globals with explicit alignment requests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24355 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| ac7fd7fcc67948475c89f033b90d94b666722dd7 |
14-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Teach the PPC asmwriter to honor globals with explicit section requests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24353 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 5684598f3fbebc7629e7fb2c2b5e120a99597c46 |
10-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Make BB and CPI labels use the function number, not the function name as a
uniquing id. This makes things happy when the function name is quoted,
preventing labels like LBB"foo"_2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24295 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 85eac0d9411c0a2005b2f4111528f276f672fee3 |
10-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Darwin supports quoted labels. This implements:
test/Regression/CodeGen/PowerPC/darwin-labels.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24287 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 3459bfbc395914ec895aef13123f3b180242577f |
10-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Make the aix asm printer interface properly with the parent class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24274 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| df2e425f2a3b64eb17be927539cd39cb1f1c5f77 |
08-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Add a new option to indicate we want the code generator to emit code quickly,
not spending tons of time microoptimizing it. This is useful for an -O0
style of build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24235 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| ae232e7a1055033436370c0b3aecf054fa44d5e7 |
06-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Add the necessary support to the ISel to allow targets to codegen the new
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack. Support for
arbitrarily aligned dynamic allocas coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24224 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| ae4664a9f2da955c9d2a3f38b28f0a4395851ace |
05-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
add a case Nate sent me
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24195 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 6cee630070b1a7183ed56a8404e812629f5ca538 |
01-Nov-2005 |
Jim Laskey <jlaskey@mac.com> |
Allow itineraries to be passed through the Target Machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24139 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 5b0ac99c9690d7534ade82848c207e202883831b |
01-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Add a flag to enable a darwin linker optimization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24130 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| bb69e39b5b8ddf7243e2b77cebe2f9f23ba819b2 |
31-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Make constant pool entries use private labels. This is important when you're
not compiling a whole program at a time :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24129 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| b685af3e60150f5bf513db161d982fcb8654c7b1 |
30-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
This is implemented
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24107 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 167f1e265161bfebb0370e7e1e0559e50bdd9234 |
29-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
New case to handle someday
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24075 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 7d7b96746c1264bd617783860a4a5ab289208fb0 |
29-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Don't emit "32" for unordered comparison
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24073 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| ed048c067dc7bf342b2947b4de39e915dcbd2bf0 |
28-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
add a hack to get code with ordered comparisons working. This hack is
tracked as PR642
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24068 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 6df2507121507c24d7155605c343e467e0106c07 |
28-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
add support for branch on ordered/unordered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24067 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| f02a916d82e35998c52b1eba6601049f8eee4fac |
28-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Do not globalize internal symbols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24064 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 01959105583ee04bd9c131db7174b6108177caf3 |
28-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
a bad case for bitfield insert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24051 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 2cbc207c76f10716b61c466f56b5b9fccbb80f4e |
26-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Typo made worse x 2 - take 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24018 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 85fd97dc8810ac16197594304f9f985a13466d19 |
26-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Fix an assert compiling MallocBench/gs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24017 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ff2fcee846addcb64b6fad0efa339949d26b7390 |
26-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Typo x 2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24016 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 581a8f79bc1ac3cbe5d621f0b4a0252ab2890bc1 |
26-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Give full control of subtarget features over to table generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24013 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
|
| f0c2be4d2b6f5b04746efae88e8bc642a864361e |
26-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Add attribute name and type to SubtargetFeatures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24012 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| 5cd61ce1bea4a1886624825607bfed150ec6b4eb |
26-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Add a note about some bitfield stuff we could be doing better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23994 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| ae749a9bb5aa4e350041e275ea26f4cc52197392 |
26-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Correctly Expand or Promote FP_TO_UINT based on the capabilities of the
machine. This allows us to generate great code for i32 FP_TO_UINT now on
targets with 64 bit extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23993 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 6e61ca6fa709edc76594602da9c78c22ba2106ea |
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
autogen undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23991 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| 3075a4e94d820402159d81896a7e5fe89a459650 |
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Allow pseudos to have patterns, no functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23988 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 9c73f095bb984fc9ae295904a8bcbcec19313a48 |
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Autogen fsel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23987 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| eb255f2b83cd87902309df1ce590f02178aabc65 |
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Expose the fextend on the DAG instead of doing it in the matcher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23986 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e6115b370ad518fa5dfbd33b216f147ab3703db7 |
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Autogen a few new ppc-specific nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23985 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| 8ecedbe2c391dd399b8b0205484f9053256f90d2 |
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
The dag isel generator generates this now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23984 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 99ea9da87242fed79fd617d79c6efb630a2db37d |
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Be a bit more paranoid about calling SelectNodeTo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23982 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 3393e80a06bbbfd9988deafae20c614ebbd5b8e6 |
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a couple of minor bugs. The first fixes povray, the second fixes things
if the dag combiner isn't run
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23981 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 34bd5d5d876212611d8b66a18f4c8604b342c6eb |
25-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Preparation of supporting scheduling info. Need to find info based on selected
CPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23974 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 2224dcc88c3f01c707cc7dfdb085975340bc0127 |
24-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Simplify this, matching changes in the tblgen emitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23909 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| aa38be17c89fbc059c51f083a9161e4e440a6dd5 |
24-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
mark this as beta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23906 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| c8d28890f6c8b769ad8160fa8a701de31f70cfad |
24-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
rearrange things a bit so that instructions can use subtarget features in the
future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23902 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| 2e1f823aed93249afba72e46ce8a2997bd2b97cf |
23-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
improve -help output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23892 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| 5476b9bfced0413cc576bf49f539193c702b9574 |
22-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's
to group appropriately and provide cues to maintainers that the lists don't
need to be ordered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23880 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| 4245f1d79068e589f8db5972917b2e393b60cc7d |
22-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
64-bit reg support should not be enabled by default, as support isn't complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23878 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
|
| dabb8291e840053a3d1a2a550d157e9c5c3c38c9 |
21-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Instead of aborting if not a case we can handle specially, break out and
let the generic code handle it. This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc.
also, reindent this code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23874 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| f5fc2cbd6bcf80cc34c8114007f31d8ffd1d138d |
21-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Plugin new subtarget backend into the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23870 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
PC.td
PCSubtarget.cpp
|
| ae1641c39fe9886e4b22a5d79b5a25b4041b62bd |
21-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Match rotate. This does actually match the rotates in an rc5 cipher, but I
haven't seen it fire on our testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23863 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 405e3ecb563f21e7b4ee30f0de57821f3eb91219 |
21-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Invert the TargetLowering flag that controls divide by consant expansion.
Add a new flag to TargetLowering indicating if the target has really cheap
signed division by powers of two, make ppc use it. This will probably go
away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23853 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
|
| 12a923408cae354c942e5b5dc8b36b2e063fad99 |
20-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Add some more patterns for i64 on ppc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23842 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6957523b9ddc6e85aede47a107502043fd1a3b2d |
20-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Move the target constant divide optimization up into the dag combiner, so
that the nodes can be folded with other nodes, and we can not duplicate
code in every backend. Alpha will probably want this too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23835 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelPattern.cpp
|
| 538421411a4a0a070bbd789e88657689ca504dbe |
19-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Added InstrSchedClass to each of the PowerPC Instructions.
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCInstrFormats.td
PCInstrInfo.td
PCSchedule.td
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
|
| 2d5aff761d32b7f4fddc982e9444d20af48f080b |
19-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Write patterns for the various shl and srl patterns that don't involve
doing something clever.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23824 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrFormats.td
PCInstrInfo.td
|
| 0de8796e68d49d57f4135aa40a1c72b03aa8ecca |
19-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Push processor descriptions to the top of target and add command line info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23820 91177308-0d34-0410-b5e6-96231b3b80d8
PCSchedule.td
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
|
| f6cd147471fb9a89661e2093731d6d40d4f41c7c |
19-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
now that tblgen is smarter, use integers directly. This should help Andrew too
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23818 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 14c09b81ead8fe8b754fca2d0a8237cb810b37d6 |
19-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
teach ppc backend these are copies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23813 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 8be1fa5dc5c66d74581a4ec4fb9920e4535ec600 |
19-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Convert these cases to patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23811 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| 8d948323942cf031e9d1c55bda2bff9d4db4cf42 |
19-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Woo, it kinda works. We now generate this atrociously bad, but correct,
code for long long foo(long long a, long long b) { return a + b; }
_foo:
or r2, r3, r3
or r3, r4, r4
or r4, r5, r5
or r5, r6, r6
rldicr r2, r2, 32, 31
rldicl r3, r3, 0, 32
rldicr r4, r4, 32, 31
rldicl r5, r5, 0, 32
or r2, r3, r2
or r3, r5, r4
add r4, r3, r2
rldicl r2, r4, 32, 32
or r4, r4, r4
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23809 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
|
| e5468305a0f46161ff4bb0c5a9e0a6988e33711a |
19-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
apply some tblgen majik to simplify the X register definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23805 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| da32c9eed6743c29d219a5c3cb13788853f18016 |
19-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Make a new reg class for 64 bit regs that aliases the 32 bit regs. This
will have to tide us over until we get real subreg support, but it prevents
the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor.
Add some initial support for TRUNCATE and ANY_EXTEND, but they don't
currently work due to issues with ScheduleDAG. Something wll have to be
figured out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23803 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCInstrInfo.td
PCRegisterInfo.td
|
| 4a95945fa5aa431110f50092f4a45d24772a553b |
19-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Add the ability to lower return instructions to TargetLowering. This
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23802 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
|
| 21f587ca243c2265e9b8aa81481f9085cd0e7b68 |
18-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Simple edits; remove unimplimented cases and clarify long haul SLU cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23788 91177308-0d34-0410-b5e6-96231b3b80d8
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
|
| 841d12d9ac489ec33d933af96d77dd4fc2a4cee2 |
18-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Fix the JIT encoding of LWA, LD, STD, and STDU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23787 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 076866c50f6b6c45271285eb268b585b00bed9dc |
18-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Checking in first round of scheduling tablegen files. Not tied in as yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23786 91177308-0d34-0410-b5e6-96231b3b80d8
PCSchedule.td
PCScheduleG3.td
PCScheduleG4.td
PCScheduleG4Plus.td
PCScheduleG5.td
|
| 3d8df55fed4b241715cdf5ebae07c45faf48646e |
18-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
add a case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23785 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 9d2b817fcbad2ee615be323c38f1ed66d81964dc |
18-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Do the right thing and enable 64 bit regs under the control of a subtarget
option. Currently the only way to enable this is to specify the
64bitregs mattr flag. It is never enabled by default on any config yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23779 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCSubtarget.cpp
PCSubtarget.h
|
| 1d9d7427c4a4e3c7bdcfd1f725447f355e509c20 |
18-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
purely mechanical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelPattern.cpp
PCInstrInfo.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
PCRegisterInfo.td
PCTargetMachine.cpp
|
| 21e463b2bf864671a87ebe386cb100ef9349a540 |
16-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
More PPC32 -> PPC changes, as well as merging some classes that were
redundant after the change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCFrameInfo.h
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCISelPattern.cpp
PCInstrBuilder.h
PCInstrInfo.cpp
PCInstrInfo.h
PCJITInfo.cpp
PCJITInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
PCRelocations.h
PCSubtarget.h
PCTargetMachine.cpp
PCTargetMachine.h
EADME.txt
|
| 4cb5a1b8967828447e525fb9f593953f5f928bdc |
16-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Remove some dead code: the ORI/ORIS cases are autogen'd. This makes
SelectIntImmediateExpr dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23753 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| de123822e5cc9a7d09b12166439cfd35a6c9ed62 |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
prune #includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23752 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCTargetMachine.h
|
| 75c9f6737080af3e0c4a772f9c314f1a6fa2c91d |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
These instructions are now autogenerated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23751 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| e0b2e6372f0bd3824ba761ddf38fc0da6ab080cc |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Add a pattern for FSQRTS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23750 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 651dea74f6a362d30bc61fd0b549da7707af5bf8 |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23749 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| d242419e17cb6d97c7e3714aa8d768fa4235ef42 |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
remove broken SRA/rlwimi case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23746 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 16e71f2f70811c69c56052dd146324fe20e31db5 |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PPC32*.h to PPC*.h
This completes the grand PPC file renaming
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelPattern.cpp
PCInstrInfo.cpp
PCInstrInfo.h
PCJITInfo.cpp
PCRegisterInfo.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| b9459b731a0b6345d1e14083fcfa6508646ba81d |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Merge PPCJITInfo.h and PPC32JITInfo.h. Note that the PowerPCJITInfo
and PPC32JITInfo classes should be merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23744 91177308-0d34-0410-b5e6-96231b3b80d8
PC32JITInfo.h
PCJITInfo.cpp
PCJITInfo.h
PCTargetMachine.cpp
PCTargetMachine.h
|
| 2668959b8879097db368aec7d76c455260abc75b |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PowerPC*.h to PPC*.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
PC32JITInfo.h
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCFrameInfo.h
PCISelDAGToDAG.cpp
PCISelLowering.h
PCISelPattern.cpp
PCInstrInfo.cpp
PCInstrInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
PCSubtarget.cpp
PCTargetMachine.cpp
PCTargetMachine.h
|
| 26bd0d48a164c419462133270e3ec1c2401a34d7 |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PowerPCInstrBuilder.h -> PPC*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23742 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCISelPattern.cpp
PCRegisterInfo.cpp
|
| ec4b73cb09723a65024c207b5ac3305c3b64b949 |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Nuke the PowerPCTargetMachine.h header. Note that the PowerPCTargetMachine
still should be merged into the PPC32TargetMachine class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23741 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCTargetMachine.cpp
PCTargetMachine.h
owerPCTargetMachine.h
|
| f379997adccb0fd187c1517181e894aa4d35933a |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PowerPC*.td -> PPC*.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23740 91177308-0d34-0410-b5e6-96231b3b80d8
PC.td
PCInstrInfo.td
|
| f1ed100bc467db710fba63716fd5080622981fa4 |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
These are dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23739 91177308-0d34-0410-b5e6-96231b3b80d8
PC32.td
owerPC.td
|
| 4c7b43b43fdf943c7298718e15ab5d6dfe345be7 |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
PC.h
PC.td
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCInstrInfo.cpp
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| e87bc1f3a841d47b037ba05a5e8350a5f17a7c1e |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Like the comment says...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23737 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 617742b1b8b7fbb07b4ab5db7c292bff78d709f6 |
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitions
from the .td file that correspond to it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23736 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCISelPattern.cpp
PCInstrFormats.td
PCInstrInfo.h
owerPCInstrInfo.h
|
| e0de44adba002479966943ab431f05f9384fafdd |
14-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove an unnecsesary file. PPC32 and PPC64 share architected registers.
We will decide with subtarget support whether we ever use an i64 register
class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23734 91177308-0d34-0410-b5e6-96231b3b80d8
PC32.td
PC32RegisterInfo.td
PCRegisterInfo.td
owerPC.td
|
| 3f31d4304cab178da207cbb795d72274ff7ecdd9 |
14-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
These are now autogenerated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23731 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 7cb6491a0deff3f6b14faf20cf9bff8256219965 |
14-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Add patterns for FP round/extend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23727 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 7b1fe15de0f7a8d2fa89f98172de0350107c48c2 |
10-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
These definitions have been moved to common code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23681 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 65a419a1045972729f91f82a378b7f4b7f6a2be5 |
09-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Disable formation of rlwinm instructions from SRA bases. This fixes
the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23670 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 7d47a61496fc4c1f14aca192ec8055fcd633b86b |
08-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove another unused file. Preparing for the great "enable i64 on ppc32"
merge, and using subtarget info for ptr size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23668 91177308-0d34-0410-b5e6-96231b3b80d8
PC64.td
|
| 02f77d1e8357c0abe3fc51b421cb6c0be006f3a0 |
08-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove a file that is no longer used
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23666 91177308-0d34-0410-b5e6-96231b3b80d8
PC64RegisterInfo.td
|
| cf01a70550a25af39f979eb36a9e95aadcb12e00 |
08-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
When preselecting, favor things that have low depth to select first. This
is faster and uses less stack space. This reduces our stack requirement
enough to compile sixtrack, and though it's a hack, should be enough until
we switch to iterative isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23664 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| eb5d47d99db0d9e4fc11f136fbacbd507c71a4c2 |
07-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a CQ regression from my patch to split F32/F64 into seperate register
classes on PPC. We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced. This fixes Regression/CodeGen/PowerPC/fpcopy.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23654 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 6a16f6a14f344eb49a218b3fe159858e95d73e94 |
06-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Pull out Call, reducing stack frame size from 6032 bytes to 5184 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23650 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 222adac30a642b5ea4a916eb3e97d8d95eb32bea |
06-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Pull out setcc, this reduces stack frame size from 7520 to 6032 bytes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23649 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2b63e4c5e2281ebc5575be3339d311d34f850b3b |
06-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Pull two more methods out, reducing stack frame size from 8224 -> 7520 bytes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23648 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| bd937b98f48cac17bd3d5102b2182943b97f8c28 |
06-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Add a recursive-iterative hybrid stage to attempt to reduce stack space, this
helps but not enough.
Start pulling cases out of PPC32DAGToDAGISel::Select. With GCC 4, this function
required 8512 bytes of stack space for each invocation (GCC 3 required less
than 700 bytes). Pulling this first function out gets us down to 8224. More
to come :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23647 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 8ca02914e53b953e880f3d9eec303c2b2fcd9150 |
03-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Speed up the asm printer a lot by not printing formatted LLVM asm output
for globals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23608 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| dff06f4348878838eb9edc7414dec7c485aec3c3 |
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
add patterns for float binops and fma ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23592 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 43f07a4bbcac695c51def1d0bcd9c9ddb9e6a94d |
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
another solution to the fsel issue. Instead of having 4 variants, just force
the comparison to be 64-bits. This is fine because extensions from float
to double are free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23589 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelPattern.cpp
PCInstrInfo.td
|
| 867940d1b738504a3186276542e94f088821c7f3 |
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
fsel can take a different FP type for the comparison and for the result. As such
split the FSEL family into 4 things instead of just two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23588 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelPattern.cpp
PCInstrInfo.td
|
| 7c0d664c2118d1c5da50b137856d4a6b1c962ec3 |
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
fix an f32/f64 type mismatch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23587 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| ca0a4778a8e3036df7e51ed375cc867e6bf024bd |
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Minor tweak to the branch selector. When emitting a two-way branch, and if
we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch. For example, emit this:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
ble cr0, LBBl29_z__44
b LBBl29_z__48 *** NOT PART OF LOOP
Instead of:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
bgt cr0, LBBl29_z__48 *** PART OF LOOP!
b LBBl29_z__44
The former sequence has one fewer dispatch group for the loop body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23582 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| b91956e7f80141c198d3348f06164b6990913233 |
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
like the comment says, enable this
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23581 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 2c1760f636df659df8fcbc91055c0afd970f16c8 |
01-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23578 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 919c032fa4511468aadc6f50d6ed9c50890710b3 |
01-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
These are used to represent float and double values, and the two regclasses
contain the same physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
PC32RegisterInfo.td
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelPattern.cpp
PCInstrInfo.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 242f2557cc242b2d132e5a3e6c3a98961a7e4349 |
01-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Should be using flag and not chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23572 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2b5e66fc6e3a72ea1e832a51d0d4aab5eb519065 |
30-Sep-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove some now-dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23571 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 5802be13e0eb0f6730b75fee2ea0b3cf6cb148a4 |
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
constant fold these calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23558 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| b48d2cf5eb4a2576314490e43bef0ac0d87732b2 |
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
pass extra args
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23539 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 0ffb1a56ff8439604556afd09ee0774655d7197c |
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
these methods get extra args
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23538 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.h
|
| ff201eebea35c7e7d37897276e3df0153197b2fd |
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Use the 32-bit version for now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23534 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC.td
|
| 67ab118a6d97160762c3f4fbb1b28a6ae2a1a968 |
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Add a bunch of patterns for F64 FP ops, add some more integer ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23533 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 237733e9335f4d2bb16a818ab184929e12fae407 |
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Remove code for patterns that are autogenerated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23532 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| c7a37a52cd05c27aa0ddf743bfaf02cee4a2580e |
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
tblgen autogens this pattern now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23530 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 68fd4866ded709e53672cfc303e8303e212e3fba |
29-Sep-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
copy and paste error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23528 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.h
|
| 221e53caeac3be62f92dc3d76340557f8c2875f1 |
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
now that tblgen is smarter, this pattern is not needed. Also, tblgen
now inverts commuted versions of ANDC/ORC with the current .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23527 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 52897f827e6604b9ec0d351b81b3b9df9fb4274f |
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
consistency with other cases, no functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23524 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| f13befb456076d591267b8e126537f839a8ecd9a |
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Make the JIT default to the DAG isel instead of the pattern isel, like LLC.
The Pattern isel has some strange memory corruption issues going on. :(
This should have been converted over anyway, but it got forgotten somehow
when switching to the dag isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23523 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| d3d2cf52bbb776941bf8cb03d8732ff3f407cdea |
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Never rely on ReplaceAllUsesWith when selecting, use CodeGenMap instead.
ReplaceAllUsesWith does not replace scalars SDOperand floating around on
the stack, permitting things to be selected multiple times.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23515 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 79d0e9f3d1c9c88ee301a0551b60f6aa8cadb48f |
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Codegen ADD X, IMM -> addis/addi if needed.
This implements PowerPC/fold-li.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23514 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| d8ead9e25021d5c07b222f8550b621b4f31c874f |
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Autogen MUL, move FP cases together
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23512 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 88add100b3db715df4275c8ab408e6b51f28ff8f |
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
disentangle FP from INT versions of div/mul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23511 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 4a7de219b4bd776e5ae89f3cf5f6638afac4e5d3 |
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Use the autogenerated matcher for ADD/SUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23510 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| e025574370f6375d0fa1ccb9ead5d6124226239b |
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
add a patter for SUBFIC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23509 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 0648ccf1e99b2748144f736e1ab89c935fd6f6f7 |
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Mark int binops as int-only, add FP binops. Mark FADD/FMUL as commutative but
not associative. Add [SU]REM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23508 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 615c2d0920862ae7d4d766ee3da660ecf2197308 |
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23506 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelPattern.cpp
|
| a5cac6f6eb939b033c020cc59499756d2b95b349 |
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Mark associative nodes as associative
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23503 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 645992f595193a651f291c661502ed3df0841ca0 |
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Nate pointed out that mulh[us] are commutative as well. Thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23500 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6bcf1b7eed0fabed92298cedce0fcacdc55fdfd7 |
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
expose commutativity information
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23498 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 393e138f603d50a37425d625126491e314f3a9d0 |
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
All (xor *) cases are autogenerated now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23497 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| cfc828a3d050b0e07fd01b643586a3d61e230b13 |
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
add support for missed eqv tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23496 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 1bd8b7b06e8031f1140570eb3bb240075b334687 |
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Implement PowerPC/eqv-andc-orc-nor.ll:EQV3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23494 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 91da8623bef655542f4402fd8b48987a0594adfc |
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
learn to codegen not as NOR instead of xoris/xori
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23490 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| d135fa4fd6f70944a7944d8de2a4e625a240351b |
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
These nodes are all autogenerated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23489 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| d145a61f8f581cfe7dc7abb023a3b1ab534606c7 |
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Darwin, like many BSD systems, has a setjmp/longjmp which saves the signal mask
on setjmp calls and restores it on longjmp calls (both of which require syscalls).
This makes the calls REALLY slow. Use _setjmp/_longjmp instead. This speeds up
hexxagon from 120.31s to 15.68s: from 5.53x slower than GCC to 28% faster than GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23482 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 333bd835bd0d01f0e49b2f3d590be685a4959e16 |
27-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Make sure to clear the CodeGenMap after each basic block is selected to avoid
cross MBB pollution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23470 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 5e8d2dc19790b2262a27a67a1900ce187d661172 |
27-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Move the post-lsr simplify cfg pass after lowereh, so it can clean up after
eh lowering as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23459 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 30e21a46f00e638b2fdafb394058e1e6355f4e70 |
27-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
minor pattern shuffling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23458 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| ea874f3306c26ed425c05b2de202a176e2f32ed2 |
24-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Teach the dag isel generator how to construct arbitrary immediates. The
generated isel now tries li then lis, then lis+ori.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23418 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6a78c2157ad1ca9608ebdb33a8cc9f86f4a74f2c |
17-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Implement hook for ppc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23374 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 4ac85b3e94b5eca5c8e6decea570f207daee419f |
15-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
disable this for now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23366 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 43ef1318c61222ab9fd571255d9163c9249bd323 |
14-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
give all operands names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23356 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 4345a4a452c3ba3d99d374026e77b21382df44fe |
14-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Fix some issues exposed by more testing. XORIS had the wrong operands
specified. The various *imm operands defined by PPC are really all i32,
even though the actual immediate is restricted to a smaller value in it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23352 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| c36d065dce953259bbc6d5e55a2d4dd40042b47f |
14-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Fix some bugs noticed by new checking code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23350 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 303b555164e82139e0f88c183f1fc176fbb2d16c |
14-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
we don't need this proto any longer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23342 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| af165385112037cb942e94ea562a67990b7d6220 |
14-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
move the #include for the generated code into the isel class body so we
can use/define class methods
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23339 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 7b738342f0b27b9f7fdcf93f08ebb99fa510ae09 |
13-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Change the arg lowering code to use copyfromreg from vregs associated
with incoming arguments instead of the pregs themselves. This fixes
the scheduler from causing problems by moving a copyfromreg for an argument
to after a select_cc node (now it can, and bad things won't happen).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23334 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 31262ce53d8ce1558fb03b41d0a1afab840e5130 |
13-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Remove some dead vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23329 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| e6ec9f20c9df6387b68874e4c49035d3c9c5527f |
10-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
PowerPC cannot truncstore i1 natively
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23304 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelPattern.cpp
|
| c9fe7508a5e072479d4ab5711c60aa5142c64f10 |
09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
I forgot that we always spill fp values as 64-bits. Implement spill folding
for FP as well. This triggers a couple dozen times on 177.mesa (for example).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23299 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| f38df04c3a0c2aa766fa50b254d2d0fc743f8152 |
09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a problem that Nate noticed, where spill code was not getting coallesced
with copies, leading to code like this:
lwz r4, 380(r1)
or r10, r4, r4 ;; Last use of r4
By teaching the PPC backend how to fold spills into copies, we now get this
code:
lwz r10, 380(r1)
wow. :)
This reduces a testcase nate sent me from 1505 instructions to 1484.
Note that this could handle FP values but doesn't currently, for reasons
mentioned in the patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23298 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 1463019e84cea6857914cea30c0180ec7289f09f |
09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
code cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23297 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 043870dd85ea41e8972c304b122070a417c8a4bc |
09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Teach the code generator that rlwimi is commutable if the rotate amount
is zero. This lets the register allocator elide some copies in some cases.
This implements CodeGen/PowerPC/rlwimi-commute.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23292 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
PCInstrInfo.h
PCInstrInfo.td
|
| 2eb2517fbe55dd14f0a24a229e72ec5a5fa67b4f |
09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Introduce two new concepts:
1. Add support for defining Pattern's, which can match expressions when there
is no instruction that directly implements something. Instructions usually
implicitly define patterns.
2. Add support for defining SDNodeXForm's, which are node transformations.
This seperates the concept of a node xform out from the existing predicate
support.
Using this new stuff, we add a few instruction patterns, one for testing, and
two for OR/XOR by an arbitrary immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23286 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| b85c64c4d882d24fe727f28126f83fce993ed8c8 |
09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
whitespace/comment changes, no functionality diffs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23283 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 47f01f1b442356f3580b2b230daf30267b4a732e |
08-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Add a bunch of stuff needed for node type inference. Move 'BLR' down with
the rest of the instructions, add comment markers to seperate portions of
the file into logical parts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23277 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| bfde080ce0ef03f6a95de38089b306d3c7a50f51 |
08-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
add patterns for x?oris?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23268 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 3e63ead49b2166c7bc9e7b6bcc54e8ce3b4abe9d |
08-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
add patterns to the addi/addis/mulli etc instructions. Define predicates
for matching signed 16-bit and shifted 16-bit ppc immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23267 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| d1cdc7028cbf5c58c3b3791d89c3bffa15944f65 |
08-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Add patterns for some new instructions, allowing the use of the ineg fragment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23266 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 19c0907ba1c11c81dc231cf7b4143fdaf03466e4 |
08-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Remove some cases handled by the generated portion of the isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23262 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| c98d8236490666ad3f5c9224226bda12269fed77 |
07-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
On non-apple systems, when using -march=ppc32, do not print:
'' is not a recognized processor for this target (ignoring processor)
Default to "generic" instead of "" for the default CPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23257 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| c09eeec0ebc378644bafd04916e5efafa7d98152 |
07-Sep-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when we
are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.
This speeds up 189.lucas from 81.99 to 32.64 seconds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23250 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCISelPattern.cpp
|
| 92cce90c66f9b231275db210f1df97efe21c2dd5 |
06-Sep-2005 |
Nate Begeman <natebegeman@mac.com> |
Add note about future optimization noted in the ppc compiler writer's guide
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23245 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| d401dff7966ca3ac644cddcda4f1e6d30074923e |
06-Sep-2005 |
Nate Begeman <natebegeman@mac.com> |
Add accessor for 64bit flag, so that we can tell when it is safe to
generate the fun in-register fp<->long instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23244 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
|
| e147ceb2fa377edb14c7977f16c92e2815ff25aa |
03-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
explicitly specify an operands list for patterns with inputs (e.g. neg)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23240 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6cd40d5888f905a3820d5d6c71e57cc0e02abb4a |
03-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
include the dag isel fragment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23239 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| bb38b6f8c0bf843d630504165b1bfed006dd676b |
03-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
ask for a dag isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23238 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 25dae727f3b0c3511c17d7b7a8d476b1eed04f20 |
03-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Change the isel to not break out of the big giant switch. Instead, the
switch should never be exited, so its bottom is now unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23234 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 7cd09cf94269ad728b59b201957b25790e6b9b78 |
03-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
rearrange logical ops to group them together more consistently.
Define the PatFrag class which can be used to define subpatterns to match
things with. Define 'not', and use it to define the patterns for andc,
nand, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23233 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6159fb20c2b18686fa7d3e002e387b4c33809fe1 |
03-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Add AND/OR/XOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23232 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 218a15d02c6b5276e26050bbb6bc13db085ad83d |
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Add some initial patterns to simple binary instructions, though they
currently don't do anything. This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.
This patch also removes PPC::SUB, because it is dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23230 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 73e37c35be074588f7709a626acfbba5b2a33afa |
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
turn on dag isel by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23226 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 839615a510c582ddcdb09a8e2934f30775daa032 |
02-Sep-2005 |
Jim Laskey <jlaskey@mac.com> |
Add help support for -mcpu and -mattr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23222 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 1e9de3ed2db440fac99e5cc85b7d98b0a23a2727 |
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Decouple fsqrt from gpul optimizations, implementing fsqrt.ll.
Remove the -enable-gpopt option which is subsumed by feature flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23218 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCSubtarget.cpp
PCSubtarget.h
|
| f505949580e1a4af3d49cb5dcff9fd78f31a00fb |
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Restore this patch now that the latent bug has been fixed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23209 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 5b3224fe7ecafd486b75ebfa113a95783112ec3d |
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Revert the previous patch which causes a mysterious regression in toast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23207 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2a00daac5895879afdf14adf936cd93deaadbb99 |
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Implement small-arguments.ll:test3 by teaching the DAG optimizer that
the results of calls to functions returning small values are properly
sign/zero extended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23198 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 2b8ad8e55ac04472af769fa36d80893330f90f3d |
02-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Align functions to 16-byte boundaries, to eliminate noise in performance measurements. This improves the performance of 'treeadd' by about 20% with the dag
isel, restoring it to the pattern-isel level (which happens to get the alignment right).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23194 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| a82f7b2be074e7471e35854a395b1b140c5a7fba |
01-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Local labels on darwin apparently start with just 'L', not .L like other
platforms. This reduces executable size and makes shark realize the actual
bounds of functions instead of showing each MBB as a function :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23193 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| b1e1180ca0b32f37aa74d7ad703eeaf91e66c8fa |
01-Sep-2005 |
Jim Laskey <jlaskey@mac.com> |
1. Use SubtargetFeatures in llc/lli.
2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23192 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
PCTargetMachine.h
owerPCTargetMachine.h
|
| 75592e4137c3ae7800e1fb8736db28a65bb3c94d |
01-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Implement dynamic allocas correctly. In particular, because we were copying
directly out of R1 (without using a CopyFromReg, which uses a chain), multiple
allocas were getting CSE'd together, producing bogus code. For this:
int %foo(bool %X, int %A, int %B) {
br bool %X, label %T, label %F
F:
%G = alloca int
%H = alloca int
store int %A, int* %G
store int %B, int* %H
%R = load int* %G
ret int %R
T:
ret int 0
}
We were generating:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
li r2, 16
subf r2, r2, r1 ;; One alloca
or r1, r2, r2
or r3, r1, r1
or r1, r2, r2
or r2, r1, r1
stw r4, 0(r3)
stw r5, 0(r2)
lwz r3, 0(r3)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
Now we generate:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
or r2, r1, r1
li r3, 16
subf r2, r3, r2 ;; Alloca 1
or r1, r2, r2
or r2, r1, r1
or r6, r1, r1
subf r3, r3, r6 ;; Alloca 2
or r1, r3, r3
or r3, r1, r1
stw r4, 0(r2)
stw r5, 0(r3)
lwz r3, 0(r2)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
This fixes Povray and SPASS with the dag isel, the last two failing cases.
Tommorow we will hopefully turn it on by default! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23190 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 393ecd6d2dbc844ae9e34fea34f15d914ec7c43c |
01-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a bug where we were useing HA to get the high part, which seems like it
could cause a miscompile. Fixing this didn't fix the two programs that fail
though. :(
This also changes the implementation to follow the pattern selector more
closely, causing us to select 0 to li instead of lis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23189 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 50ff55c2c7909818165e51bbdc103a05b143dcb1 |
01-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Do not select the operands being passed into SelectCC. IT does this itself
and selecting early prevents folding immediates into the cmpw* instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23188 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| f76053269ecc6c7bd3d0b1e90ebdd0cef1bb2bdc |
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Move FCTIWZ handling out of the instruction selectors and into legalization,
getting them out of the business of making stack slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23180 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCISelPattern.cpp
|
| 8346bb6c29cb6268c99117f6c86d6696b373d03e |
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23179 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelPattern.cpp
|
| bc11c3482c2d38af514031c38c417f106b8f3c91 |
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Move SHL,SHR i64 -> legalizer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23178 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| c22af9e5dfad453b93e0ce528af1809bc527bd6a |
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Remove code that is now dead from the pattern isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23177 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| eb9b62e35e16f90ab1f641e9ba8d077bd591ff0b |
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
lower sra_parts on the dag, implementing it for the dag isel, and exposing
the ops to dag optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23176 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 99296ffd36662f0a64a2b4922e2b133b46222113 |
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add assert zext/sext to the dag isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23171 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 5dd7fea3f2fdcca7f2ab092d0042b9b0151449fd |
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Handle AssertSext/AssertZext nodes, fixing the regressions last night.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23170 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 49296f1f48251945635fcebf562331b5ca5eb9c5 |
31-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Enable generation of AssertSext and AssertZext in the PPC backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23168 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 7a49fdcd1136c26d9c60b19c087ca9d578cc9834 |
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix 'ret long' to return the high and lo parts in the right registers. This
fixes crafty and probably others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23167 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| eb80fe8ff684121c8130db716fe4a7cb5ca3ac0d |
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
now that physregs can exist in the same dag with multiple types, remove some
ugly hacks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23162 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2ea0c66ae56b3254698c960f7b89b4eaed6bd83f |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix type mismatches when passing f32 values to calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23159 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 1368721d532d0d291a03bb3fff7f94805e5919b6 |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix some indentation (first hunks).
Remove code (last hunk) that miscompiled immediate and's, such as
and uint %tmp.30, 4294958079
into
andi. r8, r8, 56319
andis. r8, r8, 65535
instead of:
li r9, -9217
and r8, r8, r9
The first always generates zero.
This fixes espresso.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23155 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| b551ba7661d5f8263979a5905fd3d1b9e5387e45 |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a problem Nate found where we swapped the operands of SHL/SHR_PARTS. This
fixes fourinarow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23153 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 14b86c72a28a064373ac1670ed8ee62dab41e2f4 |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
codegen ADD_PARTS correctly: put the results in the right registers! This
fixes fhourstones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23152 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2501d5e29c13f41fc15c0be5fece011db27c8ab3 |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add operands in the right order, fixing McCat/18-imp with the dag isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23150 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 31ce12f4f57db4375392e9129772773bed1bd4cc |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Make sure the selector emits register register copies with flag operands
linking them to calls when appropriate, this prevents the scheduler from
pulling these copies away from the call.
This fixes Ptrdist/yacr2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23143 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 15055733f85da5dc9a29e64cc1a2eeda38898f68 |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
The first operand to AND does not always have more than two operands. This
fixes MediaBench/toast with the dag selector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23141 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 6de08f4377302cb73ca6a378410889be423af20f |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in my patch for legalizing to fsel. It cannot handle seteq/setne,
which I failed to include when I moved the code over. This fixes
MallocBench/gs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23140 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8f838720ad578349e7929b32fa9117aa317bb3a5 |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
emit FMR instructions to convert f64<->f32 instructions, so things like
STOREs, know the right type to store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23139 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 915fb302b103cc53b14693a8dad7e2a83d3037d3 |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix some really strange indentation that xcode likes to use.
no xcode, this is not right:
if (!foo) break;
X;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23138 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8bbcc20a9dccd258d5977d1d99520367b9ca9e7e |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
fix a crash in cfrac
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23137 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 9c2dece8e2daed25eb2db0f034e004a8342462e6 |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement DYNAMIC_STACKALLOC, wrap some long lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23136 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 7107c10501e62d2e3ed34b349585e616b8f6da3e |
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a dumb bug of mine where we were mishandling the PPC ABI (undef handling).
This fixes voronoi and bh in Olden, allowing all of olden to pass!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23133 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| efa6abcb957b9002a7e6708eb6f7885a93957ea7 |
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a bug the last patch exposed in treeadd among others
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23127 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2fef809b5b6a38d38aadc3399b5f7a78b537d092 |
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
A hack to fix a problem folding immedaites. This fixes Olden/power.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23126 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2a06a5ef363382479e74cae2d39f139e11f40225 |
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix order of operands for copytoreg node when emitting calls. This fixes
Olden/msFix order of operands for copytoreg node when emitting calls. This fixes
Olden/mstt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23125 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| b9efd14568531fc5d6150a4471c1bfb6cb98928f |
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add operands in the correct order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23123 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| c8a89a1fcb900b8204c166fc4e9f5c3a1a3937de |
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in FP_EXTEND, implement FP_TO_SINT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23121 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 528f58e813ec4929a7997afbf121eb54e8bacf4c |
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
fix an assertion failure in treeadd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23120 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| e3f1c9773420bf6e51b39906609329d21cc9269c |
27-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
The condition register being branched on may not be cr0, as such, print it.
This fixes: UnitTests/2005-07-17-INT-To-FP.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23112 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| f48e83ded0a27788a4790e73c2c4ad6bed8a7c71 |
27-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Propagate cr# from COND_BRANCH to the actual branch instruction as appropriate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23111 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 28b9cc2d1323f3814b902c3dd55899b091803762 |
27-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
allow code using mtcrf to assemble
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23107 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| a0df5d8da5d4ba1e75fd3c3449ae535b283b8621 |
27-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove operand type 'crbit', since it is no longer used
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23106 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCInstrInfo.td
|
| 82972705df381178eea94121dacb6576f6bc9e30 |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
teach getClass what a condition reg is
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23105 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 5087daac23d841a5acb3b6d5a3e7857129ce558c |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Minor cleanups:
* avoid calling getClass() multiple times (it is relatively expensive)
* Allow -disable-fp-elim to turn of frame pointer elimination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23104 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 8a2d3ca7dff8f37ee0f1fc0042f47c194045183d |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement SELECT_CC fully for the DAG->DAG isel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23101 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCInstrInfo.td
|
| 0bbea954331b8f08afa5b094dfb0841829c70eaa |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Make fsel emission work with both the pattern and dag-dag selectors, by
giving it a non-instruction opcode. The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23091 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelLowering.cpp
PCISelLowering.h
PCISelPattern.cpp
|
| 13794f5d01317d76ec698b43bdf1c35eea57eae5 |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement the fold for:
bool %test(int %X, int %Y) {
%C = setne int %X, 0
ret bool %C
}
to:
_test:
addic r2, r3, -1
subfe r3, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23089 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 52987f4f6531ffcfcc61b1319f5219f3704d426b |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Changes to adjust to new ReplaceAllUsesWith syntax. Change FP_EXTEND to
just return its input, instead of emitting an explicit copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23088 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 60675f7562bd6007b23f4a8e9e92cbd82e10b0f7 |
26-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove some code made dead by the fsel patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23085 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 28b9be300cab414da42f9da016a2e89b797b9ddc |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
now that fsel is formed during legalization, this code is dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23084 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelPattern.cpp
|
| 0b1e4e508b1fb76408a2c6a434b0f4df3cad3578 |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement the other half of the select_cc -> fsel lowering, which handles
when the RHS of the comparison is 0.0. Turn this on by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23083 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 5839bf2b3bd22689d9dd0e9de66c2dce71d130ae |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Change ConstantPoolSDNode to actually hold the Constant itself instead of
putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23081 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelPattern.cpp
|
| 95e0682a4276fb9f5978039dc4bae675bdf66ee3 |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix some warnings in an optimized build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23080 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelPattern.cpp
|
| 2bb06cdf27905cf95bd39e4120f1ad57c68ac73e |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a huge annoyance: SelectNodeTo took types before the opcode unlike
every other SD API. Fix it to take the opcode before the types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23079 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 6718f11febbc4ded0a8f3964306442ad44c0fb98 |
26-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix JIT encoding of conditional branches
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23076 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| e4bc9ea0a560d8a0ba42f5a2da617e1f1f834710 |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add initial support for converting select_cc -> fsel in the legalizer
instead of in the backend. This currently handles fsel cases with registers,
but doesn't have the 0.0 and -0.0 optimization enabled yet.
Once this is finished, special hack for fp immediates can go away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23075 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCISelPattern.cpp
|
| bb22df31d9cf329deca2cf770885869bd7c26c94 |
26-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
SUBFIC produces two results, not one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23073 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 6660cd65cf79f4be328f072526580471bde5fe22 |
26-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement SHL_PARTS and SRL_PARTS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23072 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| b20c318df02c19a5ba4ba89c76f2bf3daae64ad2 |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Emit the lo/hi parts in the right order :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23068 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| a9317ed361847c96989664b84ae8502a783a9956 |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement support for 64-bit add/sub, fix a broken assertion for 64-bit
return. Allow the udiv breaker-upper to work with any non-zero constant
operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23066 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 801d5f56bb2c20031a0abf330642c6f77d027d38 |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
simplify the add/sub_parts code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23065 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 047b952e298352fe6feffedf02e359601133f465 |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Finish implementing SDIV/UDIV by copying over the majik constant code from
ISelPattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23062 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| c70b4afce20ad37252d83442a83d84928918264d |
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Simplify some code. It's not clear why the UDIV expanded sequence
doesn't work for large uint constants, but we'll keep the current behavior
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23061 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 957fcfbd8935b2973376167861a53e4a9220aefc |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement setcc correctly for G5 and non-G5 systems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23060 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 64906a06b3d1cafec41c6b562f0f8130724decf6 |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement setcc on the G5. We're still missing the non-g5 specific bits, but
they will come later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23059 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| c8e27db5c58abc2c2aa1b60d6a58aef251766ee7 |
25-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove option to make SetCC illegal on PowerPC after long discussion with
Chris. This will be accomplished through correctly modeling CR's and
subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23056 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 8784a23075f8544f78f8b46cfd10457c1109d433 |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add support for sdiv by 2^k and -2^k. Producing code like:
_test:
srawi r2, r3, 2
addze r3, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23052 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| ee84f11577bf788be496b9464fd03c926a8ec2f4 |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
fit in 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23051 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 34e17052a77e1a52cae58b2f6d203c663af97ece |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement support for taking the address of constant pool indices, which
is used by the int -> FP code among other things. This gets
2005-05-12-Int64ToFP past that failure, to dying on lack of support for add_parts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23042 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2fe76e58eb734a09ec08ea006a32700572ffc0ca |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add support for FP constants, fixing UnitTests/2004-02-02-NegativeZero
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23038 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| e28e40a2733c5d9a568d1569e2d1d8461716b22d |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fully implement frame index, so that we can pass the address of alloca's
around to functions and stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23036 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 89532c7db03543402dd5376172b87233575beb44 |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement unconditional branches, fixing UnitTests/2003-05-02-DependentPHI.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23034 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| fdf8366ecc67b2f3ac21c3b9155c1bc2e9d3dad4 |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
LFS/STFS load and store FP values, not integer ones. This change allows us
to codegen this: float foo() { return 1.245; }
into this:
_foo:
lis r2, ha16(.CPI_foo_0)
lfs f1, lo16(.CPI_foo_0)(r2)
blr
instead of this:
_foo:
lis r2, ha16(.CPI_foo_0)
lfs r2, lo16(.CPI_foo_0)(r2) <-- ouch
or f1, r2, r2 <-- ouch
blr
with the dag isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23033 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| ed7956bfe4bbe9445cbf0a74299f714ffe4fd7a4 |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a broken assertion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23032 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 2b54400f085391a247dd2c3fffc9f36f7b2dc867 |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the
instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23028 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCISelDAGToDAG.cpp
PCISelPattern.cpp
PCInstrInfo.td
|
| fb0c964364ba9f2c54ea28e0b7f404e18f7327b4 |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement support for calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23026 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 86fac6b00ab79ee5353f28aee4e7fff2713098c9 |
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Remove some dead cases.
Emit the indcall sequence as:
mtctr inreg
mr R12, inreg
btctr
If inreg and R12 aren't coallesced, this reduces the odds of having the mtctr
and btctr in the same dispatch group. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23023 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| a3c4454c5fb70ab94c7de4faf2600ed729fffda0 |
24-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add an idea
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23020 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 6ef4949a0bea3f22e7572119d3692b1a5866ffe8 |
24-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Whoops, fix a thinko. All cases except SETNE are now handled by the
target independent code in SelectionDAG.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23002 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| c6b0717a6caa32fc9029fd1337af4bf0d07b54e8 |
24-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove unused statistic
Prefer 'neg X' to 'subfic 0, X' since neg does not set XER[CA]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23001 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 4b46fc094d219da7f9fa02acfa0bf228519f952d |
24-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add the "ppc specific" setcc-equivalent select_cc cases
Prefer 'neg X' to 'subfic 0, X' since it does not set XER[CA]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23000 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| a2590c5b3eaa24002e3f83f146f0e5b6c95a89c8 |
24-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add callseq_begin/end support
Call stil not supported yet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22998 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 424dcbdb3bb2eae7972b097f56ab97439643d1bf |
23-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22982 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 8ca5693c517054c89a557391267fe305baa3407e |
23-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Ack, typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22981 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| a50d53e5ef9f2ef9866937511075f873e31d7c1d |
23-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add an option to make SetCC illegal as a beta option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22979 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 354df0ae6dfaf904cfba1c70c576ee55a62bec75 |
23-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove some instructions we no longer generate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22976 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 1f24df632481c09eb45672c16a95eb0987000388 |
23-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Remove some regs that are not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22975 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
PCRegisterInfo.td
|
| 9dc4d3cbac284b8301832fb1b575364490c745f3 |
23-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Nate noticed that 30% of the malloc/frees in llc come from calls to LowercaseString
in the asmprinter. This changes the .td files to use lower case register names,
avoiding the need to do this call. This speeds up the asmprinter from 1.52s
to 1.06s on kc++ in a release build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22974 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCRegisterInfo.td
|
| f7f22555053a8992b2f97db77a62458ff8a69d7f |
22-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22963 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| ddf3e7dfd791f7cdbcd1bb5feb168067b5b9c16d |
22-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix compilation of:
float %test2(float* %P) {
%Q = load float* %P
%R = add float %Q, %Q
ret float %R
}
By returning the right result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22961 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| b30ee6a41a00d7fcd45960b3869fc6bcb3f7bdf4 |
22-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Make sure expressions only have one use before emitting them into a place that is conditionally executed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22960 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 9944b76cfe74981d2c41c8237d25267ba0c467c7 |
22-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement most of load support. There is still a bug though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22959 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 1db1adbdee847906b4541ae582dc5be001fe2214 |
21-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Don't print out the MBB label for the entry mbb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22953 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| f913d3f91c8e72000a41dd58e0118a1763fe6d7e |
21-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Simplify the logic for BRTWOWAY_CC handling. The isel code already
simplifies BRTWOWAY into BR if one of the results is a fall-through.
Unless I'm missing something, there is no reason to duplicate this
in the target-specific code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22952 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 2fbb4579d6d6bbde8387283b78307c2ea477a312 |
21-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement selection for branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22951 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 4dd4a2d278ac65c871924bb5235805a6a07e3d69 |
21-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
If the false value for a select_cc is really simple (has no inputs), evaluate
it in the block. This codegens:
int %test(bool %c) {
%retval = select bool %c, int 17, int 1
ret int %retval
}
as:
_test:
rlwinm r2, r3, 0, 31, 31
li r2, 17
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
li r2, 1
.LBB_test_2: ;
or r3, r2, r2
blr
instead of:
_test:
rlwinm r2, r3, 0, 31, 31
li r2, 17
li r4, 1
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
or r2, r4, r4
.LBB_test_2: ;
or r3, r2, r2
blr
... which is one fewer instruction. The savings are more significant for
global address and constantfp nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22946 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 4416f1a0a5b17906b9e162209fd506656a2e07d8 |
20-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add support for global address, including PIC support.
This REALLY should be lowered by the legalizer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22941 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 7e65997c43cc91a5e6eaa0f460b844ef1b5d2fb1 |
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a typeo, no wonder all tokenfactor edges were the same!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22935 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| ecbce617ca5ca4c8f881c56297b9aac931d91744 |
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Split RegisterClass 'Methods' into MethodProtos and MethodBodies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22929 91177308-0d34-0410-b5e6-96231b3b80d8
PC32RegisterInfo.td
PC64RegisterInfo.td
|
| fabc8ffacb0bceeaad7bbde79b49f8ad7b5666e3 |
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Put reg classes into namespaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22926 91177308-0d34-0410-b5e6-96231b3b80d8
PC32RegisterInfo.td
PC64RegisterInfo.td
|
| 0b1e641b8217e10b04e767bd0b70933c70cc17d3 |
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Now that the simple isels are dead, so is this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22913 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
PCRegisterInfo.h
|
| 27d53ba6dd58543b1a3f5f92be522e0d6d75daf8 |
19-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix a bug where we were passing the wrong number of arguments to an
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22901 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 02b88a4586704f34bc65afca3348453eae69d1d3 |
19-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
ISD::OR, and it's accompanying SelectBitfieldInsert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22889 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 73bfa7152481620d60bf63d5397dfe35bbc9c098 |
19-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove the X86 and PowerPC Simple instruction selectors; their time has
passed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22886 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PC32ISelSimple.cpp
PCTargetMachine.cpp
|
| c15ed447f494c77a76c24661893e22192ebb2103 |
19-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22884 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 45fcb8f410dd00ea9df9234fdff151593713ca79 |
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix operand numbers by marking variable arity nodes as such and by fixing
the operand lists of a few other nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22883 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 3f852b45fcfb0dde647eff77f9186378c3f0448a |
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
MFLR doesn't take an operand, the LR register is implicit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22882 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCISelPattern.cpp
PCRegisterInfo.cpp
|
| 0bc04231c0aa42fbb50cc4fd531340d35b60450d |
18-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Move this to the emitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22877 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 5b5f0b7fd5ff6975920e65d4b1b019e456d6e850 |
18-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
More optimal solution for loading constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22870 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| d607c12e8e8533028a66c9f533007c6c32a64cef |
18-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
After selecting the instructions for a basic block, emit the instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22869 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| f5fac3b4a6c41a2ea344a24c5f9ecc51cfca0723 |
18-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
remove some unused stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22866 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 58dfb08319b1415637b36c16ce52d6424c254574 |
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix int foo() { return 65535; } by using the top 16 bits of the constant
as the argument to LIS rather than the result of HA16(constant).
The DAG->DAG ISel was already doing the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22865 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| a69404781344c4aee05935ee921bbf2844911bc0 |
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Improve ISD::Constant codegen.
Now for int foo() { return -1; } we generate:
_foo:
li r3, -1
blr
instead of
_foo:
lis r2, -1
ori r3, r2, 65535
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22864 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
PCISelPattern.cpp
|
| 0c09a411e0c763d69aaefa2321c2ae8daabc80e4 |
18-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
replace switch stmt with an assert, generate li 0 instead of lis 0 for 0,
to make the code follow people's expectations better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22861 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 3285aadce9fb037d684d704e07610b09fb940ad7 |
18-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
Handle loading of 0x????0000 constants with a single instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22858 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| cffc32b6e2e1edc2ddd62a00159f7008ee765d3e |
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support for ISD::AND, and its various optimized forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22857 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 131a8805205c383f67b3b6a11777401e27b90371 |
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Maintain consistency in negating things
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22855 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 0f3257a3302b60c128a667db6736e81335316c1e |
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement XOR, remove a broken sign_extend_inreg case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22854 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 305a1c75cfcc1b2e97c2bccebd42a70d99e7d127 |
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add a bunch more simple nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22851 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 6a7d61179c77c23dc22cd64e5e922bc40ed234e9 |
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add a couple more nodes that are easy to handle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22850 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| b5a0668d43582297e19d03df34e0a0c09a1f6c45 |
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Be fruitful and multiply!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22849 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| b454cfd45362215a11edef8e2131aefe0aa7c456 |
18-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
Better version of isIntImmediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22848 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 26653500bbbc21cd1c2d12ecc433fa439536b657 |
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Teach the DAG->DAG ISel about FNEG, and how it can be used to invert
several of the PowerPC opcodes that come in both negated and non-negated
forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22845 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| 8482dd894d7d64134f999d8e62bc9adf5cb239a9 |
17-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add a beta option for turning on dag->dag isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22837 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| a5a91b10262f5bbcf1ec8abd1e66ee6585d3f00e |
17-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
initial hack at a dag->dag instruction selector. This is obviously woefully
incomplete, but it is a start. It handles basic argument/retval stuff, immediates,
add and sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22836 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelDAGToDAG.cpp
|
| d1c4626e147b8c9ee6dfe8bbec05f3a2dc27af9d |
17-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add prototype, remove dead proto
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22835 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
|
| 6d9aed4f8febdf24d60fde175747ca6df289dfd9 |
17-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a few small typos I noticed when converting this over to the DAG->DAG
selector. Also, there is no difference between addSImm and addImm, so just
use addImm, folding some branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22819 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| a033b4d8eb560e88914b376c17f2513730c6e3b4 |
17-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
Removed UINT_TO_FP and SINT_TO_FP from ISel outright.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22818 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 361ca5c927eae645069e73cebc9840c5ee8d5a5f |
17-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
Remove ISel code generation for UINT_TO_FP and SINT_TO_FP. Now asserts if
marked as legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22816 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| ad23c9d4f256469881e4e6ca9e6fd4605e12ec36 |
17-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
Make UINT_TO_FP and SINT_TO_FP use generic expansion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22815 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
|
| 456f1e890cb059fedb9f5d3f315c80e4f98f429b |
17-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement a couple improvements:
Remove dead code in ISD::Constant handling
Add support for add long, imm16
We now codegen 'long long foo(long long a) { return ++a; }'
as:
addic r4, r4, 1
addze r3, r3
blr
instead of:
li r2, 1
li r5, 0
addc r2, r4, r2
adde r3, r3, r5
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22811 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| a8cd01524f08d5e7aef84b6aed8745b3f618a2a3 |
16-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
updates for changes in nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22808 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelPattern.cpp
|
| 7cbd525ba85ebe440d15fa359ec940e404d14906 |
16-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nasty
fixme from the PowerPC backend. Emit slightly better code for legalizing
select_cc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22805 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelPattern.cpp
|
| 7c5a3d390a463fb50a6eee7ae3174817925e6d28 |
16-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Pull the LLVM -> DAG lowering code out of the pattern selector so that it
can be shared with the DAG->DAG selector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22799 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelLowering.cpp
PCISelLowering.h
PCISelPattern.cpp
|
| b0096bd19d6d519c8cc60c69c2658af6f1a2dbfd |
16-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Turn loop strength reduction on by default.
Only run createLowerConstantExpressionsPass for the simple isel. The DAG
isel has no need for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22794 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| ea0617a0235d0413a52d08e406a675e84eabe341 |
15-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
Broke 80 column rule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22792 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 30679e691db00a613e90ef01416aab2d4b371c0c |
15-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
Changed code gen for int to f32 to use rounding. This makes FP results
consistent with gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22791 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 2d56e72f09337a1cab3ba199a9467c159296f3fa |
14-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix last night's PPC32 regressions by
1. Not selecting the false value of a select_cc in the false arm, which
isn't legal for nested selects.
2. Actually returning the node we created and Legalized in the FP_TO_UINT
Expander.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22789 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 5a01481585387a9af267c7cc824b0aaedf665838 |
14-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Make FP_TO_UINT Illegal. This allows us to generate significantly better
codegen for FP_TO_UINT by using the legalizer's SELECT variant.
Implement a codegen improvement for SELECT_CC, selecting the false node in
the MBB that feeds the phi node. This allows us to codegen:
void foo(int *a, int b, int c) { int d = (a < b) ? 5 : 9; *a = d; }
as:
_foo:
li r2, 5
cmpw cr0, r4, r3
bgt .LBB_foo_2 ; entry
.LBB_foo_1: ; entry
li r2, 9
.LBB_foo_2: ; entry
stw r2, 0(r3)
blr
insted of:
_foo:
li r2, 5
li r5, 9
cmpw cr0, r4, r3
bgt .LBB_foo_2 ; entry
.LBB_foo_1: ; entry
or r2, r5, r5
.LBB_foo_2: ; entry
stw r2, 0(r3)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22784 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
EADME.txt
|
| 8f331325a22746d89fc30ea59672012c8c58cf49 |
13-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove support for 64b PPC, it's been broken for a long time. It'll be
back once a DAG->DAG ISel exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22778 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
PC64CodeEmitter.cpp
PC64ISelPattern.cpp
PC64InstrInfo.cpp
PC64InstrInfo.h
PC64JITInfo.h
PC64RegisterInfo.cpp
PC64RegisterInfo.h
PC64TargetMachine.h
PCTargetMachine.cpp
|
| cf083e312cced297961b65e353904bbe59f7604a |
13-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
Fix for 2005-08-12-rlwimi-crash.ll. Make allowance for masks being shifted to
zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22773 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 847c3a976bb225a1ce9efdd5d11b8ef292c01d9a |
13-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
1. This changes handles the cases of (~x)&y and x&(~y) yielding ANDC, and
(~x)|y and x|(~y) yielding ORC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22771 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 191cf943e68a8b3a14e5f19cf0279b8216da8dd7 |
11-Aug-2005 |
Jim Laskey <jlaskey@mac.com> |
1. Added the function isOpcWithIntImmediate to simplify testing of operand with
specified opcode and an integer constant right operand.
2. Modified ISD::SHL, ISD::SRL, ISD::SRA to use rlwinm when applied after a mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22761 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 2b48bc6f9556d8dc3af50e6acde06f7a69a5280a |
11-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Tidied up the use of dyn_cast<ConstantSDNode> by using isIntImmediate more.
Patch by Jim Laskey.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22760 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 54abfc5ee426e214b6f0a101dd9c71f9ee850531 |
11-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Use a more efficient method of creating integer and float virtual registers
(avoids an extra level of indirection in MakeReg).
defined MakeIntReg using RegMap->createVirtualRegister(PPC32::GPRCRegisterClass)
defined MakeFPReg using RegMap->createVirtualRegister(PPC32::FPRCRegisterClass)
s/MakeReg(MVT::i32)/MakeIntReg/
s/MakeReg(MVT::f64)/MakeFPReg/
Patch by Jim Laskey!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22759 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| c24d484b7813524b9d87373992cd3ba8831dae51 |
10-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Make SELECT illegal on PPC32, switch to using SELECT_CC, which more closely
reflects what the hardware is capable of. This significantly simplifies
the CC handling logic throughout the ISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22756 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| b4138c475e30a5ec91e9a51ffd7c1dc7a11f3eed |
10-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Changes for PPC32ISelPattern.cpp
1. Clean up how SelectIntImmediateExpr handles use counts.
2. "Subtract from" was not clearing hi 16 bits.
Patch by Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22754 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| df706e3f0c3a7936b3bdb6e36bf20642f467ebae |
10-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Changed the XOR case to use the isOprNot predicate.
Patch by Jim Laskey!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22750 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 0d7d99fd44bb1eaa0c034d26d50d025a160bdb04 |
10-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
1. Refactored handling of integer immediate values for add, or, xor and sub.
New routine: ISel::SelectIntImmediateExpr
2. Now checking use counts of large constants. If use count is > 2 then drop
thru so that the constant gets loaded into a register.
Source:
int %test1(int %a) {
entry:
%tmp.1 = add int %a, 123456789 ; <int> [#uses=1]
%tmp.2 = or int %tmp.1, 123456789 ; <int> [#uses=1]
%tmp.3 = xor int %tmp.2, 123456789 ; <int> [#uses=1]
%tmp.4 = sub int %tmp.3, -123456789 ; <int> [#uses=1]
ret int %tmp.4
}
Did Emit:
.machine ppc970
.text
.align 2
.globl _test1
_test1:
.LBB_test1_0: ; entry
addi r2, r3, -13035
addis r2, r2, 1884
ori r2, r2, 52501
oris r2, r2, 1883
xori r2, r2, 52501
xoris r2, r2, 1883
addi r2, r2, 52501
addis r3, r2, 1883
blr
Now Emits:
.machine ppc970
.text
.align 2
.globl _test1
_test1:
.LBB_test1_0: ; entry
lis r2, 1883
ori r2, r2, 52501
add r3, r3, r2
or r3, r3, r2
xor r3, r3, r2
add r3, r3, r2
blr
Patch by Jim Laskey!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22749 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 979a21e766eaea8881ee8b3b26c24b0771a8dfcf |
10-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a bug compiling: select (i32 < i32), f32, f32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22747 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| c7e18a10d412b24fd1054851a8ad277a3a747471 |
10-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add a optimization note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22732 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 88ac32ca266e1e3cdace905b8e364e4f4a9a900d |
09-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Update the targets to the new SETCC/CondCodeSDNode interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22729 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| 59b21c25d470c58e0575d5b2f31dd703fa7681ae |
09-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Minor cleanup patch, no functionality changes. Written by Jim Laskey.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22727 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 2f46055cc22ff5a0118425d7823b93d3992acbd0 |
09-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/Generic/div-neg-power-2.ll, a regression from last night.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22726 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| d3ded2d8a7a579fa31f0c350ed9a06e7433e03ef |
09-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Factor out some common code, and be smarter about when to emit load hi/lo
code sequences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22719 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 0045776d33d6d9d1033235025e67cda4b83b6987 |
08-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Remove getImmediateForOpcode, which is now dead.
Patch by Jim Laskey.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22716 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| fd78454477c7aef827eb4881abbb937f160d2d76 |
08-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add new immediate handling support for mul/div.
Patch by Jim Laskey!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22715 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 5b90917400414d09f30ae43b387b1be3fc5ccc3d |
08-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add support for OR/XOR/SUB immediates that are handled with the new immediate
way. This allows ORI/ORIS pairs, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22714 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 2f57c4da2164de3dfeebb3c25d81c49e6574a12a |
08-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Modify the ISD::AND opcode case to use new immediate constant predicates.
Includes wider support for rotate and mask cases.
Patch by Jim Laskey.
I've requested that Jim add new regression tests the newly handled cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22712 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 39c6896d22a89444292494107c89e10c79c0de13 |
08-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Modify the ISD::ADD opcode case to use new immediate constant predicates.
Includes support for 32-bit constants using addi/addis.
Patch by Jim Laskey.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22711 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 8fd1980ce6427bee4b4778e8adf199060451b933 |
08-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Modify existing support functions to use new immediate constant predicates.
Patch by Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22710 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| cf1cf1886e4ffdcedb069093da30e99bb04ee578 |
08-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add support predicates for future immediate constant changes.
Patch by Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22709 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 02efa6c140fe3f1076f9ceb29db9716329ca3ba6 |
08-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Move IsRunOfOnes to a more logical place and rename to a proper predicate form
(lowercase isXXX).
Patch by Jim Laskey.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22708 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 394cd13ba3249d6aa8f8a21603e377b923fe4675 |
08-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix JIT encoding of ppc mfocrf instruction; the operands were reversed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22707 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 3c304a3ba18a040d3c3dbd15ab69da5543cdbd54 |
06-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Consolidate the GPOpt stuff to all use the Subtarget, instead of still
depending on the command line option. Now the command line option just
sets the subtarget as appropriate. G5 opts will now default to on on
G5-enabled nightly testers among other machines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22688 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCAsmPrinter.cpp
PCISelPattern.cpp
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
|
| ba253651402f5d12172b3feed8909e28d01b7e1d |
05-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Enable gp optimizations by default when available, even when a target triple
is available, since the target triple doesn't specify whether to use gpopts
or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22685 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
|
| 6281ae4bf0d99650c42bda934a44f316db9c6707 |
05-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22681 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 4e624ecd0713d8444e7ec6054877b01e86ebd104 |
05-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
don't crash when running the PPC backend on non-ppc hosts without specifying
a subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22677 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 99558806f8c4c6867a335fe896350302b126a2b5 |
04-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Hack to naturally align doubles in the constant pool. Remove this once we
know what The Right Thing To Do is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22660 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 3d72d148871918cfdd930919cb11767a8c2bb7e6 |
04-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Use the new subtarget support to automatically choose the correct ABI
and asm printer for PowerPC if one is not specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22659 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PC32RegisterInfo.td
PC64RegisterInfo.cpp
PC64RegisterInfo.td
PCRegisterInfo.cpp
PCTargetMachine.cpp
|
| 8c00f8cdc7ae0cdd18d91b3a31a70da0f78aa04f |
04-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add Subtarget support to PowerPC. Next up, using it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22644 91177308-0d34-0410-b5e6-96231b3b80d8
PCSubtarget.cpp
PCSubtarget.h
PCTargetMachine.cpp
owerPCTargetMachine.h
|
| 0a3f677f0912e2fc9f45ce44cca1a0f4cacfc4c6 |
03-Aug-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix grammar: apostrophe-s ('s) is possessive, not plural; also iff vs. if.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22619 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| a34cbcc50a39a53e212a754592479ceab56c84c0 |
03-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
minor capitalization thing, patch by Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22617 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| c0d590b6f23e772ede680f998ee3486ce8344c66 |
02-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
This hunk accidentally got dropped. Patch by Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22595 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 0561b3ff9fd08f9cda48551f2f91590ca5f60656 |
02-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Update to use the new MathExtras.h support for log2 computation.
Patch contributed by Jim Laskey!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22594 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PC64ISelPattern.cpp
PCAsmPrinter.cpp
PCISelPattern.cpp
|
| 3f270130b575ca29d8039d6dc07b50fed4bc041e |
02-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add a pass name to make debugging dumps nicer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22588 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| d29b6aa608d69f19b57ebd2ae630b040b1c4951d |
30-Jul-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Keep tabs and trailing spaces out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22565 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 422f3d58a8a9d346e0bb34f77c30184b0dfc2838 |
30-Jul-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
turn off GOT on archs that didn't use it (not that it appeard to harm them much with it on)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22553 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.h
|
| 988b1dd608ed596879e29ad27d4aafdbf3a8f1ac |
28-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
Eliminate an extra copy from R1 that Nate noticed on function calls that
have to write arguments to the stack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22536 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 4015ea871113165cbf2d0d9b7513fd90e5ddaf46 |
28-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
Specify the correct number of operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22535 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 2a05c8e260bb4a3cb54c825371317e4e6164075d |
28-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Fold constant adds into loads and stores to frame indices.
For the following code:
double %ext(int %A.0__, long %A.1__) {
%A_addr = alloca %typedef.DComplex ; <%typedef.DComplex*> [#uses=2]
%tmp.1 = cast %typedef.DComplex* %A_addr to int* ; <int*> [#uses=1]
store int %A.0__, int* %tmp.1
%tmp.2 = getelementptr %typedef.DComplex* %A_addr, int 0, uint 1 ; <double*> [#uses=2]
%tmp.3 = cast double* %tmp.2 to long* ; <long*> [#uses=1]
store long %A.1__, long* %tmp.3
%tmp.5 = load double* %tmp.2 ; <double> [#uses=1]
ret double %tmp.5
}
We now generate:
_ext:
.LBB_ext_0: ;
stw r3, -12(r1)
stw r4, -8(r1)
stw r5, -4(r1)
lfd f1, -8(r1)
blr
Instead of:
_ext:
.LBB_ext_0: ;
stw r3, -12(r1)
addi r2, r1, -12
stw r4, 4(r2)
stw r5, 8(r2)
lfd f1, 4(r2)
blr
This also fires hundreds of times on MultiSource.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22533 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 3dee17581c38ce598376e83666c54a6b5d96ef05 |
28-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix some comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22530 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
PCRegisterInfo.cpp
|
| 00b16889ab461b7ecef1c91ade101186b7f1fce2 |
27-Jul-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Eliminate all remaining tabs and trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22523 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCISelPattern.cpp
PCTargetMachine.cpp
|
| 54eed36da595f09c46a46b2b0b15757ea486b4c1 |
27-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement the optimization for the Red Zone on Darwin. This removes the
unnecessary SP manipulation in leaf routines that don't need it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22522 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
EADME.txt
|
| 9eb59ec548b861d6ede05b4e6dc22aabf645e665 |
27-Jul-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Eliminate tabs and trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22520 91177308-0d34-0410-b5e6-96231b3b80d8
PCRelocations.h
|
| b65975a6ed58ee6696818e785bee49fcbe0b2a0c |
26-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
add a note about the red zone
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22518 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 2e00d7d0ae32a87ec978fc99849e718f1914279a |
26-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
Wrap some long lines, fix emission of weak global variables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22517 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 4ad870ddcc41f53da4fd63d62285769a5e41a8c7 |
26-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Update the PPC readme
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22516 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 7b4f0a81ffc97095fac4b1b9536e86136e6b23a7 |
25-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix an optimization put in for accessing static globals. This obviates
the need to build PIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22512 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| aa68f7fa0920bd7eaf61e1f9a838f8aeb4f61b2a |
23-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
PowerPC no-pic code is not quite ready for prime-time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22507 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 908bc862d58bdb66d22a6a58bddb4e108a64e469 |
22-Jul-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
update interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22498 91177308-0d34-0410-b5e6-96231b3b80d8
PC32JITInfo.h
PCJITInfo.cpp
|
| 2497e6391f8df05926fe17b5cf08dad61c4797d2 |
21-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Support building non-PIC
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22494 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PC32ISelSimple.cpp
PC64ISelPattern.cpp
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelPattern.cpp
PCInstrInfo.td
PCTargetMachine.cpp
|
| 2130c0893041718f6d5c2bf3df4ba0ddce9adb08 |
21-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
revert to using 4-byte alignment for doubles, as specified by the ABI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22493 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 18ed029a7b75b2a39d39cd4c7f2ec68284c10102 |
21-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Support assembling fsqrt on darwin. This will be implemented better when
PowerPC gets subtarget support up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22489 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| adeb43ddf4eac9e75b7c8e79fa832f72922a2926 |
21-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5.
8-byte align doubles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22486 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCISelPattern.cpp
PCInstrInfo.td
PCTargetMachine.cpp
|
| a3fd400fa87f2d7f23b2c54195bf283cbec1758a |
19-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Integrate SelectFPExpr into SelectExpr. This gets PPC32 closer to being
automatically generated from a target description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22470 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCISelPattern.cpp
PCTargetMachine.cpp
|
| 63b3f9acae5ccfc7f806c461a2e9509318eac5b8 |
12-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove some code that moved to the generic asm printer a long time ago.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22407 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| bce81ae51ececbd03ffdb17d56c4a1206edfc52e |
10-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode.
This is the last MVTSDNode.
This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.
Also, remove some uses of dyn_cast that should really be cast (which is
cheaper in a release build).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22368 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| 9fadb4c1c0a6d223aa468f9f72f8c2562dc66839 |
10-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
Change TRUNCSTORE to use a VTSDNode operand instead of being an MVTSTDNode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22366 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| 72b286b0a0f8987bc247ae052ac86008c553e9ae |
08-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support for assembling .s files on mac os x for intel
Add support for running bugpoint on mac os x for intel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22351 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| e0fe225e8912b6308e3e1db442ba7b96d9f09ff3 |
05-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
Make several cleanups to Andrews varargs change:
1. Pass Value*'s into lowering methods so that the proper pointers can be
added to load/stores from the valist
2. Intrinsics that return void should only return a token chain, not a token
chain/retval pair.
3. Rename LowerVAArgNext -> LowerVAArg, because VANext is long gone.
4. Now that we have Value*'s available in the lowering methods, pass them
into any load/stores from the valist that are emitted
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22339 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| f84a2ace5e0a034691ca3d75ffd5b3e793a50512 |
05-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
Fix PowerPC varargs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22335 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| c1671e2d7ddd81f0ac59652cc889ba2a40278ebf |
02-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
Varargs is apparently currently broken on PPC. This hacks it so that it
is at least overloading the right virtual methods. The implementations
are currently wrong though. This fixes Ptrdist/bc, but not other programs
(e.g. siod).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22326 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 0431c96cec9576611f06c513d6adcab0f950c18c |
25-Jun-2005 |
Chris Lattner <sabre@nondot.org> |
Refactor the addPassesToEmitAssembly interface into a addPassesToEmitFile
interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22282 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
owerPCTargetMachine.h
|
| 213e557cef3e653e2d3a00b07b137c143128430a |
22-Jun-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
If we support structs as va_list, we must pass pointers to them to va_copy
See last commit for LangRef, this implements it on all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22273 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
|
| 558bc88a00930fce283b240b7c9555f649a18f1b |
18-Jun-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
core changes for varargs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22254 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PC64ISelPattern.cpp
|
| 4b828e6384e1e6c9936130dd9fe805c2140b05fc |
18-Jun-2005 |
Reid Spencer <rspencer@reidspencer.com> |
Clean up some uninitialized variables and missing return statements that
GCC 4.0.0 compiler (sometimes incorrectly) warns about under release build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22249 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| b157f858a233b30a7aaf56c5f1559ea2d7f13dd5 |
17-Jun-2005 |
Chris Lattner <sabre@nondot.org> |
silence incredibly braindead GCC 4 warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22246 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 439009c81e9e4799da64d3c40f4442f01c8f0d32 |
15-Jun-2005 |
Nate Begeman <natebegeman@mac.com> |
Commit fix for generating conditional branch pseudo instructions that
avoids dereferencing the end() iterator when selecting the fallthrough
block. This requires an ilist change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22212 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| a43b176f5141b263113841ba62bde2ad7fbab66d |
14-Jun-2005 |
Nate Begeman <natebegeman@mac.com> |
Commit a small improvement that is already in the x86 and ia64 backends to
not generate unnecessary register copies. This improves compile time by
2-5% depending on the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22210 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| ac609ddf823d6d955f74ec6f82ca3b388ed9d610 |
13-Jun-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix a memory smasher caught by Mac OS X's debug malloc library. We were
incorrectly using an iterator after it was invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22207 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| eae435de837ea659fba924c1531ced120a6dde76 |
08-Jun-2005 |
Reid Spencer <rspencer@reidspencer.com> |
For PR572:
Undefine the PPC symbol which is defined by Linux/PPC (erroneously) so it
doesn't pollute the user namespace and clash with our namespace declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22202 91177308-0d34-0410-b5e6-96231b3b80d8
PCRelocations.h
|
| b2c4bf3ff696577e8f00930cabe90d80f275fa80 |
08-Jun-2005 |
Nate Begeman <natebegeman@mac.com> |
Handle some more real world cases of rlwimi. These don't come up that
regularly in "normal" code, but for things like software graphics, they
make a big difference.
For the following code:
unsigned short Trans16Bit(unsigned srcA,unsigned srcB,unsigned alpha)
{
unsigned tmpA,tmpB,mixed;
tmpA = ((srcA & 0x03E0) << 15) | (srcA & 0x7C1F);
tmpB = ((srcB & 0x03E0) << 15) | (srcB & 0x7C1F);
mixed = (tmpA * alpha) + (tmpB * (32 - alpha));
return ((mixed >> 5) & 0x7C1F) | ((mixed >> 20) & 0x03E0);
}
We now generate:
_Trans16Bit:
.LBB_Trans16Bit_0: ; entry
andi. r2, r4, 31775
rlwimi r2, r4, 15, 7, 11
subfic r4, r5, 32
mullw r2, r2, r4
andi. r4, r3, 31775
rlwimi r4, r3, 15, 7, 11
mullw r3, r4, r5
add r2, r2, r3
srwi r3, r2, 5
andi. r3, r3, 31775
rlwimi r3, r2, 12, 22, 26
blr
Instead of:
_Trans16Bit:
.LBB_Trans16Bit_0: ; entry
slwi r2, r4, 15
rlwinm r2, r2, 0, 7, 11
andi. r4, r4, 31775
or r2, r2, r4
subfic r4, r5, 32
mullw r2, r2, r4
slwi r4, r3, 15
rlwinm r4, r4, 0, 7, 11
andi. r3, r3, 31775
or r3, r4, r3
mullw r3, r3, r5
add r2, r2, r3
srwi r3, r2, 5
andi. r3, r3, 31775
srwi r2, r2, 20
rlwimi r3, r2, 0, 22, 26
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22201 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| fc87928ebb4d50850e9b2b36f0c24c4fb17877ba |
15-May-2005 |
Chris Lattner <sabre@nondot.org> |
PPC "branch and link" instructions are branches in the PPC sense, but not
in the LLVM code generator sense (they are calls). Don't mark them as such,
which fixes the regressions on the ppc tester last night
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22065 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 022ed327bd455348dbe0fbe0915219cb8b4cb6e1 |
15-May-2005 |
Chris Lattner <sabre@nondot.org> |
Fix andrews changes to fit in 80 columns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22064 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| b5d8e6ece62b16be441d1a13609878eefa7908b9 |
13-May-2005 |
Chris Lattner <sabre@nondot.org> |
treat TAILCALL nodes identically to CALL nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21977 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| adf6a965a321372c640845407195594835921eb4 |
13-May-2005 |
Chris Lattner <sabre@nondot.org> |
Add an isTailCall flag to LowerCallTo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21958 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| 32f3cf612ef54c3d81467dbbc9808217c7a02cf2 |
13-May-2005 |
Chris Lattner <sabre@nondot.org> |
Realize that we don't support fmod directly, fixing CodeGen/Generic/print-arith-fp.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21939 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| 16cd04d26c53c6f81313cafb85f6c0e7a07cdff6 |
13-May-2005 |
Chris Lattner <sabre@nondot.org> |
rename the ADJCALLSTACKDOWN/ADJCALLSTACKUP nodes to be CALLSEQ_START/BEGIN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21915 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| c57f682113c46af22cc593dc15b70aad7aa51eab |
12-May-2005 |
Chris Lattner <sabre@nondot.org> |
Pass in Calling Convention to use into LowerCallTo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21899 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| 9bce0f92c3f1be7ad738ed018c7dd4f4c4bd979a |
12-May-2005 |
Chris Lattner <sabre@nondot.org> |
These targets don't like setcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21884 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| d7c4a4a6c048d4174b8795598f50fd76c30731ed |
12-May-2005 |
Nate Begeman <natebegeman@mac.com> |
Necessary changes to codegen cttz efficiently on PowerPC
1. Teach LegalizeDAG how to better legalize CTTZ if the target doesn't have
CTPOP, but does have CTLZ
2. Teach PPC32 how to do sub x, const -> add x, -const for valid consts
3. Teach PPC32 how to do and (xor a, -1) b -> andc b, a
4. Teach PPC32 that ISD::CTLZ -> PPC::CNTLZW
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21880 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| cafb67b25027d7d237ba9c562d1aeac460c0580c |
09-May-2005 |
Chris Lattner <sabre@nondot.org> |
fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are possible,
include and (srl) and the inverses (shl and) etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21820 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| b5884d311672a0d84c6b2627254001b27af45e2d |
04-May-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21693 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| 691ef2ba066dda14ae4ac0ad645054fbc967785a |
03-May-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
Implement count leading zeros (ctlz), count trailing zeros (cttz), and count
population (ctpop). Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.
More coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21676 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| 08cae7f519363000928004239fdd56a4ead0a4ca |
30-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Doesn't support these nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21634 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
|
| 17234b7d78944151b844e07a427df5b218add76b |
30-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
This target doesn't support the FSIN/FCOS/FSQRT nodes yet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21633 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 2d86ea21dd76647cb054fd5d27df9e49efc672b6 |
27-Apr-2005 |
Andrew Lenharth <andrewl@lenharth.org> |
Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends.
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*. Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21599 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| 7847fcac174bdda94373447676526af1bb1bc630 |
22-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
Convert tabs to spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21452 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PC64ISelPattern.cpp
PC64RegisterInfo.cpp
PCISelPattern.cpp
PCRegisterInfo.cpp
|
| b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0 |
22-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PC32ISelSimple.cpp
PC32JITInfo.h
PC64CodeEmitter.cpp
PC64ISelPattern.cpp
PC64InstrInfo.cpp
PC64InstrInfo.h
PC64JITInfo.h
PC64RegisterInfo.cpp
PC64RegisterInfo.h
PC64TargetMachine.h
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCFrameInfo.h
PCISelPattern.cpp
PCInstrBuilder.h
PCInstrInfo.cpp
PCInstrInfo.h
PCJITInfo.cpp
PCJITInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
PCRelocations.h
PCTargetMachine.cpp
PCTargetMachine.h
owerPCInstrInfo.h
owerPCTargetMachine.h
|
| 837a521c48b5bb481b61ba971092044cdbf0387f |
21-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Match another form of eqv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21413 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| f577c6122f8b51c4e4889f1e1c647ae210c501b8 |
19-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Add completely untested support for mtcrf/mfcrf encoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21353 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 14522e31d98fd44bbc2b0584aa8f2cbbd9104f43 |
19-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
switch over the rest of the formats that use RC to use isDOT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21352 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 883059fb583c9bd2d88d31d20e5615a1cf1e979a |
19-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Convert the XForm instrs and XSForm instruction over to use isDOT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21351 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 97a2d42999e43e440e48f65ba9560ef97be36d23 |
19-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Now that the ppc64 and vmx operands of I are always 0, forward substitute
them away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21350 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| a611ab72cab77ea9ca94495ee64615709afa595f |
19-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
convert over bform and iform instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21349 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 57226fbc7b84e78ee2563734c628563811743bc8 |
19-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Convert over DForm and DSForm instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21348 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| e19d0b11308a6026a58954c283d4de9d568fb33a |
19-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Convert XLForm and XForm instructions over to use PPC64 when appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21347 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 5035cef732e964427d2cdcd1d3048b26eeb77ef5 |
19-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Convert XO XS and XFX forms to use isPPC64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21346 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 0bdc6f1fd49badb3266ded6ccc311954b794075b |
19-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Turn PPC64 and VMX into classes that can be added to instructions instead of
bits that must be passed up the inheritance hierarchy. Convert MForm and AForm
instructions over
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21345 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 1cbf3abbb8c716721b502da6d5ff75a9755b525a |
18-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Next round of PPC CR optimizations. For the following code:
int %bar(float %a, float %b, float %c, float %d) {
entry:
%tmp.1 = setlt float %a, %d
%tmp.2 = setlt float %b, %d
%or = or bool %tmp.1, %tmp.2
%tmp.3 = setgt float %c, %d
%tmp.4 = or bool %or, %tmp.3
%tmp.5 = and bool %tmp.4, true
%retval = cast bool %tmp.5 to int
ret int %retval
}
We now emit:
_bar:
.LBB_bar_0: ; entry
fcmpu cr0, f1, f4
fcmpu cr1, f2, f4
cror 0, 0, 4
fcmpu cr1, f3, f4
cror 28, 0, 5
mfcr r2
rlwinm r3, r2, 29, 31, 31
blr
Instead of:
_bar:
.LBB_bar_0: ; entry
fcmpu cr7, f1, f4
mfcr r2
rlwinm r2, r2, 29, 31, 31
fcmpu cr7, f2, f4
mfcr r3
rlwinm r3, r3, 29, 31, 31
or r2, r2, r3
fcmpu cr7, f3, f4
mfcr r3
rlwinm r3, r3, 30, 31, 31
or r3, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21321 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 16ac709c632dd4d6dff8fdfe0b79a47c783b362a |
18-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Change codegen for setcc to read the bit directly out of the condition
register. Added support in the .td file for the g5-specific variant
of cr -> gpr moves that executes faster, but we currently don't
generate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21314 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
PCInstrFormats.td
PCInstrInfo.td
|
| 477d1de9b2c77455192b6e67dd9496851f4ed8d0 |
18-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Handle ExternalSymbol operands in the PPC JIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21312 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| f8b02949e3d13e9b7cd38e029fcbf3e799366aa7 |
16-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Make pattern isel default for ppc
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
0 == off
1 == on
2 == target default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21309 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCISelPattern.cpp
PCTargetMachine.cpp
|
| 7bfba7d5e3efd90134584447e534ad65998a809b |
14-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement multi-way branches through logical ops on condition registers.
This can generate considerably shorter code, reducing the size of crafty
by almost 1%. Also fix the printing of mcrf. The code is currently
disabled until it gets a bit more testing, but should work as-is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21298 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
PCInstrInfo.td
|
| ef7288c824e082d560edb783156a74ee310bfe28 |
14-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Add the necessary support to codegen condition register logical ops with
register allocated condition registers. Make sure that the printed
output is gas compatible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21295 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCAsmPrinter.cpp
PCInstrFormats.td
PCInstrInfo.td
|
| 1b7f7fbf95b373fa54e67f9d5b603da8a7f77a31 |
14-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Start allocating condition registers. Almost all explicit uses of CR0 are
now gone. Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21294 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 3664ceffdd91d8e146e5c7e61b2a8c08262661c6 |
14-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement the fold shift X, zext(Y) -> shift X, Y at the target level,
where it is safe to do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21293 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| eea805e74ce49f98e03c87a20cf2e6a6ff1b7c52 |
13-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Disbale the broken fold of shift + sz[ext] for now
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
always produces zero or one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21291 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 519f40ba4e88df9a6c6742dda68f6208db99917f |
13-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
remove one more occurance of this that snuck in
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21271 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| c951d87fe99ab464b933af7170de6f2e51953907 |
13-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21268 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| b882752bd04602249d391699dc7183de007f8964 |
13-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fold shift by size larger than type size to undef
Make llvm undef values generate ISD::UNDEF nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21261 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 9765c25eb775e223612cd996d78a5a141360dabf |
12-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement setcc op, -1 sequences
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21260 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 7af0248af47fbd86ec65d308adda22ec367accc4 |
12-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Initial support for allocation condition registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
PC32RegisterInfo.td
PCInstrFormats.td
PCInstrInfo.cpp
PCInstrInfo.td
PCRegisterInfo.cpp
|
| 9f833d30856c75d7d27498f20f1f453bea818375 |
12-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement bitfield clears
Implement divide by negative power of two
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21240 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
PCInstrInfo.td
|
| ef9531efedd2233269f670227fb0e6aae7480d53 |
11-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Update PPC readme. Remove things that are done or aren't ppc specific
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21232 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 5eef9f3bc9fa6effeb8fd481668304d7ee289d88 |
11-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
ORo sets CR0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21227 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6b4ea2cfa29be829a4003ac061f17c7942d617e2 |
11-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Revert the previous patch, which I didn't mean to check in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21226 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 26d4fdb968f14874e397c553a82834c75bce844e |
11-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a minor bug (ORo didn't mark that it set CR0).
Refactor how . instructions are handled. In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.
For example, instead of this:
-def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and. $rA, $rS, $rB">;
We now have this:
+def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB">;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| c7bd4827cd24ff63a604bbfb5f68f99da7498dce |
11-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Add recording variants of ISD::AND and ISD::OR. This kills almost 1000
(1.5%) instructions in 186.crafty
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21222 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
PCInstrInfo.td
|
| 709c806a1e1f4905466af2bf282d6bc7adb93f43 |
10-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix another fixme: factor out the constant fp generation code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21207 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| c5b1cd22b57d36229560a8919d3e59b4dae34e2a |
10-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix 64 bit argument loading that straddles the args in regs / args on stack
boundary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21206 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 340f2907839cc5ecb34c5045cb24ef31588f2a39 |
10-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not
have to inform the register allocator it might be stepped on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21202 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| 27499e3f1beaf21b5afa95c0008649a6cfcadf7a |
10-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Make sure that BRCOND branches can be converted into long branches too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21198 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelPattern.cpp
|
| a0e3e9474f429e6bd0dc902c1fe3236d43ff1276 |
10-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21197 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 51d2ed976f30913e173536e244d9f0e7259e4b1e |
10-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be more
correct. Remove the EmitComparison retvalue, as it is always the first arg.
Fix a place where we incorrectly passed in the setcc opcode instead of the
setcc number, causing us to miscompile crafty. Crafty now works!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21195 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 706471e2912ee55f45804cf8318e07d360ecda6d |
10-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
fix ISD::BRCONDTWOWAY codegen to not deference the end() iterator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21193 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 9184bfbbf47558da3e23d1b3483b7bac684925c1 |
10-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap.
This caused the "use before a def" assertion on some programs.
With this patch, 254.gap now passes with the PPC backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21191 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 91277ea45c7a6f052dd588edee51644f23194619 |
09-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
do not set the root to null if an argument is dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21188 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| cd08e4cb7e35ef1fbde7954786a5220116ca7d04 |
09-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Add rlwnm instruction for variable rotate
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21187 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
PCInstrInfo.td
|
| 27ee3a332d0b0e01109b907a73e932d1886a8db9 |
09-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a crash on 173.applu by asking for a constant bigger than 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21185 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| f429a3e0f60ad9e372a3291629bfb27d35f1b33e |
09-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Switch this instruction selector over to using liveins and liveouts, eliminating
implicit defs on entry to the function. yaay :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21184 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| af4ab1b103b1e67d5893f3a53751ee8568d7d486 |
09-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Optimize FSEL a bit for fneg arguments. This fixes the recently added test
case so that we emit
_test_fneg_sel:
.LBB_test_fneg_sel_0: ;
fsel f1, f1, f3, f2
blr
instead of:
_test_fneg_sel:
.LBB_test_fneg_sel_0: ;
fneg f0, f1
fneg f0, f0
fsel f1, f0, f3, f2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21177 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 644db4ec5fbf7978da1c49799da7f916b210416e |
09-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
This target does not yet support ISD::BRCONDTWOWAY
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21163 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| e88aa5b4d16b05d530cd4ff2b79c05c4b519ef59 |
09-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
64b: Expand S/UREM
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
Pattern match fsub a, mul(b, c) as fnmsub
Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21161 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
|
| a9532d5dde34b9f29f944c9d08fa8c99387b2c1b |
09-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix 64b shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21159 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
|
| f3f2d6d378b209eead702579d46f8a6dfa2f281f |
08-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Match Mac OS X 64 bit calling conventions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21157 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
|
| 7e7fadd2ea20f8b78bf9d6d7ff9ac4488df67152 |
07-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Optimized code sequences for setcc reg, 0
Optimized code sequence for (a < 0) ? b : 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21150 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| cbd06fc3d7511d8dcb64386ffa446f1b20b30ae6 |
07-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
PowerPC zero extends setcc results
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21147 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 7ddecb4186eb5fb3114d3fe12ac8678deb64c2e4 |
07-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Pattern match bitfield insert, which helps shift long by immediate, among
other things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21127 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 020ef42c19bd1e2e7dff202d98e2f71091e76178 |
07-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix some shift bugs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21126 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 27b4c23b8085563158d1b6a4e8892fad999b579c |
06-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fixed version of optimized integer divide is now fixed. Calculate the
quotient, not the remainder. Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21111 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 8f52980f032da74b72425fd23d4639c232a85e28 |
06-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Turn off the div -> mul optimization until it works correctly 100% of the
time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21105 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 815d6dac1ecc6ad661cebb308f9c06583fcd3cf0 |
06-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support for MULHS and MULHU nodes
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21104 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
PCISelPattern.cpp
PCInstrInfo.td
|
| ad5f65c74bb2b06fdb5544d2dcdf586b26c44ca0 |
05-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Behold, rlwinm with certain immediate arguments is printed as the much more
readable slwi or srwi (shift left/right word immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21099 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| a3829d55806e5aa5e4dafd54e2e156444e7e8b1e |
05-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix cut & paste errors (32->64), and codegen float->int more optimally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21098 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelPattern.cpp
|
| d3e6b94020ac6ed827fb1dfe1f4abe9ff39e4ec7 |
05-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove 64 bit simple ISel, it never worked correctly
Add initial (buggy) implementation of 64 bit pattern ISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21096 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PC64ISelPattern.cpp
PC64ISelSimple.cpp
PCTargetMachine.cpp
|
| c8c5c8f0fad4d1bd54ccd372255c9802287625f2 |
05-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Back out the previous change to SelectBranchCC, since there are cases it
could miscompile. A correct solution will be found in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21095 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 439b444cad649fb24d59fb02685e525afee82f71 |
05-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21094 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCISelPattern.cpp
|
| 80196b1331537455056044adfa70c4589dc08df3 |
05-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement SDIV by power of 2 as srawi/addze rather than load imm, divw
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21091 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 93075ec0a5dafbdde1b2596b32dbc3db182b148a |
05-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21090 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 178bb34ee57f7aab604644f6f4cc37f26fe96cad |
05-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support for multiply-add, multiply-sub, and their negated versions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21089 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| d860aa62ac686b7a3b7c8978fee5c4ed3304fd01 |
05-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Make sure that arg regs used by the call instruction are marked as such, so
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21086 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 04ec80173beda1e4309678b7ff32a5d984fa51cb |
04-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove unnecessary register copy now that regalloc is fixed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21085 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| c3e2db407eee81631ccfbc4bec95f0b631f48fff |
04-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
i1 loads should also be from the low byte of the argument word.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21077 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| e584668f04723777e5c17292ddf7c1098c94fc71 |
04-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix i64 return, fix CopyFromReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21076 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 6644d4c9335f0e31ffdf317e9db59a18f1870564 |
04-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Full varargs support. All of UnitTests now passes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21070 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 4ec0cbdf156e13fad4d8e0a27869d345b6cdea24 |
04-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Pass the correct value for the chain to the store
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21066 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| fa55470e39780f038fb69a44b2159647f0711278 |
04-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix SHL_PARTS
Start implementation of integer varargs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21065 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| aa73a9f16fcd1aa74c53bc66b1f28579e0edbb57 |
03-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Keeping up with the Joneses.
Implement not, nor, nand, and eqv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21060 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 27eeb00a1a64f46d64732222a31c38d04f507073 |
02-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Set shift amount to Extend
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21018 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
PCInstrInfo.td
|
| 43fdea070cd54094b5c3b69ce5a25c04d93c91af |
02-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
This target doesn't support fabs/fneg yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21010 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 27523a1c9295403a8a44b2204f51e23bc7224427 |
02-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix i64 returns
Generate PowerPC 'subfic' instruction when appropriate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20995 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| fc1b1dad88a256ab5ab16dd548ad82df8efa2ca9 |
02-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Add ISD::UNDEF node
Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
arguments, but not shadowing their value. This allows us to do the right
thing with both fixed and vararg floating point arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20988 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 6cb2e1b124887e5ef3ff77c6ba4ca9b8de051bb5 |
01-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix Olden/bh, CR0 was being set in the wrong order
LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20981 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 31318e4b6c1cc3a3ae0426780b2d360915fae3c4 |
01-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Also apply Chris's fix to FP select and SETCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20979 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 3071019026ee62899f2535d313b35c59d37ae218 |
01-Apr-2005 |
Chris Lattner <sabre@nondot.org> |
Move the selection of the arms of the select operation up to the conditional
part to make sure we get the side effects and to avoid confusing the CFG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20977 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| a7e11a4bb5a432ba94421655f7ebc63d2acebd1a |
01-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix stores to global addresses
Fix calls with no arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20975 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 04730361b52a9639ac7578d110feb9237b0c8ae0 |
01-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Support indexed loads and stores. This drops Shootout/matrix time from
18.8 to 14.8 seconds. The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20973 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 6b55997df5c334d3b8e18af72fd89c7f9efbe9a7 |
01-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement FP_TO_SINT and FP_TO_UINT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20972 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 6d369ccae002bd0f1e506545b7f4590b081d778d |
01-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support for adding 0.0 and -0.0 to the constant pool, since we lie and
say that we support them, for the purposes of generating fsel instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20970 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| dffcfccc13f0cc39b774c47b93ac8a64e93f0d8d |
01-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Factor out common code, support FP comparison in folded SetCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20969 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 3e89716ad7011d76bb0b650342f727cc9c9bf428 |
01-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
fsel generation for f32 and f64 select
generate compare immediate for integer compare with constant
fold setcc into branch
fold setcc into select
Code generation quality for Shootout is now on par with the Simple ISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20968 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 96fc681d7e7bf7b40fa61c1d33065a8025acdeb9 |
31-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Pass the correct values to the chain argument for node construction during
LowerCallTo.
Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for
loads and stores, amazing!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20946 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 74d734574e02c35074bca9cadc6694fafe9fef5c |
31-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Rewrite LowerCallTo and Select(ISD::CALL) to properly handle float varargs
Tell the SelectionDAG ISel to expand SEXTLOAD of i1 and i8, rather than
complicate the code in ISD::SEXTLOAD to do it by hand
Combine the FP and Int ISD::LOAD codegen
Generate better code for constant pool loads
As a result, all of Shootout, and likely many other programs are now
working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20945 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| fdcf3418e0618b435fdb07decec87e35feefc95f |
30-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix calls whose arguments fit entirely in registers to not break the Chain.
Implement SINT_TO_FP and UINT_TO_FP
Remove some dead code from the simple ISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20944 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCISelPattern.cpp
|
| 58f718cd97b0b2e267d60c520a00431f29408417 |
30-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix frame index code to generate legal PowerPC instructions. About half of
Shootout now works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20940 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 01d05266f9efcbd011f3ef1d19d4b78bc395b0c1 |
30-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix external symbol printing in the AsmPrinter. Tell the ISel that we
don't support things like memcpy directly. This allows a handful of the
Shootout programs to work, yay!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20939 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCISelPattern.cpp
|
| 23afcfb063ae7ee8b96d72771d80aefd5b9ddc4d |
30-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix BranchCC (it's still dumb), and implement FP select (also dumb)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20935 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 74747861b937045b2940a11774d62ebf9019d7f9 |
30-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement integer select and i1 sign extend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20934 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 33162520343f499e3000da8bad50dec415f3a115 |
29-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement SetCC, fix ZERO_EXTEND_INREG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20933 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
PCInstrInfo.td
|
| 848132d671c12df1dd04ec54f3e27b551f6e2803 |
29-Mar-2005 |
Chris Lattner <sabre@nondot.org> |
fix a warning in the optimized build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20920 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| f3d08f31b37fd9c6610c5894e93c698f00a440e9 |
29-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement div, rem, and frameindex
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20907 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| f70b576cccfb2e32f5f0fa66e1509f8d9f2b05be |
29-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Pattern ISel: fix argument loading for i64s (thanks chris)
Simple ISel: fix i64 subtract
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20903 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCISelPattern.cpp
|
| ca12a2bd91afd49ccd4084cfe9d9003e4d0a51d2 |
29-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove fake instruction 'subc' (mnemonic for subfc).
More pattern isel updates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20902 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCISelPattern.cpp
PCInstrInfo.td
|
| 9db505ca9dca58421f3b819ced5112789dafba31 |
28-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement proper loads and zero-extends of all types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20897 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 7532e2f55554b9f7944a358931a22f74f8dd226e |
26-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix that pesky floats in integer regs problem by assigning the f32 type to
the correct register class. Also remove the loading of float data into int
regs part of varargs; it will need to be implemented differently later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20857 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| f7e43380354107a925dca1a1a4d7d7e70cab04e4 |
26-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Get closer to having varargs working. There's still something strange
going on with copies between floating point and integer register files
being generated. Once that is solved, varargs will be done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20856 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| f26226155e2a49fa453f20b850849c5852c3af58 |
26-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Make 64bit args and float args work correct with calls. Thanks to Chris
for explaining EXTRACT_ELEMENT to me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20847 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 307e7443b8e2f4ffb126a33355f0568f07da8421 |
26-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Next round of pattern isel changes, mostly dealing with calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20841 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| c13a7f0eb3af81bb569d415b1dcf678159aae7a1 |
26-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Correct a documention link
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20840 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| c7b09f1f01b31eb8bfbb5ee4adb4d4b8d3b0968c |
25-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Support global addresses and fix call returns. Varargs still aren't
handled correctly for floating point arguments, or more than 8 arguemnts.
This does however, allow hello world to run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20832 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 9e3e1b5d444caec0976c8e1de61edfae4b78d3b7 |
25-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement next round of Pattern ISel fixes
1. void returns
2. multiplies
3. calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20822 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| 7ca541b75aaa5d5caf7efedb32c0e1f91a2a456d |
25-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix an incorrect argument being passed to BuildMI for indirect calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20821 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 2daec457510247c8b931d3f4af8a32066e442dca |
24-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Commit Gabor Greif's patch to use iterators in lowering intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20816 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 1bcb9abb30b81aa6987de5107ff366a3aa33ae8d |
24-Mar-2005 |
Chris Lattner <sabre@nondot.org> |
eliminate dead variables, patch contributed by Gabor Greif!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20812 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PC64ISelSimple.cpp
|
| 5e9666129a0273b73f7a11fbb46acb234a8760c7 |
24-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement more of the PPC32 Pattern ISel:
1) dynamic stack alloc
2) loads
3) shifts
4) subtract
5) immediate form of add, and, or, xor
6) change flag from -pattern-isel to -enable-ppc-pattern-isel
Remove dead arguments from getGlobalBaseReg in the simple ISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20810 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCISelPattern.cpp
PCTargetMachine.cpp
|
| 246fa6316db341a199a1992ea74c16fbb20e3f48 |
24-Mar-2005 |
Chris Lattner <sabre@nondot.org> |
Fix silly "no newline at end of file" warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20809 91177308-0d34-0410-b5e6-96231b3b80d8
PCISelPattern.cpp
|
| a9795f81e91c02d8824c70533c2ab944b13c14e6 |
24-Mar-2005 |
Nate Begeman <natebegeman@mac.com> |
Addition of the PPC32 Pattern ISel. While it is far from complete, it will
be brought up to parity with the current simple ISel in the coming days.
Currently, -pattern-isel is required to trigger it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20805 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCISelPattern.cpp
PCTargetMachine.cpp
|
| c7cd5e56726d845faf94de6dacbbf62303bf6f70 |
21-Mar-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
We may be adding functions to the Module during initialization, so
conservatively, it's modified
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20735 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| e4d5c441e04bdc00ccf1804744af670655123b07 |
15-Mar-2005 |
Chris Lattner <sabre@nondot.org> |
This mega patch converts us from using Function::a{iterator|begin|end} to
using Function::arg_{iterator|begin|end}. Likewise Module::g* -> Module::global_*.
This patch is contributed by Gabor Greif, thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20597 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PC64ISelSimple.cpp
PCAsmPrinter.cpp
|
| 411eba0eafd60f54f89623e90992a1c125d2378a |
08-Mar-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a crash handling 'undef bool', fixing an llc crash on 186.crafty
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20523 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 4318a3d0e9d7aa9ab36f376e8c98ee61d5465aaa |
02-Mar-2005 |
Chris Lattner <sabre@nondot.org> |
cleanup the cfg after lsr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20410 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 0c7490617a62b0622d52949c0651da907b3d6c04 |
02-Mar-2005 |
Chris Lattner <sabre@nondot.org> |
Add a temporary option for llc-beta: -enable-lsr-for-ppc, which turns on
Loop Strength Reduction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20399 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 7a823bd01fafa9393c6aa1e8ded163b9fd8266be |
15-Feb-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a problem where the PPC backend lost track of the fact that it had
to save and restore the LR register on entry and exit of a leaf function
that needed to access globals or the constant pool. This should hopefully
fix oscar from sending the PPC tester spinning out of control.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20197 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 3c707649070b16aae70ac1952f69c2342d0a80e7 |
14-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Fix Regression/CodeGen/PowerPC/2005-01-14-UndefLong.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19557 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| fbd4de1d9b0d10fcc600bbd4816c09544d5f0628 |
14-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Fix: Regression/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19555 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 35e5c7c186338c788b5476a0e722db4386b58856 |
03-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
This hunk:
- unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
+ unsigned TrueValue = getReg(TrueVal);
Fixes the PPC regressions from last night.
The other hunk is just a clarity improvement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19263 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 6dec0b09d5f01bf2fe4f26209f339310b2de4440 |
01-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a FIXME: Select instructions on longs were miscompiled.
While we're at it, improve codegen of select instructions. For this
testcase:
int %test(bool %C, int %A, int %B) {
%D = select bool %C, int %A, int %B
ret int %D
}
We used to generate this code:
_test:
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
b .LBB_test_3 ;
.LBB_test_2: ;
or r5, r4, r4
.LBB_test_3: ;
or r3, r5, r5
blr
Now we emit:
_test:
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
or r4, r5, r5
.LBB_test_2: ;
or r3, r4, r4
blr
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19214 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 47f9dd14b2c30bbb6c27d8cbb24a21f59e3a92af |
16-Dec-2004 |
Chris Lattner <sabre@nondot.org> |
Specify all of the targets built.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18985 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| be686a88974eecd49673ae1312481d3c0aefeffd |
16-Dec-2004 |
Chris Lattner <sabre@nondot.org> |
Factor out common .td file chunks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18982 91177308-0d34-0410-b5e6-96231b3b80d8
PC32.td
PC64.td
PCInstrInfo.td
owerPC.td
|
| 869f45937b843cf342865ba5b03196df0601d10b |
12-Dec-2004 |
Chris Lattner <sabre@nondot.org> |
Fix Regression/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll, and all programs
when compiled with debug information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18835 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 8363ad6bfc1448d5ad186075ac9e1258d4018f36 |
12-Dec-2004 |
Chris Lattner <sabre@nondot.org> |
CSE calls to getTypeSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18833 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 3ea78c4276dfbf5a078292ad8fd8dc952c4ff8b9 |
12-Dec-2004 |
Chris Lattner <sabre@nondot.org> |
Use the target triple to pick this target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18830 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 0284628e8eee8a68263ff06f586e6171b2ecbce7 |
30-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix several bugs in 'op x, imm' handling. Foremost is that we now emit
addi r3, r3, -1
instead of
addi r3, r3, 1
for 'sub int X, 1'.
Secondarily, this fixes several cases where we could crash given an unsigned
constant. And fixes a couple of minor missed optimization cases, such as
xor X, ~0U -> not X
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18379 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 35f2bbe8c644f3c1efbbeb61d2da3695a34aa87b |
30-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/PowerPC/2004-11-30-shr-var-crash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18376 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| e74ed0d53b5c12eb9cb463698df8e81c8a99549d |
30-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix test/Regression/CodeGen/PowerPC/2004-11-29-ShrCrash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18374 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 7747040410fbeb4dcdc0edcdb450302427dd1762 |
30-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix test/Regression/CodeGen/PowerPC/2004-11-30-shift-crash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18371 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 9d0087e043b7f6ab0f4c3ff448c832f5209b489c |
28-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
The LLVM bool type shall have 1 byte alignment on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18311 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 3330e08888143e5935c182ac63c1f561bb21648a |
27-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Remove the ISel->AsmPrinter link via the TargetMachine that was put in
place to help bring up the PowerPC back end on Darwin. This code is no
longer serves any purpose now that the AsmPrinter does the right thing
all the time printing GlobalValues. --Cruft.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18267 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCAsmPrinter.cpp
owerPCTargetMachine.h
|
| 15ee8adb00535834ad7962939868b4a9583577ca |
26-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
There is no reason to store <x,x>, just store <x>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18263 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| d4c8bea47fd3403ff1f3786b99ff11e6e1b5fc09 |
25-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Enable optimization suggested by Chris Lattner to not emit reloc stubs for
static global variables whose addresses are taken. This allows us to
convert the following code for taking the address of a static function foo
addis r2, r30, ha16(Ll1__2E_foo_2$non_lazy_ptr-"L00001$pb")
lwz r3, lo16(Ll1__2E_foo_2$non_lazy_ptr-"L00001$pb")(r2)
which also includes linker stub code emitted at the end of the .s file not
shown here, and replace it with this:
addis r2, r30, ha16(l1__2E_foo_2-"L00001$pb")
la r3, lo16(l1__2E_foo_2-"L00001$pb")(r2)
which in addition to not needing linker help, also has no load instruction.
For those not up on PowerPC mnemonics, la is shorthand for add immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18239 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCAsmPrinter.cpp
PCCodeEmitter.cpp
|
| fde839b4ff3c2c3f3658d45b2f7e9806f1d14032 |
25-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix the build on non ppc machines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18235 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 2a0c0dff0b957cc38c35798dd85aca8838da4977 |
25-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
The JIT works enough
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18228 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 5cbf3bc202c8e1661370af15727d508595d194ed |
25-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix encoding of fsel, fixing olden/power, McCat/bisort and several others.
All of Olden passes now! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18227 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| a1ab451392847efe826f11dadcde26f518342a3a |
25-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix encoding of fneg instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18226 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| cd61ec837feac06f54ba4578ceb3846bb8113589 |
25-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix encoding of swari, fixing several programs, including Olden/mst
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18225 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| b752a97ca41de789434fa792b6de01f6c04fe13e |
25-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
There is not a 1-1 mappign between llvm blocks and PPC blocks, do not use
LLVM blocks as the keys for the branch rewriter. This fixes treeadd and
many other programs with the JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18223 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 5efb75daed48edfeb03ba62f3f0afe81b86f5d7f |
24-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
* Rename existing relocations to be more specific
* Add relocations for refernces to non-lazy darwin stubs and implement
them correctly.
With this change, we can correctly references external globals, and now
all but two UnitTests and all but 1 Regression/C tests pass.
More importantly, bugpoint-jit will start giving us useful testcases,
instead of always telling us that references to external globals don't
work :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18222 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
PCJITInfo.cpp
PCRelocations.h
|
| 53e4aa57c6bdc9bc99d7d8843e1b2b693a16fbfa |
24-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Add the same optimization that we do loading from fixed alloca slots to
storing to fixed alloca slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18221 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 73278080c8078002beb4706d5b1592e9b9c5f9b3 |
24-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Write CompilationCallback as an explicit assembly stub to avoid getting GCC's
prolog.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18220 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 892afa9556eabf358ef632f1be0bde1587b3d610 |
24-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
When rewriting the original call instruction, make sure to rewrite it to
call the right address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18213 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| fb887e010dea16ecfe5204132dacf453af0d62c2 |
24-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Force the intregs ptr into R2 and the FPregs ptr into R3. This fixes a really
obscure problem where we were doing:
lmw r3,0(r9)
which is undefined on PPC. Now we do:
lmw r3,0(r2)
by force, not relying on the GCC register allocator for luck :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18212 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 69efbdd4f350e94e3f352e34053a12ba6f826e80 |
24-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix a few more tests by encoding the extsb and other XForm11 instructions
correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18200 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 2f5091ac2ace9e8fd79166810a7d20a9c4692254 |
24-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix the encoding of ORi and other DForm4 instructions. This brings us to
36/42 SingleSource/UnitTests passing!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18199 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 00a8c0199901db28ecd2e96f9e1abb017991060c |
24-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Loads are relocatable too
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18198 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| b765ff121958d14d6dcfbd7475938cfc52975dd1 |
24-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Calls do not need a MovPCtoLR instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18197 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| b9f26da5dd6c404e0a6eabcb60fb3c61ac0ee173 |
24-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Get constant pools working. This fixes even more programs, allowing us to
pass 24/42 in UnitTests (up from 20).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18196 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 8599d385a2f1fbafaaead903ea5be5a9b33a6509 |
24-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Rewrite branches more closely to correct. This makes more stuff pass, and
stops the infinite loops!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18194 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 310a75287291b8a06d27c14849f184716e2aa666 |
24-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Branch instructions explicitly represent CRx in them. bEcause of this, encode
them explicitly as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18193 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 3b78e3b6a9865ab5e30fc5dc8fe194a805aebcf6 |
24-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix encoding of bctrl, and remove some unused instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18192 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6f407893e2df521aef5240b1731afa95fdb4634c |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix encoding of blr and bctr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18178 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 65b7f3ed2af7450bb2cd22cd200c04d9493ddd65 |
23-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Use the correct register class as a constaint to gcc's inline assembly, so
that we don't end up trying to use r0 as a base register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18176 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| ca6d0f53ffb0a3112b55a665f7a446f86d5cd6dc |
23-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Save/Restore arg regs and nonvolatile regs the compiler might use during
CompilationCallback
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18175 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 5afa9af81b63e26a4510e0538e6ce19f01f8abf7 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix the encoding of OR, AND and many other instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18174 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| d162032013dd10d9cf54426fc69e89c57b22ac9a |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Remove argtype and argcount magic, which was used by the old asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18170 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 583e32b653877be4d842fcf3b1a0a34bbcc2780b |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Get rid of flags that are dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18169 91177308-0d34-0410-b5e6-96231b3b80d8
PC32.td
PC64.td
owerPC.td
owerPCInstrInfo.h
|
| 89d60de90e2dc809f001e4d9084fcfe21c7f4d6b |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix encoding of rlwinm?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18165 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 943f45208c48505d53b1a024eca0cb460735fa05 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18164 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 9ba12359e3b4ca5bce5469d86ae38eb1237752ee |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Enumerate CR registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18162 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| d9d06b3af1bf34ca680759c86a142a2c6c732896 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Initial implementation of exiting CompilationCallback
This should save all argument registers on entry and restore on exit, despite
that, simple things seem to work!!!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18161 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 22cd028eef97ea5ea7193fd69ed109bf0c7c347b |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
This method is dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18160 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.h
|
| 05ad23711edc5ab56b302571419314da29d79199 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Remove this method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18159 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| d7fa35c6d2acc2fe95346b1b9eaa3c0a30342c85 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Squelch a bogus warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18156 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| dd30751654aaa85efa9dbe2f610a90f38a248800 |
23-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Don't return value from void function. This is only temporary anyway while
the JIT is made to work!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18155 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 7598bbac664097768aa0841dc54aabd8753269eb |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Fix a minor bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18153 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| c9a6b1f4f6b62ed4dd58bdf9a3772e8d9b12aa37 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Be really paranoid about not breaking stuff yet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18152 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| e61198b3233f0c46900ced6d856534b11bd3d9f2 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Implement the first hunk of CompilationCallback. The pieces missing are the
ones noted, which require funny PPC specific inline assembly.
If some angel felt the desire to help me, I think this is that last bit missing
for JIT support (however, generic code emitter might night work right with
the constant pool yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18151 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 7c83dc2714d9d92068cc2c742e0baa90a3fd0363 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Implement the stub needed to get into compilation callback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18147 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| 64729d064a98f5ee7681c0c8cc71f7681d0b3fb3 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Simplify code a bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18146 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 9b3d989cb7b3473fbb7f268dbc02ae32052a9cbb |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Initial implementation of the JIT interfaces. Relocation is done and stubs
for external functions work. CompilationCallback has not been written, and
stubs for internal functions are not generated yet. This means you can call
printf and exit, and use global variables, but cannot call functions local to
a module yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18145 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.cpp
|
| e94c517bb52095f1ad070bb029617d532af405b8 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Emit relocations for the global variable using instructions. This gets us
LA, LOADHiAddr, CALLpcrel, and MovePCtoLR working, though the constant pool
probably is not right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18144 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 163393732a9a781b6b057c39ee6b1e0c96b9d199 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Implement all of the methods
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18142 91177308-0d34-0410-b5e6-96231b3b80d8
PC32JITInfo.h
|
| 42edd31209a14710196262c728d4863e19a1c5a9 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Initial checkin of the 32-bit PPC relocation types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18141 91177308-0d34-0410-b5e6-96231b3b80d8
PCRelocations.h
|
| e4fce6f19c2f7f4982d9b0a022ddda541e5135fb |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Move JITInfo from PPCTM to PPC32TM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18140 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
PCTargetMachine.h
|
| 942d7b5a68d58e05a6dbfc3a83e31274c13d85e6 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Do not provide the non-specialized PowerPCJITInfo object, it is pretty useless.
Instead, let derived classes provide specialized ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18139 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCTargetMachine.h
|
| 6540c6c344ec09fc2a3e9ffe3424a0a09c225e05 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
LA is really addi. Be consistent with operand ordering to avoid confusing the code emitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18138 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCInstrInfo.td
|
| f2190b39d035dfca78442cdd5ddd1fc6660cc050 |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Remove some dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18136 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| dd99885da319dfc8d8438736b348cdf2bc953d9c |
23-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Comment out a couple of unused instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18135 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 213c969c92ce8cffbc085429a5f4eb08a412d195 |
22-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Disable this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18130 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 99b394db151615414fc3de24e72c199799a05398 |
22-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
This chunk of code needs to be rewritten
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18127 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 486ebfd7049a42682762cc25c368d1a9ce3aed7b |
21-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix Shootout-C++/wc, which was broken by my recent changes to emit fewer
reg-reg copies. The necessary conditions for this bug are a GEP that is
used outside the basic block in which it is defined, whose components
other than the pointer are all constant zero, and where the use is
selected before the definition (backwards branch to successsor block).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18084 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| cdc79e37635ef62c6870ac5996fa71d3da107dd5 |
21-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
ignore generated files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18072 91177308-0d34-0410-b5e6-96231b3b80d8
cvsignore
|
| 1deb74d7ee65308ec08c261482c659e89e3a11f6 |
20-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Remove this method, it's not clear how it could be implemented indep of 32 or 64-bit mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18038 91177308-0d34-0410-b5e6-96231b3b80d8
PCJITInfo.h
PCTargetMachine.cpp
|
| a8b0fa5172dc46f53cf8b8ef1aa9c9b4e70ff998 |
20-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
getJITStubForFunction is optional and unimplemented, just remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18036 91177308-0d34-0410-b5e6-96231b3b80d8
PC32JITInfo.h
PC64CodeEmitter.cpp
PC64JITInfo.h
PCCodeEmitter.cpp
|
| bc3a5378d0854f352da38ad3574409103220fc9d |
19-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Eliminate another 6k register copies that the register allocator would just
coalesce out of hbd. Speeds up compilation by 2% (0.6s)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17987 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 8531f6f42aa2adfb1acf77c87c629d796f6e0151 |
19-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Generate fewer reg-reg copies for the register allocator to deal with.
This eliminates over 2000 in hbd alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17973 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| db869aad8c19230060e11494e12db182573eeccc |
18-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Eliminate another common source of moves that the register allocator
shouldn't be forced to coalesce for us: folded GEP operations. This too
fires thousands of times across the testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17947 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 1f5308e5b54c14deee2e0e981b19bd398cb1f90b |
18-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
When accessing the base register for global variables, use the register
directly rather than making a copy for the register allocator to coalesce.
This kills thousands of live intervals across the testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17946 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 0113638073ffe734a5fe4ffa1d534c9e044fcb06 |
18-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Clean up and fix cast codegen by removing cases that are handled elsewhere,
and properly emitting signed short to unsigned int. This fixes the last
regression vs. the CBE, MultiSource/Applications/hbd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17942 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| eea9b134fcd97aa6c11277864fecf2d30640d27f |
16-Nov-2004 |
Chris Lattner <sabre@nondot.org> |
Simplify namespaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17870 91177308-0d34-0410-b5e6-96231b3b80d8
PC64CodeEmitter.cpp
PCCodeEmitter.cpp
|
| 145a5a374631449bd0d483c036a3390150b7dc86 |
15-Nov-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add BCTR and LWZU instruction opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17851 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 3a8a42a9b403ac4d25bb405e3577a8ad1f209e25 |
14-Nov-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Handle GhostLinkage (should not ever reach the assembly printing stage!)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17749 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| fc256599b3b64af0ad09c416e12a3479e6534ce6 |
14-Nov-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix build on Linux/PowerPC64 using SuSE GCC (#undef PPC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17744 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
|
| a59145785719462aec77a5995cde54e0a82f8a5b |
09-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Allow hbd to be bugpointable on darwin by fixing common and linkonce codegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17637 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 676dee6ae97587768f07f423e3c54057be014114 |
08-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Put int the getReg cast optimization from x86 so that we generate fewer
move instructions for the register allocator to coalesce.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17608 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
EADME.txt
|
| 075cdc655e2466d6b7e98f88d2fccec26223298c |
07-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Disable bogus cast elimination when the cast is used by a setcc instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17583 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 28dd2fc240749d77d4251b4a29b8cace2a65460c |
04-Nov-2004 |
Nate Begeman <natebegeman@mac.com> |
Thanks to sabre for pointing out that we were incorrectly codegen'ing
int test(int x) { return 32768 - x; }
Fixed by teaching the function that checks a constant's validity to be used
as an immediate argument about subtract-from instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17476 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 6cb21d443eff9369e4f9035af28efd627e8f3909 |
28-Oct-2004 |
Reid Spencer <rspencer@reidspencer.com> |
Change Library Names Not To Conflict With Others When Installed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17286 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 17304c393e14a9ddb10ae0483d45d7e926c41078 |
26-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Remove file that is no longer used, and move include of MRegisterInfo.h
from PowerPCFrameInfo.h to PowerPCAsmPrinter.cpp where it is actually
needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17244 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
PCFrameInfo.h
owerPCRegisterInfo.h
|
| dfd0e7bc342f1252a2d2088ca5a759b6f04a65d7 |
26-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Eliminate usage of MRegisterInfo::getRegClass(physreg)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17240 91177308-0d34-0410-b5e6-96231b3b80d8
PC64RegisterInfo.cpp
PCRegisterInfo.cpp
|
| 4a0de07e7814c19e82f51fc785564381f234490c |
26-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Update to-do list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17235 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 9b508c36196b3cb7f349f6435b02fd7a335831dc |
26-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix treecc. Also fix a latent bug in emitBinaryConstOperation that would
allow and const, 0 to be incorrectly codegen'd into a rlwinm instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17234 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 097714b319f6be0f53211e57909de464993739f9 |
25-Oct-2004 |
Chris Lattner <sabre@nondot.org> |
Disable the JIT until it can sorta kinda work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17230 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 905a29152f1d40541c822a505fa7bfff861d670b |
24-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Implement more complete and correct codegen for bitfield inserts, as tested
by the recently committed rlwimi.ll test file. Also commit initial code
for bitfield extract, although it is turned off until fully debugged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17207 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| d4b4a99587a0856473b9334455f6cebcb4fe2583 |
24-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Correctly handle the MovePCtoLR pseudo-instr with a bl to next instr
* Stop the confusion of using rv and Addr for global addresses: just use rv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17195 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 40a55e1e291f1e28eadae19e5ce6f9087d99e085 |
23-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add BA, BL, and BLA opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17193 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| a4df350ba1193b2f0421d06a135beb21afb80035 |
23-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Do not emit IMPLICIT_DEF pseudo-instructions
* Convert register numbers from their opcode value to the real value, e.g.
PPC::R1 => 1 and PPC::F1 => 1
* Add correct handling of loading of global values which are PC-relative --
implement ha16() and lo16()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17190 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| bd7780bc6004e8545042e0aaf7d0d98082baf422 |
23-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
DForm_1, particularly used by store instructions, needs the immediate operand to
be listed second as that is how the instructions are usually created (and is the
correct asm syntax) so that it's assembled correctly from its constituents
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17183 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| da8d96d1a1769d0614c46d9880ac3c21cbc8e74c |
23-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions.
The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17182 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 15f74b3f4f371d5ef556644a7a2d61a0993a8053 |
23-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
The value of the XO field for MFLR and MFCTR is 339, not 399
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17181 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| bb482494149d96a04b0146a8d6aa8ec5a10a40fa |
23-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove extraneous blank line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17180 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 3a060e5279e27a3597905d6859407f33ec5009a4 |
23-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Align function arguments in function headers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17178 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 31dfc52b81cc4d03f8b0c87b15b53412229b0154 |
23-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Kill casts from integer types to unsigned byte, when the cast was only used
as the shift amount operand to a shift instruction. This was causing us to
emit unnecessary clear operations for code such as:
int foo(int x) { return 1 << x; }
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17175 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 8c2c3152d64aafe24b5b67cd7d670658eb65df18 |
22-Oct-2004 |
Reid Spencer <rspencer@reidspencer.com> |
Adjust to changes in Makefile.rules
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17167 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
PC32ISelSimple.cpp
|
| cac731ecbe6a80e0c607ece2833525a92601db99 |
22-Oct-2004 |
Reid Spencer <rspencer@reidspencer.com> |
We won't use automake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17155 91177308-0d34-0410-b5e6-96231b3b80d8
akefile.am
akefile.in
|
| 9691a898c702b5ad6ec122dd38f8b4196316876c |
21-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove debug code emitter from the JIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17151 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 4f9a6c30a2a3742a24b23ccefc38c751be92a04a |
21-Oct-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Make this compile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17150 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 3070e2ff790e106f5969f503487db5e4b8639ce4 |
21-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Added basic support for JITing functions, basic blocks, instruction encoding,
including registers, constants, and partial support for global addresses
* The JIT is disabled by default to allow building llvm-gcc, which wants to test
running programs during configure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17149 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| 0797d4905a2cabd928cf0ffdf80690f4e6c89845 |
20-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Don't clear or sign extend bool->int. This fires a few dozen times on the test suite
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17147 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 86d341b204171d53a470c361ee58811bfc22bf1a |
19-Oct-2004 |
Reid Spencer <rspencer@reidspencer.com> |
Initial automake generated Makefile template
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17136 91177308-0d34-0410-b5e6-96231b3b80d8
akefile.in
|
| fcf4a42cdf5d34b7761f34e3cb978b4cef93e2cb |
18-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Generate correct stubs for weak-linked symbols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17101 91177308-0d34-0410-b5e6-96231b3b80d8
PCAsmPrinter.cpp
|
| 761920301dcc873773c697c232e9a365076de937 |
17-Oct-2004 |
Reid Spencer <rspencer@reidspencer.com> |
PPC32GenCodeEmitter instead of PowerPCGenCodeEmitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17087 91177308-0d34-0410-b5e6-96231b3b80d8
akefile.am
|
| 1b75022cd3f23ff86d36f5ba92d8bfcbc4d76351 |
17-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Implement bitfield insert by recognizing the following pattern:
1. optional shift left
2. and x, immX
3. and y, immY
4. or z, x, y
==> rlwimi z, x, y, shift, mask begin, mask end
where immX == ~immY and immX is a run of set bits. This transformation
fires 32 times on voronoi, once on espresso, and probably several
dozen times on external benchmarks such as gcc.
To put this in terms of actual code generated for
struct B { unsigned a : 3; unsigned b : 2; };
void storeA (struct B *b, int v) { b->a = v;}
void storeB (struct B *b, int v) { b->b = v;}
Old:
_storeA:
rlwinm r2, r4, 0, 29, 31
lwz r4, 0(r3)
rlwinm r4, r4, 0, 0, 28
or r2, r4, r2
stw r2, 0(r3)
blr
_storeB:
rlwinm r2, r4, 3, 0, 28
rlwinm r2, r2, 0, 27, 28
lwz r4, 0(r3)
rlwinm r4, r4, 0, 29, 26
or r2, r2, r4
stw r2, 0(r3)
blr
New:
_storeA:
lwz r2, 0(r3)
rlwimi r2, r4, 0, 29, 31
stw r2, 0(r3)
blr
_storeB:
lwz r2, 0(r3)
rlwimi r2, r4, 3, 27, 28
stw r2, 0(r3)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17078 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 2d4c98d79b5526aaf94b87d21a7d672f35b183a9 |
16-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly
flag rotate left word immediate then mask insert (rlwimi) as a two-address
instruction, and update the ISel usage of the instruction accordingly.
This will allow us to properly schedule rlwimi, and use it to efficiently
codegen bitfield operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17068 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCInstrInfo.td
|
| 289a49ab7de9eef5d0ede1f07272a4c390174613 |
16-Oct-2004 |
Chris Lattner <sabre@nondot.org> |
ADd support for undef and unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17050 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| e0c83a86b0f609e7212fba6679453b8e5bd7fa33 |
15-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Better codegen of binary integer ops with 32 bit immediate operands.
This transformation fires a few dozen times across the testsuite.
For example, int test2(int X) { return X ^ 0x0FF00FF0; }
Old:
_test2:
lis r2, 4080
ori r2, r2, 4080
xor r3, r3, r2
blr
New:
_test2:
xoris r3, r3, 4080
xori r3, r3, 4080
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17004 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| c982cfad875f64284ae0fb2f822b0867657171eb |
14-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Claim to support machine code emission - return false from
addPassesToEmitMachineCode()
* Add support for registers and constants in getMachineOpValue()
This enables running "int main() { ret 0 }" via the PowerPC JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16983 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| d37faba5b485eefe94e36e0f88da899b8fec42e5 |
14-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Include the real (generated) version of getBinaryCodeForInstr()
* Add implementation of getMachineOpValue() for generated code emitter
* Convert assert()s in unimplemented functions to abort()s so that non-debug
builds fail predictably
* Add file header comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16981 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
|
| bab2adf49691014fedcffe0744e22e0277ddf1b8 |
14-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Make a PPC32-specific code emitter because we have separate classes for 32-
and 64-bit code emitters that cannot share code unless we use virtual
functions
* Identify components being built by tablegen with more detail by assigning them
to PowerPC, PPC32, or PPC64 more specifically; also avoids seeing 'building
PowerPC XYZ' messages twice, where one is for PPC32 and one for PPC64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16980 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| a671f3b1d43507ed5f24e409f83d0db7f99c25ee |
14-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
There is only one field in an instruction, and that is `Inst', the final view of
the instruction binary format, all others are simply operands and should not
have the `field' label
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16978 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 315d3341fd9386a55c9f9ca55e9e76ae3fecfb51 |
14-Oct-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
PowerPC instruction definitions use LittleEndian-style encoding [0..31]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16977 91177308-0d34-0410-b5e6-96231b3b80d8
PC32.td
PC64.td
owerPC.td
|
| d96cb6eaa0a878467d9594a12dfe3a55466706f0 |
13-Oct-2004 |
Reid Spencer <rspencer@reidspencer.com> |
Update to reflect changes in Makefile rules.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16950 91177308-0d34-0410-b5e6-96231b3b80d8
akefile.am
|
| 81f76b324e0b22731d06ed34641032de983428b1 |
11-Oct-2004 |
Reid Spencer <rspencer@reidspencer.com> |
Initial version of automake Makefile.am file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16893 91177308-0d34-0410-b5e6-96231b3b80d8
akefile.am
|
| cbb9812d0df6b64d42c3b2687c877050612a7129 |
10-Oct-2004 |
Chris Lattner <sabre@nondot.org> |
bling bling!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16873 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| bdf69847a9448dc64c6aae9abacf65822af016eb |
08-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Implement logical and with an immediate that consists of a contiguous block
of one or more 1 bits (may wrap from least significant bit to most
significant bit) as the rlwinm rather than andi., andis., or some longer
instructons sequence.
int andn4(int z) { return z & -4; }
int clearhi(int z) { return z & 0x0000FFFF; }
int clearlo(int z) { return z & 0xFFFF0000; }
int clearmid(int z) { return z & 0x00FFFF00; }
int clearwrap(int z) { return z & 0xFF0000FF; }
_andn4:
rlwinm r3, r3, 0, 0, 29
blr
_clearhi:
rlwinm r3, r3, 0, 16, 31
blr
_clearlo:
rlwinm r3, r3, 0, 0, 15
blr
_clearmid:
rlwinm r3, r3, 0, 8, 23
blr
_clearwrap:
rlwinm r3, r3, 0, 24, 7
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16832 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| b816f0298d21d258af07d6fe5909589b9b9ecba2 |
08-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Several fixes and enhancements to the PPC32 backend.
1. Fix an illegal argument to getClassB when deciding whether or not to
sign extend a byte load.
2. Initial addition of isLoad and isStore flags to the instruction .td file
for eventual use in a scheduler.
3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
that we can emit the PowerPC shifted immediate instructions far more
often. This allows us to emit the following code:
int foo(int x) { return x | 0x00F0000; }
_foo:
.LBB_foo_0: ; entry
; IMPLICIT_DEF
oris r3, r3, 15
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16826 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PC64ISelSimple.cpp
PCInstrInfo.td
|
| cb90de37a720b0b00d6303b49b8df6d5ac5f34f9 |
08-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Add ori reg, reg, 0 as a move instruction. This can be generated from
loading a 32bit constant into a register whose low halfword is all zeroes.
We now omit the ori after the lis for the following C code:
int bar(int y) { return y * 0x00F0000; }
_bar:
.LBB_bar_0: ; entry
; IMPLICIT_DEF
lis r2, 15
mullw r3, r3, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16825 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.cpp
|
| 5a181c848bc9994265ef27d3f9fc50144968f61b |
08-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Remove unnecessary header include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16824 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| 7c348e1c9f0b905a189e0c6ad870fff5ef296ad0 |
06-Oct-2004 |
Chris Lattner <sabre@nondot.org> |
Correct some typeos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16770 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 35b020df39c5ddddbb27b5cbebb1def4cae3c28a |
06-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Turning on fsel code gen now that we can do so would be good.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16765 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 087d5d92f1df677848fcf6a8bcb0757e5bddf3fa |
06-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Implement floating point select for lt, gt, le, ge using the powerpc fsel
instruction.
Now, rather than emitting the following loop out of bisect:
.LBB_main_19: ; no_exit.0.i
rlwinm r3, r2, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f2, f2, f1
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fcmpu cr0, f1, f4
bge .LBB_main_64 ; no_exit.0.i
.LBB_main_63: ; no_exit.0.i
b .LBB_main_65 ; no_exit.0.i
.LBB_main_64: ; no_exit.0.i
fmr f2, f1
.LBB_main_65: ; no_exit.0.i
addi r3, r2, 1
rlwinm r3, r3, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f4, f4, f1
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3)
fcmpu cr0, f1, f5
bge .LBB_main_67 ; no_exit.0.i
.LBB_main_66: ; no_exit.0.i
b .LBB_main_68 ; no_exit.0.i
.LBB_main_67: ; no_exit.0.i
fmr f4, f1
.LBB_main_68: ; no_exit.0.i
fadd f1, f2, f4
addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
fmul f1, f1, f2
rlwinm r3, r2, 3, 0, 28
lfdx f2, r3, r28
fadd f4, f2, f1
fcmpu cr0, f4, f0
bgt .LBB_main_70 ; no_exit.0.i
.LBB_main_69: ; no_exit.0.i
b .LBB_main_71 ; no_exit.0.i
.LBB_main_70: ; no_exit.0.i
fmr f0, f4
.LBB_main_71: ; no_exit.0.i
fsub f1, f2, f1
addi r2, r2, -1
fcmpu cr0, f1, f3
blt .LBB_main_73 ; no_exit.0.i
.LBB_main_72: ; no_exit.0.i
b .LBB_main_74 ; no_exit.0.i
.LBB_main_73: ; no_exit.0.i
fmr f3, f1
.LBB_main_74: ; no_exit.0.i
cmpwi cr0, r2, -1
fmr f16, f0
fmr f17, f3
bgt .LBB_main_19 ; no_exit.0.i
We emit this instead:
.LBB_main_19: ; no_exit.0.i
rlwinm r3, r2, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f2, f2, f1
fsel f1, f1, f1, f2
addi r3, r2, 1
rlwinm r3, r3, 3, 0, 28
lfdx f2, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f4, f4, f2
fsel f2, f2, f2, f4
fadd f1, f1, f2
addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
fmul f1, f1, f2
rlwinm r3, r2, 3, 0, 28
lfdx f2, r3, r28
fadd f4, f2, f1
fsub f5, f0, f4
fsel f0, f5, f0, f4
fsub f1, f2, f1
addi r2, r2, -1
fsub f2, f1, f3
fsel f3, f2, f3, f1
cmpwi cr0, r2, -1
fmr f16, f0
fmr f17, f3
bgt .LBB_main_19 ; no_exit.0.i
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16764 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 1f49e868aad763540be5e2076b5af6dbff5bf1c1 |
29-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
Generate better code by being far less clever when it comes to the select instruction. Don't create overlapping register lifetimes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16580 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 1b99fd3e8a352c078d52f8648273cc6d1d5cd884 |
29-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
improve Type::BoolTy codegen by eliminating unnecessary clears and sign extends
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16578 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| a41fc77ae40db49d711fc6f9c43b704a3b408e60 |
29-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
To go along with sabre's improved InstCombining, improve recognition of
integers that we can use as immediate values in instructions.
Example from yacr2:
- lis r10, -1
- ori r10, r10, 65535
- add r28, r28, r10
+ addi r28, r28, -1
addi r7, r7, 1
addi r9, r9, 1
b .LBB_main_9 ; loopentry.1.i214
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16566 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| da721e74f87c3098bdb1373a7a1c7aef4cf7d574 |
27-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
Correct some BuildMI arguments for the upcoming simple scheduler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16519 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PC64RegisterInfo.cpp
PCRegisterInfo.cpp
|
| 645495d2e6a36644d9d5e4bd08a7665e6fc195e8 |
23-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix the last of the major PPC GEP folding deficiencies. This will allow
the ISel to use indexed and non-zero immediate offsets for GEPs that have
more than one use. This is common for instruction sequences such as a load
followed by a modify and store to the same address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16493 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| a2de102a5bd43131dd0ee5c5498cb18ee0ac4282 |
22-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
add optimized code sequences for setcc x, 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16478 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCAsmPrinter.cpp
PCInstrInfo.td
|
| 540c82a7003c09f62cb863a32e8ad49bed18316e |
21-Sep-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
s/ISel/PPC64ISel/ to have unique class names for debugging via gdb because the
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16471 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelSimple.cpp
|
| a1dca55a3ab450ca3b0b361d6a3e6f21116b2f3a |
21-Sep-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
s/ISel/PPC32ISel/ to have unique class names for debugging via gdb because the
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16470 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| b228657acc4afbdc74dc523e9f465d08935f9e8d |
14-Sep-2004 |
Chris Lattner <sabre@nondot.org> |
Revamp the Register class, and allow the use of the RegisterGroup class to
specify aliases directly in register definitions.
Patch contributed by Jason Eckhardt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16330 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 20136a21ba5ae64f97ed22ee0f59259209fa233c |
06-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
Add 64 bit divide instructions, and use them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16198 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelSimple.cpp
PCInstrInfo.td
|
| 3e0b51ab3ba2b8e411fc9cedb7e762068671691b |
05-Sep-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Change PPC32AsmPrinter => PowerPCAsmPrinter since it is now shared between
Darwin and AIX and is not 32- or 64-bit specific
* Bring back PowerPC.td as a result, to make it use the `PowerPC' class name
* Adjust Makefile accordingly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16174 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
PCAsmPrinter.cpp
owerPC.td
|
| b986b7de5090d7ae4d91959f508f7a2f171466e8 |
05-Sep-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Renamed PPC32AsmPrinter.cpp => PowerPCAsmPrinter.cpp as the Darwin and AIX asm
printers are now unified into one file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16173 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
|
| a11c2e8fb99bb93f618894aaa92b5d4c6c2e4ea6 |
04-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
Include MathExtras.h to fix build breakage, thanks to Vladimir
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16164 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| ed42853be1ef530890043da7c8966dc6678cf9bf |
04-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
All PPC instructions are now auto-printed
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16163 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PC32AsmPrinter.cpp
PC32ISelSimple.cpp
PC64AsmPrinter.cpp
PCAsmPrinter.cpp
PCInstrFormats.td
PCInstrInfo.td
PCTargetMachine.cpp
PCTargetMachine.h
owerPCTargetMachine.h
EADME.txt
|
| b7a8f2cdaa3db15861c7f06238fcacc4b10b74f3 |
02-Sep-2004 |
Nate Begeman <natebegeman@mac.com> |
Convert remaining X-Form and Pseudo instructions over to asm writer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16142 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PC32ISelSimple.cpp
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCInstrFormats.td
PCInstrInfo.td
|
| 551ccae044b0ff658fe629dd67edd5ffe75d10e8 |
02-Sep-2004 |
Reid Spencer <rspencer@reidspencer.com> |
Changes For Bug 352
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16137 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PC32ISelSimple.cpp
PC64AsmPrinter.cpp
PC64ISelSimple.cpp
PC64RegisterInfo.cpp
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCCodeEmitter.cpp
PCRegisterInfo.cpp
PCTargetMachine.cpp
|
| cc8bd9ca7c4991774e40c9d8974ff48ad1a60d38 |
31-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
convert M and MD form instructions to generated asm writer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16121 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 07aada8b0fcac511424623a632dec909e40cd201 |
30-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Move yet more instructions over to being printed by the generated asm writer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16112 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
PCInstrFormats.td
PCInstrInfo.td
|
| 6b3dc55ef84946935bda6964352fb6e44a60721c |
30-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Convert A-Form instructions to auto-generated asm writer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16107 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| d332fd54f57e4d91267d7f4e4ee8d35003c7ef78 |
30-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Improvements to int->float cast code for PPC-64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16105 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelSimple.cpp
PCInstrInfo.td
EADME.txt
|
| f2f0781a109f0a9fe0c3597d2bb1c995de2dab4a |
29-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Implement the following missing functionality in the PPC backend:
cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite. Fixes Regression/casts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16081 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCInstrInfo.td
EADME.txt
|
| 5709998993cade99e4aeda1c9d44a1bdf54aa720 |
27-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Register sizes are in bits, not bytes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16070 91177308-0d34-0410-b5e6-96231b3b80d8
PC64RegisterInfo.cpp
PCRegisterInfo.cpp
|
| 0e5e5f56bde3556aa231bf19f7fc9b62c31a2fcc |
22-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Kill a majority of unnecessary sign extensions for byte loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15991 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 1f4a132599974d448cbaa4519006d38ce9b1bf16 |
22-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Don't hard code the offset of the saved R31 in functions with frame pointers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15990 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.cpp
|
| a96c4af7f1c75ec9b964fe84d980f01ae5c136c1 |
21-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Back out branchless SetCC code. While it helped a lot in some cases, it
hurt a lot in others. Instead, improve branching version of SetCC and
Select instructions. The old code will be in CVS should we ever need to
dig it up again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15979 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 608034ec1a11c5b546f20775736652bcaf30049c |
21-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Switch from bytes to bits for alignment.
Also, change GPRC for PPC32 to align on 32-bit boundary instead of 64-bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15975 91177308-0d34-0410-b5e6-96231b3b80d8
PC32RegisterInfo.td
PC64RegisterInfo.td
|
| 8edcd8465361f3aa29082e1b1f2a1c88afc0836a |
21-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Reduce uses of getRegClass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15968 91177308-0d34-0410-b5e6-96231b3b80d8
PC64RegisterInfo.cpp
PCRegisterInfo.cpp
|
| 12585baf1a086f7d54e0ac963e3b0e7b6792b80c |
21-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Fix warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15964 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| c3306120cc66b1c5bc73bd0e95e1f613e27b12dc |
21-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Move XForm instructions over to the auto-generated asm writer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15962 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
PCInstrFormats.td
PCInstrInfo.td
|
| b65eadb7f50c3e4c67efea4901e96b334d69700e |
20-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
remove some things from the todo list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15956 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| f9088885539eb6daab8a5c95e29d609ce4fefaf0 |
20-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Do not register ppc64 yet, as it breaks the SparcV9 backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15955 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| b47321ba2bd9dcd45af187bf55e850f2086d9723 |
20-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Implement code to convert SetCC into straight line code where appropriate. Add necessary instructions for this transformation to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15952 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCInstrInfo.td
|
| 43f20a56b28c52339d2a007e88043fa42744641b |
19-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix opcodes being printed in caps (the more general fix may be `AsmWriter')
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15932 91177308-0d34-0410-b5e6-96231b3b80d8
PC64AsmPrinter.cpp
|
| 1601d9c1f0c4045d68e38986780fa2ff4098836c |
19-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Stack space for argument passing is 32 regardless of 32- vs. 64-bit arch.
Thanks to Nate Begeman for pointing this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15930 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelSimple.cpp
|
| 983e92dc0db2cd86cc53fe03a33fc1d4758b1f43 |
19-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
LR needs to be saved at 16-byte offset on a 64-bit arch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15929 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
PCTargetMachine.cpp
|
| 4debafbea461a756481eacf72d3372a55ff1d8af |
19-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
On 64-bit PowerPC, pointers are 8 bytes, so parameter area offset is 48, not 24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15928 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelSimple.cpp
|
| d2cbb871d06e514ead12aa5b3af47ce44d8ab113 |
19-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
This PHI has 4 additional operands, not 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15926 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 95ab78af3cf0d440f159c2d549e0564b74f12364 |
19-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Use the appropriate 64-bit register description file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15922 91177308-0d34-0410-b5e6-96231b3b80d8
PC64.td
|
| 5e9867e71c8a099b470a6ac3b794b161c3035a63 |
19-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix more remaining 32-bit vestiges of PowerPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15919 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelSimple.cpp
|
| cc55ad5fe9ce5d971d9d88527e551ca84265c646 |
19-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix another vestige of the 32-bit PowerPC backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15918 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelSimple.cpp
|
| ab566eaa682484fa94f58ff784d0360ecda031af |
19-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Correct character prepended to global symbols ('.'), use Mangler consistently
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15917 91177308-0d34-0410-b5e6-96231b3b80d8
PC64AsmPrinter.cpp
|
| 1c514ec89dc1fe01adf591584755d0c3ff622361 |
19-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Eliminate global base register, r2 is used for that on AIX/PowerPC
* Fix bug from 32-bit PowerPC days of 2-register long split
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15916 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelSimple.cpp
|
| 85aa4d0cc5ed00b875a8c9814ad25cc39199fbc5 |
19-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Wrap long lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15915 91177308-0d34-0410-b5e6-96231b3b80d8
PC64RegisterInfo.cpp
|
| 1e67d4d7bae24793de849a5a97f7e194fd2f741a |
19-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Convert casts that will have no effect into move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15914 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 81d265d692f0043bdbc9eab9cf833ead06a88ad7 |
19-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Clean up floating point instruction selection.
Change int->float cast code to put conversion constants in constant pool.
Shorten code sequence for constant pool fp loads.
Remove LOADLoDirect/LOADLoIndirect psuedo instructions and tweak asmwriter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15913 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PC32ISelSimple.cpp
PC64ISelSimple.cpp
PCAsmPrinter.cpp
PCInstrInfo.td
|
| f746a7d09b219619b16ffa875e762d6e24868d6f |
18-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Rename var
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15897 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| 5069438763391b78a434a6e2a6d04418c4f88530 |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
This file is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15893 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC.td
|
| 69d485e64689533c80e62f530968ca6bf1eef864 |
17-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Start using alignment output routines from AsmPrinter.
Changes to make this more similar to the X86 asmprinter
Fix overalignment of globals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15891 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| 5676310c5dd8c31a6a42eecdf3621df52801558b |
17-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Print comments with ;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15881 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| 07a73755d365af178050d3945c9c3dcdf2576ea0 |
17-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Re-fix hiding the Frame Pointer from the register allocator in functions
that have a frame pointer. This change fixes Burg. In addition, make
the necessary changes to floating point code gen and constant loading after
Chris Lattner's fixes to the asm writer. These changes fix MallocBench/gs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15873 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PC32RegisterInfo.td
PC64RegisterInfo.td
|
| 79835d9f9fd6890249414c55b5f4fd80a355eb65 |
17-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Use the emitGlobalConstant defined in AsmPrinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15869 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| b462e47d2d706cea7d8035c155b0f4f25d58a8f9 |
17-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
New, more general, interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15866 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PC64AsmPrinter.cpp
PCAsmPrinter.cpp
|
| 9e36843964abce1e4f2db23b0b2c3ec8490fe601 |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Rewrite targets/rules to generate files for just PowerPC or PPC{32,64}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15862 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 8283ec7c1cb7ec34e5393c553df3edbaba671693 |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Register classes are target-dependent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15861 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 6316181ee0b4a9f1ea992f9b90ff1b48382c0b8a |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
#include <map> is not necessary here
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15860 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
|
| 1dcddfefbda4f76730b7d60623370a37d593aed5 |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
`PowerPC' is no longer a real target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15859 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC.td
|
| f2f8cfb945e5fc20a3793cf715d380cebd8ade98 |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Move variables and methods which need PPC{32,64}* distinction to subclasses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15858 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCTargetMachine.h
|
| 66aa3e0e8baeb4074ced9f4427c89145cc91550b |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
No need for an `is64bit' flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15857 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| a2a27b3c85d56495268c5426442fb9e356a885f9 |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
PowerPCInstrInfo and PowerPCRegisterInfo have gone away; they are replaced
by 32- and 64-bit customized files, named appropriately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15856 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCInstrInfo.cpp
owerPCRegisterInfo.cpp
|
| 08dde0ba85f7f7e70293fd9075a0df99c32de29b |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Consistently name passed with 32 or 64 in their name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15855 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
|
| 3d58b8f531a32d329cddb714bffc47914890343c |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
PowerPCRegisterInfo no longer takes a bool to differentiate 32 vs 64 bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15854 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.h
|
| db50bd3e7ae75f15107740acefb7c0eb357c929f |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
The PowerPCInstrInfo class has gone away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15853 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCInstrInfo.h
|
| 363dd073202c40d019415719bfeaf9a40c9e1cac |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
PowerPCInstrInfo has gone away, PPC32 and PPC64 share opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15852 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| adde6994ac8b29ae75ea9edad310c673dfbb96ec |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
PowerPC 32-/64-bit split: Part II, 64-bit customizations on PowerPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15851 91177308-0d34-0410-b5e6-96231b3b80d8
PC64.td
PC64AsmPrinter.cpp
PC64ISelSimple.cpp
PC64InstrInfo.cpp
PC64InstrInfo.h
PC64RegisterInfo.cpp
PC64RegisterInfo.h
PC64RegisterInfo.td
PC64TargetMachine.h
|
| f2ccb77ee9d8ab35866dae111fa36929689c7511 |
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15850 91177308-0d34-0410-b5e6-96231b3b80d8
PC32.td
PC32AsmPrinter.cpp
PC32ISelSimple.cpp
PC32RegisterInfo.td
PCAsmPrinter.cpp
PCInstrInfo.cpp
PCInstrInfo.h
PCRegisterInfo.cpp
PCRegisterInfo.h
PCTargetMachine.h
|
| 469ab79584cd31d9f632988abccefc16c7a215e0 |
17-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Print float constants as 4 byte values.
Also, fix endianness problems when cross compiling from little-endian host.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15847 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| 505e783d8cecda3262eb5ef24326ef2e74da2ce3 |
17-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Make sure to put an _ prefix on all identifiers!
Also, add some (currently disabled) code to print float's as 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15846 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| 416ca3384afcd4277b41c230736eb0a4552165f7 |
17-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
More changes to make PPC32 and X86 more similar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15842 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| 36aacdb974a65e1f5c76c38a008a01c3f44202d9 |
17-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Minor changes to make the diff be nothing against the X86 version
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15841 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| a3840795a58b3fe3c7d986bfa20951e8d5e1d6e2 |
17-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Finegrainify namespacification
Start using the AsmPrinter base class to factor out a bunch of code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15840 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| b6482069f034afebc0355fc438e0351c9a2edf1f |
16-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
There is no need for a cast here
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15810 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
|
| 746a49516c7c8a9bb0f5fc1051e1768086c4b8a9 |
16-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Update the current state of the world
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15809 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 7e0fd576d30518d2b68df1d7bf7f6b16387d165c |
16-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix typo of the word 'implicit' I made resolving a CVS conflict. Whoops!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15808 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 1cffdf0798eb2bb495bc234b27f9455dbb476d02 |
16-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix frame pointer handling:
Reserve R0 in store/load from stack slot for building >32k offsets from SP
or FP. This also requires we use R11 rather than R0 for holding the LR
value we want to save or restore. Also, tell the register allocator not
to use R31 (our FP) in functions that have a frame pointer. These changes
fix Burg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15807 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
owerPCRegisterInfo.cpp
|
| 865075ed350ec6cee8ccd6723362dc5aa3823b25 |
16-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix mismatched adjust down/up of SP in functions that contain variable
sized allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15806 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 6ff3f83ef035e1db026d5e49dca5ad273e58af84 |
16-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Insertion methods now return void instead of #instrs inserted. Also, use
more powerful forms of BuildMI to concisify the code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15782 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
owerPCRegisterInfo.h
|
| 57f1b67c347b9ba1f8a1cdc3a55362d4f2aa8653 |
15-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
These methods no longer take a TargetRegisterClass* operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15774 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
owerPCRegisterInfo.h
|
| 8c9b4de5744ea6c4ce8b79e8a55130df268761cd |
15-Aug-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Make this compile on gc 3.4.1 (static_cast to non-const type was not
allowed).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15766 91177308-0d34-0410-b5e6-96231b3b80d8
PCFrameInfo.h
|
| f7bb8c0caa550db44d60637c8ae6cc6dc4a13ad9 |
15-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Add future optimization opportunity
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15760 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 43d64eae53cda02910a68bc211f95daaa1b81e18 |
15-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix float to int codepath by always allocating 8 bytes for the target of a double store; optimize cmplwi generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15759 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 08eceec98df96a0eb0a8afe8b5667c75b659f0db |
15-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Zimm16 is now dead. Its entry is not removed from the enum, to avoid having
to renumber everything. Similar elimination should be applied to other
operand enum values that are only used to format printing in the .s file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15755 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PC64AsmPrinter.cpp
PCAsmPrinter.cpp
|
| 0ea3171fbfaf78672264a9299c33c81c63b2a522 |
15-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Convert all of the DForm_6* operations, which makes all of the Zimm16 users
dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15754 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
PCInstrFormats.td
PCInstrInfo.td
|
| d15575d39f56d1440c7e0005c98094bb6deb6ca4 |
15-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Reenable the CCRC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15752 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 97b2a2e389834ae237641cd068ad03b44eaa1e08 |
15-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Convert the DForm_4 over to the asmprintergen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15751 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
PCInstrFormats.td
PCInstrInfo.td
|
| ad9c242605ae694017e41a4e528a81f9fea291c6 |
15-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15750 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| 7bb424fafcfc3452c209556cd764e60b45ae6a5d |
15-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Print mflr using the asmwriter generator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15749 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
PCInstrInfo.td
|
| ca068e861b7f1184d31f6c8f26f88feb076badf1 |
15-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Replace PowerPCPEI.cpp with target independant PrologEpilogInserter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15746 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCFrameInfo.h
PCTargetMachine.cpp
owerPCPEI.cpp
owerPCTargetMachine.h
EADME.txt
|
| ffde1de597c40ebecdd6479756f101197a844b46 |
15-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Add support for frame pointers, and large offsets from stack and frame pointers. Adopt elimination of MachineFunction& arg from eliminateFrameIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15745 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
owerPCRegisterInfo.h
|
| b0b8b93e58f6e09c2471730ad7113f38ce04098e |
15-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Add indexed forms of load doubleword and load word algebraic for 64 bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15743 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 6d1e2dfd865927d59208ca37cef1a8832619f20b |
15-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix handling of FP constants with single precision, and loading of internal linkage function addresses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15742 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| e59bf59ba55c6bdba82a7126e91f5bb53118e84c |
15-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Add initial support for using the generated asm writer. Also, fix FP constant printing to always print 8 byte intializers. Move printing of LinkOnce stubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15741 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
|
| 14d89d68101e603ff570b9fdbe83a98cf4ee85fc |
15-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Add generation of asm writer from tablegen files to Makefile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15740 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 1c284ac5ec72c86b9ed787b3f4e1a6978c919370 |
13-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Remove an unneeded header and forward declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15722 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.h
|
| b73a711ed7c1da332ae8d22b0defcbdf0411d1a4 |
13-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix siod by switching BoolTy to byte rather than int until CFE changes for
Darwin. Also, change asm printer to output proper stubs for external
functions whose address is passed as an argument to aid in bugpointing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15721 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PC32ISelSimple.cpp
PCAsmPrinter.cpp
|
| 293d88ca8b776f6c8b0d36375458602cb2ae67d5 |
13-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix 177.mesa compilation, don't use floating point regs for base addresses!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15720 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 8cfa427d9c5a95c96658c033e0f348ffd23920f5 |
13-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix llc crasher compiling siod by giving BuildMI the correct number of arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15719 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 5a104b0ec5b392b5f2ba42a774adce4b8668af8a |
13-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Longs are in one register on PowerPC 64; use appropriate instructions to operate on them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15711 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelSimple.cpp
|
| 244e64ead21760aa87438f9d221c6b4f12a7ccf9 |
13-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15710 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| f5f70685b6915682d3f5b89e7c023dea98842b1b |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Disable PPC64 backend by default because LLC cannot choose automatically between
SparcV9 and PowerPC64 without target triples, since they are both 64-bit
big-endian targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15688 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| a1b6ae9d7cf39e4589192eac4ad2288ec29e2de1 |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Correct 64-bit version: blr 1 (not 0)
* BuildMI() can build 0-param instructions (e.g., NOP)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15681 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelSimple.cpp
|
| e4d093c356c7853f7acfd2228dda2ab7c7b3db00 |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Print out full names for non-GPR or -FPR registers
* BuildMI() really *does* handle 0 params!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15680 91177308-0d34-0410-b5e6-96231b3b80d8
PC64AsmPrinter.cpp
|
| cc6b01b1e68cd87807f94a8c51088be9ff096e71 |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Pointers are 8 bytes, hence cLong type on 64-bit PPC
* Fix loading of GlobalValues
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15678 91177308-0d34-0410-b5e6-96231b3b80d8
PC64ISelSimple.cpp
|
| 8e63dcebcc3256a9bf656c21f163b478b82e00a6 |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Eliminate special-casing 14-bit immediate load/store opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15677 91177308-0d34-0410-b5e6-96231b3b80d8
PC64AsmPrinter.cpp
|
| c90f2963c4ba579e28acf458966bb18d0fa6cf5b |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Correctly print out ASCII literal strings on AIX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15674 91177308-0d34-0410-b5e6-96231b3b80d8
PC64AsmPrinter.cpp
|
| ef9468cfe5d3ec033fe95dcaad71717938456945 |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Mark R2 as available for allocation on Darwin/PPC32, but not AIX/PPC64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15673 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 1d3527edbf473d357ee79fb8638e24d1bf992831 |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Move AIX into the llvm namespace to be accessed from RegisterInfo
* Mark InstrInfo with 32 vs. 64 bit flag
* Enable the 64-bit isel and asm printer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15672 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
owerPCTargetMachine.h
|
| a6ecd9ee47ea0a80362c58c4fbd7b29d9b61ee61 |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Set the is64bit flag and propagate it to PowerPCRegisterInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15671 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCInstrInfo.cpp
owerPCInstrInfo.h
|
| dceb4576075546962ac816a05267afbc606234a6 |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Set the is64bit boolean flag in PowerPCRegisterInfo
* Doubles are 8 bytes in 64-bit PowerPC, and use the general register class
* Use double-word loads and stores for restoring from/saving to stack
* Do not allocate R2 if compiling for AIX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15670 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
owerPCRegisterInfo.cpp
owerPCRegisterInfo.h
|
| ca9309f22e626db9019de371cf7b61a7e35d08e2 |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
64-bit instruction selector and AIX-specific 64-bit asm printer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15669 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PC64AsmPrinter.cpp
PC64ISelSimple.cpp
|
| 55eee3dc7aa74164e5e223420855e7740141da56 |
12-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix names of 64-bit CMP*D* opcodes, add LWA and STD* opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15668 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| f1f6cef161f2005c85b5fb54587dcb0b74c6a82a |
11-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add support for 64-bit CMPDI, CMPLDI, and CMPLD opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15667 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 96b611068577140c0619259e5fa09135b1f6d6ed |
11-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add doubleword load/store (64-bit only).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15665 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 9582822341bd8a7847b1f796be19c621a74bd616 |
11-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Hyphenate ##-bit and remove first-person from comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15663 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 7a4fe9be7ee67dafa8d172d16bc6799e599ad495 |
11-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15662 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PC32.h
PC32ISelSimple.cpp
PC32JITInfo.h
PC32TargetMachine.cpp
PC64.h
PC64JITInfo.h
PC64TargetMachine.cpp
PC64TargetMachine.h
PCTargetMachine.cpp
PCTargetMachine.h
owerPCTargetMachine.h
|
| 74a806cd3dc7ba2d64705b91b40616ca53925924 |
11-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Fix a case where constantexprs could leak into the PPC isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15661 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 8d963e602b752f6c071063a5e769f6058018c733 |
11-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix 255.vortex by using getClassB instead of getClass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15648 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
|
| 0145881cb985b2165bbd1aded733e0183c50e63a |
11-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Breaking up the PowerPC target into 32- and 64-bit subparts, Part III: the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15636 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCJITInfo.h
PCTargetMachine.cpp
owerPCAsmPrinter.cpp
owerPCCodeEmitter.cpp
owerPCISelSimple.cpp
owerPCInstrInfo.h
owerPCTargetMachine.h
|
| c0f6420b96d88e67253a20a866236575dccbfd25 |
11-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Breaking up the PowerPC target into 32- and 64-bit subparts: Part II: 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15635 91177308-0d34-0410-b5e6-96231b3b80d8
PC64.h
PC64CodeEmitter.cpp
PC64JITInfo.h
PC64TargetMachine.cpp
PC64TargetMachine.h
|
| 3d9a6c2842599b9d8659ae97e19c413d435d7b34 |
11-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Breaking up the PowerPC target into 32- and 64-bit subparts, Part I: 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15634 91177308-0d34-0410-b5e6-96231b3b80d8
PC32.h
PC32AsmPrinter.cpp
PC32ISelSimple.cpp
PC32JITInfo.h
PC32TargetMachine.cpp
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCTargetMachine.h
|
| 5b5708106e409d2b8bb23335f7de8dda361dca3e |
11-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15631 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PC32ISelSimple.cpp
PCAsmPrinter.cpp
PCBranchSelector.cpp
PCInstrFormats.td
PCRegisterInfo.td
owerPCAsmPrinter.cpp
owerPCISelSimple.cpp
owerPCInstrInfo.cpp
owerPCInstrInfo.h
owerPCPEI.cpp
owerPCRegisterInfo.cpp
|
| 698fbd5b940c7ea0b3855499c879a465385f6f52 |
10-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Fix file header to use tablegen emacs mode instead of c++
* Wrap long line to 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15630 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC.td
|
| b64af918cbf6a18d1bed4c588622bee75b1107c8 |
10-Aug-2004 |
Nate Begeman <natebegeman@mac.com> |
Fix casts of float to unsigned long
Replace STDX (store 64 bit int indexed) with STFDX (store double indexed)
Fix latent bug in indexed load generation
Generate indexed loads and stores in many more cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15626 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCInstrInfo.td
owerPCISelSimple.cpp
EADME.txt
|
| 42efb87410b55ad39d1f34257fdc59a5da7e4070 |
10-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
DForm 5/6 extended mneumonics take 3 arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15620 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| a91f53634ccec6df7e63d0488cc6b6c457829215 |
10-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix DForm_4: format is `op r, r, i'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15613 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| b05daff7faf694a8d18f00ef00132384c8207cd4 |
10-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Stub definition of the PowerPC CodeEmitter class; this isn't functional (yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15600 91177308-0d34-0410-b5e6-96231b3b80d8
PCCodeEmitter.cpp
owerPCCodeEmitter.cpp
|
| 7103fba019a8c6e2436d6d5d0e708b98cb5b3f83 |
10-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
CodePrinter -> AsmPrinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15599 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
PCTargetMachine.cpp
owerPCAsmPrinter.cpp
|
| 812402019264506bea49749b23d0ead1be9fde7c |
09-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove ClassPrefix variable as it's no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15586 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 929072eb0460f3ea090cf68e4300a5a5e34c6e97 |
09-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Define a ClassPrefix for PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15580 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| f588548a867e3af493054396409020e826a3076e |
09-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Generate a code emitter for PowerPC as well, this will be used in the JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15578 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 4ad7d1bee7405d1eb323e71671026ec7d8cd7405 |
09-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Use instruction formats as defined in the PowerPC ISA manual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15577 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 524a60587d1505aa441400a0065d60d8203aac82 |
09-Aug-2004 |
Reid Spencer <rspencer@reidspencer.com> |
Fix stack size processing now that the return address isn't an implied
push onto the top of the stack like x86, which uses the local area
offset. This will allow the removal of PowerPCPEI.cpp soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15573 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 3ea934668b77f5126e8de0648b8d21a128971e11 |
06-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Changes commited for Nate Begeman:
Use a PowerPC specific prolog epilog inserter to control where spilled
callee save regs are placed on the stack.
Get rid of implicit return address stack slot, save return address reg
(LR) in appropriate slot
Improve code generated for functions that don't have calls or access
globals
Note from Chris: PowerPCPEI will eventually be eliminated, once the
functionality is merged into CodeGen/PrologEpilogInserter.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15536 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PC32ISelSimple.cpp
PCTargetMachine.cpp
owerPC.td
owerPCISelSimple.cpp
owerPCPEI.cpp
owerPCRegisterInfo.cpp
EADME.txt
|
| aaf10ab5a2c2c9ddcc0f4d63dfd5d434118dacc6 |
06-Aug-2004 |
John Criswell <criswell@uiuc.edu> |
Added Louis Gerbarg. Louis is given credit in the CREDITS.TXT file, so I
assume Louis also holds copyright.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15534 91177308-0d34-0410-b5e6-96231b3b80d8
ICENSE.TXT
|
| 2c2ba762a332cd01b898080998422e05e10e6246 |
05-Aug-2004 |
John Criswell <criswell@uiuc.edu> |
Add additional copyright notice for the PowerPC backend.
Thanks Nate!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15531 91177308-0d34-0410-b5e6-96231b3b80d8
ICENSE.TXT
|
| 2f947865cba52eb555728f98c78a1f539552e55b |
05-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Simplify makefile by combining all TableGen dependencies into one variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15527 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| dee0f9b94c1b61cb36d623605f5ab4cbb3948b33 |
04-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Align dependencies so they don't hurt the eyes to look at them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15504 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 7338ae5b88cc527d4e763926d9b9adeb997042a0 |
04-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove unused instruction classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15501 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| db01356c1599220655ad021cb7ea686860362103 |
04-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Make tablegen targets depend on PowerPCInstrFormats.td as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15500 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| 6173cd9c163de5288aa8c3a241f21515f60c8b20 |
04-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
getValues does not exist
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15495 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 68f34599949d1fdf88833164e9a3b2ca6944a7fb |
03-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove unused opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15447 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 37dcae63ebd2b3030468e6bb210c404db1766ae4 |
02-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Use simpler instruction templates to define instructions
* Fix several extended opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15423 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| c681a4e476acefb08d26c3d221a5cf5e99640a75 |
02-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Replace patterns 0, 4, and 5 with simpler heirarchical definitions that use the
official PowerPC instruction format lingo: X- and D-form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15422 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
|
| 28791dd17f40d9e71a53f19a06ffacf13ab2b2cb |
02-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Separate instruction formats from instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15414 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrFormats.td
PCInstrInfo.td
|
| 88f8f9226f5e62ad50acf7683d9c2691aa190103 |
30-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Conditional save/restore of LR disabled as it's not quite correct
* sumarray2d fixed: large fixed-size alloca
* make is now compileable
* Re-organized tests to fit them under proper headings
Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15347 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| a9c528f0aa1a4cd27a8fb5feda39c9ccbae73804 |
30-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Do not mark LR as callee-save: not quite correctly done. Patch: Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15346 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC.td
|
| 4ffddc5228f679323599158b77435b39de8e944b |
30-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Temporarily suspend LR save/restore optimization as it is not quite correct
* Implement large fixed-size allocas Entire patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15345 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 83660c5aed4902dd218ba0f730dc7801b99b30cb |
28-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Minor corrections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15309 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 8b88d906a2a5bd4a6824c83ae1ee4f3aae54664d |
28-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add notes on bug involving casting ulong -> double, thanks to Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15307 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| a0af38c46a665a58c733062955e1cb7f244569f7 |
28-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Simplify loading (un)signed constants to registers, patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15306 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| b7697a6dd27b747dd186022d67ff43d45125d365 |
28-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove an extra 8 byte distance penalty. Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15305 91177308-0d34-0410-b5e6-96231b3b80d8
PCBranchSelector.cpp
|
| f63bc199c65a19952c480eb4d0c592dfd58c966f |
28-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Find longs by type, not by their primitive size being 64. Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15304 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 8b29776d680f1b80b7471291b7d41df753d28511 |
28-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
LI can only take signed values, so values > 32767 can only be loaded with ORI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15299 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| b9b8ba58e7024917b6a44e776445cf6649bb83c2 |
28-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Reorganize tests to place them in proper directories.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15298 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 56d38c6ca13d3d2c96af474b39ab7180356134a1 |
28-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
UnitTests 2003-05-26-Shorts and 2003-07-09-LoadShorts have been fixed;
2003-05-22-VarSizeArray is broken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15297 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| af313fb188a8d03ad863de81fa9f87b0a76579fc |
28-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix printing of immediate operands by looking at their operand types in
the TargetInstrInfo. This fixes UnitTests 2003-05-26-Shorts and
2003-07-09-LoadShorts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15296 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 8c02c1cbb89c69a6716ae4201ad62113562cbb69 |
28-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Renamed files:
* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15295 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
PCInstrInfo.td
PCRegisterInfo.td
owerPC.td
|
| 4ce5ce25e8d5157225a3d9a36b8d4260fff7b284 |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Branch selection support implemented by Nate Begeman for long branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15288 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| ab96790f2c343fe9cb97a425825adaf794b1ef98 |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Correctly print out long branches, assert on finding pseudo instr COND_BRANCH
Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15286 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| bd2c8705396b007dd236629fec1ee90aed37ff5d |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Run the branch selection pass right before the asm printer.
Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15285 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 596c23134bbb8e62be1c8cc53f09149f9829454e |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove empty unused method processFunctionBeforeFrameFinalized()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15284 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
owerPCRegisterInfo.h
|
| f228fa05803e84f0439d1793125619218fb24154 |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add COND_BRANCH pseudo instruction, patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15283 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| fa20a6dfd78c0f53c6a2c69ff1de97b544a303ab |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Build COND_BRANCHes which may become long or short, decided by a later pass.
Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15282 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 8aebe9f96cc7a16e4bacb043a4cc022aa706fa1d |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Moved definition of invertPPCBranchOpcode() into PowerPCInstrInfo class.
Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15281 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCInstrInfo.h
|
| 999d9cfde515a6735b376071090b89efb25cf8e6 |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add PowerPCBranchSelector to discover which are `long' branches.
Contributed by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15280 91177308-0d34-0410-b5e6-96231b3b80d8
PC.h
PCBranchSelector.cpp
|
| c91bc304366399fab9eecd338725ee90f5519778 |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fixed saving/restoring LR unconditionally, only done as necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15275 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 9a771d55fe7de74e3e30421869c665b21c1072a0 |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Save and restore LR just like any other register and ONLY if we actually modify
it (due to calls or globals access). We now compile `void empty(){}' to `blr'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15274 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| e862f306fb630f0301bb04d8a5a2868db4f7fcd6 |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
LR is a 32-bit int reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15273 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 53f567817caa1bf3346484a35e2ea69be2dd8210 |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
MovePCtoLR (which is `bl' in disguise) modifies LR implicitly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15272 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 08cc7b30bbc1a2885755865073c216794231c9de |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Register LR is callee-saved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15271 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC.td
|
| 435c785803b98f5e6f837a4564ddc4e78b22d659 |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add IMPLICIT_DEF of LR for branch-and-link instrs (calls and global accesses)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15270 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| ab640a572827b40eebc9963f3f409cf3ea273d46 |
27-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Do not store the stack pointer if the stack size is 0.
Also, convert C-style comments to C++ and make sure code wraps at 80 cols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15245 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 3ada3e3f823179f6d077abbb6e7e885222175e7d |
26-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
ADDI can take several forms, including:
addi r1, r2, 0
addi r1, <frame index #n>, 0
so we must check for the second parameter being a register for this instruction
to be considered a reg-to-reg copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15244 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCInstrInfo.cpp
|
| 8790d474533ac9b67798241dfb373f68ed37eaff |
26-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
assert() on MachineInstr properties instead of checking them dynamically
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15243 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCInstrInfo.cpp
|
| 774a297c831b35a91a3138ce4c0da45ed189b20d |
26-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Recognize `addi r1, r2, 0' a move instruction
* List formats of instructions currently recognized as moves
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15242 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCInstrInfo.cpp
|
| b097f216b0fe35303f519fda6cf0dceda0587d44 |
26-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Rewrote casts
* Implemented GEP folding
* Dynamically output global address stuff once per function
* Fix casting fp<->short/byte
Patch contributed by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15237 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| cf8d24439458ac77e3d3565b51964e0a8802b339 |
26-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Increment the label number in runOnFunction() rather than while printing out
some instruction. Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15236 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| bb966a4a592091b7206027a1090c92ad52f0f3e8 |
26-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
More notes on bugs, unimplemented features, and suggested code improvements.
Written by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15235 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 3c616b45e7f843c64426da74076e6d9e31f4c904 |
26-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix subtracting values > 2^15 in the prologue/epilogue, by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15234 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 1be339ac4c7f1dcf32cf6f2d35bfe3d9c62a35d1 |
24-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Running list of bugs, unimplemented features, currently broken tests, until we
have a nightly tester set up for PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15147 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 472254485534bb32da9ecab680e523668766a6ac |
24-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Eliminate spurious empty space; make code easier to page through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15146 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 1245c3593575d0a754cc679f9964fc35f841feee |
23-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Simplify boolean test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15145 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| b160d1f9f7c39e00f103096afb69aca144ef5b6e |
23-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Implement casting a floating point to 32-bit unsigned value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15143 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| e2eceb5c739285a6c507ac766ab2807429e13101 |
23-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Codegen of GEPs dramatically improved by folding multiplies and adds
* Function pointers implemented correctly using appropriate stubs
Contributed by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15133 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PC32ISelSimple.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
owerPCISelSimple.cpp
owerPCTargetMachine.h
|
| 9accb24c897879f8e0f3f8ecf3389261a7924bc6 |
23-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Bool alignment on MacOSX/PowerPC is 4 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15122 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 4c14f3384486deea8d8d5c4ce7a1b452a5a1a9a0 |
23-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Change class of BoolTy back to cInt
* Fix indentation back to 2 spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15121 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 2ed17cadb4fb2f7867494702ca58813254fff853 |
22-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Change bool from cInt to cByte (for now)
* Don't allow negative immediates to users of unsigned immediates
* Fix long compares
* Support <const int>, op as a potential immediate candidate
* Fix sign extension of short and byte loads
* Fix and improve integer casts
* Fix passing of doubles as vararg functions
Patch contributed by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15109 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| a31f1f7cb273156a90aa197db9a97946c0e5812c |
21-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Add the lost fix to define the second reg of a 2-reg representation of longs
* Fix opcode RLWNM -> RLWINM since it uses an immediate const shift value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15087 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 17a9000ac81de110eabe222aa6f93a4f14fbfbfe |
21-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Speed up canUseAsImmediateForOpcode() by comparing Operand before
dyn_cast<>ing and checking Constant's value
* Convert tabs to spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15086 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 97a296f743c3cb78ae106a8e4800a5daa0ca6fc9 |
21-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Fix printing of signed immediate values (Nate Begeman)
* Fix printing of `zeroinitializer'
* Fix printing of `linkonce' globals, complete with stubs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15084 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 1013ef52285949d851b5c8782e08c5152f9990a9 |
21-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Fix printing of signed immediate values
* Generation of opcodes that take 16 bit immediates
* Rewrote multiply to be correct for 64 bit values
* Rewrote all the long handling to be correct for PowerPC
* Fix visitSelectInst() to define the upper register of the pair of regs
representing a long value
Patch contributed by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15083 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| e0380e0c4298d6d4c62846dbef4026991cf9336d |
21-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Use addSImm() instead of addImm() for stack offsets, which may be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15081 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 53d9a48855a91d2cb35a4ddd7375fe2d82cbeacf |
21-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add SUBI instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15077 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| cd2273f4a795eacf474adff5b016511032e20a24 |
20-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Shorts are aligned to 2 bytes, bools to 1 byte (in structs).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15048 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| bf417a6d46d6e1e09fd10e20e863d451924bf083 |
20-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Treat external variables similarly to those with weak linkage: load indirect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15047 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 86ddcf9d4feabad01359e487382fb96c60407c4e |
20-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Differentiate between global and weak symbol loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15037 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| ec6319a00c91b000128608c57fd8a7a79adfe51b |
20-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Differentiate between global and weak symbol loads
* Fix functions that take more than 32 bytes of args
* Alignment of doubles in structs is 4 bytes, not 8
* Fix passing long args: rN = hi, rN+1 = lo
* Rewrite signed divide
* Rewrite Intrinsic::returnaddress
Patch courtesy of Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15036 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| e48178e8a652623c5c675f0f9dc495053ca76d2b |
20-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Differentiate between global and weak symbol loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15035 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 5c4544160f9ea80da80ef3f4fd5877284f87981d |
20-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Double alignment in structs is 4 bytes, not 8. Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15034 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| d43b9fd1ae9e46fc52194b06d44c159d9ea148e3 |
20-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix stack frame layout in prologue/epilogue. Patch courtesy of Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15026 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| ba1c1da36ab778fe3c5b9a8c9fb0d0f0b0e0089e |
20-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Move handing of GlobalValues from getReg() to copyConstantToRegister(), this
will avoid extra register-to-register copies. Thanks to Chris for the idea.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15019 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 61114619bcd71c11cf0fcd8d4de36be12406b589 |
20-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Fn args passed in registers are now recorded as used by the call instruction
`-> asm printer updated to not print out those registers with the call instr
All of Shootout tests now work. Great thanks to Nate Begeman for the patch!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15015 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 7e898c3e0409fca30b0b442c76a10971b0636654 |
20-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* cFP class split into cFP32 and cFP64
* Fn args passed in registers are now recorded as used by the call instruction
`-> asm printer updated to not print out those registers with the call instr
* Stack frame layout in prolog/epilog fixed, spills and vararg fns now work
* float/double to signed int codegen now correct
* various single precision float codegen bugs fixed
* const integer multiply codegen fixed
* select and setcc blocks inserted into the correct place in machine CFG
* load of integer constant code optimized
All of Shootout tests now work. Great thanks to Nate Begeman for the patch!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15014 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| a51e4f63015b59b05dd0be5a1987bdfd074bb267 |
18-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Fix infinite loop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14971 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 67910e1eb024bb78cab2f4ffb48c3a79b5647f64 |
18-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
CPR Fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14961 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PC32ISelSimple.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
owerPCISelSimple.cpp
|
| a57b76fece438af3e18398e890c1146497883402 |
17-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
We don't really need to #include IPO.h into this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14911 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| bebde759e51bcae46adcc4b6ea328b2355495b61 |
16-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Use LI(S) to copy constants into registers intead of ADDI(S) as the latter is
a funky way to "use" R0 for a 0-valued operand
* Add IMPLICIT_DEFs for incoming function arguments via registers to help the
register allocator not clobber those registers
* Implement comparisons with longs
* Teach emitSelectOperation() to fold the SetCC operation
Patch contributed by Nate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14901 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| af7f28cdacc68cf155869752a690e03e8675fe7e |
16-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Store all non-volatile int registers R13-31 on the stack, restore on exit
* Fix comment formatting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14900 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| be15f67af735a81f028679b495243f2dceb3d59d |
16-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix code formatting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14899 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCInstrInfo.cpp
|
| 01d46e9c5562cdc8d7514be66343efd31491ad52 |
16-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Implement PowerPCInstrInfo::isMoveInstr(), patch by Nate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14898 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCInstrInfo.cpp
|
| 6b4ea88e83e14de84e3ea185dcf5044be53396c2 |
16-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add prototype for TargetInstrInfo::isMoveInstr()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14897 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCInstrInfo.h
|
| 86fd274790383963f33341aa161da4c888d0fe10 |
16-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Enable allocation of registers r2-r10
* Allocate registers 13-31 backwards (to be able to store them all at once)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14896 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 2bf54389311e371eac556924ce2926ad0d7a10e7 |
16-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add IMPLICIT_DEFS pseudo-instruction; patch by: Nate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14895 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 039ba763d1da901bcd1ef0020a2aa97704c7962a |
16-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
The generated instruction selector isn't (yet) functional
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14894 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
|
| da2b13f694b3866b7201b6ab9596981c9eaab983 |
16-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Output non-lazy linking stubs for external global variables
* Get rid of dead and #if 0'd code
* Minor for loop speed-up: save end iterator instead of querying every time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14893 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 6f14ad1ca0647d0111605f2ac78e0a0756be6fd7 |
16-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Define double alignment as 8 bytes now that assert(DoubleAlignment == PointerSize)
has been eliminated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14891 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 29188c6ff653aa69fac958077b62a06013be98f9 |
16-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Add spaces between words and numbers in comments printed out for longs/floats
* Print out IMPLICIT_DEFS as comments in the assembly, patch by Nate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14890 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 81d54465d9c245bbc3cdf18ef99a50df470ad773 |
16-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
The powerpc is now gone. However it is now just known as the Skeleton target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14877 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC.h
owerPCInstrs.td
owerPCJITInfo.h
owerPCReg.td
owerPCTargetMachine.cpp
|
| 017fdcb76def65c32083fa7e2e4cb1f69b77eed0 |
15-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Revert stuff that I didn't mean to checkin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14844 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
PCTargetMachine.cpp
|
| 76e2df264560b6c5aae1b820a6ccfdf0615bb935 |
15-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Patches towards fixing PR341
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14841 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
PC32ISelSimple.cpp
PCTargetMachine.cpp
owerPCISelSimple.cpp
|
| 5f8cce13486dd9c5e7374c5e467750298791bac8 |
14-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Make sure MTSPR instruction is inserted into the BasicBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14822 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 32caa8de629d9872e50264905b9a29b740c44db7 |
14-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Don't define the same register twice when loading a ConstantPointerRef to a reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14819 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 8d442c2dc4aaf627969b052f597d101761f2a432 |
14-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Fix multiplication by powers of two and otherwise
* Clarify variable name (StoreInst SI instead of LI)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14818 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| a596f8c3aaeba95fa20706bb0c441ff1b3afc8b8 |
13-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Specify that FP arith options have 3 operands
* Correctly load FP constants from the constant pool, should be refactored
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14799 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| d9aa7836e23e518388ed7426ce3d19111074e0bc |
13-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Correctly load FP constants out of the constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14782 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 01eca8d2c2528d16967575320c801930eb9f4e82 |
13-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Implement getModuleMatchQuality and getJITMatchQuality() for PowerPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14780 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
owerPCTargetMachine.h
|
| 68905bb6fc8848b6437057f3998b89cbf5d6f837 |
11-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Delete the allocate*TargetMachine function, which is now dead.
The shared command line options are now in a header that makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14757 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
owerPCRegisterInfo.cpp
|
| 0cf0c3746995e8b95fc055cdf8e7210200cb942d |
11-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Delete the allocate*TargetMachine function, which is now dead .
The shared command line options are now in a header that makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14756 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCTargetMachine.cpp
|
| 71d24aab2d52986cc8203d0c268adb88b0001bc4 |
11-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Make these format a bit nicer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14747 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
owerPCTargetMachine.cpp
|
| d36c970a11633414e56ac1e03010dafa4a63b9c4 |
11-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Auto-registrate target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14745 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
owerPCTargetMachine.cpp
|
| 98599d098f714c3982e6c096bc21a13bb8d3d055 |
11-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Add compilability
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14744 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
owerPCRegisterInfo.cpp
|
| 313efcb88635ce3b8f192d56d4c363eebffb219a |
09-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Add support for indexing into structures, thanks to Chris (x86)
The large diff is because of indentation of a whole region
* Fix querying predecessor blocks in SelectPHINodes(), thanks to Brian (v8)
* Add support for external functions malloc() and free()
* Fix some code indentation
Remember, kids: It's not plagiarism if you "creatively borrow" from your
sources. It's called "research"!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14723 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| c1ef127ae2326d0565163169d361b4b9e145d828 |
09-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Read/write the offset value for stack-relative loads via correct instr operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14722 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| f3f63824238b383946e921328e45246f2dd8bfdb |
08-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add support for __fixdfdi(), __floatdisf(), and __floatdidf() external functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14703 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 0aa97c625bdb47ee6336536222cfdd872a7cd977 |
08-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Use several Function* for external functions instead of a std::map
* Non-const FP values must be loaded into int regs (for vararg fns) via memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14701 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| fc879c336be0c19981a10c909118c6a522f7eada |
08-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Add support for loading FP constants from the constant pool
* Load FP values into int regs as well for vararg functions; without memory ops!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14700 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 05fcd0c891c1cab4b90368094081a96ebf655e96 |
08-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Fix header comment, excise references to X86
* Add suport for printing out references to constant pool indices
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14699 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 2834a4dd1d947461f53df000e2fba65cf99ba63c |
07-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Use a map for caching lookups to external functions (fp div/rem)
* Tabs to spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14673 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| e62cd37c2add34dc6caa9cf9a7a0d5b9836694d7 |
07-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Wrap long lines (comments and code)
* Tabs to spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14672 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrBuilder.h
|
| b093259edde0a0557d27f0925ca06bf10e78ecca |
07-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add fmod() to the Module being compiled so that it gets a stub in the asm file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14670 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| d18a31d2fab7626bc3396106990d982a0b699b38 |
07-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Add support for calling vararg functions (must pass doubles in int regs too)
* Make visitSetCondInst() share condition-generating code with EmitComparison()
* There are 13 FPRs for function-passing arguments, not 8
* Do not rely on registers being sequential, use an array lookup
* In unimplemented switch cases, send an error and abort instead of silent
fall-through
* Add doInitialization() for adding function prototypes for external math fns
* Minor changes: fix indentation, spacing, code clarity
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14653 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 4cf51125007f2c5a32a6de710ba8df094cb441db |
07-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Use the more compact `bl' instead of cryptic (but equivalent) `bcl 20,31'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14652 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| e9c6551fed0a66f050c3c68a6cc0dbe2b254780f |
06-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Add utility functions: convert SetCC => PPC opcode and invert PPC opcode
* If SetCondInst is folded into BranchInst (and it is the only user), do not
emit code for SetCondInst
* Fix assembly opcodes in comments in visitSetCondInst()
* Fix codegen of conditional branches
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14643 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 68a9b04e770c8d871bdc2163e7d53e0763e2d722 |
02-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add FIXME notes for spilling int/fp regs (need to calculate stack space).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14581 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| fab96f0b69da768bf837c8042e522d93701ccccf |
02-Jul-2004 |
Chris Lattner <sabre@nondot.org> |
Fix all of those problems that the PPC backend has running 176.gcc :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14565 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 452069abccca2a2ea2887220aceeedda8bb6b6d7 |
01-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Follow the PowerPC convention of leaving 24 bytes for linking on the stack.
* Also leave space for spilling integer registers (this should be calculated)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14554 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 425ff24bb3cd74a46cad98688547d33a12ea0ab6 |
01-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Get rid of constant-expr handling code: we use the ConstantExpr lowering pass
* Use the SetCC handling code in the format of Brian's V8
* Add FIXMEs where calls to functions are being made without adding them to the
Module first... they cause missing symbols at assembly-time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14553 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| f233a84b3c8f0e4386c7d24acbd6c4d7016fff57 |
01-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Wrap long line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14552 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 15eb0a15e568f46d2d2e56f8785b668fe8b48b13 |
01-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Do not allocate r0 as we use it indiscriminantly in the instr selector.
* Do not define CR register class because we don't (yet) have the i4 type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14551 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 4363bdb0e5d20ebfa5b0a1f703c5a8102e637541 |
01-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Check if operand has an allocated reg before requesting it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14550 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| c661c3001ce27bd6c6a2035a3ad68d0530f00269 |
01-Jul-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Coalesce the handy CALL* alias opcodes with the standard ones
* Congregate more branch-and-link opcodes together
* Mark FP, CPR, and special registers as volatile across calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14511 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| da7515a37879543e77e7e9e12adb33a3816e7e5e |
30-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Allow more registers to be allocated from the general register pool
* Define the condition register class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14510 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| b9e8f97aef725324724d9e59e55dbafec02c79e9 |
30-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Inquire about the number of operands from the instruction directly
* Only check for a register if we are sure the instruction has one allocated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14509 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| ce76db9083900d0998fc0a847d215d92b24dba67 |
30-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Always assume a function may have calls because the printer may add `bl' to get
the PC in a code sequence for global variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14506 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 14d8c7a6a051e2aaa5f419b0959a0d64c297e7e7 |
30-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Don't save LR when outputting globals: it's already saved on the stack once
for the function
* Registers aren't necessarily sequential wrt their enums, don't rely on it
when emitting function arguments into sequential registers
* Remove X86-specific comments about AL/BL/AH/BH/EDX/etc
* Add an abort() for an unimplemented signed right shift
* The src operand for a GEP was never emitted! Fixed.
* We can skip zero-valued GEP indices as they are no-ops.
"Hello, World!" now works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14505 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 61297ee1185fd267471a1cb1fa28c585b51c5e08 |
30-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Stop using BBNumbering, we don't really need it
* Only increment labelNumber once, because it's used by both Load{hi,lo}Addr
* There is no .bss section on PowerPC
* Use .align 2 instead of other random numbers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14504 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| cbcdb9c0a777f2f14784193e19454e5aacf28e2a |
30-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Set up the prologue and epilogue to be more like the manual and GCC output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14502 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 5fa2b028b85beebf8f5565315b2b66647d411968 |
30-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Use LA instead of LWZ for LoadLoAddr
* Specify the isCall bit and caller-save registers for some call instrs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14501 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 8ee0100880ef6fd414cda4d6d04f5940aa4a1822 |
30-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Only allocate non-volatile registers R13-31 (for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14500 91177308-0d34-0410-b5e6-96231b3b80d8
PCRegisterInfo.td
|
| 60f35813fc4ac2a7b86a03024201c734c6a452de |
30-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Lower ConstantExpressions before the code generator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14497 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| e19ca38a3221a84da03be5d818c879bf53073c77 |
29-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Fix saving LR in function prologue
* Adjust epilogue restore sequence to match the PowerPC documentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14480 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 218bec7bd3a2deb94768e298025f07d7682c4377 |
29-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Assembly syntax/comment fixes by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14479 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 1b17438aa8bfba56ed98e6a40db48c5df40de623 |
29-Jun-2004 |
Chris Lattner <sabre@nondot.org> |
The code generator should work with unreachable blocks. If not, then this
is a bug that should be fixed in the code generator, not papered over with
the simplifycfg pass. Eliminating this makes bugpoint much more useful
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14477 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 7cd444082e54207fbb8ed0c958c7a23ed334650c |
28-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Can't print out machine code before it is constructed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14472 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| 3905b57442ba9c2920ab87b5105f8dfa505a3839 |
28-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix the assembly opcode on LOADLoAddr, courtesy of Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14470 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| b2edb443e03ca5e8723018fb0fad41bc4e3849b3 |
28-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Set isBranch and isTerminator bits on all branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14469 91177308-0d34-0410-b5e6-96231b3b80d8
PCInstrInfo.td
|
| 7e5812cd174c9f29135dc1567aecf7fe3b6450ef |
28-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix loading and storing PC-relative static variables, courtesy of Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14468 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| a6e58b3cfb4b5a9be2512bd4fb936a1cb2010924 |
28-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
No need to generate a lazy-linking stub for internal functions, they can be
resolved by the static linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14467 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 9c661c8e26e93cbc1080d881e422cbcb4ca02e7b |
28-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Do not set the `link' bit when branching to the first BB of a function, as it
will cause an infinite loop. The link bit is only used for calling functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14466 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| bb4a90820c8a5e018c5a67728d0b3e3400cc8e2f |
28-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix spacing around function arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14463 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 34fa8714a47212ca422948e47651fcced4910051 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Allow debugging machine instrs (by printout) before/after isel and regalloc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14416 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| c6cc10f48f5956eee4c1947c7b2417423f818077 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Combine several if stmts with returns into an if-then-elseif-else chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14414 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| d47bbf7ce53ada1c6a810de82987a05db725f13d |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Do not move any values into registers for a void return (there isn't anything).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14413 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 1cbb3ee75f3ea86913bd95e9e266663a57c6dd89 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Convert tabs to spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14412 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 972569a22f4add23e03d750a130ebede99575eb0 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix opcode: no immediate in an `or r1, r2, r3' (all registers) instr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14411 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 2bf183c092138e426c7f66bb072d8e0f7de36648 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Be consistent about MachineBB labels and references to them in instr stream
* Use MachineBB's built-in numbering system instead of reinventing one
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14408 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 22e12076e9bd62401d28b0c6bae380955a76abff |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Initialize the entire array statically, not member-at-a-time
* Remove x86-specific comment re: intel vs. at&t assembly syntax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14406 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 9ecf3bf7085c818849257f5f3f7d1345bfaba802 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fix bug in previous checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14405 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 911afde4aee1d7b30a9c1345a92ec11aa03b7257 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Wrap long lines
* Replace silent fall-through FIXME comments with an error to cerr and an abort
* No need to set size of statically initialized arrays
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14404 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 179d97cfa3264688ac05a717da91f36bdd2d4373 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Excise X86-specific comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14403 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 75afe1f90472b1605ea05a2d13e615956998f8d1 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add option to print out machine code before register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14387 91177308-0d34-0410-b5e6-96231b3b80d8
PCTargetMachine.cpp
|
| f3e50bea063c5d2870d210f224693cb636cc9520 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Use DEBUG() guard for printing out debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14386 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| e327e499138dac76c85076ba9494dab9500f81fa |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add a `break' in the switch/case statement between the int/fp sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14385 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 7f484a5fff140ade284a1af34641da067bea11ae |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Lowercase the register names
* Parenthesize assert() expressions correctly
* Fix spacing around for() and if() statements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14384 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| ca428df792b40a73d904670e03b23080b1cabb1a |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Tabs to spaces
* Send an error message to std::cerr before abort()ing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14381 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 46fd00aec6a674003a565c60ae2894966ccb9a36 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Tabs to spaces
* Remove unnecessary parens, braces, clean up code layout
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14379 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| fadb82f920da055d10ddd15744b6803a9b4c2d06 |
25-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Unindent some more code to be consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14377 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 1916bf942746b4f41312ce287329af3c6ec8bf6f |
24-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Unindent some code, it only needs 2 spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14376 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 98649d17966f3c32d2f67c16ec2a6183748bb243 |
24-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
In emitting code for a GEP instr, iterate over GEPTypes because there is one
more operand in GEPOps than there are types in GEPTypes: the pointer that is the
first operand of the GEP instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14375 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 05794498d95903d22e4402d005d1f03fab3bc78a |
24-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Order #includes
* Use the DEBUG() guard for debug printouts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14367 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
|
| 3d357441bf870a2b6774fbc430f932f1a369cf6b |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Spell out `NoFramePointerElim'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14300 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 83eaa0b567156875d8d5f831dec0287627706da2 |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Use the common `NoFPElim' setting instead of our own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14298 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCRegisterInfo.cpp
|
| 2fec9905aa5fcd14e156c7520be84d24158b6335 |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
* Make indentation consistent at 2 chars
* Doxygenify function comments
* Wrap code at 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14295 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 1e32f79d20e78186d3d54fc347a9713e34632037 |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
This file is no longer applicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14294 91177308-0d34-0410-b5e6-96231b3b80d8
EADME.txt
|
| 8c9f520b331af7469934f5e75bc02e79d358fd69 |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
llvm/IntrinsicLowering.h => llvm/CodeGen/IntrinsicLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14292 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
PCTargetMachine.cpp
owerPCISelSimple.cpp
|
| a2916ce49a9c7c2e0c6d8b91467baaca61a5f77e |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Intrinsic::isnan has gone away, support for it commented out.
Intrinsic::isunordered has arrived, and we just use the standard lowering
pass for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14290 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 422791fa0b860df682138c90cd3f0303b5409445 |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Convert tabs to spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14289 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| 358829f1510031794ed9419ac869ab31c31c337f |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Type::getPrimitiveID() -> getTypeID()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14288 91177308-0d34-0410-b5e6-96231b3b80d8
PC32ISelSimple.cpp
owerPCISelSimple.cpp
|
| d71bd56caa4bddc1219584fce81af6e8a53c85a1 |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Type::getPrimitiveID() -> getTypeID()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14287 91177308-0d34-0410-b5e6-96231b3b80d8
PC32AsmPrinter.cpp
PCAsmPrinter.cpp
owerPCAsmPrinter.cpp
owerPCRegisterInfo.cpp
|
| 5dfe3a9c3bd9091f9adecc909665d52bdd4edd8c |
21-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Initial revision
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14283 91177308-0d34-0410-b5e6-96231b3b80d8
akefile
PC.h
PC32AsmPrinter.cpp
PC32ISelSimple.cpp
PCAsmPrinter.cpp
PCCodeEmitter.cpp
PCInstrBuilder.h
PCInstrInfo.td
PCJITInfo.h
PCRegisterInfo.td
PCTargetMachine.cpp
owerPC.td
owerPCAsmPrinter.cpp
owerPCCodeEmitter.cpp
owerPCISelSimple.cpp
owerPCInstrInfo.cpp
owerPCInstrInfo.h
owerPCRegisterInfo.cpp
owerPCRegisterInfo.h
owerPCTargetMachine.h
EADME.txt
|
| 5478c7a18a949c17c8a605818a0c64e1b58de9c3 |
14-Jun-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Add file comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14172 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCReg.td
|
| 32305f7763ac0ab7ddad2ee97bd075591962cb3a |
10-Jun-2004 |
Chris Lattner <sabre@nondot.org> |
Fix the fixed stack offset, patch contributed by Vladimir Prus
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14110 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCTargetMachine.cpp
|
| 9a89f37dc7b72ab14a752a65f7e271312f876e9d |
28-Feb-2004 |
Chris Lattner <sabre@nondot.org> |
fine grainify namespacification
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11959 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCTargetMachine.cpp
|
| c81efdc59cd2ce5410cefd7ab5cb52cfd7ac3aad |
15-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Add back machine code deleter pass until we get a MachineCode pass
that will be responsible for the creation of MachineFunctions and will
be required by all MachineFunctionPass passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11453 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCTargetMachine.cpp
|
| c0b9dc5be79f009d260edb5cd5e1d8346587aaa2 |
12-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Change MachineBasicBlock's vector of MachineInstr pointers into an
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCTargetMachine.cpp
|
| 03f84a969c85aa10dd6096666080ae0868eb30b6 |
02-Feb-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Include PowerPC.h. Flesh out the stub versions of addPassesToEmitAssembly()
and addPassesToJITCompile() slightly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11076 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCTargetMachine.cpp
|
| b77232d1fc2796a5917f4044dfe82162e32cc0a7 |
02-Feb-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Add comments describing how you would add prototypes for factory methods for
PowerPC-specific passes here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11073 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC.h
|
| 954e3164be831712a6df2620870f80e7f58bf644 |
23-Jan-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Add the JITInfo object, accessor & initializer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10972 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCTargetMachine.cpp
|
| 7b0cd6d6cb2a3674156df2a1d388a9e3332b5b3e |
23-Jan-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Add CodeEmitter and JITInfo stubs. Dump the old
PowerPCTargetMachine::addPassesToJITCompile() method, in favor of the
TargetJITInfo interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10971 91177308-0d34-0410-b5e6-96231b3b80d8
owerPCJITInfo.h
owerPCTargetMachine.cpp
|
| ca78f49234d52fca9d44800dbe6ec1ac387564d7 |
21-Jan-2004 |
Brian Gaeke <gaeke@uiuc.edu> |
Import of skeletal PowerPC backend I have had laying around for months...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10937 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC.h
owerPCInstrs.td
owerPCReg.td
owerPCTargetMachine.cpp
|